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[RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.
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Authored by craig.topper on Jun 23 2021, 3:31 PM.

Details

Summary

These allow getting a whole register from a larger lmul. Or
inserting a whole register into a larger lmul register. Fractional
lmuls are not supported as they would require a vslide.

Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/99

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Event Timeline

craig.topper created this revision.Jun 23 2021, 3:31 PM
craig.topper requested review of this revision.Jun 23 2021, 3:31 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 23 2021, 3:31 PM
JojoR added a subscriber: JojoR.Jun 23 2021, 6:33 PM

Thanks for your commit :)

This revision is now accepted and ready to land.Jun 23 2021, 8:45 PM

What's supposed to happen if the provided index is invalid? I'm suspecting we'd currently get a IR verification error on the insert/extract indices. I'm wondering if we can/should catch that earlier?

Add constant argument range checking to SemaChecking