[PowerPC] Floating Point Builtins for XL Compat.

[quinnp]

Summary

This patch is in a series of patches to provide
builtins for compatibility with the XL compiler.
This patch adds builtins related to floating point
operations

[quinnp]

Changed the target architecture of tests to follow the convention: BE-pwr7 LE-pwr8.

[qiucf]

clang/test/CodeGen/builtins-ppc-xlcompat-sync.c

2 ↗

(On Diff #352240)

Why change pwr7 to pwr8?

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3324

Seems we didn't exploit XXSEL in this case. But for sqrt/rsqrt, PPC has VSX and non-VSX versions for them:

frsqrte - xsrsqrtedp
frsqrtes - xsrsqrtesp
fsqrt - xssqrtdp
fsqrts - xssqrtsp

So needs to add frsqrte here and xsrsqrtesp/xssqrtsp in VSX part?

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

10

You can use update_llc_test script to automatically update this file.

And add non-vsx test?

[quinnp]

Addressing some comments and updating tests

[quinnp]

Fixing the 32bit AIX run line in the testcases.

[quinnp]

Added non-vsx implementation of builtins and non-vsx backend tests

[NeHuang]

Overall looks good. Some nits as below.

clang/test/CodeGen/builtins-ppc-xlcompat-fp.c

10

• You can define three extern variables for all the bulitins.

extern double a;
extern float b；
extern float c；

• You can auto update the test case with utils/update_cc_test_checks.py

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4990

you can delete blank line and better add comments for the operation below.

4992

Please use Ops as the variable name.

[NeHuang]

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

19

you can remove #0, #1 and #2

[quinnp]

Addressing review comments.

[quinnp]

Fixing a typo and the format of a test.

[quinnp]

clang/test/CodeGen/builtins-ppc-xlcompat-sync.c

2 ↗

(On Diff #352240)

This was to match the testing convention for XL compatibility builtins of targeting pwr7 for big endian and pwr8 for little endian. However, I will not be changing the sync tests in this patch, I have reversed those changes and will be putting them into a different patch.

[amyk]

clang/test/CodeGen/builtins-ppc-xlcompat-fp.c

4

nit: indentation on every second run line. We usually do two spaces more than the previous line. So I think it would look like:

20

Do the entry lines cause an issue when we don't have asserts?

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1529

Minor indentation nit.

1532

Minor indentation nit to make it aligned with above.

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

3

Minor indentation nit:

[quinnp]

Adressing some review comments.

[nemanjai]

clang/test/CodeGen/builtins-ppc-xlcompat-fp.c

6

AFAICT, nothing changes with Power8 so you might as well just have run lines for Power7 (AIX) and Power8 (LE).

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1529

I don't think this indentation is desired. This makes it look like the first type on line 1529 belongs in the first list rather than the second list it belongs to. I suggest the following:

def int_ppc_fsel :
  GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty,
                               llvm_double_ty, llvm_double_ty], [IntrNoMem]>;

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4990

I agree that this warrants a comment. However I don't think this is really what Victor had in mind. In general if your comment boils down to "this is what we are doing" and simply describes the code, it is not very useful. What your comment should address is "why are we doing this here and this way".

To me as a reader, it is not at all clear why we manually select this to PPC::FSELS here. All the other intrinsics are matched with patterns in the .td file but this one is matched specifically here. Why?

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

3

Again, this is excessive. There should be run lines for Power8, Power8-32-bit, Power8-no-vsx, Power7. We don't really need a cross-product of triples and CPUs.

[nemanjai]

Requesting changes to remove it from the queue until comments are addressed or answered.

[quinnp]

Addressing some review comments.

[quinnp]

Adding a better comment for the handling of the ppc_fsels intrinsic.

[quinnp]

Fixing a run line in a test.

[nemanjai]

LGTM aside from a very minor nit.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4990

s/ppc_fels intrinsic/PPC::FSELS instruction

since we aren't emitting an intrinsic, we are consuming it and emitting the instruction (well a MachineSDNode, but it represents an instruction).

[amyk]

My comments were addressed and I agree with the new indentation - LGTM.

[NeHuang]

LGTM

[quinnp]

Addressing review comment.

[lei]

please rebase to ToT

[quinnp]

Rebasing patch. Moving macro definitions from a header file to a src file.

[quinnp]

Rebasing to ToT

[quinnp]

Rebasing to ToT.

[DavidSpickett]

You missed a REQUIRES for the llvm test, I added one in: https://reviews.llvm.org/rG2404834c206a8930b0c420d94f4941b31c355de5

So if you see Arm-AArch64 quick bot failures, that was the reason.

[quinnp]

In D103986#2893177, @DavidSpickett wrote:

You missed a REQUIRES for the llvm test, I added one in: https://reviews.llvm.org/rG2404834c206a8930b0c420d94f4941b31c355de5

So if you see Arm-AArch64 quick bot failures, that was the reason.

Right, sorry about that. Thank you, I will also move the test to llvm/test/CodeGen/PowerPC

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_ppc_iospace_sync, "v", "")
 BUILTIN(__builtin_ppc_dcbfl, "vvC*", "")
 BUILTIN(__builtin_ppc_dcbflp, "vvC*", "")
 BUILTIN(__builtin_ppc_dcbst, "vvC*", "")
 BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
+BUILTIN(__builtin_ppc_fric, "dd", "")
+BUILTIN(__builtin_ppc_frim, "dd", "")
+BUILTIN(__builtin_ppc_frims, "ff", "")
+BUILTIN(__builtin_ppc_frin, "dd", "")
+BUILTIN(__builtin_ppc_frins, "ff", "")
+BUILTIN(__builtin_ppc_frip, "dd", "")
+BUILTIN(__builtin_ppc_frips, "ff", "")
+BUILTIN(__builtin_ppc_friz, "dd", "")
+BUILTIN(__builtin_ppc_frizs, "ff", "")
+BUILTIN(__builtin_ppc_fsel, "dddd", "")
+BUILTIN(__builtin_ppc_fsels, "ffff", "")
+BUILTIN(__builtin_ppc_frsqrte, "dd", "")
+BUILTIN(__builtin_ppc_frsqrtes, "ff", "")
+BUILTIN(__builtin_ppc_fsqrt, "dd", "")
+BUILTIN(__builtin_ppc_fsqrts, "ff", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
 // This is just a placeholder, the types and attributes are wrong.
 BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "")
 
 BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "")

clang/lib/Basic/Targets/PPC.h

void defineXLCompatMacros(MacroBuilder &Builder) const {
     Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
     Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
     Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
     Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
     Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
     Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
     Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
     Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
+    Builder.defineMacro("__fric", "__builtin_ppc_fric");
+    Builder.defineMacro("__frim", "__builtin_ppc_frim");
+    Builder.defineMacro("__frims", "__builtin_ppc_frims");
+    Builder.defineMacro("__frin", "__builtin_ppc_frin");
+    Builder.defineMacro("__frins", "__builtin_ppc_frins");
+    Builder.defineMacro("__frip", "__builtin_ppc_frip");
+    Builder.defineMacro("__frips", "__builtin_ppc_frips");
+    Builder.defineMacro("__friz", "__builtin_ppc_friz");
+    Builder.defineMacro("__frizs", "__builtin_ppc_frizs");
+    Builder.defineMacro("__fsel", "__builtin_ppc_fsel");
+    Builder.defineMacro("__fsels", "__builtin_ppc_fsels");
+    Builder.defineMacro("__frsqrte", "__builtin_ppc_frsqrte");
+    Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
+    Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
+    Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
   }
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
 public:
   PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : PPCTargetInfo(Triple, Opts) {
     if (Triple.isOSAIX())

clang/lib/CodeGen/CGBuiltin.cpp

if (Accumulate) {
       CallOps.push_back(Acc);
     }
     for (unsigned i=1; i<Ops.size(); i++)
       CallOps.push_back(Ops[i]);
     llvm::Function *F = CGM.getIntrinsic(ID);
     Value *Call = Builder.CreateCall(F, CallOps);
     return Builder.CreateAlignedStore(Call, Ops[0], MaybeAlign(64));
   }
+  case PPC::BI__builtin_ppc_fric:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::rint,
+                           Intrinsic::experimental_constrained_rint))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_frim:
+  case PPC::BI__builtin_ppc_frims:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::floor,
+                           Intrinsic::experimental_constrained_floor))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_frin:
+  case PPC::BI__builtin_ppc_frins:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::round,
+                           Intrinsic::experimental_constrained_round))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_frip:
+  case PPC::BI__builtin_ppc_frips:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::ceil,
+                           Intrinsic::experimental_constrained_ceil))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_friz:
+  case PPC::BI__builtin_ppc_frizs:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::trunc,
+                           Intrinsic::experimental_constrained_trunc))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_fsqrt:
+  case PPC::BI__builtin_ppc_fsqrts:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::sqrt,
+                           Intrinsic::experimental_constrained_sqrt))
+        .getScalarVal();
   }
 }
 
 namespace {
 // If \p E is not null pointer, insert address space cast to match return
 // type of \p E if necessary.
 Value *EmitAMDGPUDispatchPtr(CodeGenFunction &CGF,
                              const CallExpr *E = nullptr) {

clang/test/CodeGen/builtins-ppc-xlcompat-fp.c

+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double a;
+extern double b;
+extern double c;
+extern float d;
+extern float e;
+extern float f;
+
+// CHECK-LABEL: @test_fric(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.rint.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_fric() {
+  return __fric(a);
+}
+
+// CHECK-LABEL: @test_frim(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.floor.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_frim() {
+  return __frim(a);
+}
+
+// CHECK-LABEL: @test_frims(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.floor.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_frims() {
+  return __frims(d);
+}
+
+// CHECK-LABEL: @test_frin(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.round.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_frin() {
+  return __frin(a);
+}
+
+// CHECK-LABEL: @test_frins(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.round.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_frins() {
+  return __frins(d);
+}
+
+// CHECK-LABEL: @test_frip(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.ceil.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_frip() {
+  return __frip(a);
+}
+
+// CHECK-LABEL: @test_frips(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.ceil.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_frips() {
+  return __frips(d);
+}
+
+// CHECK-LABEL: @test_friz(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.trunc.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_friz() {
+  return __friz(a);
+}
+
+// CHECK-LABEL: @test_frizs(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.trunc.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_frizs() {
+  return __frizs(d);
+}
+
+// CHECK-LABEL: @test_fsel(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = call double @llvm.ppc.fsel(double [[TMP0]], double [[TMP1]], double [[TMP2]])
+// CHECK-NEXT:    ret double [[TMP3]]
+//
+double test_fsel() {
+  return __fsel(a, b, c);
+}
+
+// CHECK-LABEL: @test_fsels(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:    [[TMP3:%.*]] = call float @llvm.ppc.fsels(float [[TMP0]], float [[TMP1]], float [[TMP2]])
+// CHECK-NEXT:    ret float [[TMP3]]
+//
+float test_fsels() {
+  return __fsels(d, e, f);
+}
+
+// CHECK-LABEL: @test_frsqrte(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = call double @llvm.ppc.frsqrte(double [[TMP0]])
+// CHECK-NEXT:    ret double [[TMP1]]
+//
+double test_frsqrte() {
+  return __frsqrte(a);
+}
+
+// CHECK-LABEL: @test_frsqrtes(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = call float @llvm.ppc.frsqrtes(float [[TMP0]])
+// CHECK-NEXT:    ret float [[TMP1]]
+//
+float test_frsqrtes() {
+  return __frsqrtes(d);
+}
+
+// CHECK-LABEL: @test_fsqrt(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.sqrt.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_fsqrt() {
+  return __fsqrt(a);
+}
+
+// CHECK-LABEL: @test_fsqrts(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.sqrt.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_fsqrts() {
+  return __fsqrts(d);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_fric(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.rint.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_builtin_ppc_fric() {
+  return __builtin_ppc_fric(a);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_frim(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.floor.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_builtin_ppc_frim() {
+  return __builtin_ppc_frim(a);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_frims(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.floor.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_builtin_ppc_frims() {
+  return __builtin_ppc_frims(d);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_frin(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.round.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_builtin_ppc_frin() {
+  return __builtin_ppc_frin(a);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_frins(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.round.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_builtin_ppc_frins() {
+  return __builtin_ppc_frins(d);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_frip(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.ceil.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_builtin_ppc_frip() {
+  return __builtin_ppc_frip(a);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_frips(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.ceil.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_builtin_ppc_frips() {
+  return __builtin_ppc_frips(d);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_friz(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.trunc.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_builtin_ppc_friz() {
+  return __builtin_ppc_friz(a);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_frizs(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.trunc.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_builtin_ppc_frizs() {
+  return __builtin_ppc_frizs(d);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_fsel(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = call double @llvm.ppc.fsel(double [[TMP0]], double [[TMP1]], double [[TMP2]])
+// CHECK-NEXT:    ret double [[TMP3]]
+//
+double test_builtin_ppc_fsel() {
+  return __builtin_ppc_fsel(a, b, c);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_fsels(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:    [[TMP3:%.*]] = call float @llvm.ppc.fsels(float [[TMP0]], float [[TMP1]], float [[TMP2]])
+// CHECK-NEXT:    ret float [[TMP3]]
+//
+float test_builtin_ppc_fsels() {
+  return __builtin_ppc_fsels(d, e, f);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_frsqrte(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = call double @llvm.ppc.frsqrte(double [[TMP0]])
+// CHECK-NEXT:    ret double [[TMP1]]
+//
+double test_builtin_ppc_frsqrte() {
+  return __builtin_ppc_frsqrte(a);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_frsqrtes(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = call float @llvm.ppc.frsqrtes(float [[TMP0]])
+// CHECK-NEXT:    ret float [[TMP1]]
+//
+float test_builtin_ppc_frsqrtes() {
+  return __builtin_ppc_frsqrtes(d);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_fsqrt(
+// CHECK:    [[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP1:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:    [[TMP2:%.*]] = call double @llvm.sqrt.f64(double [[TMP1]])
+// CHECK-NEXT:    ret double [[TMP2]]
+//
+double test_builtin_ppc_fsqrt() {
+  return __builtin_ppc_fsqrt(a);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_fsqrts(
+// CHECK:    [[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP1:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:    [[TMP2:%.*]] = call float @llvm.sqrt.f32(float [[TMP1]])
+// CHECK-NEXT:    ret float [[TMP2]]
+//
+float test_builtin_ppc_fsqrts() {
+  return __builtin_ppc_fsqrts(d);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_lwsync : GCCBuiltin<"__builtin_ppc_lwsync">,
                        Intrinsic<[], [], []>;
   def int_ppc_iospace_lwsync : GCCBuiltin<"__builtin_ppc_iospace_lwsync">,
                                Intrinsic<[], [], []>;
   // eieio instruction
   def int_ppc_eieio : GCCBuiltin<"__builtin_ppc_eieio">,
                       Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
                               Intrinsic<[],[],[]>;
+
+  def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
+                     Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty, 
+                                                  llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fsels : GCCBuiltin<"__builtin_ppc_fsels">,
+                      Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
+                                                  llvm_float_ty], [IntrNoMem]>;
+  def int_ppc_frsqrte : GCCBuiltin<"__builtin_ppc_frsqrte">,
+                        Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_frsqrtes : GCCBuiltin<"__builtin_ppc_frsqrtes">,
+                         Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
 }
 

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

void PPCDAGToDAGISel::Select(SDNode *N) {
   case ISD::Constant:
     if (N->getValueType(0) == MVT::i64) {
       ReplaceNode(N, selectI64Imm(CurDAG, N));
       return;
     }
     break;
 
   case ISD::INTRINSIC_WO_CHAIN: {
+    // We emit the ppc_fsels intrinsic here because of type conflicts with the
+    // comparison operand. The FSELS instruction is defined to use an 8-byte
+    // comparison like the FSELD version. The fsels intrinsic takes a 4-byte
+    // value for the comparison. When selecting through a .td file, a type
+    // error is raised. Must check this first so we never break on the
+    // !Subtarget->isISA3_1() check.
+    if (N->getConstantOperandVal(0) == Intrinsic::ppc_fsels) {
+      SDValue Ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3)};
+      CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32, Ops);
+      return;
+    }
+
     if (!Subtarget->isISA3_1())
       break;
     unsigned Opcode = 0;
     switch (N->getConstantOperandVal(0)) {
     default:
       break;
     case Intrinsic::ppc_altivec_vstribr_p:
       Opcode = PPC::VSTRIBR_rec;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

defm FSUBS : AForm_2r<59, 20,
                         "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
                         [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>;
   }
 }
 
 let hasSideEffects = 0 in {
 let PPC970_Unit = 1 in {  // FXU Operations.
   let isSelect = 1 in
   def ISEL  : AForm_4<31, 15,
                      (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
                      "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
                      []>;
 }
 
 let PPC970_Unit = 1 in {  // FXU Operations.
 // M-Form instructions.  rotate and mask instructions.
 //
def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
                               "#ANDI_rec_1_GT_BIT8",
                               [(set i1:$dst, (trunc i64:$in))]>;
 
 def : Pat<(i1 (not (trunc i32:$in))),
            (ANDI_rec_1_EQ_BIT $in)>;
 def : Pat<(i1 (not (trunc i64:$in))),
            (ANDI_rec_1_EQ_BIT8 $in)>;
 
+def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>;
+def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>;
+def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>;
+
 //===----------------------------------------------------------------------===//
 // PowerPC Instructions used for assembler/disassembler only
 //
 
 // FIXME: For B=0 or B > 8, the registers following RT are used.
 // WARNING: Do not add patterns for this instruction without fixing this.
 def LSWI  : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT),
                                   (ins gprc:$A, u5imm:$B),

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 let AddedComplexity = 0 in {
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 967)),
           (VCMPGTUB_rec DblwdCmp.MRGSGT, (v2i64 (XXLXORz)))>;
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 711)),
           (VCMPGTUB_rec DblwdCmp.MRGUGT, (v2i64 (XXLXORz)))>;
 def : Pat<(v2i64 (PPCvcmp_rec v2i64:$vA, v2i64:$vB, 199)),
           (VCMPGTUB_rec DblwdCmp.MRGEQ, (v2i64 (XXLXORz)))>;
 } // AddedComplexity = 0
+
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
 } // HasVSX
 
 // Any big endian VSX subtarget.
 let Predicates = [HasVSX, IsBigEndian] in {
 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
           (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>;
 
 def : Pat<(f64 (extractelt v2f64:$S, 0)),

 def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),
           (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),
           (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
           (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
 def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
           (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+
+def : Pat<(int_ppc_frsqrtes vssrc:$XB), (XSRSQRTESP $XB)>;
 } // HasVSX, HasP8Vector
 
 // Any big endian Power8 VSX subtarget.
 let Predicates = [HasVSX, HasP8Vector, IsBigEndian] in {
 def : Pat<DWToSPExtractConv.El0SS1,
           (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>;
 def : Pat<DWToSPExtractConv.El1SS1,
           (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-PWR7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mattr=-vsx -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-NOVSX
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsel:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: test_fsel:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: test_fsel:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:    blr
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+  ret double %0
+}
+
+declare double @llvm.ppc.fsel(double, double, double)
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_fsels:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    fsel 1, 1, 2, 3
+; CHECK-PWR7-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: test_fsels:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    fsel 1, 1, 2, 3
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: test_fsels:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    fsel 1, 1, 2, 3
+; CHECK-NOVSX-NEXT:    blr
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+  ret float %0
+}
+
+declare float @llvm.ppc.fsels(float, float, float)
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrte:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    xsrsqrtedp 1, 1
+; CHECK-PWR7-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: test_frsqrte:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsrsqrtedp 1, 1
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrte:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    frsqrte 1, 1
+; CHECK-NOVSX-NEXT:    blr
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+  ret double %0
+}
+
+declare double @llvm.ppc.frsqrte(double)
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr {
+; CHECK-PWR7-LABEL: test_frsqrtes:
+; CHECK-PWR7:       # %bb.0: # %entry
+; CHECK-PWR7-NEXT:    frsqrtes 1, 1
+; CHECK-PWR7-NEXT:    blr
+;
+; CHECK-PWR8-LABEL: test_frsqrtes:
+; CHECK-PWR8:       # %bb.0: # %entry
+; CHECK-PWR8-NEXT:    xsrsqrtesp 1, 1
+; CHECK-PWR8-NEXT:    blr
+;
+; CHECK-NOVSX-LABEL: test_frsqrtes:
+; CHECK-NOVSX:       # %bb.0: # %entry
+; CHECK-NOVSX-NEXT:    frsqrtes 1, 1
+; CHECK-NOVSX-NEXT:    blr
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+  ret float %0
+}
+
+declare float @llvm.ppc.frsqrtes(float)