[PowerPC] Floating Point Builtins for XL Compat.

[quinnp]

Summary

This patch is in a series of patches to provide
builtins for compatibility with the XL compiler.
This patch adds builtins related to floating point
operations

[quinnp]

Changed the target architecture of tests to follow the convention: BE-pwr7 LE-pwr8.

[qiucf]

clang/test/CodeGen/builtins-ppc-xlcompat-sync.c

2 ↗

(On Diff #352240)

Why change pwr7 to pwr8?

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3324

Seems we didn't exploit XXSEL in this case. But for sqrt/rsqrt, PPC has VSX and non-VSX versions for them:

frsqrte - xsrsqrtedp
frsqrtes - xsrsqrtesp
fsqrt - xssqrtdp
fsqrts - xssqrtsp

So needs to add frsqrte here and xsrsqrtesp/xssqrtsp in VSX part?

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

10

You can use update_llc_test script to automatically update this file.

And add non-vsx test?

[quinnp]

Addressing some comments and updating tests

[quinnp]

Fixing the 32bit AIX run line in the testcases.

[quinnp]

Added non-vsx implementation of builtins and non-vsx backend tests

[NeHuang]

Overall looks good. Some nits as below.

clang/test/CodeGen/builtins-ppc-xlcompat-fp.c

10

• You can define three extern variables for all the bulitins.

extern double a;
extern float b；
extern float c；

• You can auto update the test case with utils/update_cc_test_checks.py

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4990

you can delete blank line and better add comments for the operation below.

4992

Please use Ops as the variable name.

[NeHuang]

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

19

you can remove #0, #1 and #2

[quinnp]

Addressing review comments.

[quinnp]

Fixing a typo and the format of a test.

[quinnp]

clang/test/CodeGen/builtins-ppc-xlcompat-sync.c

2 ↗

(On Diff #352240)

This was to match the testing convention for XL compatibility builtins of targeting pwr7 for big endian and pwr8 for little endian. However, I will not be changing the sync tests in this patch, I have reversed those changes and will be putting them into a different patch.

[amyk]

clang/test/CodeGen/builtins-ppc-xlcompat-fp.c

4

nit: indentation on every second run line. We usually do two spaces more than the previous line. So I think it would look like:

20

Do the entry lines cause an issue when we don't have asserts?

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1529

Minor indentation nit.

1532

Minor indentation nit to make it aligned with above.

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

3

Minor indentation nit:

[quinnp]

Adressing some review comments.

[nemanjai]

clang/test/CodeGen/builtins-ppc-xlcompat-fp.c

6

AFAICT, nothing changes with Power8 so you might as well just have run lines for Power7 (AIX) and Power8 (LE).

llvm/include/llvm/IR/IntrinsicsPowerPC.td

1529

I don't think this indentation is desired. This makes it look like the first type on line 1529 belongs in the first list rather than the second list it belongs to. I suggest the following:

def int_ppc_fsel :
  GCCBuiltin<"__builtin_ppc_fsel">,
  Intrinsic<[llvm_double_ty], [llvm_double_ty,
                               llvm_double_ty, llvm_double_ty], [IntrNoMem]>;

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4990

I agree that this warrants a comment. However I don't think this is really what Victor had in mind. In general if your comment boils down to "this is what we are doing" and simply describes the code, it is not very useful. What your comment should address is "why are we doing this here and this way".

To me as a reader, it is not at all clear why we manually select this to PPC::FSELS here. All the other intrinsics are matched with patterns in the .td file but this one is matched specifically here. Why?

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

3

Again, this is excessive. There should be run lines for Power8, Power8-32-bit, Power8-no-vsx, Power7. We don't really need a cross-product of triples and CPUs.

[nemanjai]

Requesting changes to remove it from the queue until comments are addressed or answered.

[quinnp]

Addressing some review comments.

[quinnp]

Adding a better comment for the handling of the ppc_fsels intrinsic.

[quinnp]

Fixing a run line in a test.

[nemanjai]

LGTM aside from a very minor nit.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4990

s/ppc_fels intrinsic/PPC::FSELS instruction

since we aren't emitting an intrinsic, we are consuming it and emitting the instruction (well a MachineSDNode, but it represents an instruction).

[amyk]

My comments were addressed and I agree with the new indentation - LGTM.

[NeHuang]

LGTM

[quinnp]

Addressing review comment.

[lei]

please rebase to ToT

[quinnp]

Rebasing patch. Moving macro definitions from a header file to a src file.

[quinnp]

Rebasing to ToT

[quinnp]

Rebasing to ToT.

[DavidSpickett]

You missed a REQUIRES for the llvm test, I added one in: https://reviews.llvm.org/rG2404834c206a8930b0c420d94f4941b31c355de5

So if you see Arm-AArch64 quick bot failures, that was the reason.

[quinnp]

In D103986#2893177, @DavidSpickett wrote:

You missed a REQUIRES for the llvm test, I added one in: https://reviews.llvm.org/rG2404834c206a8930b0c420d94f4941b31c355de5

So if you see Arm-AArch64 quick bot failures, that was the reason.

Right, sorry about that. Thank you, I will also move the test to llvm/test/CodeGen/PowerPC

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_ppc_iospace_sync, "v", "")
 BUILTIN(__builtin_ppc_dcbfl, "vvC*", "")
 BUILTIN(__builtin_ppc_dcbflp, "vvC*", "")
 BUILTIN(__builtin_ppc_dcbst, "vvC*", "")
 BUILTIN(__builtin_ppc_dcbt, "vv*", "")
 BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
 BUILTIN(__builtin_ppc_dcbz, "vv*", "")
 BUILTIN(__builtin_ppc_icbt, "vv*", "")
+BUILTIN(__builtin_ppc_fric, "dd", "")
+BUILTIN(__builtin_ppc_frim, "dd", "")
+BUILTIN(__builtin_ppc_frims, "ff", "")
+BUILTIN(__builtin_ppc_frin, "dd", "")
+BUILTIN(__builtin_ppc_frins, "ff", "")
+BUILTIN(__builtin_ppc_frip, "dd", "")
+BUILTIN(__builtin_ppc_frips, "ff", "")
+BUILTIN(__builtin_ppc_friz, "dd", "")
+BUILTIN(__builtin_ppc_frizs, "ff", "")
+BUILTIN(__builtin_ppc_fsel, "dddd", "")
+BUILTIN(__builtin_ppc_fsels, "ffff", "")
+BUILTIN(__builtin_ppc_frsqrte, "dd", "")
+BUILTIN(__builtin_ppc_frsqrtes, "ff", "")
+BUILTIN(__builtin_ppc_fsqrt, "dd", "")
+BUILTIN(__builtin_ppc_fsqrts, "ff", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
 // This is just a placeholder, the types and attributes are wrong.
 BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "")
 
 BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "")

clang/lib/Basic/Targets/PPC.h

void defineXLCompatMacros(MacroBuilder &Builder) const {
     Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
     Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
     Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
     Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
     Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
     Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
     Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
     Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
+    Builder.defineMacro("__fric", "__builtin_ppc_fric");
+    Builder.defineMacro("__frim", "__builtin_ppc_frim");
+    Builder.defineMacro("__frims", "__builtin_ppc_frims");
+    Builder.defineMacro("__frin", "__builtin_ppc_frin");
+    Builder.defineMacro("__frins", "__builtin_ppc_frins");
+    Builder.defineMacro("__frip", "__builtin_ppc_frip");
+    Builder.defineMacro("__frips", "__builtin_ppc_frips");
+    Builder.defineMacro("__friz", "__builtin_ppc_friz");
+    Builder.defineMacro("__frizs", "__builtin_ppc_frizs");
+    Builder.defineMacro("__fsel", "__builtin_ppc_fsel");
+    Builder.defineMacro("__fsels", "__builtin_ppc_fsels");
+    Builder.defineMacro("__frsqrte", "__builtin_ppc_frsqrte");
+    Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
+    Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
+    Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
   }
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
 public:
   PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : PPCTargetInfo(Triple, Opts) {
     if (Triple.isOSAIX())

clang/lib/CodeGen/CGBuiltin.cpp

if (Accumulate) {
       CallOps.push_back(Acc);
     }
     for (unsigned i=1; i<Ops.size(); i++)
       CallOps.push_back(Ops[i]);
     llvm::Function *F = CGM.getIntrinsic(ID);
     Value *Call = Builder.CreateCall(F, CallOps);
     return Builder.CreateAlignedStore(Call, Ops[0], MaybeAlign(64));
   }
+  case PPC::BI__builtin_ppc_fric:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::rint,
+                           Intrinsic::experimental_constrained_rint))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_frim:
+  case PPC::BI__builtin_ppc_frims:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::floor,
+                           Intrinsic::experimental_constrained_floor))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_frin:
+  case PPC::BI__builtin_ppc_frins:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::round,
+                           Intrinsic::experimental_constrained_round))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_frip:
+  case PPC::BI__builtin_ppc_frips:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::ceil,
+                           Intrinsic::experimental_constrained_ceil))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_friz:
+  case PPC::BI__builtin_ppc_frizs:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::trunc,
+                           Intrinsic::experimental_constrained_trunc))
+        .getScalarVal();
+  case PPC::BI__builtin_ppc_fsqrt:
+    return RValue::get(emitUnaryMaybeConstrainedFPBuiltin(
+                           *this, E, Intrinsic::sqrt,
+                           Intrinsic::experimental_constrained_sqrt))
+        .getScalarVal();
   }
 }
 
 namespace {
 // If \p E is not null pointer, insert address space cast to match return
 // type of \p E if necessary.
 Value *EmitAMDGPUDispatchPtr(CodeGenFunction &CGF,
                              const CallExpr *E = nullptr) {

clang/test/CodeGen/builtins-ppc-xlcompat-fp.c

+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:    -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s
+
+double test_fric(double a) {
+// CHECK-LABEL: @test_fric
+// CHECK-NEXT:  entry:
+
+  return __fric(a);
+// CHECK: %2 = call double @llvm.rint.f64(double %1)
+}
+
+double test_frim(double a) {
+// CHECK-LABEL: @test_frim
+// CHECK-NEXT:  entry:
+
+  return __frim(a);
+// CHECK: %2 = call double @llvm.floor.f64(double %1) 
+}
+
+float test_frims(float a) {
+// CHECK-LABEL: @test_frims
+// CHECK-NEXT:  entry:
+
+  return __frims(a);
+// CHECK: %2 = call float @llvm.floor.f32(float %1)
+}
+
+double test_frin(double a) {
+// CHECK-LABEL: @test_frin
+// CHECK-NEXT:  entry:
+
+  return __frin(a);
+// CHECK: %2 = call double @llvm.round.f64(double %1)
+}
+
+float test_frins(float a) {
+// CHECK-LABEL: @test_frins
+// CHECK-NEXT:  entry:
+
+  return __frins(a);
+// CHECK: %2 = call float @llvm.round.f32(float %1)
+}
+
+double test_frip(double a) {
+// CHECK-LABEL: @test_frip
+// CHECK-NEXT:  entry:
+
+  return __frip(a);
+// CHECK: %2 = call double @llvm.ceil.f64(double %1)
+}
+
+float test_frips(float a) {
+// CHECK-LABEL: @test_frips
+// CHECK-NEXT: entry:
+
+  return __frips(a);
+// CHECK: %2 = call float @llvm.ceil.f32(float %1)
+}
+
+double test_friz(double a) {
+// CHECK-LABEL: @test_friz
+// CHECK-NEXT:  entry:
+
+  return __friz(a);
+// CHECK: %2 = call double @llvm.trunc.f64(double %1)
+}
+
+float test_frizs(float a) {
+// CHECK-LABEL: @test_frizs
+// CHECK-NEXT:  entry:
+
+  return __frizs(a);
+// CHECK: %2 = call float @llvm.trunc.f32(float %1)
+}
+
+double test_fsel(double a, double b, double c) {
+// CHECK-LABEL: @test_fsel
+// CHECK-NEXT:  entry:
+
+  return __fsel(a, b, c);
+// CHECK: %3 = call double @llvm.ppc.fsel(double %0, double %1, double %2)
+}
+
+float test_fsels(float a, float b, float c) {
+// CHECK-LABEL: @test_fsels
+// CHECK-NEXT:  entry:
+
+  return __fsels(a, b, c);
+// CHECK: %3 = call float @llvm.ppc.fsels(float %0, float %1, float %2)
+}
+
+double test_frsqrte(double a) {
+// CHECK-LABEL: @test_frsqrte
+// CHECK-NEXT:  entry:
+
+  return __frsqrte(a);
+// CHECK: %1 = call double @llvm.ppc.frsqrte(double %0)
+}
+
+float test_frsqrtes(float a) {
+// CHECK-LABEL: @test_frsqrtes
+// CHECK-NEXT:  entry:
+
+  return __frsqrtes(a);
+// CHECK: %1 = call float @llvm.ppc.frsqrtes(float %0)
+}
+
+double test_fsqrt(double a) {
+// CHECK-LABEL: @test_fsqrt
+// CHECK-NEXT:  entry:
+
+  return __fsqrt(a);
+// CHECK: %2 = call double @llvm.sqrt.f64(double %1)
+}
+
+float test_fsqrts(float a) {
+// CHECK-LABEL: @test_fsqrts
+// CHECK-NEXT:  entry:
+
+  return __fsqrts(a);
+// CHECK: %1 = call float @llvm.ppc.fsqrts(float %0)
+}
+
+double test_builtin_ppc_fric(double a) {
+// CHECK-LABEL: @test_builtin_ppc_fric
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_fric(a);
+// CHECK: %2 = call double @llvm.rint.f64(double %1)
+}
+
+double test_builtin_ppc_frim(double a) {
+// CHECK-LABEL: @test_builtin_ppc_frim
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_frim(a);
+// CHECK: %2 = call double @llvm.floor.f64(double %1) 
+}
+
+float test_builtin_ppc_frims(float a) {
+// CHECK-LABEL: @test_builtin_ppc_frims
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_frims(a);
+// CHECK: %2 = call float @llvm.floor.f32(float %1)
+}
+
+double test_builtin_ppc_frin(double a) {
+// CHECK-LABEL: @test_builtin_ppc_frin
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_frin(a);
+// CHECK: %2 = call double @llvm.round.f64(double %1)
+}
+
+float test_builtin_ppc_frins(float a) {
+// CHECK-LABEL: @test_builtin_ppc_frins
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_frins(a);
+// CHECK: %2 = call float @llvm.round.f32(float %1)
+}
+
+double test_builtin_ppc_frip(double a) {
+// CHECK-LABEL: @test_builtin_ppc_frip
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_frip(a);
+// CHECK: %2 = call double @llvm.ceil.f64(double %1)
+}
+
+float test_builtin_ppc_frips(float a) {
+// CHECK-LABEL: @test_builtin_ppc_frips
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_frips(a);
+// CHECK: %2 = call float @llvm.ceil.f32(float %1)
+}
+
+double test_builtin_ppc_friz(double a) {
+// CHECK-LABEL: @test_builtin_ppc_friz
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_friz(a);
+// CHECK: %2 = call double @llvm.trunc.f64(double %1)
+}
+
+float test_builtin_ppc_frizs(float a) {
+// CHECK-LABEL: @test_builtin_ppc_frizs
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_frizs(a);
+// CHECK: %2 = call float @llvm.trunc.f32(float %1)
+}
+
+double test_builtin_ppc_fsel(double a, double b, double c) {
+// CHECK-LABEL: @test_builtin_ppc_fsel
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_fsel(a, b, c);
+// CHECK: %3 = call double @llvm.ppc.fsel(double %0, double %1, double %2)
+}
+
+float test_builtin_ppc_fsels(float a, float b, float c) {
+// CHECK-LABEL: @test_builtin_ppc_fsels
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_fsels(a, b, c);
+// CHECK: %3 = call float @llvm.ppc.fsels(float %0, float %1, float %2)
+}
+
+double test_builtin_ppc_frsqrte(double a) {
+// CHECK-LABEL: @test_builtin_ppc_frsqrte
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_frsqrte(a);
+// CHECK: %1 = call double @llvm.ppc.frsqrte(double %0)
+}
+
+float test_builtin_ppc_frsqrtes(float a) {
+// CHECK-LABEL: @test_builtin_ppc_frsqrtes
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_frsqrtes(a);
+// CHECK: %1 = call float @llvm.ppc.frsqrtes(float %0)
+}
+
+double test_builtin_ppc_fsqrt(double a) {
+// CHECK-LABEL: @test_builtin_ppc_fsqrt
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_fsqrt(a);
+// CHECK: %2 = call double @llvm.sqrt.f64(double %1)
+}
+
+float test_builtin_ppc_fsqrts(float a) {
+// CHECK-LABEL: @test_builtin_ppc_fsqrts
+// CHECK-NEXT:  entry:
+
+  return __builtin_ppc_fsqrts(a);
+// CHECK: %1 = call float @llvm.ppc.fsqrts(float %0)
+}
+

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_lwsync : GCCBuiltin<"__builtin_ppc_lwsync">,
                        Intrinsic<[], [], []>;
   def int_ppc_iospace_lwsync : GCCBuiltin<"__builtin_ppc_iospace_lwsync">,
                                Intrinsic<[], [], []>;
   // eieio instruction
   def int_ppc_eieio : GCCBuiltin<"__builtin_ppc_eieio">,
                       Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
                               Intrinsic<[],[],[]>;
+
+  def int_ppc_fsel : GCCBuiltin<"__builtin_ppc_fsel">,
+                     Intrinsic<[llvm_double_ty], [llvm_double_ty, 
+                     llvm_double_ty, llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_fsels : GCCBuiltin<"__builtin_ppc_fsels">,
+                      Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty,
+                      llvm_float_ty], [IntrNoMem]>;
+  def int_ppc_frsqrte : GCCBuiltin<"__builtin_ppc_frsqrte">,
+                        Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+  def int_ppc_frsqrtes : GCCBuiltin<"__builtin_ppc_frsqrtes">,
+                         Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
+  def int_ppc_fsqrts : GCCBuiltin<"__builtin_ppc_fsqrts">,
+                       Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;
 }
 

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

void PPCDAGToDAGISel::Select(SDNode *N) {
   case ISD::Constant:
     if (N->getValueType(0) == MVT::i64) {
       ReplaceNode(N, selectI64Imm(CurDAG, N));
       return;
     }
     break;
 
   case ISD::INTRINSIC_WO_CHAIN: {
+
+    if (N->getConstantOperandVal(0) == Intrinsic::ppc_fsels) {
+      SDValue ops[] = {N->getOperand(1), N->getOperand(2), N->getOperand(3)};
+      CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32, ops);
+      return;
+    }
+
     if (!Subtarget->isISA3_1())
       break;
     unsigned Opcode = 0;
     switch (N->getConstantOperandVal(0)) {
     default:
       break;
     case Intrinsic::ppc_altivec_vstribr_p:
       Opcode = PPC::VSTRIBR_rec;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

defm FSUB  : AForm_2r<63, 20,
                         [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>;
   defm FSUBS : AForm_2r<59, 20,
                         (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
                         "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
                         [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>;
   }
 }
 
+def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>;
+def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>;  
+def : Pat<(int_ppc_fsqrts f4rc:$frB), (FSQRTS $frB)>;
+
 let hasSideEffects = 0 in {
 let PPC970_Unit = 1 in {  // FXU Operations.
   let isSelect = 1 in
   def ISEL  : AForm_4<31, 15,
                      (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
                      "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
                      []>;
 }

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
             (RLDIMI AnyExts.C, AnyExts.D, 32, 0),
             (RLDIMI AnyExts.A, AnyExts.B, 32, 0))>;
 
 def : Pat<(f128 (PPCbuild_fp128 i64:$rA, i64:$rB)),
           (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>;
 } // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian
 } // AddedComplexity = 400
 
+def : Pat<(int_ppc_frsqrte vsfrc:$XB), (XSRSQRTEDP $XB)>;
+
 //---------------------------- Instruction aliases ---------------------------//
 def : InstAlias<"xvmovdp $XT, $XB",
                 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
 def : InstAlias<"xvmovsp $XT, $XB",
                 (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
 
 // Certain versions of the AIX assembler may missassemble these mnemonics.
 let Predicates = [ModernAs] in {

llvm/test/CodeGen/builtins-ppc-xlcompat-fp.ll

+; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local double @test_fsel(double %a, double %b, double %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsel 
+
+entry:
+  %0 = tail call double @llvm.ppc.fsel(double %a, double %b, double %c)
+; CHECK: fsel f1, f1, f2, f3
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.fsel(double, double, double) #2
+
+define dso_local float @test_fsels(float %a, float %b, float %c) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsels
+
+entry:
+  %0 = tail call float @llvm.ppc.fsels(float %a, float %b, float %c)
+; CHECK: fsel f1, f1, f2, f3
+
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.fsels(float, float, float) #2
+
+define dso_local double @test_frsqrte(double %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrte
+
+entry:
+  %0 = tail call double @llvm.ppc.frsqrte(double %a)
+; CHECK: xsrsqrtedp f1, f1
+
+  ret double %0
+; CHECK: blr
+}
+
+declare double @llvm.ppc.frsqrte(double) #2
+
+define dso_local float @test_frsqrtes(float %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_frsqrtes
+
+entry:
+  %0 = tail call float @llvm.ppc.frsqrtes(float %a)
+; CHECK: frsqrtes f1, f1
+ 
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.frsqrtes(float) #2
+
+define dso_local float @test_fsqrts(float %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fsqrts
+
+entry:
+  %0 = tail call float @llvm.ppc.fsqrts(float %a)
+; CHECK fsqrts f1, f1
+
+  ret float %0
+; CHECK: blr
+}
+
+declare float @llvm.ppc.fsqrts(float) #2
+