[AArch64] Add S/UQXTRN tablegen patterns.

[dmgreen]

Summary

I found these on my computer so cleaned them up and added extra tests/types. This adds simple patterns for signed and unsigned saturating extract narrow instructions. They combine a min/max/truncate into a single instruction, providing that the immediates on the min/max are correct for the saturation type. This is just handled in tablegen with some extra patterns.

v2i64->v2i32 is not handled here as the min/max nodes are not legal, making the lowering quite different.

[sdesmalen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

4233

From the comment, I deduce that (v8i16 (AArch64NvCast (v2i64 (AArch64movi_edit (i32 85))))) <=> v8i16 splat(255). Is there a reason this is not using AArch64dup?
If so, can we use a more generic pattern fragment to see if something is a dup of <value>? That may cover more cases and would also make the pattern more readable.

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

4233

It will lower any constant that it can into a AArch64ISD::MOVIedit/AArch64ISD::MOVIshift/etc. These become the various flavours of MOVI instructions. They are no longer dup's at this stage, if they ever were.

I have created PatFrags names for the constants used here. hopefully that makes it easier to read.

[dmgreen]

ping

[SjoerdMeijer]

Looks reasonable to me.

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

4234

Sander pointed out that these should be 7F, not EF. Doh! I'll update those.

[sdesmalen]

LGTM if you fix s/EF/7F/ before you land it!

llvm/lib/Target/AArch64/AArch64InstrInfo.td

4236

It is nearly impossible to understand how these PatLeafs work, but that's nothing to do with your patch, since BuildVectors are lowered earlier on. It would be nice if these would just have been dup() nodes instead, but I'll just rely on the tests that you have implemented these PatLeafs correctly. At least the names of the PatLeafs (when you fix s/EF/7F/) make it a bit more understandable, thanks for making that change!

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

4236

I have in the past looking into using VECTOR_SPLAT as the canonical representation of a splat in MVE, as opposed to a BUILD_VECTOR. That would mean moving the VMOVimm nodes into tablegen. It would involve a lot a changes, but feels like a sensible direction to me in the long run.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
   def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
             (SHLLv4i32 V128:$Rn)>;
 }
 
 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
 
+// trunc(umin(X, 255)) -> UQXTRN v8i8
+def : Pat<(v8i8 (trunc (umin (v8i16 V128:$Vn),
+                             (v8i16 (AArch64NvCast (v2i64 (AArch64movi_edit (i32 85)))))))),
+          (UQXTNv8i8 V128:$Vn)>;
+// trunc(umin(X, 65535)) -> UQXTRN v4i16
+def : Pat<(v4i16 (trunc (umin (v4i32 V128:$Vn),
+                              (v4i32 (AArch64NvCast (v2i64 (AArch64movi_edit (i32 51)))))))),
+          (UQXTNv4i16 V128:$Vn)>;
+// trunc(smin(smax(X, -32768), 32767)) -> SQXTRN
+//  with reversed min/max
+def : Pat<(v8i8 (trunc (smin (smax (v8i16 V128:$Vn),
+                                   (v8i16 (AArch64mvni_shift (i32 127), (i32 0)))),
+                             (v8i16 (AArch64movi_shift (i32 127), (i32 0)))))),
+          (SQXTNv8i8 V128:$Vn)>;
+def : Pat<(v8i8 (trunc (smax (smin (v8i16 V128:$Vn),
+                                   (v8i16 (AArch64movi_shift (i32 127), (i32 0)))),
+                             (v8i16 (AArch64mvni_shift (i32 127), (i32 0)))))),
+          (SQXTNv8i8 V128:$Vn)>;
+// trunc(smin(smax(X, -128), 128)) -> SQXTRN
+//  with reversed min/max
+def : Pat<(v4i16 (trunc (smin (smax (v4i32 V128:$Vn),
+                                    (v4i32 (AArch64mvni_msl (i32 127), (i32 264)))),
+                              (v4i32 (AArch64movi_msl (i32 127), (i32 264)))))),
+          (SQXTNv4i16 V128:$Vn)>;
+def : Pat<(v4i16 (trunc (smax (smin (v4i32 V128:$Vn),
+                                    (v4i32 (AArch64movi_msl (i32 127), (i32 264)))),
+                              (v4i32 (AArch64mvni_msl (i32 127), (i32 264)))))),
+          (SQXTNv4i16 V128:$Vn)>;
+
 //===----------------------------------------------------------------------===//
 // Advanced SIMD three vector instructions.
 //===----------------------------------------------------------------------===//
 
 defm ADD     : SIMDThreeSameVector<0, 0b10000, "add", add>;
 defm ADDP    : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
 defm CMEQ    : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
 defm CMGE    : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;

llvm/test/CodeGen/AArch64/qmovn.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s
 
 define <4 x i16> @vqmovni32_smaxmin(<4 x i32> %s0) {
 ; CHECK-LABEL: vqmovni32_smaxmin:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v1.4s, #127, msl #8
-; CHECK-NEXT:    smin v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    mvni v1.4s, #127, msl #8
-; CHECK-NEXT:    smax v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    xtn v0.4h, v0.4s
+; CHECK-NEXT:    sqxtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
 entry:
   %c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767>
   %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
   %c2 = icmp sgt <4 x i32> %s1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
   %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
   %t = trunc <4 x i32> %s2 to <4 x i16>
   ret <4 x i16> %t
 }
 
 define <4 x i16> @vqmovni32_sminmax(<4 x i32> %s0) {
 ; CHECK-LABEL: vqmovni32_sminmax:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mvni v1.4s, #127, msl #8
-; CHECK-NEXT:    smax v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    movi v1.4s, #127, msl #8
-; CHECK-NEXT:    smin v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    xtn v0.4h, v0.4s
+; CHECK-NEXT:    sqxtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
 entry:
   %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
   %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
   %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>
   %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
   %t = trunc <4 x i32> %s2 to <4 x i16>
   ret <4 x i16> %t
 }
 
 define <4 x i16> @vqmovni32_umaxmin(<4 x i32> %s0) {
 ; CHECK-LABEL: vqmovni32_umaxmin:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
-; CHECK-NEXT:    umin v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    xtn v0.4h, v0.4s
+; CHECK-NEXT:    uqxtn v0.4h, v0.4s
 ; CHECK-NEXT:    ret
 entry:
   %c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
   %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
   %t = trunc <4 x i32> %s1 to <4 x i16>
   ret <4 x i16> %t
 }
 
 define <8 x i8> @vqmovni16_smaxmin(<8 x i16> %s0) {
 ; CHECK-LABEL: vqmovni16_smaxmin:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v1.8h, #127
-; CHECK-NEXT:    smin v0.8h, v0.8h, v1.8h
-; CHECK-NEXT:    mvni v1.8h, #127
-; CHECK-NEXT:    smax v0.8h, v0.8h, v1.8h
-; CHECK-NEXT:    xtn v0.8b, v0.8h
+; CHECK-NEXT:    sqxtn v0.8b, v0.8h
 ; CHECK-NEXT:    ret
 entry:
   %c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
   %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
   %c2 = icmp sgt <8 x i16> %s1, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
   %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
   %t = trunc <8 x i16> %s2 to <8 x i8>
   ret <8 x i8> %t
 }
 
 define <8 x i8> @vqmovni16_sminmax(<8 x i16> %s0) {
 ; CHECK-LABEL: vqmovni16_sminmax:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mvni v1.8h, #127
-; CHECK-NEXT:    smax v0.8h, v0.8h, v1.8h
-; CHECK-NEXT:    movi v1.8h, #127
-; CHECK-NEXT:    smin v0.8h, v0.8h, v1.8h
-; CHECK-NEXT:    xtn v0.8b, v0.8h
+; CHECK-NEXT:    sqxtn v0.8b, v0.8h
 ; CHECK-NEXT:    ret
 entry:
   %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
   %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
   %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
   %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
   %t = trunc <8 x i16> %s2 to <8 x i8>
   ret <8 x i8> %t
 }
 
 define <8 x i8> @vqmovni16_umaxmin(<8 x i16> %s0) {
 ; CHECK-LABEL: vqmovni16_umaxmin:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v1.2d, #0xff00ff00ff00ff
-; CHECK-NEXT:    umin v0.8h, v0.8h, v1.8h
-; CHECK-NEXT:    xtn v0.8b, v0.8h
+; CHECK-NEXT:    uqxtn v0.8b, v0.8h
 ; CHECK-NEXT:    ret
 entry:
   %c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
   %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
   %t = trunc <8 x i16> %s1 to <8 x i8>
   ret <8 x i8> %t
 }