[RISCV] Add the DebugLoc parameter to getVLENFactoredAmount().

[HsiangKai]

Summary

The MachineBasicBlock::iterator is continuously changing during
generating the frame handling instructions. We should use the DebugLoc
from the caller, instead of getting it from the changing iterator.

[kito-cheng]

Maybe you could pre-commit the test case to easier demonstrate the change of this patch?

[HsiangKai]

In D102386#2756225, @kito-cheng wrote:

Maybe you could pre-commit the test case to easier demonstrate the change of this patch?

The test case will crash without this patch. The point is all the prologue instructions located in a basic block without other instructions at the end. As generating these prologue instructions, the iterator will be updated to the boundary of the basic block and it is invalid to use the iterator to access DebugLoc.

[frasercrmck]

LGTM but if this (also) fixes a crash I think the description could be updated to reflect that. I inferred from the description that this was just about improving the debug information.

[HsiangKai]

In D102386#2756330, @frasercrmck wrote:

LGTM but if this (also) fixes a crash I think the description could be updated to reflect that. I inferred from the description that this was just about improving the debug information.

It makes sense. I will do it. Thanks.

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
   Register SPReg = getSPReg(STI);
   unsigned Opc = RISCV::ADD;
   if (Amount < 0) {
     Amount = -Amount;
     Opc = RISCV::SUB;
   }
 
   // 1. Multiply the number of v-slots to the length of registers
-  Register FactorRegister = TII->getVLENFactoredAmount(MF, MBB, MBBI, Amount);
+  Register FactorRegister =
+      TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, Amount);
   // 2. SP = SP - RVV stack size
   BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
       .addReg(SPReg)
       .addReg(FactorRegister, RegState::Kill);
 }
 
 void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {

llvm/lib/Target/RISCV/RISCVInstrInfo.h

public:
   bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
                              unsigned &SrcOpIdx2) const override;
   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
                                        unsigned OpIdx1,
                                        unsigned OpIdx2) const override;
 
   Register getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator II,
-                                 int64_t Amount) const;
+                                 const DebugLoc &DL, int64_t Amount) const;
 
   Optional<std::pair<unsigned, unsigned>>
   isRVVSpillForZvlsseg(unsigned Opcode) const;
 
 protected:
   const RISCVSubtarget &STI;
 };
 

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 #undef CASE_VFMA_CHANGE_OPCODE_COMMON
 #undef CASE_VFMA_SPLATS
 #undef CASE_VFMA_OPCODE_LMULS
 #undef CASE_VFMA_OPCODE_COMMON
 
 Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
                                                MachineBasicBlock &MBB,
                                                MachineBasicBlock::iterator II,
+                                               const DebugLoc &DL,
                                                int64_t Amount) const {
   assert(Amount > 0 && "There is no need to get VLEN scaled value.");
   assert(Amount % 8 == 0 &&
          "Reserve the stack by the multiple of one vector size.");
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
-  DebugLoc DL = II->getDebugLoc();
   int64_t NumOfVReg = Amount / 8;
 
   Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
   BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
   assert(isInt<12>(NumOfVReg) &&
          "Expect the number of vector registers within 12-bits.");
   if (isPowerOf2_32(NumOfVReg)) {
     uint32_t ShiftAmount = Log2_32(NumOfVReg);

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   if (Offset.getScalable()) {
     int64_t ScalableValue = Offset.getScalable();
     if (ScalableValue < 0) {
       ScalableValue = -ScalableValue;
       ScalableAdjOpc = RISCV::SUB;
     }
     // 1. Get vlenb && multiply vlen with the number of vector registers.
     ScalableFactorRegister =
-        TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);
+        TII->getVLENFactoredAmount(MF, MBB, II, DL, ScalableValue);
   }
 
   if (!isInt<12>(Offset.getFixed())) {
     // The offset won't fit in an immediate, so use a scratch register instead
     // Modify Offset and FrameReg appropriately
     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
     if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {

llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -mattr=+experimental-v -o - %s \
+# RUN:   -stop-after=prologepilog | FileCheck %s
+
+--- |
+  define void @foo() !dbg !0 {
+  entry:
+    %va = alloca <vscale x 2 x i32>, align 4, !dbg !1
+    br label %end
+  end:
+    ret void, !dbg !2
+  }
+
+  !0 = distinct !DISubprogram(name: "foo", line: 3, scopeLine: 3)
+  !1 = !DILocation(line: 4, column: 14, scope: !0)
+  !2 = !DILocation(line: 5, column: 3, scope: !0)
+
+...
+---
+name: foo
+tracksRegLiveness: true
+stack:
+  - { id: 0, stack-id: scalable-vector, offset: 0, size: 8, alignment: 8 }
+body: |
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   $x2 = frame-setup ADDI $x2, -16
+  ; CHECK:   CFI_INSTRUCTION def_cfa_offset 16
+  ; CHECK:   $x10 = PseudoReadVLENB
+  ; CHECK:   $x10 = SLLI killed $x10, 1
+  ; CHECK:   $x2 = SUB $x2, killed $x10
+  ; CHECK: bb.1:
+  ; CHECK:   $x10 = PseudoReadVLENB
+  ; CHECK:   $x10 = SLLI killed $x10, 1
+  ; CHECK:   $x2 = ADD $x2, killed $x10
+  ; CHECK:   $x2 = frame-destroy ADDI $x2, 16
+  ; CHECK:   PseudoRET
+  bb.0:
+  bb.1:
+    PseudoRET