[ValueTypes] Rename MVT::getVectorNumElements() to MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements()

[craig.topper]

Summary

getVectorNumElements() returns a value for scalable vectors
without any warning so it is effectively getVectorMinNumElements().
By renaming it and making getVectorNumElements() forward to
it, we can insert a check for scalable vectors into getVectorNumElements()
similar to EVT. I didn't do that in this patch because there are still more
fixes needed, but I was able to temporarily do it and passed the RISCV
lit tests with these changes.

The changes to isPow2VectorType and getPow2VectorType are copied from EVT.

The change to TypeInfer::EnforceSameNumElts reduces the size of AArch64's isel table.
We're now considering SameNumElts to require the scalable property to match which
removes some unneeded type checks.

This was motivated by the bug I fixed yesterday in 80b9510806cf11c57f2dd87191d3989fc45defa8

[sdesmalen]

Thanks, this looks like sensible changes to me! Do you have a ballpark figure of how many tests currently fail when adding a check to getVectorNumElements? The fact that the RISCV lit-tests already pass sounds promising.
I've taken the liberty to accept the patch, but maybe just wait a day or two to give other reviewers a chance to take a look as well.

[craig.topper]

In D102262#2752042, @sdesmalen wrote:

Thanks, this looks like sensible changes to me! Do you have a ballpark figure of how many tests currently fail when adding a check to getVectorNumElements? The fact that the RISCV lit-tests already pass sounds promising.
I've taken the liberty to accept the patch, but maybe just wait a day or two to give other reviewers a chance to take a look as well.

There are failures coming from computeRegisterProperties on multiple targets that cause a very high test fallout.

[craig.topper]

Fix a few more issues in some target's getPreferredAction.

Majority of remaining issues are in GlobalISel on AArch64
due to LLT not handling scalable vectors. Failing cases are
LLT is constructed from getMinimalRegClassLLT.

There are two additional failures
test/Analysis/CostModel/AArch64/sve-intrinsics.ll
Transforms/LoopVectorize/AArch64/first-order-recurrence.ll
Both may be from getExtractSubvectorOverhead in TTI

[frasercrmck]

LGTM, with some optional nits.

llvm/lib/Target/X86/X86ISelLowering.cpp

2104

You could probably also express this (and elsewhere) with !VT.getVectorElementCount().isScalar() as is done in some other places, but I'm undecided which is better

llvm/utils/TableGen/CodeGenDAGPatterns.cpp

699–702

I don't know if there's a way of making this a bit cleaner without impacting TableGen performance. Would ElementCount with getNull for scalars work? T.isVector() ? T.getVectorElementCount() : ElementCount::getNull()

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

2104

Wouldn't !VT.getVectorElementCount().isScalar() be equivalent to (isScalableVector || VT.getVectorNumElements() != 1). I don't think that's what we want here.

[frasercrmck]

llvm/lib/Target/X86/X86ISelLowering.cpp

2104

Oh yes I was thinking of a case I was dealing with where I *do* want to allow widening for the vscale x 1 scalable vectors (D102073). I didn't notice that you wanted something different, sorry.

With that in mind -- and maybe it's academic because X86, PPC, Hexagon etc won't encounter scalable types -- perhaps !isScalar is more consistent between the scalable types?

llvm/include/llvm/Support/MachineValueType.h

MVT getHalfNumVectorElementsVT() const {
       MVT EltVT = getVectorElementType();
       auto EltCnt = getVectorElementCount();
       assert(EltCnt.isKnownEven() && "Splitting vector, but not in half!");
       return getVectorVT(EltVT, EltCnt.divideCoefficientBy(2));
     }
 
     /// Returns true if the given vector is a power of 2.
     bool isPow2VectorType() const {
-      unsigned NElts = getVectorNumElements();
+      unsigned NElts = getVectorMinNumElements();
       return !(NElts & (NElts - 1));
     }
 
     /// Widens the length of the given vector MVT up to the nearest power of 2
     /// and returns that type.
     MVT getPow2VectorType() const {
       if (isPow2VectorType())
         return *this;
 
-      unsigned NElts = getVectorNumElements();
-      unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
-      return MVT::getVectorVT(getVectorElementType(), Pow2NElts);
+      ElementCount NElts = getVectorElementCount();
+      unsigned NewMinCount = 1 << Log2_32_Ceil(NElts.getKnownMinValue());
+      NElts = ElementCount::get(NewMinCount, NElts.isScalable());
+      return MVT::getVectorVT(getVectorElementType(), NElts);
     }
 
     /// If this is a vector, return the element type, otherwise return this.
     MVT getScalarType() const {
       return isVector() ? getVectorElementType() : *this;
     }
 
     MVT getVectorElementType() const {
MVT getVectorElementType() const {
       case v256f64:
       case nxv1f64:
       case nxv2f64:
       case nxv4f64:
       case nxv8f64: return f64;
       }
     }
 
-    unsigned getVectorNumElements() const {
+    /// Given a vector type, return the minimum number of elements it contains.
+    unsigned getVectorMinNumElements() const {
       switch (SimpleTy) {
       default:
         llvm_unreachable("Not a vector MVT!");
       case v2048i32:
       case v2048f32: return 2048;
       case v1024i1:
       case v1024i32:
       case v1024f32: return 1024;
unsigned getVectorMinNumElements() const {
       case nxv1f16:
       case nxv1bf16:
       case nxv1f32:
       case nxv1f64: return 1;
       }
     }
 
     ElementCount getVectorElementCount() const {
-      return ElementCount::get(getVectorNumElements(), isScalableVector());
+      return ElementCount::get(getVectorMinNumElements(), isScalableVector());
     }
 
-    /// Given a vector type, return the minimum number of elements it contains.
-    unsigned getVectorMinNumElements() const {
-      return getVectorElementCount().getKnownMinValue();
+    unsigned getVectorNumElements() const {
+      // TODO: Check that this isn't a scalable vector.
+      return getVectorMinNumElements();
     }
 
     /// Returns the size of the specified MVT in bits.
     ///
     /// If the value type is a scalable vector type, the scalable property will
     /// be set and the runtime size will be a positive integer multiple of the
     /// base size.
     TypeSize getSizeInBits() const {

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
   const MemSDNode *MemNode = cast<MemSDNode>(N);
 
   return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
 }
 
 TargetLoweringBase::LegalizeTypeAction
 SITargetLowering::getPreferredVectorAction(MVT VT) const {
-  int NumElts = VT.getVectorNumElements();
-  if (NumElts != 1 && VT.getScalarType().bitsLE(MVT::i16))
+  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
+      VT.getScalarType().bitsLE(MVT::i16))
     return VT.isPow2VectorType() ? TypeSplitVector : TypeWidenVector;
   return TargetLoweringBase::getPreferredVectorAction(VT);
 }
 
 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                          Type *Ty) const {
   // FIXME: Could be smarter if called for vector constants.
   return true;

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

 
 bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef<int> Mask,
                                                EVT VT) const {
   return true;
 }
 
 TargetLoweringBase::LegalizeTypeAction
 HexagonTargetLowering::getPreferredVectorAction(MVT VT) const {
-  unsigned VecLen = VT.getVectorNumElements();
+  unsigned VecLen = VT.getVectorMinNumElements();
   MVT ElemTy = VT.getVectorElementType();
 
   if (VecLen == 1 || VT.isScalableVector())
     return TargetLoweringBase::TypeScalarizeVector;
 
   if (Subtarget.useHVXOps()) {
     unsigned Action = getPreferredHvxVectorAction(VT);
     if (Action != ~0u)

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case NVPTXISD::Suld3DV4I16Zero:       return "NVPTXISD::Suld3DV4I16Zero";
   case NVPTXISD::Suld3DV4I32Zero:       return "NVPTXISD::Suld3DV4I32Zero";
   }
   return nullptr;
 }
 
 TargetLoweringBase::LegalizeTypeAction
 NVPTXTargetLowering::getPreferredVectorAction(MVT VT) const {
-  if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
+  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
+      VT.getScalarType() == MVT::i1)
     return TypeSplitVector;
   if (VT == MVT::v2f16)
     return TypeLegal;
   return TargetLoweringBase::getPreferredVectorAction(VT);
 }
 
 SDValue NVPTXTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
                                              int Enabled, int &ExtraSteps,

llvm/lib/Target/PowerPC/PPCISelLowering.h

public:
     /// than code we generate if we widen the type for applicable vector types.
     /// The issue with promoting is that the vector is scalaraized, individual
     /// elements promoted and then the vector is rebuilt. So say we load a pair
     /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
     /// loads, moves back into VSR's (or memory ops if we don't have moves) and
     /// then the VPERM for the shuffle. All in all a very slow sequence.
     TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
       const override {
-      if (VT.getVectorNumElements() != 1 && VT.getScalarSizeInBits() % 8 == 0)
+      if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
+          VT.getScalarSizeInBits() % 8 == 0)
         return TypeWidenVector;
       return TargetLoweringBase::getPreferredVectorAction(VT);
     }
 
     bool useSoftFloat() const override;
 
     bool hasSPE() const;
 

llvm/lib/Target/X86/X86ISelLowering.cpp

 }
 
 TargetLoweringBase::LegalizeTypeAction
 X86TargetLowering::getPreferredVectorAction(MVT VT) const {
   if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
       !Subtarget.hasBWI())
     return TypeSplitVector;
 
-  if (VT.getVectorNumElements() != 1 &&
+  if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
       VT.getVectorElementType() != MVT::i1)
     return TypeWidenVector;
 
   return TargetLoweringBase::getPreferredVectorAction(VT);
 }
 
 static std::pair<MVT, unsigned>
 handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,

llvm/utils/TableGen/CodeGenDAGPatterns.cpp

if (!B.isVector() || !P.isVector())
       return false;
     // Logically a <4 x i32> is a valid subvector of <n x 4 x i32>
     // but until there are obvious use-cases for this, keep the
     // types separate.
     if (B.isScalableVector() != P.isScalableVector())
       return false;
     if (B.getVectorElementType() != P.getVectorElementType())
       return false;
-    return B.getVectorNumElements() < P.getVectorNumElements();
+    return B.getVectorMinNumElements() < P.getVectorMinNumElements();
   };
 
   /// Return true if S has no element (vector type) that T is a sub-vector of,
   /// i.e. has the same element type as T and more elements.
   auto NoSubV = [&IsSubVec](const TypeSetByHwMode::SetType &S, MVT T) -> bool {
     for (auto I : S)
       if (IsSubVec(T, I))
         return false;
bool TypeInfer::EnforceSameNumElts(TypeSetByHwMode &V, TypeSetByHwMode &W) {
   if (V.empty())
     Changed |= EnforceAny(V);
   if (W.empty())
     Changed |= EnforceAny(W);
 
   // An actual vector type cannot have 0 elements, so we can treat scalars
   // as zero-length vectors. This way both vectors and scalars can be
   // processed identically.
-  auto NoLength = [](const SmallSet<unsigned,2> &Lengths, MVT T) -> bool {
-    return !Lengths.count(T.isVector() ? T.getVectorNumElements() : 0);
+  auto NoLength = [](const SmallDenseSet<ElementCount> &Lengths,
+                     MVT T) -> bool {
+    return !Lengths.count(T.isVector() ? T.getVectorElementCount()
+                                       : ElementCount::getNull());
   };
 
   SmallVector<unsigned, 4> Modes;
   union_modes(V, W, Modes);
   for (unsigned M : Modes) {
     TypeSetByHwMode::SetType &VS = V.get(M);
     TypeSetByHwMode::SetType &WS = W.get(M);
 
-    SmallSet<unsigned,2> VN, WN;
+    SmallDenseSet<ElementCount> VN, WN;
     for (MVT T : VS)
-      VN.insert(T.isVector() ? T.getVectorNumElements() : 0);
+      VN.insert(T.isVector() ? T.getVectorElementCount()
+                             : ElementCount::getNull());
     for (MVT T : WS)
-      WN.insert(T.isVector() ? T.getVectorNumElements() : 0);
+      WN.insert(T.isVector() ? T.getVectorElementCount()
+                             : ElementCount::getNull());
 
     Changed |= berase_if(VS, std::bind(NoLength, WN, std::placeholders::_1));
     Changed |= berase_if(WS, std::bind(NoLength, VN, std::placeholders::_1));
   }
   return Changed;
 }
 
 namespace {

llvm/utils/TableGen/IntrinsicEmitter.cpp

return EncodeFixedType(R->getValueAsDef("ElTy"), ArgCodes, NextArgCode, Sig,
                            Mapping);
   }
   }
 
   if (MVT(VT).isVector()) {
     MVT VVT = VT;
     if (VVT.isScalableVector())
       Sig.push_back(IIT_SCALABLE_VEC);
-    switch (VVT.getVectorNumElements()) {
+    switch (VVT.getVectorMinNumElements()) {
     default: PrintFatalError("unhandled vector type width in intrinsic!");
     case 1: Sig.push_back(IIT_V1); break;
     case 2: Sig.push_back(IIT_V2); break;
     case 4: Sig.push_back(IIT_V4); break;
     case 8: Sig.push_back(IIT_V8); break;
     case 16: Sig.push_back(IIT_V16); break;
     case 32: Sig.push_back(IIT_V32); break;
     case 64: Sig.push_back(IIT_V64); break;