[ELF] Implement X86_64::getImplicitAddend()

[arichardson]

Summary

This allows checking dynamic relocation addends for -z rel and
--apply-dynamic-relocs output.

Depends on D101450

[MaskRay]

Do you have a branch where I can apply the patch series at once?

[MaskRay]

LGTM.

[arichardson]

In D101451#2730184, @MaskRay wrote:

Do you have a branch where I can apply the patch series at once?

Apologies for the late reply - I had to switch to other tasks and was on holiday after that. The patches are currently mixed up with lots of unrelated ones. I'll try to cleanup the patch series and push it to my github fork early next week.

[arichardson]

rebase

[MaskRay]

Thanks!

lld/ELF/Arch/X86_64.cpp

public:
   RelType getDynRel(RelType type) const override;
   void writeGotPltHeader(uint8_t *buf) const override;
   void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
   void writePltHeader(uint8_t *buf) const override;
   void writePlt(uint8_t *buf, const Symbol &sym,
                 uint64_t pltEntryAddr) const override;
   void relocate(uint8_t *loc, const Relocation &rel,
                 uint64_t val) const override;
+  int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
   void applyJumpInstrMod(uint8_t *loc, JumpModType type,
                          unsigned size) const override;
 
   RelExpr adjustGotPcExpr(RelType type, int64_t addend,
                           const uint8_t *loc) const override;
   void relaxGot(uint8_t *loc, const Relocation &rel,
                 uint64_t val) const override;
   void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
case J_JAE_32:
     } else
       *loc = 0x73;
     break;
   case J_UNKNOWN:
     llvm_unreachable("Unknown Jump Relocation");
   }
 }
 
+int64_t X86_64::getImplicitAddend(const uint8_t *buf, RelType type) const {
+  switch (type) {
+  case R_X86_64_8:
+  case R_X86_64_PC8:
+    return SignExtend64<8>(*buf);
+  case R_X86_64_16:
+  case R_X86_64_PC16:
+    return SignExtend64<16>(read16le(buf));
+  case R_X86_64_32:
+  case R_X86_64_32S:
+  case R_X86_64_TPOFF32:
+  case R_X86_64_GOT32:
+  case R_X86_64_GOTPC32:
+  case R_X86_64_GOTPC32_TLSDESC:
+  case R_X86_64_GOTPCREL:
+  case R_X86_64_GOTPCRELX:
+  case R_X86_64_REX_GOTPCRELX:
+  case R_X86_64_PC32:
+  case R_X86_64_GOTTPOFF:
+  case R_X86_64_PLT32:
+  case R_X86_64_TLSGD:
+  case R_X86_64_TLSLD:
+  case R_X86_64_DTPOFF32:
+  case R_X86_64_SIZE32:
+    return SignExtend64<32>(read32le(buf));
+  case R_X86_64_64:
+  case R_X86_64_TPOFF64:
+  case R_X86_64_DTPOFF64:
+  case R_X86_64_DTPMOD64:
+  case R_X86_64_PC64:
+  case R_X86_64_SIZE64:
+  case R_X86_64_GLOB_DAT:
+  case R_X86_64_GOT64:
+  case R_X86_64_GOTOFF64:
+  case R_X86_64_GOTPC64:
+  case R_X86_64_IRELATIVE:
+  case R_X86_64_RELATIVE:
+    return read64le(buf);
+  case R_X86_64_JUMP_SLOT:
+  case R_X86_64_NONE:
+    // These relocations are defined as not having an implicit addend.
+    return 0;
+  default:
+    internalLinkerError(getErrorLocation(buf),
+                        "cannot read addend for relocation " + toString(type));
+    return 0;
+  }
+}
+
 void X86_64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
   switch (rel.type) {
   case R_X86_64_8:
     checkIntUInt(loc, val, 8, rel);
     *loc = val;
     break;
   case R_X86_64_PC8:
     checkInt(loc, val, 8, rel);

lld/ELF/Driver.cpp

static void setConfigs(opt::InputArgList &args) {
   config->writeAddends = args.hasFlag(OPT_apply_dynamic_relocs,
                                       OPT_no_apply_dynamic_relocs, false) ||
                          !config->isRela;
   // Validation of dynamic relocation addends is on by default for assertions
   // builds (for supported targets) and disabled otherwise. Ideally we would
   // enable the debug checks for all targets, but currently not all targets
   // have support for reading Elf_Rel addends, so we only enable for a subset.
 #ifndef NDEBUG
-  bool checkDynamicRelocsDefault = m == EM_ARM || m == EM_386 || m == EM_MIPS;
+  bool checkDynamicRelocsDefault =
+      m == EM_ARM || m == EM_386 || m == EM_MIPS || m == EM_X86_64;
 #else
   bool checkDynamicRelocsDefault = false;
 #endif
   config->checkDynamicRelocs =
       args.hasFlag(OPT_check_dynamic_relocations,
                    OPT_no_check_dynamic_relocations, checkDynamicRelocsDefault);
   config->tocOptimize =
       args.hasFlag(OPT_toc_optimize, OPT_no_toc_optimize, m == EM_PPC64);

lld/test/ELF/invalid/broken-relaxation-x64.test

 # REQUIRES: x86
-# Needs https://reviews.llvm.org/D101451 to read the implicit addends.
-# XFAIL: *
 
 # RUN: yaml2obj %s -o %t.o
 # RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck --check-prefix=ERR %s
 # ERR: R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only
 # ERR: R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only
 
 ## YAML below contains 2 relocations of type R_X86_64_GOTTPOFF, and a .text
 ## with fake content filled by 0xFF. That means instructions for relaxation are

lld/test/ELF/reloc-sec-before-relocated.test

 ## If the section header index of a SHT_REL[A] section is smaller than the
 ## section header index of the relocated section, we should handle it properly.
 ## Normally it is not what compilers would emit, but some custom tools might
 ## want to use this feature, which is not restricted by ELF gABI.
 ## GNU ld supports this as well.
 
-# Needs https://reviews.llvm.org/D101451 to read the implicit addends.
-# XFAIL: *
-
 # RUN: yaml2obj %s -DTYPE=SHT_RELA -o %t1.o
 # RUN: ld.lld -shared %t1.o -o %t1
 # RUN: llvm-readelf --relocs %t1 | FileCheck %s
 
 # RUN: yaml2obj %s -DTYPE=SHT_REL -o %t2.o
 # RUN: ld.lld -shared %t2.o -o %t2
 # RUN: llvm-readelf --relocs %t2 | FileCheck %s