[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics

[jrtc27]

Summary

Unlike normal loads these don't have an extension field, but we know
from TargetLowering whether these are sign-extending or zero-extending,
and so can optimise away unnecessary extensions.

This was noticed on RISC-V, where sign extensions in the calling
convention would result in unnecessary explicit extension instructions,
but this also fixes some Mips inefficiencies. PowerPC sees churn in the
tests as all the zero extensions are only for promoting 32-bit to
64-bit, but these zero extensions are still not optimised away as they
should be, likely due to i32 being a legal type.

This also simplifies the WebAssembly code somewhat, which currently
works around the lack of target-independent combines with some ugly
patterns that break once they're optimised away.

[jrtc27]

llvm/test/CodeGen/RISCV/atomic-signext.ll

19

NB: These tests aren't in the tree, this is just showing the diff to my local pre-commit.

[luismarques]

The SelectionDAG changes LGTM.

[RKSimon]

@jrtc27 Please can you pre-commit your local tests and then rebase this patch?

[jrtc27]

Rebased with tests pre-committed

[RKSimon]

LGTM - please can you raise a bug detailing the PPC poor codegen for i32/i64 promotions

[jrtc27]

In D101342#2735912, @RKSimon wrote:

LGTM - please can you raise a bug detailing the PPC poor codegen for i32/i64 promotions

Filed as https://bugs.llvm.org/show_bug.cgi?id=50217. Does this need a review from a WASM person given the changes there?

[RKSimon]

@tlively @sunfish Any final comments on the wasm change?

[tlively]

The Wasm changes LGTM! This is a nice simplification.

[atanasyan]

The MIPS changes LGTM

[jrtc27]

Reverted due to assertion failures during sanitiser builds on the buildbots. Will try and reproduce+debug over the coming days.

[nemanjai]

In D101342#2735929, @jrtc27 wrote:

In D101342#2735912, @RKSimon wrote:

LGTM - please can you raise a bug detailing the PPC poor codegen for i32/i64 promotions

Filed as https://bugs.llvm.org/show_bug.cgi?id=50217. Does this need a review from a WASM person given the changes there?

Thanks for opening the bug. This is a fairly long standing issue in the PPC back end and isn't specific to atomics. We do plan to address it when we find time.

[stefanp]

@jrtc27
It looks like this patch has broken one of out Big Endian PowerPC buildbots:
https://lab.llvm.org/buildbot/#/builders/93/builds/3021

We are currently investigating but if we cannot find the solution quickly we will pull the patch and continue investigating after that.

[jrtc27]

In D101342#2748417, @stefanp wrote:

@jrtc27
It looks like this patch has broken one of out Big Endian PowerPC buildbots:
https://lab.llvm.org/buildbot/#/builders/93/builds/3021

We are currently investigating but if we cannot find the solution quickly we will pull the patch and continue investigating after that.

The only thing I can think of is if any atomics are lowered with sign-extending rather than zero-extending instructions, thereby violating what getExtendForAtomicOps claims?

[stefanp]

Hi @jrtc27

I apologize but we have not been able to get to the bottom of this quickly. As a result we have pulled the change with:

commit 8d37411e48202b490c62ee3548df4b90f5974e12 (HEAD -> main, origin/main, origin/HEAD)
Author: Stefan Pintilie <[e-mail]>
Date:   Wed May 12 09:42:09 2021 -0500

    Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"
    
    This reverts commit 6c80361b8474535852afb2f7201370fb5f410091.
    Breaks PowerPC Big Endian buildbots.

I will keep you up to date as we have more information.
I have reopened this review.

[jrtc27]

In D101342#2754160, @stefanp wrote:

Hi @jrtc27

I apologize but we have not been able to get to the bottom of this quickly. As a result we have pulled the change with:

commit 8d37411e48202b490c62ee3548df4b90f5974e12 (HEAD -> main, origin/main, origin/HEAD)
Author: Stefan Pintilie <[e-mail]>
Date:   Wed May 12 09:42:09 2021 -0500

    Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"
    
    This reverts commit 6c80361b8474535852afb2f7201370fb5f410091.
    Breaks PowerPC Big Endian buildbots.

I will keep you up to date as we have more information.
I have reopened this review.

I have access to big-endian PowerPC hardware. Is the reproducer as simple as running the compiler-rt test suite?

[stefanp]

In D101342#2754174, @jrtc27 wrote:

In D101342#2754160, @stefanp wrote:

Hi @jrtc27

I apologize but we have not been able to get to the bottom of this quickly. As a result we have pulled the change with:

commit 8d37411e48202b490c62ee3548df4b90f5974e12 (HEAD -> main, origin/main, origin/HEAD)
Author: Stefan Pintilie <[e-mail]>
Date:   Wed May 12 09:42:09 2021 -0500

    Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"
    
    This reverts commit 6c80361b8474535852afb2f7201370fb5f410091.
    Breaks PowerPC Big Endian buildbots.

I will keep you up to date as we have more information.
I have reopened this review.

I have access to big-endian PowerPC hardware. Is the reproducer as simple as running the compiler-rt test suite?

To reproduce the issue I use a stage2 bootstrap build and then run ninja check-asan. Check test will not finish.

To add to this more info.
I can reproduce the issue locally with this command:

Asan-powerpc64-calls-Test --gtest_filter=AddressSanitizer.OOBRightTest

I will get:

[==========] Running 1 test from 1 test case.
[----------] Global test environment set-up.
[----------] 1 test from AddressSanitizer
[ RUN      ] AddressSanitizer.OOBRightTest

and then nothing... the test won't finish the run.

I have narrowed it down to the compilation of libclang_rt.asan-powerpc64.a if I link in a different version of that library when I link Asan-powerpc64-calls-Test then everything works as expected.

[stefanp]

It seems that this patch has exposed an issue in the PowerPC backend where the partword atomics were not actually guaranteed to be zero extended.
I've added a patch:
https://reviews.llvm.org/D102819
to fix the issue.

[stefanp]

The fix has been committed.
You may now try to recommit this patch.

Thank you for your patience!

[jrtc27]

In D101342#2771738, @stefanp wrote:

The fix has been committed.
You may now try to recommit this patch.

Thank you for your patience!

Thanks; have you been able to verify the tests now pass on PPC64, or is that a "see what happens with the buildbots"? And will I need to update any of the tests you added when re-committing?

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (Known.isUnknown())
       break;
     Known2 = computeKnownBits(Op.getOperand(2), DemandedElts, Depth+1);
 
     // Only known if known in both the LHS and RHS.
     Known = KnownBits::commonBits(Known, Known2);
     break;
   case ISD::SMULO:
   case ISD::UMULO:
-  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
     if (Op.getResNo() != 1)
       break;
     // The boolean result conforms to getBooleanContents.
     // If we know the result of a setcc has the top bits zero, use this info.
     // We know that we have an integer-based boolean since these operations
     // are only available for integer.
     if (TLI->getBooleanContents(Op.getValueType().isVector(), false) ==
             TargetLowering::ZeroOrOneBooleanContent &&
case ISD::SMAX: {
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
     if (IsMax)
       Known = KnownBits::smax(Known, Known2);
     else
       Known = KnownBits::smin(Known, Known2);
     break;
   }
+  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
+    if (Op.getResNo() == 1) {
+      // The boolean result conforms to getBooleanContents.
+      // If we know the result of a setcc has the top bits zero, use this info.
+      // We know that we have an integer-based boolean since these operations
+      // are only available for integer.
+      if (TLI->getBooleanContents(Op.getValueType().isVector(), false) ==
+              TargetLowering::ZeroOrOneBooleanContent &&
+          BitWidth > 1)
+        Known.Zero.setBitsFrom(1);
+      break;
+    }
+    LLVM_FALLTHROUGH;
+  case ISD::ATOMIC_CMP_SWAP:
+  case ISD::ATOMIC_SWAP:
+  case ISD::ATOMIC_LOAD_ADD:
+  case ISD::ATOMIC_LOAD_SUB:
+  case ISD::ATOMIC_LOAD_AND:
+  case ISD::ATOMIC_LOAD_CLR:
+  case ISD::ATOMIC_LOAD_OR:
+  case ISD::ATOMIC_LOAD_XOR:
+  case ISD::ATOMIC_LOAD_NAND:
+  case ISD::ATOMIC_LOAD_MIN:
+  case ISD::ATOMIC_LOAD_MAX:
+  case ISD::ATOMIC_LOAD_UMIN:
+  case ISD::ATOMIC_LOAD_UMAX:
+  case ISD::ATOMIC_LOAD: {
+    unsigned MemBits =
+        cast<AtomicSDNode>(Op)->getMemoryVT().getScalarSizeInBits();
+    // If we are looking at the loaded value.
+    if (Op.getResNo() == 0) {
+      if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND)
+        Known.Zero.setBitsFrom(MemBits);
+    }
+    break;
+  }
   case ISD::FrameIndex:
   case ISD::TargetFrameIndex:
     TLI->computeKnownBitsForFrameIndex(cast<FrameIndexSDNode>(Op)->getIndex(),
                                        Known, getMachineFunction());
     break;
 
   default:
     if (Opcode < ISD::BUILTIN_OP_END)
case ISD::INSERT_SUBVECTOR: {
     }
     if (!!DemandedSrcElts) {
       Tmp2 = ComputeNumSignBits(Src, DemandedSrcElts, Depth + 1);
       Tmp = std::min(Tmp, Tmp2);
     }
     assert(Tmp <= VTBits && "Failed to determine minimum sign bits");
     return Tmp;
   }
+  case ISD::ATOMIC_CMP_SWAP:
+  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
+  case ISD::ATOMIC_SWAP:
+  case ISD::ATOMIC_LOAD_ADD:
+  case ISD::ATOMIC_LOAD_SUB:
+  case ISD::ATOMIC_LOAD_AND:
+  case ISD::ATOMIC_LOAD_CLR:
+  case ISD::ATOMIC_LOAD_OR:
+  case ISD::ATOMIC_LOAD_XOR:
+  case ISD::ATOMIC_LOAD_NAND:
+  case ISD::ATOMIC_LOAD_MIN:
+  case ISD::ATOMIC_LOAD_MAX:
+  case ISD::ATOMIC_LOAD_UMIN:
+  case ISD::ATOMIC_LOAD_UMAX:
+  case ISD::ATOMIC_LOAD: {
+    Tmp = cast<AtomicSDNode>(Op)->getMemoryVT().getScalarSizeInBits();
+    // If we are looking at the loaded value.
+    if (Op.getResNo() == 0) {
+      if (Tmp == VTBits)
+        return 1; // early-out
+      if (TLI->getExtendForAtomicOps() == ISD::SIGN_EXTEND)
+        return VTBits - Tmp + 1;
+      if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND)
+        return VTBits - Tmp;
+    }
+    break;
+  }
   }
 
   // If we are looking at the loaded value of the SDNode.
   if (Op.getResNo() == 0) {
     // Handle LOADX separately here. EXTLOAD case will fallthrough.
     if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
       unsigned ExtType = LD->getExtensionType();
       switch (ExtType) {

llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

 defm ATOMIC_LOAD16_U_I64 : AtomicLoad<I64, "i64.atomic.load16_u", 0x15>;
 defm ATOMIC_LOAD32_U_I64 : AtomicLoad<I64, "i64.atomic.load32_u", 0x16>;
 
 // Fragments for extending loads. These are different from regular loads because
 // the SDNodes are derived from AtomicSDNode rather than LoadSDNode and
 // therefore don't have the extension type field. So instead of matching that,
 // we match the patterns that the type legalizer expands them to.
 
-// We directly match zext patterns and select the zext atomic loads.
-// i32 (zext (i8 (atomic_load_8))) gets legalized to
-// i32 (and (i32 (atomic_load_8)), 255)
-// These can be selected to a single zero-extending atomic load instruction.
-def zext_aload_8_32 :
-  PatFrag<(ops node:$addr), (and (i32 (atomic_load_8 node:$addr)), 255)>;
-def zext_aload_16_32 :
-  PatFrag<(ops node:$addr), (and (i32 (atomic_load_16 node:$addr)), 65535)>;
 // Unlike regular loads, extension to i64 is handled differently than i32.
 // i64 (zext (i8 (atomic_load_8))) gets legalized to
 // i64 (and (i64 (anyext (i32 (atomic_load_8)))), 255)
+// Extension to i32 is elided by SelectionDAG as our atomic loads are
+// zero-extending.
 def zext_aload_8_64 :
   PatFrag<(ops node:$addr),
-          (and (i64 (anyext (i32 (atomic_load_8 node:$addr)))), 255)>;
+          (i64 (zext (i32 (atomic_load_8 node:$addr))))>;
 def zext_aload_16_64 :
   PatFrag<(ops node:$addr),
-          (and (i64 (anyext (i32 (atomic_load_16 node:$addr)))), 65535)>;
+          (i64 (zext (i32 (atomic_load_16 node:$addr))))>;
 def zext_aload_32_64 :
   PatFrag<(ops node:$addr),
-          (zext (i32 (atomic_load node:$addr)))>;
+          (i64 (zext (i32 (atomic_load_32 node:$addr))))>;
 
 // We don't have single sext atomic load instructions. So for sext loads, we
 // match bare subword loads (for 32-bit results) and anyext loads (for 64-bit
 // results) and select a zext load; the next instruction will be sext_inreg
 // which is selected by itself.
 def sext_aload_8_64 :
   PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_8 node:$addr)))>;
 def sext_aload_16_64 :
   PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_16 node:$addr)))>;
 
 // Select zero-extending loads with no constant offset.
-defm : LoadPatNoOffset<i32, zext_aload_8_32, "ATOMIC_LOAD8_U_I32">;
-defm : LoadPatNoOffset<i32, zext_aload_16_32, "ATOMIC_LOAD16_U_I32">;
 defm : LoadPatNoOffset<i64, zext_aload_8_64, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatNoOffset<i64, zext_aload_16_64, "ATOMIC_LOAD16_U_I64">;
 defm : LoadPatNoOffset<i64, zext_aload_32_64, "ATOMIC_LOAD32_U_I64">;
 
 // Select sign-extending loads with no constant offset
 defm : LoadPatNoOffset<i32, atomic_load_8, "ATOMIC_LOAD8_U_I32">;
 defm : LoadPatNoOffset<i32, atomic_load_16, "ATOMIC_LOAD16_U_I32">;
 defm : LoadPatNoOffset<i64, sext_aload_8_64, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatNoOffset<i64, sext_aload_16_64, "ATOMIC_LOAD16_U_I64">;
 // 32->64 sext load gets selected as i32.atomic.load, i64.extend_i32_s
 
 // Zero-extending loads with constant offset
-defm : LoadPatImmOff<i32, zext_aload_8_32, regPlusImm, "ATOMIC_LOAD8_U_I32">;
-defm : LoadPatImmOff<i32, zext_aload_16_32, regPlusImm, "ATOMIC_LOAD16_U_I32">;
-defm : LoadPatImmOff<i32, zext_aload_8_32, or_is_add, "ATOMIC_LOAD8_U_I32">;
-defm : LoadPatImmOff<i32, zext_aload_16_32, or_is_add, "ATOMIC_LOAD16_U_I32">;
 defm : LoadPatImmOff<i64, zext_aload_8_64, regPlusImm, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatImmOff<i64, zext_aload_16_64, regPlusImm, "ATOMIC_LOAD16_U_I64">;
 defm : LoadPatImmOff<i64, zext_aload_32_64, regPlusImm, "ATOMIC_LOAD32_U_I64">;
 defm : LoadPatImmOff<i64, zext_aload_8_64, or_is_add, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatImmOff<i64, zext_aload_16_64, or_is_add, "ATOMIC_LOAD16_U_I64">;
 defm : LoadPatImmOff<i64, zext_aload_32_64, or_is_add, "ATOMIC_LOAD32_U_I64">;
 
 // Sign-extending loads with constant offset
 defm : LoadPatImmOff<i32, atomic_load_8, regPlusImm, "ATOMIC_LOAD8_U_I32">;
 defm : LoadPatImmOff<i32, atomic_load_16, regPlusImm, "ATOMIC_LOAD16_U_I32">;
 defm : LoadPatImmOff<i32, atomic_load_8, or_is_add, "ATOMIC_LOAD8_U_I32">;
 defm : LoadPatImmOff<i32, atomic_load_16, or_is_add, "ATOMIC_LOAD16_U_I32">;
 defm : LoadPatImmOff<i64, sext_aload_8_64, regPlusImm, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatImmOff<i64, sext_aload_16_64, regPlusImm, "ATOMIC_LOAD16_U_I64">;
 defm : LoadPatImmOff<i64, sext_aload_8_64, or_is_add, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatImmOff<i64, sext_aload_16_64, or_is_add, "ATOMIC_LOAD16_U_I64">;
 // No 32->64 patterns, just use i32.atomic.load and i64.extend_s/i64
 
 // Extending loads with just a constant offset
-defm : LoadPatOffsetOnly<i32, zext_aload_8_32, "ATOMIC_LOAD8_U_I32">;
-defm : LoadPatOffsetOnly<i32, zext_aload_16_32, "ATOMIC_LOAD16_U_I32">;
 defm : LoadPatOffsetOnly<i64, zext_aload_8_64, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatOffsetOnly<i64, zext_aload_16_64, "ATOMIC_LOAD16_U_I64">;
 defm : LoadPatOffsetOnly<i64, zext_aload_32_64, "ATOMIC_LOAD32_U_I64">;
 defm : LoadPatOffsetOnly<i32, atomic_load_8, "ATOMIC_LOAD8_U_I32">;
 defm : LoadPatOffsetOnly<i32, atomic_load_16, "ATOMIC_LOAD16_U_I32">;
 defm : LoadPatOffsetOnly<i64, sext_aload_8_64, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatOffsetOnly<i64, sext_aload_16_64, "ATOMIC_LOAD16_U_I64">;
 
-defm : LoadPatGlobalAddrOffOnly<i32, zext_aload_8_32, "ATOMIC_LOAD8_U_I32">;
-defm : LoadPatGlobalAddrOffOnly<i32, zext_aload_16_32, "ATOMIC_LOAD16_U_I32">;
 defm : LoadPatGlobalAddrOffOnly<i64, zext_aload_8_64, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatGlobalAddrOffOnly<i64, zext_aload_16_64, "ATOMIC_LOAD16_U_I64">;
 defm : LoadPatGlobalAddrOffOnly<i64, zext_aload_32_64, "ATOMIC_LOAD32_U_I64">;
 defm : LoadPatGlobalAddrOffOnly<i32, atomic_load_8, "ATOMIC_LOAD8_U_I32">;
 defm : LoadPatGlobalAddrOffOnly<i32, atomic_load_16, "ATOMIC_LOAD16_U_I32">;
 defm : LoadPatGlobalAddrOffOnly<i64, sext_aload_8_64, "ATOMIC_LOAD8_U_I64">;
 defm : LoadPatGlobalAddrOffOnly<i64, sext_aload_16_64, "ATOMIC_LOAD16_U_I64">;
 
defm : BinRMWPattern<atomic_load_xor_32, atomic_load_xor_64,
                      "ATOMIC_RMW_XOR_I32", "ATOMIC_RMW_XOR_I64">;
 defm : BinRMWPattern<atomic_swap_32, atomic_swap_64,
                      "ATOMIC_RMW_XCHG_I32", "ATOMIC_RMW_XCHG_I64">;
 
 // Truncating & zero-extending binary RMW patterns.
 // These are combined patterns of truncating store patterns and zero-extending
 // load patterns above.
 class zext_bin_rmw_8_32<PatFrag kind> :
-  PatFrag<(ops node:$addr, node:$val),
-          (and (i32 (kind node:$addr, node:$val)), 255)>;
-class zext_bin_rmw_16_32<PatFrag kind> :
-  PatFrag<(ops node:$addr, node:$val),
-          (and (i32 (kind node:$addr, node:$val)), 65535)>;
+  PatFrag<(ops node:$addr, node:$val), (i32 (kind node:$addr, node:$val))>;
+class zext_bin_rmw_16_32<PatFrag kind> : zext_bin_rmw_8_32<kind>;
 class zext_bin_rmw_8_64<PatFrag kind> :
   PatFrag<(ops node:$addr, node:$val),
-    (and (i64 (anyext (i32 (kind node:$addr,
-                                 (i32 (trunc (i64 node:$val))))))), 255)>;
-class zext_bin_rmw_16_64<PatFrag kind> :
-  PatFrag<(ops node:$addr, node:$val),
-    (and (i64 (anyext (i32 (kind node:$addr,
-                                 (i32 (trunc (i64 node:$val))))))), 65535)>;
-class zext_bin_rmw_32_64<PatFrag kind> :
-  PatFrag<(ops node:$addr, node:$val),
           (zext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>;
+class zext_bin_rmw_16_64<PatFrag kind> : zext_bin_rmw_8_64<kind>;
+class zext_bin_rmw_32_64<PatFrag kind> : zext_bin_rmw_8_64<kind>;
 
 // Truncating & sign-extending binary RMW patterns.
 // These are combined patterns of truncating store patterns and sign-extending
 // load patterns above. We match subword RMWs (for 32-bit) and anyext RMWs (for
 // 64-bit) and select a zext RMW; the next instruction will be sext_inreg which
 // is selected by itself.
 class sext_bin_rmw_8_32<PatFrag kind> :
   PatFrag<(ops node:$addr, node:$val), (kind node:$addr, node:$val)>;

 defm : TerRMWPattern<atomic_cmp_swap_32, atomic_cmp_swap_64,
                      "ATOMIC_RMW_CMPXCHG_I32", "ATOMIC_RMW_CMPXCHG_I64">;
 
 // Truncating & zero-extending ternary RMW patterns.
 // DAG legalization & optimization before instruction selection may introduce
 // additional nodes such as anyext or assertzext depending on operand types.
 class zext_ter_rmw_8_32<PatFrag kind> :
   PatFrag<(ops node:$addr, node:$exp, node:$new),
-          (and (i32 (kind node:$addr, node:$exp, node:$new)), 255)>;
-class zext_ter_rmw_16_32<PatFrag kind> :
-  PatFrag<(ops node:$addr, node:$exp, node:$new),
-          (and (i32 (kind node:$addr, node:$exp, node:$new)), 65535)>;
+          (i32 (kind node:$addr, node:$exp, node:$new))>;
+class zext_ter_rmw_16_32<PatFrag kind> : zext_ter_rmw_8_32<kind>;
 class zext_ter_rmw_8_64<PatFrag kind> :
   PatFrag<(ops node:$addr, node:$exp, node:$new),
           (zext (i32 (assertzext (i32 (kind node:$addr,
                                             (i32 (trunc (i64 node:$exp))),
                                             (i32 (trunc (i64 node:$new))))))))>;
 class zext_ter_rmw_16_64<PatFrag kind> : zext_ter_rmw_8_64<kind>;
 class zext_ter_rmw_32_64<PatFrag kind> :
   PatFrag<(ops node:$addr, node:$exp, node:$new),

llvm/test/CodeGen/Mips/atomic.ll

 define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
 ; MIPS32-LABEL: AtomicLoadAdd8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32-NEXT:    addu $1, $2, $25
 ; MIPS32-NEXT:    lw $1, %got(y)($1)
 ; MIPS32-NEXT:    addiu $2, $zero, -4
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    and $3, $1, $2
 ; MIPS32-NEXT:    andi $1, $1, 3
-; MIPS32-NEXT:    sll $3, $1, 3
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    sllv $5, $1, $3
+; MIPS32-NEXT:    sll $1, $1, 3
+; MIPS32-NEXT:    ori $2, $zero, 255
+; MIPS32-NEXT:    sllv $5, $2, $1
 ; MIPS32-NEXT:    nor $6, $zero, $5
-; MIPS32-NEXT:    sllv $4, $4, $3
+; MIPS32-NEXT:    sllv $4, $4, $1
 ; MIPS32-NEXT:  $BB8_1: # %entry
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32-NEXT:    ll $7, 0($2)
+; MIPS32-NEXT:    ll $7, 0($3)
 ; MIPS32-NEXT:    addu $8, $7, $4
 ; MIPS32-NEXT:    and $8, $8, $5
 ; MIPS32-NEXT:    and $9, $7, $6
 ; MIPS32-NEXT:    or $9, $9, $8
-; MIPS32-NEXT:    sc $9, 0($2)
+; MIPS32-NEXT:    sc $9, 0($3)
 ; MIPS32-NEXT:    beqz $9, $BB8_1
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %entry
-; MIPS32-NEXT:    and $1, $7, $5
-; MIPS32-NEXT:    srlv $1, $1, $3
-; MIPS32-NEXT:    sll $1, $1, 24
-; MIPS32-NEXT:    sra $1, $1, 24
+; MIPS32-NEXT:    and $2, $7, $5
+; MIPS32-NEXT:    srlv $2, $2, $1
+; MIPS32-NEXT:    sll $2, $2, 24
+; MIPS32-NEXT:    sra $2, $2, 24
 ; MIPS32-NEXT:  # %bb.3: # %entry
-; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    jr $ra
-; MIPS32-NEXT:    sra $2, $1, 24
+; MIPS32-NEXT:    nop
 ;
 ; MIPS32O0-LABEL: AtomicLoadAdd8:
 ; MIPS32O0:       # %bb.0: # %entry
 ; MIPS32O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32O0-NEXT:    addu $1, $2, $25
 ; MIPS32O0-NEXT:    lw $1, %got(y)($1)

 ;
 ; MIPS32R2-LABEL: AtomicLoadAdd8:
 ; MIPS32R2:       # %bb.0: # %entry
 ; MIPS32R2-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R2-NEXT:    addu $1, $2, $25
 ; MIPS32R2-NEXT:    lw $1, %got(y)($1)
 ; MIPS32R2-NEXT:    addiu $2, $zero, -4
-; MIPS32R2-NEXT:    and $2, $1, $2
+; MIPS32R2-NEXT:    and $3, $1, $2
 ; MIPS32R2-NEXT:    andi $1, $1, 3
-; MIPS32R2-NEXT:    sll $3, $1, 3
-; MIPS32R2-NEXT:    ori $1, $zero, 255
-; MIPS32R2-NEXT:    sllv $5, $1, $3
+; MIPS32R2-NEXT:    sll $1, $1, 3
+; MIPS32R2-NEXT:    ori $2, $zero, 255
+; MIPS32R2-NEXT:    sllv $5, $2, $1
 ; MIPS32R2-NEXT:    nor $6, $zero, $5
-; MIPS32R2-NEXT:    sllv $4, $4, $3
+; MIPS32R2-NEXT:    sllv $4, $4, $1
 ; MIPS32R2-NEXT:  $BB8_1: # %entry
 ; MIPS32R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R2-NEXT:    ll $7, 0($2)
+; MIPS32R2-NEXT:    ll $7, 0($3)
 ; MIPS32R2-NEXT:    addu $8, $7, $4
 ; MIPS32R2-NEXT:    and $8, $8, $5
 ; MIPS32R2-NEXT:    and $9, $7, $6
 ; MIPS32R2-NEXT:    or $9, $9, $8
-; MIPS32R2-NEXT:    sc $9, 0($2)
+; MIPS32R2-NEXT:    sc $9, 0($3)
 ; MIPS32R2-NEXT:    beqz $9, $BB8_1
 ; MIPS32R2-NEXT:    nop
 ; MIPS32R2-NEXT:  # %bb.2: # %entry
-; MIPS32R2-NEXT:    and $1, $7, $5
-; MIPS32R2-NEXT:    srlv $1, $1, $3
-; MIPS32R2-NEXT:    seb $1, $1
+; MIPS32R2-NEXT:    and $2, $7, $5
+; MIPS32R2-NEXT:    srlv $2, $2, $1
+; MIPS32R2-NEXT:    seb $2, $2
 ; MIPS32R2-NEXT:  # %bb.3: # %entry
 ; MIPS32R2-NEXT:    jr $ra
-; MIPS32R2-NEXT:    seb $2, $1
+; MIPS32R2-NEXT:    nop
 ;
 ; MIPS32R6-LABEL: AtomicLoadAdd8:
 ; MIPS32R6:       # %bb.0: # %entry
 ; MIPS32R6-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6-NEXT:    addu $1, $2, $25
 ; MIPS32R6-NEXT:    lw $1, %got(y)($1)
 ; MIPS32R6-NEXT:    addiu $2, $zero, -4
-; MIPS32R6-NEXT:    and $2, $1, $2
+; MIPS32R6-NEXT:    and $3, $1, $2
 ; MIPS32R6-NEXT:    andi $1, $1, 3
-; MIPS32R6-NEXT:    sll $3, $1, 3
-; MIPS32R6-NEXT:    ori $1, $zero, 255
-; MIPS32R6-NEXT:    sllv $5, $1, $3
+; MIPS32R6-NEXT:    sll $1, $1, 3
+; MIPS32R6-NEXT:    ori $2, $zero, 255
+; MIPS32R6-NEXT:    sllv $5, $2, $1
 ; MIPS32R6-NEXT:    nor $6, $zero, $5
-; MIPS32R6-NEXT:    sllv $4, $4, $3
+; MIPS32R6-NEXT:    sllv $4, $4, $1
 ; MIPS32R6-NEXT:  $BB8_1: # %entry
 ; MIPS32R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R6-NEXT:    ll $7, 0($2)
+; MIPS32R6-NEXT:    ll $7, 0($3)
 ; MIPS32R6-NEXT:    addu $8, $7, $4
 ; MIPS32R6-NEXT:    and $8, $8, $5
 ; MIPS32R6-NEXT:    and $9, $7, $6
 ; MIPS32R6-NEXT:    or $9, $9, $8
-; MIPS32R6-NEXT:    sc $9, 0($2)
+; MIPS32R6-NEXT:    sc $9, 0($3)
 ; MIPS32R6-NEXT:    beqzc $9, $BB8_1
 ; MIPS32R6-NEXT:  # %bb.2: # %entry
-; MIPS32R6-NEXT:    and $1, $7, $5
-; MIPS32R6-NEXT:    srlv $1, $1, $3
-; MIPS32R6-NEXT:    seb $1, $1
+; MIPS32R6-NEXT:    and $2, $7, $5
+; MIPS32R6-NEXT:    srlv $2, $2, $1
+; MIPS32R6-NEXT:    seb $2, $2
 ; MIPS32R6-NEXT:  # %bb.3: # %entry
-; MIPS32R6-NEXT:    jr $ra
-; MIPS32R6-NEXT:    seb $2, $1
+; MIPS32R6-NEXT:    jrc $ra
 ;
 ; MIPS32R6O0-LABEL: AtomicLoadAdd8:
 ; MIPS32R6O0:       # %bb.0: # %entry
 ; MIPS32R6O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32R6O0-NEXT:    addu $1, $2, $25
 ; MIPS32R6O0-NEXT:    # kill: def $v0 killed $a0

 ; MIPS32R6O0-NEXT:    beqzc $4, $BB8_1
 ; MIPS32R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS32R6O0-NEXT:    and $1, $2, $7
 ; MIPS32R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS32R6O0-NEXT:    seb $1, $1
 ; MIPS32R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS32R6O0-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
 ; MIPS32R6O0-NEXT:  # %bb.4: # %entry
-; MIPS32R6O0-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
-; MIPS32R6O0-NEXT:    seb $2, $1
+; MIPS32R6O0-NEXT:    lw $2, 4($sp) # 4-byte Folded Reload
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, 8
 ; MIPS32R6O0-NEXT:    jrc $ra
 ;
 ; MIPS4-LABEL: AtomicLoadAdd8:
 ; MIPS4:       # %bb.0: # %entry
 ; MIPS4-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS4-NEXT:    daddu $1, $1, $25
 ; MIPS4-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS4-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS4-NEXT:    daddiu $2, $zero, -4
-; MIPS4-NEXT:    and $2, $1, $2
+; MIPS4-NEXT:    and $3, $1, $2
 ; MIPS4-NEXT:    andi $1, $1, 3
-; MIPS4-NEXT:    sll $3, $1, 3
-; MIPS4-NEXT:    ori $1, $zero, 255
-; MIPS4-NEXT:    sllv $5, $1, $3
+; MIPS4-NEXT:    sll $1, $1, 3
+; MIPS4-NEXT:    ori $2, $zero, 255
+; MIPS4-NEXT:    sllv $5, $2, $1
 ; MIPS4-NEXT:    nor $6, $zero, $5
-; MIPS4-NEXT:    sllv $4, $4, $3
+; MIPS4-NEXT:    sllv $4, $4, $1
 ; MIPS4-NEXT:  .LBB8_1: # %entry
 ; MIPS4-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS4-NEXT:    ll $7, 0($2)
+; MIPS4-NEXT:    ll $7, 0($3)
 ; MIPS4-NEXT:    addu $8, $7, $4
 ; MIPS4-NEXT:    and $8, $8, $5
 ; MIPS4-NEXT:    and $9, $7, $6
 ; MIPS4-NEXT:    or $9, $9, $8
-; MIPS4-NEXT:    sc $9, 0($2)
+; MIPS4-NEXT:    sc $9, 0($3)
 ; MIPS4-NEXT:    beqz $9, .LBB8_1
 ; MIPS4-NEXT:    nop
 ; MIPS4-NEXT:  # %bb.2: # %entry
-; MIPS4-NEXT:    and $1, $7, $5
-; MIPS4-NEXT:    srlv $1, $1, $3
-; MIPS4-NEXT:    sll $1, $1, 24
-; MIPS4-NEXT:    sra $1, $1, 24
+; MIPS4-NEXT:    and $2, $7, $5
+; MIPS4-NEXT:    srlv $2, $2, $1
+; MIPS4-NEXT:    sll $2, $2, 24
+; MIPS4-NEXT:    sra $2, $2, 24
 ; MIPS4-NEXT:  # %bb.3: # %entry
-; MIPS4-NEXT:    sll $1, $1, 24
 ; MIPS4-NEXT:    jr $ra
-; MIPS4-NEXT:    sra $2, $1, 24
+; MIPS4-NEXT:    nop
 ;
 ; MIPS64-LABEL: AtomicLoadAdd8:
 ; MIPS64:       # %bb.0: # %entry
 ; MIPS64-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS64-NEXT:    daddu $1, $1, $25
 ; MIPS64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS64-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64-NEXT:    daddiu $2, $zero, -4
-; MIPS64-NEXT:    and $2, $1, $2
+; MIPS64-NEXT:    and $3, $1, $2
 ; MIPS64-NEXT:    andi $1, $1, 3
-; MIPS64-NEXT:    sll $3, $1, 3
-; MIPS64-NEXT:    ori $1, $zero, 255
-; MIPS64-NEXT:    sllv $5, $1, $3
+; MIPS64-NEXT:    sll $1, $1, 3
+; MIPS64-NEXT:    ori $2, $zero, 255
+; MIPS64-NEXT:    sllv $5, $2, $1
 ; MIPS64-NEXT:    nor $6, $zero, $5
-; MIPS64-NEXT:    sllv $4, $4, $3
+; MIPS64-NEXT:    sllv $4, $4, $1
 ; MIPS64-NEXT:  .LBB8_1: # %entry
 ; MIPS64-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64-NEXT:    ll $7, 0($2)
+; MIPS64-NEXT:    ll $7, 0($3)
 ; MIPS64-NEXT:    addu $8, $7, $4
 ; MIPS64-NEXT:    and $8, $8, $5
 ; MIPS64-NEXT:    and $9, $7, $6
 ; MIPS64-NEXT:    or $9, $9, $8
-; MIPS64-NEXT:    sc $9, 0($2)
+; MIPS64-NEXT:    sc $9, 0($3)
 ; MIPS64-NEXT:    beqz $9, .LBB8_1
 ; MIPS64-NEXT:    nop
 ; MIPS64-NEXT:  # %bb.2: # %entry
-; MIPS64-NEXT:    and $1, $7, $5
-; MIPS64-NEXT:    srlv $1, $1, $3
-; MIPS64-NEXT:    sll $1, $1, 24
-; MIPS64-NEXT:    sra $1, $1, 24
+; MIPS64-NEXT:    and $2, $7, $5
+; MIPS64-NEXT:    srlv $2, $2, $1
+; MIPS64-NEXT:    sll $2, $2, 24
+; MIPS64-NEXT:    sra $2, $2, 24
 ; MIPS64-NEXT:  # %bb.3: # %entry
-; MIPS64-NEXT:    sll $1, $1, 24
 ; MIPS64-NEXT:    jr $ra
-; MIPS64-NEXT:    sra $2, $1, 24
+; MIPS64-NEXT:    nop
 ;
 ; MIPS64R2-LABEL: AtomicLoadAdd8:
 ; MIPS64R2:       # %bb.0: # %entry
 ; MIPS64R2-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS64R2-NEXT:    daddu $1, $1, $25
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS64R2-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64R2-NEXT:    daddiu $2, $zero, -4
-; MIPS64R2-NEXT:    and $2, $1, $2
+; MIPS64R2-NEXT:    and $3, $1, $2
 ; MIPS64R2-NEXT:    andi $1, $1, 3
-; MIPS64R2-NEXT:    sll $3, $1, 3
-; MIPS64R2-NEXT:    ori $1, $zero, 255
-; MIPS64R2-NEXT:    sllv $5, $1, $3
+; MIPS64R2-NEXT:    sll $1, $1, 3
+; MIPS64R2-NEXT:    ori $2, $zero, 255
+; MIPS64R2-NEXT:    sllv $5, $2, $1
 ; MIPS64R2-NEXT:    nor $6, $zero, $5
-; MIPS64R2-NEXT:    sllv $4, $4, $3
+; MIPS64R2-NEXT:    sllv $4, $4, $1
 ; MIPS64R2-NEXT:  .LBB8_1: # %entry
 ; MIPS64R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R2-NEXT:    ll $7, 0($2)
+; MIPS64R2-NEXT:    ll $7, 0($3)
 ; MIPS64R2-NEXT:    addu $8, $7, $4
 ; MIPS64R2-NEXT:    and $8, $8, $5
 ; MIPS64R2-NEXT:    and $9, $7, $6
 ; MIPS64R2-NEXT:    or $9, $9, $8
-; MIPS64R2-NEXT:    sc $9, 0($2)
+; MIPS64R2-NEXT:    sc $9, 0($3)
 ; MIPS64R2-NEXT:    beqz $9, .LBB8_1
 ; MIPS64R2-NEXT:    nop
 ; MIPS64R2-NEXT:  # %bb.2: # %entry
-; MIPS64R2-NEXT:    and $1, $7, $5
-; MIPS64R2-NEXT:    srlv $1, $1, $3
-; MIPS64R2-NEXT:    seb $1, $1
+; MIPS64R2-NEXT:    and $2, $7, $5
+; MIPS64R2-NEXT:    srlv $2, $2, $1
+; MIPS64R2-NEXT:    seb $2, $2
 ; MIPS64R2-NEXT:  # %bb.3: # %entry
 ; MIPS64R2-NEXT:    jr $ra
-; MIPS64R2-NEXT:    seb $2, $1
+; MIPS64R2-NEXT:    nop
 ;
 ; MIPS64R6-LABEL: AtomicLoadAdd8:
 ; MIPS64R6:       # %bb.0: # %entry
 ; MIPS64R6-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64R6-NEXT:    daddiu $2, $zero, -4
-; MIPS64R6-NEXT:    and $2, $1, $2
+; MIPS64R6-NEXT:    and $3, $1, $2
 ; MIPS64R6-NEXT:    andi $1, $1, 3
-; MIPS64R6-NEXT:    sll $3, $1, 3
-; MIPS64R6-NEXT:    ori $1, $zero, 255
-; MIPS64R6-NEXT:    sllv $5, $1, $3
+; MIPS64R6-NEXT:    sll $1, $1, 3
+; MIPS64R6-NEXT:    ori $2, $zero, 255
+; MIPS64R6-NEXT:    sllv $5, $2, $1
 ; MIPS64R6-NEXT:    nor $6, $zero, $5
-; MIPS64R6-NEXT:    sllv $4, $4, $3
+; MIPS64R6-NEXT:    sllv $4, $4, $1
 ; MIPS64R6-NEXT:  .LBB8_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R6-NEXT:    ll $7, 0($2)
+; MIPS64R6-NEXT:    ll $7, 0($3)
 ; MIPS64R6-NEXT:    addu $8, $7, $4
 ; MIPS64R6-NEXT:    and $8, $8, $5
 ; MIPS64R6-NEXT:    and $9, $7, $6
 ; MIPS64R6-NEXT:    or $9, $9, $8
-; MIPS64R6-NEXT:    sc $9, 0($2)
+; MIPS64R6-NEXT:    sc $9, 0($3)
 ; MIPS64R6-NEXT:    beqzc $9, .LBB8_1
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
-; MIPS64R6-NEXT:    and $1, $7, $5
-; MIPS64R6-NEXT:    srlv $1, $1, $3
-; MIPS64R6-NEXT:    seb $1, $1
+; MIPS64R6-NEXT:    and $2, $7, $5
+; MIPS64R6-NEXT:    srlv $2, $2, $1
+; MIPS64R6-NEXT:    seb $2, $2
 ; MIPS64R6-NEXT:  # %bb.3: # %entry
-; MIPS64R6-NEXT:    jr $ra
-; MIPS64R6-NEXT:    seb $2, $1
+; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadAdd8:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $2, $1, %lo(%neg(%gp_rel(AtomicLoadAdd8)))
 ; MIPS64R6O0-NEXT:    move $1, $4

 ; MIPS64R6O0-NEXT:    beqzc $4, .LBB8_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    and $1, $2, $7
 ; MIPS64R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS64R6O0-NEXT:    seb $1, $1
 ; MIPS64R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS64R6O0-NEXT:    sw $1, 12($sp) # 4-byte Folded Spill
 ; MIPS64R6O0-NEXT:  # %bb.4: # %entry
-; MIPS64R6O0-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
-; MIPS64R6O0-NEXT:    seb $2, $1
+; MIPS64R6O0-NEXT:    lw $2, 12($sp) # 4-byte Folded Reload
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; MM32-LABEL: AtomicLoadAdd8:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    lui $2, %hi(_gp_disp)
 ; MM32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MM32-NEXT:    addu $2, $2, $25
 ; MM32-NEXT:    lw $1, %got(y)($2)
 ; MM32-NEXT:    addiu $2, $zero, -4
-; MM32-NEXT:    and $2, $1, $2
+; MM32-NEXT:    and $3, $1, $2
 ; MM32-NEXT:    andi $1, $1, 3
-; MM32-NEXT:    sll $3, $1, 3
-; MM32-NEXT:    ori $1, $zero, 255
-; MM32-NEXT:    sllv $5, $1, $3
+; MM32-NEXT:    sll $1, $1, 3
+; MM32-NEXT:    ori $2, $zero, 255
+; MM32-NEXT:    sllv $5, $2, $1
 ; MM32-NEXT:    nor $6, $zero, $5
-; MM32-NEXT:    sllv $4, $4, $3
+; MM32-NEXT:    sllv $4, $4, $1
 ; MM32-NEXT:  $BB8_1: # %entry
 ; MM32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MM32-NEXT:    ll $7, 0($2)
+; MM32-NEXT:    ll $7, 0($3)
 ; MM32-NEXT:    addu $8, $7, $4
 ; MM32-NEXT:    and $8, $8, $5
 ; MM32-NEXT:    and $9, $7, $6
 ; MM32-NEXT:    or $9, $9, $8
-; MM32-NEXT:    sc $9, 0($2)
+; MM32-NEXT:    sc $9, 0($3)
 ; MM32-NEXT:    beqzc $9, $BB8_1
 ; MM32-NEXT:  # %bb.2: # %entry
-; MM32-NEXT:    and $1, $7, $5
-; MM32-NEXT:    srlv $1, $1, $3
-; MM32-NEXT:    seb $1, $1
+; MM32-NEXT:    and $2, $7, $5
+; MM32-NEXT:    srlv $2, $2, $1
+; MM32-NEXT:    seb $2, $2
 ; MM32-NEXT:  # %bb.3: # %entry
-; MM32-NEXT:    jr $ra
-; MM32-NEXT:    seb $2, $1
+; MM32-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadAdd8:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $2, %hi(_gp_disp)
 ; O1-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O1-NEXT:    addu $1, $2, $25
 ; O1-NEXT:    lw $1, %got(y)($1)
 ; O1-NEXT:    addiu $2, $zero, -4
-; O1-NEXT:    and $2, $1, $2
+; O1-NEXT:    and $3, $1, $2
 ; O1-NEXT:    andi $1, $1, 3
-; O1-NEXT:    sll $3, $1, 3
-; O1-NEXT:    ori $1, $zero, 255
-; O1-NEXT:    sllv $5, $1, $3
+; O1-NEXT:    sll $1, $1, 3
+; O1-NEXT:    ori $2, $zero, 255
+; O1-NEXT:    sllv $5, $2, $1
 ; O1-NEXT:    nor $6, $zero, $5
-; O1-NEXT:    sllv $4, $4, $3
+; O1-NEXT:    sllv $4, $4, $1
 ; O1-NEXT:  $BB8_1: # %entry
 ; O1-NEXT:    # =>This Inner Loop Header: Depth=1
-; O1-NEXT:    ll $7, 0($2)
+; O1-NEXT:    ll $7, 0($3)
 ; O1-NEXT:    addu $8, $7, $4
 ; O1-NEXT:    and $8, $8, $5
 ; O1-NEXT:    and $9, $7, $6
 ; O1-NEXT:    or $9, $9, $8
-; O1-NEXT:    sc $9, 0($2)
+; O1-NEXT:    sc $9, 0($3)
 ; O1-NEXT:    beqz $9, $BB8_1
 ; O1-NEXT:    nop
 ; O1-NEXT:  # %bb.2: # %entry
-; O1-NEXT:    and $1, $7, $5
-; O1-NEXT:    srlv $1, $1, $3
-; O1-NEXT:    sll $1, $1, 24
-; O1-NEXT:    sra $1, $1, 24
+; O1-NEXT:    and $2, $7, $5
+; O1-NEXT:    srlv $2, $2, $1
+; O1-NEXT:    sll $2, $2, 24
+; O1-NEXT:    sra $2, $2, 24
 ; O1-NEXT:  # %bb.3: # %entry
-; O1-NEXT:    sll $1, $1, 24
 ; O1-NEXT:    jr $ra
-; O1-NEXT:    sra $2, $1, 24
+; O1-NEXT:    nop
 ;
 ; O2-LABEL: AtomicLoadAdd8:
 ; O2:       # %bb.0: # %entry
 ; O2-NEXT:    lui $2, %hi(_gp_disp)
 ; O2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O2-NEXT:    addu $1, $2, $25
 ; O2-NEXT:    lw $1, %got(y)($1)
 ; O2-NEXT:    addiu $2, $zero, -4
-; O2-NEXT:    and $2, $1, $2
+; O2-NEXT:    and $3, $1, $2
 ; O2-NEXT:    andi $1, $1, 3
-; O2-NEXT:    sll $3, $1, 3
-; O2-NEXT:    ori $1, $zero, 255
-; O2-NEXT:    sllv $5, $1, $3
+; O2-NEXT:    sll $1, $1, 3
+; O2-NEXT:    ori $2, $zero, 255
+; O2-NEXT:    sllv $5, $2, $1
 ; O2-NEXT:    nor $6, $zero, $5
-; O2-NEXT:    sllv $4, $4, $3
+; O2-NEXT:    sllv $4, $4, $1
 ; O2-NEXT:  $BB8_1: # %entry
 ; O2-NEXT:    # =>This Inner Loop Header: Depth=1
-; O2-NEXT:    ll $7, 0($2)
+; O2-NEXT:    ll $7, 0($3)
 ; O2-NEXT:    addu $8, $7, $4
 ; O2-NEXT:    and $8, $8, $5
 ; O2-NEXT:    and $9, $7, $6
 ; O2-NEXT:    or $9, $9, $8
-; O2-NEXT:    sc $9, 0($2)
+; O2-NEXT:    sc $9, 0($3)
 ; O2-NEXT:    beqz $9, $BB8_1
 ; O2-NEXT:    nop
 ; O2-NEXT:  # %bb.2: # %entry
-; O2-NEXT:    and $1, $7, $5
-; O2-NEXT:    srlv $1, $1, $3
-; O2-NEXT:    sll $1, $1, 24
-; O2-NEXT:    sra $1, $1, 24
+; O2-NEXT:    and $2, $7, $5
+; O2-NEXT:    srlv $2, $2, $1
+; O2-NEXT:    sll $2, $2, 24
+; O2-NEXT:    sra $2, $2, 24
 ; O2-NEXT:  # %bb.3: # %entry
-; O2-NEXT:    sll $1, $1, 24
 ; O2-NEXT:    jr $ra
-; O2-NEXT:    sra $2, $1, 24
+; O2-NEXT:    nop
 ;
 ; O3-LABEL: AtomicLoadAdd8:
 ; O3:       # %bb.0: # %entry
 ; O3-NEXT:    lui $2, %hi(_gp_disp)
 ; O3-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O3-NEXT:    addu $1, $2, $25
 ; O3-NEXT:    addiu $2, $zero, -4
 ; O3-NEXT:    lw $1, %got(y)($1)
-; O3-NEXT:    and $2, $1, $2
+; O3-NEXT:    and $3, $1, $2
 ; O3-NEXT:    andi $1, $1, 3
-; O3-NEXT:    sll $3, $1, 3
-; O3-NEXT:    ori $1, $zero, 255
-; O3-NEXT:    sllv $5, $1, $3
-; O3-NEXT:    sllv $4, $4, $3
+; O3-NEXT:    ori $2, $zero, 255
+; O3-NEXT:    sll $1, $1, 3
+; O3-NEXT:    sllv $5, $2, $1
+; O3-NEXT:    sllv $4, $4, $1
 ; O3-NEXT:    nor $6, $zero, $5
 ; O3-NEXT:  $BB8_1: # %entry
 ; O3-NEXT:    # =>This Inner Loop Header: Depth=1
-; O3-NEXT:    ll $7, 0($2)
+; O3-NEXT:    ll $7, 0($3)
 ; O3-NEXT:    addu $8, $7, $4
 ; O3-NEXT:    and $8, $8, $5
 ; O3-NEXT:    and $9, $7, $6
 ; O3-NEXT:    or $9, $9, $8
-; O3-NEXT:    sc $9, 0($2)
+; O3-NEXT:    sc $9, 0($3)
 ; O3-NEXT:    beqz $9, $BB8_1
 ; O3-NEXT:    nop
 ; O3-NEXT:  # %bb.2: # %entry
-; O3-NEXT:    and $1, $7, $5
-; O3-NEXT:    srlv $1, $1, $3
-; O3-NEXT:    sll $1, $1, 24
-; O3-NEXT:    sra $1, $1, 24
+; O3-NEXT:    and $2, $7, $5
+; O3-NEXT:    srlv $2, $2, $1
+; O3-NEXT:    sll $2, $2, 24
+; O3-NEXT:    sra $2, $2, 24
 ; O3-NEXT:  # %bb.3: # %entry
-; O3-NEXT:    sll $1, $1, 24
 ; O3-NEXT:    jr $ra
-; O3-NEXT:    sra $2, $1, 24
+; O3-NEXT:    nop
 ;
 ; MIPS32EB-LABEL: AtomicLoadAdd8:
 ; MIPS32EB:       # %bb.0: # %entry
 ; MIPS32EB-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32EB-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32EB-NEXT:    addu $1, $2, $25
 ; MIPS32EB-NEXT:    lw $1, %got(y)($1)
 ; MIPS32EB-NEXT:    addiu $2, $zero, -4
-; MIPS32EB-NEXT:    and $2, $1, $2
+; MIPS32EB-NEXT:    and $3, $1, $2
 ; MIPS32EB-NEXT:    andi $1, $1, 3
 ; MIPS32EB-NEXT:    xori $1, $1, 3
-; MIPS32EB-NEXT:    sll $3, $1, 3
-; MIPS32EB-NEXT:    ori $1, $zero, 255
-; MIPS32EB-NEXT:    sllv $5, $1, $3
+; MIPS32EB-NEXT:    sll $1, $1, 3
+; MIPS32EB-NEXT:    ori $2, $zero, 255
+; MIPS32EB-NEXT:    sllv $5, $2, $1
 ; MIPS32EB-NEXT:    nor $6, $zero, $5
-; MIPS32EB-NEXT:    sllv $4, $4, $3
+; MIPS32EB-NEXT:    sllv $4, $4, $1
 ; MIPS32EB-NEXT:  $BB8_1: # %entry
 ; MIPS32EB-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32EB-NEXT:    ll $7, 0($2)
+; MIPS32EB-NEXT:    ll $7, 0($3)
 ; MIPS32EB-NEXT:    addu $8, $7, $4
 ; MIPS32EB-NEXT:    and $8, $8, $5
 ; MIPS32EB-NEXT:    and $9, $7, $6
 ; MIPS32EB-NEXT:    or $9, $9, $8
-; MIPS32EB-NEXT:    sc $9, 0($2)
+; MIPS32EB-NEXT:    sc $9, 0($3)
 ; MIPS32EB-NEXT:    beqz $9, $BB8_1
 ; MIPS32EB-NEXT:    nop
 ; MIPS32EB-NEXT:  # %bb.2: # %entry
-; MIPS32EB-NEXT:    and $1, $7, $5
-; MIPS32EB-NEXT:    srlv $1, $1, $3
-; MIPS32EB-NEXT:    sll $1, $1, 24
-; MIPS32EB-NEXT:    sra $1, $1, 24
+; MIPS32EB-NEXT:    and $2, $7, $5
+; MIPS32EB-NEXT:    srlv $2, $2, $1
+; MIPS32EB-NEXT:    sll $2, $2, 24
+; MIPS32EB-NEXT:    sra $2, $2, 24
 ; MIPS32EB-NEXT:  # %bb.3: # %entry
-; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    jr $ra
-; MIPS32EB-NEXT:    sra $2, $1, 24
+; MIPS32EB-NEXT:    nop
 entry:
   %0 = atomicrmw add i8* @y, i8 %incr monotonic
   ret i8 %0
 }
 
 define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
 ; MIPS32-LABEL: AtomicLoadSub8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32-NEXT:    addu $1, $2, $25
 ; MIPS32-NEXT:    lw $1, %got(y)($1)
 ; MIPS32-NEXT:    addiu $2, $zero, -4
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    and $3, $1, $2
 ; MIPS32-NEXT:    andi $1, $1, 3
-; MIPS32-NEXT:    sll $3, $1, 3
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    sllv $5, $1, $3
+; MIPS32-NEXT:    sll $1, $1, 3
+; MIPS32-NEXT:    ori $2, $zero, 255
+; MIPS32-NEXT:    sllv $5, $2, $1
 ; MIPS32-NEXT:    nor $6, $zero, $5
-; MIPS32-NEXT:    sllv $4, $4, $3
+; MIPS32-NEXT:    sllv $4, $4, $1
 ; MIPS32-NEXT:  $BB9_1: # %entry
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32-NEXT:    ll $7, 0($2)
+; MIPS32-NEXT:    ll $7, 0($3)
 ; MIPS32-NEXT:    subu $8, $7, $4
 ; MIPS32-NEXT:    and $8, $8, $5
 ; MIPS32-NEXT:    and $9, $7, $6
 ; MIPS32-NEXT:    or $9, $9, $8
-; MIPS32-NEXT:    sc $9, 0($2)
+; MIPS32-NEXT:    sc $9, 0($3)
 ; MIPS32-NEXT:    beqz $9, $BB9_1
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %entry
-; MIPS32-NEXT:    and $1, $7, $5
-; MIPS32-NEXT:    srlv $1, $1, $3
-; MIPS32-NEXT:    sll $1, $1, 24
-; MIPS32-NEXT:    sra $1, $1, 24
+; MIPS32-NEXT:    and $2, $7, $5
+; MIPS32-NEXT:    srlv $2, $2, $1
+; MIPS32-NEXT:    sll $2, $2, 24
+; MIPS32-NEXT:    sra $2, $2, 24
 ; MIPS32-NEXT:  # %bb.3: # %entry
-; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    jr $ra
-; MIPS32-NEXT:    sra $2, $1, 24
+; MIPS32-NEXT:    nop
 ;
 ; MIPS32O0-LABEL: AtomicLoadSub8:
 ; MIPS32O0:       # %bb.0: # %entry
 ; MIPS32O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32O0-NEXT:    addu $1, $2, $25
 ; MIPS32O0-NEXT:    lw $1, %got(y)($1)

 ;
 ; MIPS32R2-LABEL: AtomicLoadSub8:
 ; MIPS32R2:       # %bb.0: # %entry
 ; MIPS32R2-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R2-NEXT:    addu $1, $2, $25
 ; MIPS32R2-NEXT:    lw $1, %got(y)($1)
 ; MIPS32R2-NEXT:    addiu $2, $zero, -4
-; MIPS32R2-NEXT:    and $2, $1, $2
+; MIPS32R2-NEXT:    and $3, $1, $2
 ; MIPS32R2-NEXT:    andi $1, $1, 3
-; MIPS32R2-NEXT:    sll $3, $1, 3
-; MIPS32R2-NEXT:    ori $1, $zero, 255
-; MIPS32R2-NEXT:    sllv $5, $1, $3
+; MIPS32R2-NEXT:    sll $1, $1, 3
+; MIPS32R2-NEXT:    ori $2, $zero, 255
+; MIPS32R2-NEXT:    sllv $5, $2, $1
 ; MIPS32R2-NEXT:    nor $6, $zero, $5
-; MIPS32R2-NEXT:    sllv $4, $4, $3
+; MIPS32R2-NEXT:    sllv $4, $4, $1
 ; MIPS32R2-NEXT:  $BB9_1: # %entry
 ; MIPS32R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R2-NEXT:    ll $7, 0($2)
+; MIPS32R2-NEXT:    ll $7, 0($3)
 ; MIPS32R2-NEXT:    subu $8, $7, $4
 ; MIPS32R2-NEXT:    and $8, $8, $5
 ; MIPS32R2-NEXT:    and $9, $7, $6
 ; MIPS32R2-NEXT:    or $9, $9, $8
-; MIPS32R2-NEXT:    sc $9, 0($2)
+; MIPS32R2-NEXT:    sc $9, 0($3)
 ; MIPS32R2-NEXT:    beqz $9, $BB9_1
 ; MIPS32R2-NEXT:    nop
 ; MIPS32R2-NEXT:  # %bb.2: # %entry
-; MIPS32R2-NEXT:    and $1, $7, $5
-; MIPS32R2-NEXT:    srlv $1, $1, $3
-; MIPS32R2-NEXT:    seb $1, $1
+; MIPS32R2-NEXT:    and $2, $7, $5
+; MIPS32R2-NEXT:    srlv $2, $2, $1
+; MIPS32R2-NEXT:    seb $2, $2
 ; MIPS32R2-NEXT:  # %bb.3: # %entry
 ; MIPS32R2-NEXT:    jr $ra
-; MIPS32R2-NEXT:    seb $2, $1
+; MIPS32R2-NEXT:    nop
 ;
 ; MIPS32R6-LABEL: AtomicLoadSub8:
 ; MIPS32R6:       # %bb.0: # %entry
 ; MIPS32R6-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6-NEXT:    addu $1, $2, $25
 ; MIPS32R6-NEXT:    lw $1, %got(y)($1)
 ; MIPS32R6-NEXT:    addiu $2, $zero, -4
-; MIPS32R6-NEXT:    and $2, $1, $2
+; MIPS32R6-NEXT:    and $3, $1, $2
 ; MIPS32R6-NEXT:    andi $1, $1, 3
-; MIPS32R6-NEXT:    sll $3, $1, 3
-; MIPS32R6-NEXT:    ori $1, $zero, 255
-; MIPS32R6-NEXT:    sllv $5, $1, $3
+; MIPS32R6-NEXT:    sll $1, $1, 3
+; MIPS32R6-NEXT:    ori $2, $zero, 255
+; MIPS32R6-NEXT:    sllv $5, $2, $1
 ; MIPS32R6-NEXT:    nor $6, $zero, $5
-; MIPS32R6-NEXT:    sllv $4, $4, $3
+; MIPS32R6-NEXT:    sllv $4, $4, $1
 ; MIPS32R6-NEXT:  $BB9_1: # %entry
 ; MIPS32R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R6-NEXT:    ll $7, 0($2)
+; MIPS32R6-NEXT:    ll $7, 0($3)
 ; MIPS32R6-NEXT:    subu $8, $7, $4
 ; MIPS32R6-NEXT:    and $8, $8, $5
 ; MIPS32R6-NEXT:    and $9, $7, $6
 ; MIPS32R6-NEXT:    or $9, $9, $8
-; MIPS32R6-NEXT:    sc $9, 0($2)
+; MIPS32R6-NEXT:    sc $9, 0($3)
 ; MIPS32R6-NEXT:    beqzc $9, $BB9_1
 ; MIPS32R6-NEXT:  # %bb.2: # %entry
-; MIPS32R6-NEXT:    and $1, $7, $5
-; MIPS32R6-NEXT:    srlv $1, $1, $3
-; MIPS32R6-NEXT:    seb $1, $1
+; MIPS32R6-NEXT:    and $2, $7, $5
+; MIPS32R6-NEXT:    srlv $2, $2, $1
+; MIPS32R6-NEXT:    seb $2, $2
 ; MIPS32R6-NEXT:  # %bb.3: # %entry
-; MIPS32R6-NEXT:    jr $ra
-; MIPS32R6-NEXT:    seb $2, $1
+; MIPS32R6-NEXT:    jrc $ra
 ;
 ; MIPS32R6O0-LABEL: AtomicLoadSub8:
 ; MIPS32R6O0:       # %bb.0: # %entry
 ; MIPS32R6O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32R6O0-NEXT:    addu $1, $2, $25
 ; MIPS32R6O0-NEXT:    # kill: def $v0 killed $a0

 ; MIPS32R6O0-NEXT:    beqzc $4, $BB9_1
 ; MIPS32R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS32R6O0-NEXT:    and $1, $2, $7
 ; MIPS32R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS32R6O0-NEXT:    seb $1, $1
 ; MIPS32R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS32R6O0-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
 ; MIPS32R6O0-NEXT:  # %bb.4: # %entry
-; MIPS32R6O0-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
-; MIPS32R6O0-NEXT:    seb $2, $1
+; MIPS32R6O0-NEXT:    lw $2, 4($sp) # 4-byte Folded Reload
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, 8
 ; MIPS32R6O0-NEXT:    jrc $ra
 ;
 ; MIPS4-LABEL: AtomicLoadSub8:
 ; MIPS4:       # %bb.0: # %entry
 ; MIPS4-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS4-NEXT:    daddu $1, $1, $25
 ; MIPS4-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS4-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS4-NEXT:    daddiu $2, $zero, -4
-; MIPS4-NEXT:    and $2, $1, $2
+; MIPS4-NEXT:    and $3, $1, $2
 ; MIPS4-NEXT:    andi $1, $1, 3
-; MIPS4-NEXT:    sll $3, $1, 3
-; MIPS4-NEXT:    ori $1, $zero, 255
-; MIPS4-NEXT:    sllv $5, $1, $3
+; MIPS4-NEXT:    sll $1, $1, 3
+; MIPS4-NEXT:    ori $2, $zero, 255
+; MIPS4-NEXT:    sllv $5, $2, $1
 ; MIPS4-NEXT:    nor $6, $zero, $5
-; MIPS4-NEXT:    sllv $4, $4, $3
+; MIPS4-NEXT:    sllv $4, $4, $1
 ; MIPS4-NEXT:  .LBB9_1: # %entry
 ; MIPS4-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS4-NEXT:    ll $7, 0($2)
+; MIPS4-NEXT:    ll $7, 0($3)
 ; MIPS4-NEXT:    subu $8, $7, $4
 ; MIPS4-NEXT:    and $8, $8, $5
 ; MIPS4-NEXT:    and $9, $7, $6
 ; MIPS4-NEXT:    or $9, $9, $8
-; MIPS4-NEXT:    sc $9, 0($2)
+; MIPS4-NEXT:    sc $9, 0($3)
 ; MIPS4-NEXT:    beqz $9, .LBB9_1
 ; MIPS4-NEXT:    nop
 ; MIPS4-NEXT:  # %bb.2: # %entry
-; MIPS4-NEXT:    and $1, $7, $5
-; MIPS4-NEXT:    srlv $1, $1, $3
-; MIPS4-NEXT:    sll $1, $1, 24
-; MIPS4-NEXT:    sra $1, $1, 24
+; MIPS4-NEXT:    and $2, $7, $5
+; MIPS4-NEXT:    srlv $2, $2, $1
+; MIPS4-NEXT:    sll $2, $2, 24
+; MIPS4-NEXT:    sra $2, $2, 24
 ; MIPS4-NEXT:  # %bb.3: # %entry
-; MIPS4-NEXT:    sll $1, $1, 24
 ; MIPS4-NEXT:    jr $ra
-; MIPS4-NEXT:    sra $2, $1, 24
+; MIPS4-NEXT:    nop
 ;
 ; MIPS64-LABEL: AtomicLoadSub8:
 ; MIPS64:       # %bb.0: # %entry
 ; MIPS64-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS64-NEXT:    daddu $1, $1, $25
 ; MIPS64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS64-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64-NEXT:    daddiu $2, $zero, -4
-; MIPS64-NEXT:    and $2, $1, $2
+; MIPS64-NEXT:    and $3, $1, $2
 ; MIPS64-NEXT:    andi $1, $1, 3
-; MIPS64-NEXT:    sll $3, $1, 3
-; MIPS64-NEXT:    ori $1, $zero, 255
-; MIPS64-NEXT:    sllv $5, $1, $3
+; MIPS64-NEXT:    sll $1, $1, 3
+; MIPS64-NEXT:    ori $2, $zero, 255
+; MIPS64-NEXT:    sllv $5, $2, $1
 ; MIPS64-NEXT:    nor $6, $zero, $5
-; MIPS64-NEXT:    sllv $4, $4, $3
+; MIPS64-NEXT:    sllv $4, $4, $1
 ; MIPS64-NEXT:  .LBB9_1: # %entry
 ; MIPS64-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64-NEXT:    ll $7, 0($2)
+; MIPS64-NEXT:    ll $7, 0($3)
 ; MIPS64-NEXT:    subu $8, $7, $4
 ; MIPS64-NEXT:    and $8, $8, $5
 ; MIPS64-NEXT:    and $9, $7, $6
 ; MIPS64-NEXT:    or $9, $9, $8
-; MIPS64-NEXT:    sc $9, 0($2)
+; MIPS64-NEXT:    sc $9, 0($3)
 ; MIPS64-NEXT:    beqz $9, .LBB9_1
 ; MIPS64-NEXT:    nop
 ; MIPS64-NEXT:  # %bb.2: # %entry
-; MIPS64-NEXT:    and $1, $7, $5
-; MIPS64-NEXT:    srlv $1, $1, $3
-; MIPS64-NEXT:    sll $1, $1, 24
-; MIPS64-NEXT:    sra $1, $1, 24
+; MIPS64-NEXT:    and $2, $7, $5
+; MIPS64-NEXT:    srlv $2, $2, $1
+; MIPS64-NEXT:    sll $2, $2, 24
+; MIPS64-NEXT:    sra $2, $2, 24
 ; MIPS64-NEXT:  # %bb.3: # %entry
-; MIPS64-NEXT:    sll $1, $1, 24
 ; MIPS64-NEXT:    jr $ra
-; MIPS64-NEXT:    sra $2, $1, 24
+; MIPS64-NEXT:    nop
 ;
 ; MIPS64R2-LABEL: AtomicLoadSub8:
 ; MIPS64R2:       # %bb.0: # %entry
 ; MIPS64R2-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS64R2-NEXT:    daddu $1, $1, $25
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS64R2-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64R2-NEXT:    daddiu $2, $zero, -4
-; MIPS64R2-NEXT:    and $2, $1, $2
+; MIPS64R2-NEXT:    and $3, $1, $2
 ; MIPS64R2-NEXT:    andi $1, $1, 3
-; MIPS64R2-NEXT:    sll $3, $1, 3
-; MIPS64R2-NEXT:    ori $1, $zero, 255
-; MIPS64R2-NEXT:    sllv $5, $1, $3
+; MIPS64R2-NEXT:    sll $1, $1, 3
+; MIPS64R2-NEXT:    ori $2, $zero, 255
+; MIPS64R2-NEXT:    sllv $5, $2, $1
 ; MIPS64R2-NEXT:    nor $6, $zero, $5
-; MIPS64R2-NEXT:    sllv $4, $4, $3
+; MIPS64R2-NEXT:    sllv $4, $4, $1
 ; MIPS64R2-NEXT:  .LBB9_1: # %entry
 ; MIPS64R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R2-NEXT:    ll $7, 0($2)
+; MIPS64R2-NEXT:    ll $7, 0($3)
 ; MIPS64R2-NEXT:    subu $8, $7, $4
 ; MIPS64R2-NEXT:    and $8, $8, $5
 ; MIPS64R2-NEXT:    and $9, $7, $6
 ; MIPS64R2-NEXT:    or $9, $9, $8
-; MIPS64R2-NEXT:    sc $9, 0($2)
+; MIPS64R2-NEXT:    sc $9, 0($3)
 ; MIPS64R2-NEXT:    beqz $9, .LBB9_1
 ; MIPS64R2-NEXT:    nop
 ; MIPS64R2-NEXT:  # %bb.2: # %entry
-; MIPS64R2-NEXT:    and $1, $7, $5
-; MIPS64R2-NEXT:    srlv $1, $1, $3
-; MIPS64R2-NEXT:    seb $1, $1
+; MIPS64R2-NEXT:    and $2, $7, $5
+; MIPS64R2-NEXT:    srlv $2, $2, $1
+; MIPS64R2-NEXT:    seb $2, $2
 ; MIPS64R2-NEXT:  # %bb.3: # %entry
 ; MIPS64R2-NEXT:    jr $ra
-; MIPS64R2-NEXT:    seb $2, $1
+; MIPS64R2-NEXT:    nop
 ;
 ; MIPS64R6-LABEL: AtomicLoadSub8:
 ; MIPS64R6:       # %bb.0: # %entry
 ; MIPS64R6-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64R6-NEXT:    daddiu $2, $zero, -4
-; MIPS64R6-NEXT:    and $2, $1, $2
+; MIPS64R6-NEXT:    and $3, $1, $2
 ; MIPS64R6-NEXT:    andi $1, $1, 3
-; MIPS64R6-NEXT:    sll $3, $1, 3
-; MIPS64R6-NEXT:    ori $1, $zero, 255
-; MIPS64R6-NEXT:    sllv $5, $1, $3
+; MIPS64R6-NEXT:    sll $1, $1, 3
+; MIPS64R6-NEXT:    ori $2, $zero, 255
+; MIPS64R6-NEXT:    sllv $5, $2, $1
 ; MIPS64R6-NEXT:    nor $6, $zero, $5
-; MIPS64R6-NEXT:    sllv $4, $4, $3
+; MIPS64R6-NEXT:    sllv $4, $4, $1
 ; MIPS64R6-NEXT:  .LBB9_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R6-NEXT:    ll $7, 0($2)
+; MIPS64R6-NEXT:    ll $7, 0($3)
 ; MIPS64R6-NEXT:    subu $8, $7, $4
 ; MIPS64R6-NEXT:    and $8, $8, $5
 ; MIPS64R6-NEXT:    and $9, $7, $6
 ; MIPS64R6-NEXT:    or $9, $9, $8
-; MIPS64R6-NEXT:    sc $9, 0($2)
+; MIPS64R6-NEXT:    sc $9, 0($3)
 ; MIPS64R6-NEXT:    beqzc $9, .LBB9_1
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
-; MIPS64R6-NEXT:    and $1, $7, $5
-; MIPS64R6-NEXT:    srlv $1, $1, $3
-; MIPS64R6-NEXT:    seb $1, $1
+; MIPS64R6-NEXT:    and $2, $7, $5
+; MIPS64R6-NEXT:    srlv $2, $2, $1
+; MIPS64R6-NEXT:    seb $2, $2
 ; MIPS64R6-NEXT:  # %bb.3: # %entry
-; MIPS64R6-NEXT:    jr $ra
-; MIPS64R6-NEXT:    seb $2, $1
+; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadSub8:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $2, $1, %lo(%neg(%gp_rel(AtomicLoadSub8)))
 ; MIPS64R6O0-NEXT:    move $1, $4

 ; MIPS64R6O0-NEXT:    beqzc $4, .LBB9_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    and $1, $2, $7
 ; MIPS64R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS64R6O0-NEXT:    seb $1, $1
 ; MIPS64R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS64R6O0-NEXT:    sw $1, 12($sp) # 4-byte Folded Spill
 ; MIPS64R6O0-NEXT:  # %bb.4: # %entry
-; MIPS64R6O0-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
-; MIPS64R6O0-NEXT:    seb $2, $1
+; MIPS64R6O0-NEXT:    lw $2, 12($sp) # 4-byte Folded Reload
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; MM32-LABEL: AtomicLoadSub8:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    lui $2, %hi(_gp_disp)
 ; MM32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MM32-NEXT:    addu $2, $2, $25
 ; MM32-NEXT:    lw $1, %got(y)($2)
 ; MM32-NEXT:    addiu $2, $zero, -4
-; MM32-NEXT:    and $2, $1, $2
+; MM32-NEXT:    and $3, $1, $2
 ; MM32-NEXT:    andi $1, $1, 3
-; MM32-NEXT:    sll $3, $1, 3
-; MM32-NEXT:    ori $1, $zero, 255
-; MM32-NEXT:    sllv $5, $1, $3
+; MM32-NEXT:    sll $1, $1, 3
+; MM32-NEXT:    ori $2, $zero, 255
+; MM32-NEXT:    sllv $5, $2, $1
 ; MM32-NEXT:    nor $6, $zero, $5
-; MM32-NEXT:    sllv $4, $4, $3
+; MM32-NEXT:    sllv $4, $4, $1
 ; MM32-NEXT:  $BB9_1: # %entry
 ; MM32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MM32-NEXT:    ll $7, 0($2)
+; MM32-NEXT:    ll $7, 0($3)
 ; MM32-NEXT:    subu $8, $7, $4
 ; MM32-NEXT:    and $8, $8, $5
 ; MM32-NEXT:    and $9, $7, $6
 ; MM32-NEXT:    or $9, $9, $8
-; MM32-NEXT:    sc $9, 0($2)
+; MM32-NEXT:    sc $9, 0($3)
 ; MM32-NEXT:    beqzc $9, $BB9_1
 ; MM32-NEXT:  # %bb.2: # %entry
-; MM32-NEXT:    and $1, $7, $5
-; MM32-NEXT:    srlv $1, $1, $3
-; MM32-NEXT:    seb $1, $1
+; MM32-NEXT:    and $2, $7, $5
+; MM32-NEXT:    srlv $2, $2, $1
+; MM32-NEXT:    seb $2, $2
 ; MM32-NEXT:  # %bb.3: # %entry
-; MM32-NEXT:    jr $ra
-; MM32-NEXT:    seb $2, $1
+; MM32-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadSub8:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $2, %hi(_gp_disp)
 ; O1-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O1-NEXT:    addu $1, $2, $25
 ; O1-NEXT:    lw $1, %got(y)($1)
 ; O1-NEXT:    addiu $2, $zero, -4
-; O1-NEXT:    and $2, $1, $2
+; O1-NEXT:    and $3, $1, $2
 ; O1-NEXT:    andi $1, $1, 3
-; O1-NEXT:    sll $3, $1, 3
-; O1-NEXT:    ori $1, $zero, 255
-; O1-NEXT:    sllv $5, $1, $3
+; O1-NEXT:    sll $1, $1, 3
+; O1-NEXT:    ori $2, $zero, 255
+; O1-NEXT:    sllv $5, $2, $1
 ; O1-NEXT:    nor $6, $zero, $5
-; O1-NEXT:    sllv $4, $4, $3
+; O1-NEXT:    sllv $4, $4, $1
 ; O1-NEXT:  $BB9_1: # %entry
 ; O1-NEXT:    # =>This Inner Loop Header: Depth=1
-; O1-NEXT:    ll $7, 0($2)
+; O1-NEXT:    ll $7, 0($3)
 ; O1-NEXT:    subu $8, $7, $4
 ; O1-NEXT:    and $8, $8, $5
 ; O1-NEXT:    and $9, $7, $6
 ; O1-NEXT:    or $9, $9, $8
-; O1-NEXT:    sc $9, 0($2)
+; O1-NEXT:    sc $9, 0($3)
 ; O1-NEXT:    beqz $9, $BB9_1
 ; O1-NEXT:    nop
 ; O1-NEXT:  # %bb.2: # %entry
-; O1-NEXT:    and $1, $7, $5
-; O1-NEXT:    srlv $1, $1, $3
-; O1-NEXT:    sll $1, $1, 24
-; O1-NEXT:    sra $1, $1, 24
+; O1-NEXT:    and $2, $7, $5
+; O1-NEXT:    srlv $2, $2, $1
+; O1-NEXT:    sll $2, $2, 24
+; O1-NEXT:    sra $2, $2, 24
 ; O1-NEXT:  # %bb.3: # %entry
-; O1-NEXT:    sll $1, $1, 24
 ; O1-NEXT:    jr $ra
-; O1-NEXT:    sra $2, $1, 24
+; O1-NEXT:    nop
 ;
 ; O2-LABEL: AtomicLoadSub8:
 ; O2:       # %bb.0: # %entry
 ; O2-NEXT:    lui $2, %hi(_gp_disp)
 ; O2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O2-NEXT:    addu $1, $2, $25
 ; O2-NEXT:    lw $1, %got(y)($1)
 ; O2-NEXT:    addiu $2, $zero, -4
-; O2-NEXT:    and $2, $1, $2
+; O2-NEXT:    and $3, $1, $2
 ; O2-NEXT:    andi $1, $1, 3
-; O2-NEXT:    sll $3, $1, 3
-; O2-NEXT:    ori $1, $zero, 255
-; O2-NEXT:    sllv $5, $1, $3
+; O2-NEXT:    sll $1, $1, 3
+; O2-NEXT:    ori $2, $zero, 255
+; O2-NEXT:    sllv $5, $2, $1
 ; O2-NEXT:    nor $6, $zero, $5
-; O2-NEXT:    sllv $4, $4, $3
+; O2-NEXT:    sllv $4, $4, $1
 ; O2-NEXT:  $BB9_1: # %entry
 ; O2-NEXT:    # =>This Inner Loop Header: Depth=1
-; O2-NEXT:    ll $7, 0($2)
+; O2-NEXT:    ll $7, 0($3)
 ; O2-NEXT:    subu $8, $7, $4
 ; O2-NEXT:    and $8, $8, $5
 ; O2-NEXT:    and $9, $7, $6
 ; O2-NEXT:    or $9, $9, $8
-; O2-NEXT:    sc $9, 0($2)
+; O2-NEXT:    sc $9, 0($3)
 ; O2-NEXT:    beqz $9, $BB9_1
 ; O2-NEXT:    nop
 ; O2-NEXT:  # %bb.2: # %entry
-; O2-NEXT:    and $1, $7, $5
-; O2-NEXT:    srlv $1, $1, $3
-; O2-NEXT:    sll $1, $1, 24
-; O2-NEXT:    sra $1, $1, 24
+; O2-NEXT:    and $2, $7, $5
+; O2-NEXT:    srlv $2, $2, $1
+; O2-NEXT:    sll $2, $2, 24
+; O2-NEXT:    sra $2, $2, 24
 ; O2-NEXT:  # %bb.3: # %entry
-; O2-NEXT:    sll $1, $1, 24
 ; O2-NEXT:    jr $ra
-; O2-NEXT:    sra $2, $1, 24
+; O2-NEXT:    nop
 ;
 ; O3-LABEL: AtomicLoadSub8:
 ; O3:       # %bb.0: # %entry
 ; O3-NEXT:    lui $2, %hi(_gp_disp)
 ; O3-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O3-NEXT:    addu $1, $2, $25
 ; O3-NEXT:    addiu $2, $zero, -4
 ; O3-NEXT:    lw $1, %got(y)($1)
-; O3-NEXT:    and $2, $1, $2
+; O3-NEXT:    and $3, $1, $2
 ; O3-NEXT:    andi $1, $1, 3
-; O3-NEXT:    sll $3, $1, 3
-; O3-NEXT:    ori $1, $zero, 255
-; O3-NEXT:    sllv $5, $1, $3
-; O3-NEXT:    sllv $4, $4, $3
+; O3-NEXT:    ori $2, $zero, 255
+; O3-NEXT:    sll $1, $1, 3
+; O3-NEXT:    sllv $5, $2, $1
+; O3-NEXT:    sllv $4, $4, $1
 ; O3-NEXT:    nor $6, $zero, $5
 ; O3-NEXT:  $BB9_1: # %entry
 ; O3-NEXT:    # =>This Inner Loop Header: Depth=1
-; O3-NEXT:    ll $7, 0($2)
+; O3-NEXT:    ll $7, 0($3)
 ; O3-NEXT:    subu $8, $7, $4
 ; O3-NEXT:    and $8, $8, $5
 ; O3-NEXT:    and $9, $7, $6
 ; O3-NEXT:    or $9, $9, $8
-; O3-NEXT:    sc $9, 0($2)
+; O3-NEXT:    sc $9, 0($3)
 ; O3-NEXT:    beqz $9, $BB9_1
 ; O3-NEXT:    nop
 ; O3-NEXT:  # %bb.2: # %entry
-; O3-NEXT:    and $1, $7, $5
-; O3-NEXT:    srlv $1, $1, $3
-; O3-NEXT:    sll $1, $1, 24
-; O3-NEXT:    sra $1, $1, 24
+; O3-NEXT:    and $2, $7, $5
+; O3-NEXT:    srlv $2, $2, $1
+; O3-NEXT:    sll $2, $2, 24
+; O3-NEXT:    sra $2, $2, 24
 ; O3-NEXT:  # %bb.3: # %entry
-; O3-NEXT:    sll $1, $1, 24
 ; O3-NEXT:    jr $ra
-; O3-NEXT:    sra $2, $1, 24
+; O3-NEXT:    nop
 ;
 ; MIPS32EB-LABEL: AtomicLoadSub8:
 ; MIPS32EB:       # %bb.0: # %entry
 ; MIPS32EB-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32EB-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32EB-NEXT:    addu $1, $2, $25
 ; MIPS32EB-NEXT:    lw $1, %got(y)($1)
 ; MIPS32EB-NEXT:    addiu $2, $zero, -4
-; MIPS32EB-NEXT:    and $2, $1, $2
+; MIPS32EB-NEXT:    and $3, $1, $2
 ; MIPS32EB-NEXT:    andi $1, $1, 3
 ; MIPS32EB-NEXT:    xori $1, $1, 3
-; MIPS32EB-NEXT:    sll $3, $1, 3
-; MIPS32EB-NEXT:    ori $1, $zero, 255
-; MIPS32EB-NEXT:    sllv $5, $1, $3
+; MIPS32EB-NEXT:    sll $1, $1, 3
+; MIPS32EB-NEXT:    ori $2, $zero, 255
+; MIPS32EB-NEXT:    sllv $5, $2, $1
 ; MIPS32EB-NEXT:    nor $6, $zero, $5
-; MIPS32EB-NEXT:    sllv $4, $4, $3
+; MIPS32EB-NEXT:    sllv $4, $4, $1
 ; MIPS32EB-NEXT:  $BB9_1: # %entry
 ; MIPS32EB-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32EB-NEXT:    ll $7, 0($2)
+; MIPS32EB-NEXT:    ll $7, 0($3)
 ; MIPS32EB-NEXT:    subu $8, $7, $4
 ; MIPS32EB-NEXT:    and $8, $8, $5
 ; MIPS32EB-NEXT:    and $9, $7, $6
 ; MIPS32EB-NEXT:    or $9, $9, $8
-; MIPS32EB-NEXT:    sc $9, 0($2)
+; MIPS32EB-NEXT:    sc $9, 0($3)
 ; MIPS32EB-NEXT:    beqz $9, $BB9_1
 ; MIPS32EB-NEXT:    nop
 ; MIPS32EB-NEXT:  # %bb.2: # %entry
-; MIPS32EB-NEXT:    and $1, $7, $5
-; MIPS32EB-NEXT:    srlv $1, $1, $3
-; MIPS32EB-NEXT:    sll $1, $1, 24
-; MIPS32EB-NEXT:    sra $1, $1, 24
+; MIPS32EB-NEXT:    and $2, $7, $5
+; MIPS32EB-NEXT:    srlv $2, $2, $1
+; MIPS32EB-NEXT:    sll $2, $2, 24
+; MIPS32EB-NEXT:    sra $2, $2, 24
 ; MIPS32EB-NEXT:  # %bb.3: # %entry
-; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    jr $ra
-; MIPS32EB-NEXT:    sra $2, $1, 24
+; MIPS32EB-NEXT:    nop
 entry:
   %0 = atomicrmw sub i8* @y, i8 %incr monotonic
   ret i8 %0
 
 }
 
 define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
 ; MIPS32-LABEL: AtomicLoadNand8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32-NEXT:    addu $1, $2, $25
 ; MIPS32-NEXT:    lw $1, %got(y)($1)
 ; MIPS32-NEXT:    addiu $2, $zero, -4
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    and $3, $1, $2
 ; MIPS32-NEXT:    andi $1, $1, 3
-; MIPS32-NEXT:    sll $3, $1, 3
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    sllv $5, $1, $3
+; MIPS32-NEXT:    sll $1, $1, 3
+; MIPS32-NEXT:    ori $2, $zero, 255
+; MIPS32-NEXT:    sllv $5, $2, $1
 ; MIPS32-NEXT:    nor $6, $zero, $5
-; MIPS32-NEXT:    sllv $4, $4, $3
+; MIPS32-NEXT:    sllv $4, $4, $1
 ; MIPS32-NEXT:  $BB10_1: # %entry
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32-NEXT:    ll $7, 0($2)
+; MIPS32-NEXT:    ll $7, 0($3)
 ; MIPS32-NEXT:    and $8, $7, $4
 ; MIPS32-NEXT:    nor $8, $zero, $8
 ; MIPS32-NEXT:    and $8, $8, $5
 ; MIPS32-NEXT:    and $9, $7, $6
 ; MIPS32-NEXT:    or $9, $9, $8
-; MIPS32-NEXT:    sc $9, 0($2)
+; MIPS32-NEXT:    sc $9, 0($3)
 ; MIPS32-NEXT:    beqz $9, $BB10_1
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %entry
-; MIPS32-NEXT:    and $1, $7, $5
-; MIPS32-NEXT:    srlv $1, $1, $3
-; MIPS32-NEXT:    sll $1, $1, 24
-; MIPS32-NEXT:    sra $1, $1, 24
+; MIPS32-NEXT:    and $2, $7, $5
+; MIPS32-NEXT:    srlv $2, $2, $1
+; MIPS32-NEXT:    sll $2, $2, 24
+; MIPS32-NEXT:    sra $2, $2, 24
 ; MIPS32-NEXT:  # %bb.3: # %entry
-; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    jr $ra
-; MIPS32-NEXT:    sra $2, $1, 24
+; MIPS32-NEXT:    nop
 ;
 ; MIPS32O0-LABEL: AtomicLoadNand8:
 ; MIPS32O0:       # %bb.0: # %entry
 ; MIPS32O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32O0-NEXT:    addu $1, $2, $25
 ; MIPS32O0-NEXT:    lw $1, %got(y)($1)

 ;
 ; MIPS32R2-LABEL: AtomicLoadNand8:
 ; MIPS32R2:       # %bb.0: # %entry
 ; MIPS32R2-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R2-NEXT:    addu $1, $2, $25
 ; MIPS32R2-NEXT:    lw $1, %got(y)($1)
 ; MIPS32R2-NEXT:    addiu $2, $zero, -4
-; MIPS32R2-NEXT:    and $2, $1, $2
+; MIPS32R2-NEXT:    and $3, $1, $2
 ; MIPS32R2-NEXT:    andi $1, $1, 3
-; MIPS32R2-NEXT:    sll $3, $1, 3
-; MIPS32R2-NEXT:    ori $1, $zero, 255
-; MIPS32R2-NEXT:    sllv $5, $1, $3
+; MIPS32R2-NEXT:    sll $1, $1, 3
+; MIPS32R2-NEXT:    ori $2, $zero, 255
+; MIPS32R2-NEXT:    sllv $5, $2, $1
 ; MIPS32R2-NEXT:    nor $6, $zero, $5
-; MIPS32R2-NEXT:    sllv $4, $4, $3
+; MIPS32R2-NEXT:    sllv $4, $4, $1
 ; MIPS32R2-NEXT:  $BB10_1: # %entry
 ; MIPS32R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R2-NEXT:    ll $7, 0($2)
+; MIPS32R2-NEXT:    ll $7, 0($3)
 ; MIPS32R2-NEXT:    and $8, $7, $4
 ; MIPS32R2-NEXT:    nor $8, $zero, $8
 ; MIPS32R2-NEXT:    and $8, $8, $5
 ; MIPS32R2-NEXT:    and $9, $7, $6
 ; MIPS32R2-NEXT:    or $9, $9, $8
-; MIPS32R2-NEXT:    sc $9, 0($2)
+; MIPS32R2-NEXT:    sc $9, 0($3)
 ; MIPS32R2-NEXT:    beqz $9, $BB10_1
 ; MIPS32R2-NEXT:    nop
 ; MIPS32R2-NEXT:  # %bb.2: # %entry
-; MIPS32R2-NEXT:    and $1, $7, $5
-; MIPS32R2-NEXT:    srlv $1, $1, $3
-; MIPS32R2-NEXT:    seb $1, $1
+; MIPS32R2-NEXT:    and $2, $7, $5
+; MIPS32R2-NEXT:    srlv $2, $2, $1
+; MIPS32R2-NEXT:    seb $2, $2
 ; MIPS32R2-NEXT:  # %bb.3: # %entry
 ; MIPS32R2-NEXT:    jr $ra
-; MIPS32R2-NEXT:    seb $2, $1
+; MIPS32R2-NEXT:    nop
 ;
 ; MIPS32R6-LABEL: AtomicLoadNand8:
 ; MIPS32R6:       # %bb.0: # %entry
 ; MIPS32R6-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6-NEXT:    addu $1, $2, $25
 ; MIPS32R6-NEXT:    lw $1, %got(y)($1)
 ; MIPS32R6-NEXT:    addiu $2, $zero, -4
-; MIPS32R6-NEXT:    and $2, $1, $2
+; MIPS32R6-NEXT:    and $3, $1, $2
 ; MIPS32R6-NEXT:    andi $1, $1, 3
-; MIPS32R6-NEXT:    sll $3, $1, 3
-; MIPS32R6-NEXT:    ori $1, $zero, 255
-; MIPS32R6-NEXT:    sllv $5, $1, $3
+; MIPS32R6-NEXT:    sll $1, $1, 3
+; MIPS32R6-NEXT:    ori $2, $zero, 255
+; MIPS32R6-NEXT:    sllv $5, $2, $1
 ; MIPS32R6-NEXT:    nor $6, $zero, $5
-; MIPS32R6-NEXT:    sllv $4, $4, $3
+; MIPS32R6-NEXT:    sllv $4, $4, $1
 ; MIPS32R6-NEXT:  $BB10_1: # %entry
 ; MIPS32R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R6-NEXT:    ll $7, 0($2)
+; MIPS32R6-NEXT:    ll $7, 0($3)
 ; MIPS32R6-NEXT:    and $8, $7, $4
 ; MIPS32R6-NEXT:    nor $8, $zero, $8
 ; MIPS32R6-NEXT:    and $8, $8, $5
 ; MIPS32R6-NEXT:    and $9, $7, $6
 ; MIPS32R6-NEXT:    or $9, $9, $8
-; MIPS32R6-NEXT:    sc $9, 0($2)
+; MIPS32R6-NEXT:    sc $9, 0($3)
 ; MIPS32R6-NEXT:    beqzc $9, $BB10_1
 ; MIPS32R6-NEXT:  # %bb.2: # %entry
-; MIPS32R6-NEXT:    and $1, $7, $5
-; MIPS32R6-NEXT:    srlv $1, $1, $3
-; MIPS32R6-NEXT:    seb $1, $1
+; MIPS32R6-NEXT:    and $2, $7, $5
+; MIPS32R6-NEXT:    srlv $2, $2, $1
+; MIPS32R6-NEXT:    seb $2, $2
 ; MIPS32R6-NEXT:  # %bb.3: # %entry
-; MIPS32R6-NEXT:    jr $ra
-; MIPS32R6-NEXT:    seb $2, $1
+; MIPS32R6-NEXT:    jrc $ra
 ;
 ; MIPS32R6O0-LABEL: AtomicLoadNand8:
 ; MIPS32R6O0:       # %bb.0: # %entry
 ; MIPS32R6O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32R6O0-NEXT:    addu $1, $2, $25
 ; MIPS32R6O0-NEXT:    # kill: def $v0 killed $a0

 ; MIPS32R6O0-NEXT:    beqzc $4, $BB10_1
 ; MIPS32R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS32R6O0-NEXT:    and $1, $2, $7
 ; MIPS32R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS32R6O0-NEXT:    seb $1, $1
 ; MIPS32R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS32R6O0-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
 ; MIPS32R6O0-NEXT:  # %bb.4: # %entry
-; MIPS32R6O0-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
-; MIPS32R6O0-NEXT:    seb $2, $1
+; MIPS32R6O0-NEXT:    lw $2, 4($sp) # 4-byte Folded Reload
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, 8
 ; MIPS32R6O0-NEXT:    jrc $ra
 ;
 ; MIPS4-LABEL: AtomicLoadNand8:
 ; MIPS4:       # %bb.0: # %entry
 ; MIPS4-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS4-NEXT:    daddu $1, $1, $25
 ; MIPS4-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS4-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS4-NEXT:    daddiu $2, $zero, -4
-; MIPS4-NEXT:    and $2, $1, $2
+; MIPS4-NEXT:    and $3, $1, $2
 ; MIPS4-NEXT:    andi $1, $1, 3
-; MIPS4-NEXT:    sll $3, $1, 3
-; MIPS4-NEXT:    ori $1, $zero, 255
-; MIPS4-NEXT:    sllv $5, $1, $3
+; MIPS4-NEXT:    sll $1, $1, 3
+; MIPS4-NEXT:    ori $2, $zero, 255
+; MIPS4-NEXT:    sllv $5, $2, $1
 ; MIPS4-NEXT:    nor $6, $zero, $5
-; MIPS4-NEXT:    sllv $4, $4, $3
+; MIPS4-NEXT:    sllv $4, $4, $1
 ; MIPS4-NEXT:  .LBB10_1: # %entry
 ; MIPS4-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS4-NEXT:    ll $7, 0($2)
+; MIPS4-NEXT:    ll $7, 0($3)
 ; MIPS4-NEXT:    and $8, $7, $4
 ; MIPS4-NEXT:    nor $8, $zero, $8
 ; MIPS4-NEXT:    and $8, $8, $5
 ; MIPS4-NEXT:    and $9, $7, $6
 ; MIPS4-NEXT:    or $9, $9, $8
-; MIPS4-NEXT:    sc $9, 0($2)
+; MIPS4-NEXT:    sc $9, 0($3)
 ; MIPS4-NEXT:    beqz $9, .LBB10_1
 ; MIPS4-NEXT:    nop
 ; MIPS4-NEXT:  # %bb.2: # %entry
-; MIPS4-NEXT:    and $1, $7, $5
-; MIPS4-NEXT:    srlv $1, $1, $3
-; MIPS4-NEXT:    sll $1, $1, 24
-; MIPS4-NEXT:    sra $1, $1, 24
+; MIPS4-NEXT:    and $2, $7, $5
+; MIPS4-NEXT:    srlv $2, $2, $1
+; MIPS4-NEXT:    sll $2, $2, 24
+; MIPS4-NEXT:    sra $2, $2, 24
 ; MIPS4-NEXT:  # %bb.3: # %entry
-; MIPS4-NEXT:    sll $1, $1, 24
 ; MIPS4-NEXT:    jr $ra
-; MIPS4-NEXT:    sra $2, $1, 24
+; MIPS4-NEXT:    nop
 ;
 ; MIPS64-LABEL: AtomicLoadNand8:
 ; MIPS64:       # %bb.0: # %entry
 ; MIPS64-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS64-NEXT:    daddu $1, $1, $25
 ; MIPS64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS64-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64-NEXT:    daddiu $2, $zero, -4
-; MIPS64-NEXT:    and $2, $1, $2
+; MIPS64-NEXT:    and $3, $1, $2
 ; MIPS64-NEXT:    andi $1, $1, 3
-; MIPS64-NEXT:    sll $3, $1, 3
-; MIPS64-NEXT:    ori $1, $zero, 255
-; MIPS64-NEXT:    sllv $5, $1, $3
+; MIPS64-NEXT:    sll $1, $1, 3
+; MIPS64-NEXT:    ori $2, $zero, 255
+; MIPS64-NEXT:    sllv $5, $2, $1
 ; MIPS64-NEXT:    nor $6, $zero, $5
-; MIPS64-NEXT:    sllv $4, $4, $3
+; MIPS64-NEXT:    sllv $4, $4, $1
 ; MIPS64-NEXT:  .LBB10_1: # %entry
 ; MIPS64-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64-NEXT:    ll $7, 0($2)
+; MIPS64-NEXT:    ll $7, 0($3)
 ; MIPS64-NEXT:    and $8, $7, $4
 ; MIPS64-NEXT:    nor $8, $zero, $8
 ; MIPS64-NEXT:    and $8, $8, $5
 ; MIPS64-NEXT:    and $9, $7, $6
 ; MIPS64-NEXT:    or $9, $9, $8
-; MIPS64-NEXT:    sc $9, 0($2)
+; MIPS64-NEXT:    sc $9, 0($3)
 ; MIPS64-NEXT:    beqz $9, .LBB10_1
 ; MIPS64-NEXT:    nop
 ; MIPS64-NEXT:  # %bb.2: # %entry
-; MIPS64-NEXT:    and $1, $7, $5
-; MIPS64-NEXT:    srlv $1, $1, $3
-; MIPS64-NEXT:    sll $1, $1, 24
-; MIPS64-NEXT:    sra $1, $1, 24
+; MIPS64-NEXT:    and $2, $7, $5
+; MIPS64-NEXT:    srlv $2, $2, $1
+; MIPS64-NEXT:    sll $2, $2, 24
+; MIPS64-NEXT:    sra $2, $2, 24
 ; MIPS64-NEXT:  # %bb.3: # %entry
-; MIPS64-NEXT:    sll $1, $1, 24
 ; MIPS64-NEXT:    jr $ra
-; MIPS64-NEXT:    sra $2, $1, 24
+; MIPS64-NEXT:    nop
 ;
 ; MIPS64R2-LABEL: AtomicLoadNand8:
 ; MIPS64R2:       # %bb.0: # %entry
 ; MIPS64R2-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS64R2-NEXT:    daddu $1, $1, $25
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS64R2-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64R2-NEXT:    daddiu $2, $zero, -4
-; MIPS64R2-NEXT:    and $2, $1, $2
+; MIPS64R2-NEXT:    and $3, $1, $2
 ; MIPS64R2-NEXT:    andi $1, $1, 3
-; MIPS64R2-NEXT:    sll $3, $1, 3
-; MIPS64R2-NEXT:    ori $1, $zero, 255
-; MIPS64R2-NEXT:    sllv $5, $1, $3
+; MIPS64R2-NEXT:    sll $1, $1, 3
+; MIPS64R2-NEXT:    ori $2, $zero, 255
+; MIPS64R2-NEXT:    sllv $5, $2, $1
 ; MIPS64R2-NEXT:    nor $6, $zero, $5
-; MIPS64R2-NEXT:    sllv $4, $4, $3
+; MIPS64R2-NEXT:    sllv $4, $4, $1
 ; MIPS64R2-NEXT:  .LBB10_1: # %entry
 ; MIPS64R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R2-NEXT:    ll $7, 0($2)
+; MIPS64R2-NEXT:    ll $7, 0($3)
 ; MIPS64R2-NEXT:    and $8, $7, $4
 ; MIPS64R2-NEXT:    nor $8, $zero, $8
 ; MIPS64R2-NEXT:    and $8, $8, $5
 ; MIPS64R2-NEXT:    and $9, $7, $6
 ; MIPS64R2-NEXT:    or $9, $9, $8
-; MIPS64R2-NEXT:    sc $9, 0($2)
+; MIPS64R2-NEXT:    sc $9, 0($3)
 ; MIPS64R2-NEXT:    beqz $9, .LBB10_1
 ; MIPS64R2-NEXT:    nop
 ; MIPS64R2-NEXT:  # %bb.2: # %entry
-; MIPS64R2-NEXT:    and $1, $7, $5
-; MIPS64R2-NEXT:    srlv $1, $1, $3
-; MIPS64R2-NEXT:    seb $1, $1
+; MIPS64R2-NEXT:    and $2, $7, $5
+; MIPS64R2-NEXT:    srlv $2, $2, $1
+; MIPS64R2-NEXT:    seb $2, $2
 ; MIPS64R2-NEXT:  # %bb.3: # %entry
 ; MIPS64R2-NEXT:    jr $ra
-; MIPS64R2-NEXT:    seb $2, $1
+; MIPS64R2-NEXT:    nop
 ;
 ; MIPS64R6-LABEL: AtomicLoadNand8:
 ; MIPS64R6:       # %bb.0: # %entry
 ; MIPS64R6-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64R6-NEXT:    daddiu $2, $zero, -4
-; MIPS64R6-NEXT:    and $2, $1, $2
+; MIPS64R6-NEXT:    and $3, $1, $2
 ; MIPS64R6-NEXT:    andi $1, $1, 3
-; MIPS64R6-NEXT:    sll $3, $1, 3
-; MIPS64R6-NEXT:    ori $1, $zero, 255
-; MIPS64R6-NEXT:    sllv $5, $1, $3
+; MIPS64R6-NEXT:    sll $1, $1, 3
+; MIPS64R6-NEXT:    ori $2, $zero, 255
+; MIPS64R6-NEXT:    sllv $5, $2, $1
 ; MIPS64R6-NEXT:    nor $6, $zero, $5
-; MIPS64R6-NEXT:    sllv $4, $4, $3
+; MIPS64R6-NEXT:    sllv $4, $4, $1
 ; MIPS64R6-NEXT:  .LBB10_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R6-NEXT:    ll $7, 0($2)
+; MIPS64R6-NEXT:    ll $7, 0($3)
 ; MIPS64R6-NEXT:    and $8, $7, $4
 ; MIPS64R6-NEXT:    nor $8, $zero, $8
 ; MIPS64R6-NEXT:    and $8, $8, $5
 ; MIPS64R6-NEXT:    and $9, $7, $6
 ; MIPS64R6-NEXT:    or $9, $9, $8
-; MIPS64R6-NEXT:    sc $9, 0($2)
+; MIPS64R6-NEXT:    sc $9, 0($3)
 ; MIPS64R6-NEXT:    beqzc $9, .LBB10_1
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
-; MIPS64R6-NEXT:    and $1, $7, $5
-; MIPS64R6-NEXT:    srlv $1, $1, $3
-; MIPS64R6-NEXT:    seb $1, $1
+; MIPS64R6-NEXT:    and $2, $7, $5
+; MIPS64R6-NEXT:    srlv $2, $2, $1
+; MIPS64R6-NEXT:    seb $2, $2
 ; MIPS64R6-NEXT:  # %bb.3: # %entry
-; MIPS64R6-NEXT:    jr $ra
-; MIPS64R6-NEXT:    seb $2, $1
+; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadNand8:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $2, $1, %lo(%neg(%gp_rel(AtomicLoadNand8)))
 ; MIPS64R6O0-NEXT:    move $1, $4

 ; MIPS64R6O0-NEXT:    beqzc $4, .LBB10_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    and $1, $2, $7
 ; MIPS64R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS64R6O0-NEXT:    seb $1, $1
 ; MIPS64R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS64R6O0-NEXT:    sw $1, 12($sp) # 4-byte Folded Spill
 ; MIPS64R6O0-NEXT:  # %bb.4: # %entry
-; MIPS64R6O0-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
-; MIPS64R6O0-NEXT:    seb $2, $1
+; MIPS64R6O0-NEXT:    lw $2, 12($sp) # 4-byte Folded Reload
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; MM32-LABEL: AtomicLoadNand8:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    lui $2, %hi(_gp_disp)
 ; MM32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MM32-NEXT:    addu $2, $2, $25
 ; MM32-NEXT:    lw $1, %got(y)($2)
 ; MM32-NEXT:    addiu $2, $zero, -4
-; MM32-NEXT:    and $2, $1, $2
+; MM32-NEXT:    and $3, $1, $2
 ; MM32-NEXT:    andi $1, $1, 3
-; MM32-NEXT:    sll $3, $1, 3
-; MM32-NEXT:    ori $1, $zero, 255
-; MM32-NEXT:    sllv $5, $1, $3
+; MM32-NEXT:    sll $1, $1, 3
+; MM32-NEXT:    ori $2, $zero, 255
+; MM32-NEXT:    sllv $5, $2, $1
 ; MM32-NEXT:    nor $6, $zero, $5
-; MM32-NEXT:    sllv $4, $4, $3
+; MM32-NEXT:    sllv $4, $4, $1
 ; MM32-NEXT:  $BB10_1: # %entry
 ; MM32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MM32-NEXT:    ll $7, 0($2)
+; MM32-NEXT:    ll $7, 0($3)
 ; MM32-NEXT:    and $8, $7, $4
 ; MM32-NEXT:    nor $8, $zero, $8
 ; MM32-NEXT:    and $8, $8, $5
 ; MM32-NEXT:    and $9, $7, $6
 ; MM32-NEXT:    or $9, $9, $8
-; MM32-NEXT:    sc $9, 0($2)
+; MM32-NEXT:    sc $9, 0($3)
 ; MM32-NEXT:    beqzc $9, $BB10_1
 ; MM32-NEXT:  # %bb.2: # %entry
-; MM32-NEXT:    and $1, $7, $5
-; MM32-NEXT:    srlv $1, $1, $3
-; MM32-NEXT:    seb $1, $1
+; MM32-NEXT:    and $2, $7, $5
+; MM32-NEXT:    srlv $2, $2, $1
+; MM32-NEXT:    seb $2, $2
 ; MM32-NEXT:  # %bb.3: # %entry
-; MM32-NEXT:    jr $ra
-; MM32-NEXT:    seb $2, $1
+; MM32-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadNand8:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $2, %hi(_gp_disp)
 ; O1-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O1-NEXT:    addu $1, $2, $25
 ; O1-NEXT:    lw $1, %got(y)($1)
 ; O1-NEXT:    addiu $2, $zero, -4
-; O1-NEXT:    and $2, $1, $2
+; O1-NEXT:    and $3, $1, $2
 ; O1-NEXT:    andi $1, $1, 3
-; O1-NEXT:    sll $3, $1, 3
-; O1-NEXT:    ori $1, $zero, 255
-; O1-NEXT:    sllv $5, $1, $3
+; O1-NEXT:    sll $1, $1, 3
+; O1-NEXT:    ori $2, $zero, 255
+; O1-NEXT:    sllv $5, $2, $1
 ; O1-NEXT:    nor $6, $zero, $5
-; O1-NEXT:    sllv $4, $4, $3
+; O1-NEXT:    sllv $4, $4, $1
 ; O1-NEXT:  $BB10_1: # %entry
 ; O1-NEXT:    # =>This Inner Loop Header: Depth=1
-; O1-NEXT:    ll $7, 0($2)
+; O1-NEXT:    ll $7, 0($3)
 ; O1-NEXT:    and $8, $7, $4
 ; O1-NEXT:    nor $8, $zero, $8
 ; O1-NEXT:    and $8, $8, $5
 ; O1-NEXT:    and $9, $7, $6
 ; O1-NEXT:    or $9, $9, $8
-; O1-NEXT:    sc $9, 0($2)
+; O1-NEXT:    sc $9, 0($3)
 ; O1-NEXT:    beqz $9, $BB10_1
 ; O1-NEXT:    nop
 ; O1-NEXT:  # %bb.2: # %entry
-; O1-NEXT:    and $1, $7, $5
-; O1-NEXT:    srlv $1, $1, $3
-; O1-NEXT:    sll $1, $1, 24
-; O1-NEXT:    sra $1, $1, 24
+; O1-NEXT:    and $2, $7, $5
+; O1-NEXT:    srlv $2, $2, $1
+; O1-NEXT:    sll $2, $2, 24
+; O1-NEXT:    sra $2, $2, 24
 ; O1-NEXT:  # %bb.3: # %entry
-; O1-NEXT:    sll $1, $1, 24
 ; O1-NEXT:    jr $ra
-; O1-NEXT:    sra $2, $1, 24
+; O1-NEXT:    nop
 ;
 ; O2-LABEL: AtomicLoadNand8:
 ; O2:       # %bb.0: # %entry
 ; O2-NEXT:    lui $2, %hi(_gp_disp)
 ; O2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O2-NEXT:    addu $1, $2, $25
 ; O2-NEXT:    lw $1, %got(y)($1)
 ; O2-NEXT:    addiu $2, $zero, -4
-; O2-NEXT:    and $2, $1, $2
+; O2-NEXT:    and $3, $1, $2
 ; O2-NEXT:    andi $1, $1, 3
-; O2-NEXT:    sll $3, $1, 3
-; O2-NEXT:    ori $1, $zero, 255
-; O2-NEXT:    sllv $5, $1, $3
+; O2-NEXT:    sll $1, $1, 3
+; O2-NEXT:    ori $2, $zero, 255
+; O2-NEXT:    sllv $5, $2, $1
 ; O2-NEXT:    nor $6, $zero, $5
-; O2-NEXT:    sllv $4, $4, $3
+; O2-NEXT:    sllv $4, $4, $1
 ; O2-NEXT:  $BB10_1: # %entry
 ; O2-NEXT:    # =>This Inner Loop Header: Depth=1
-; O2-NEXT:    ll $7, 0($2)
+; O2-NEXT:    ll $7, 0($3)
 ; O2-NEXT:    and $8, $7, $4
 ; O2-NEXT:    nor $8, $zero, $8
 ; O2-NEXT:    and $8, $8, $5
 ; O2-NEXT:    and $9, $7, $6
 ; O2-NEXT:    or $9, $9, $8
-; O2-NEXT:    sc $9, 0($2)
+; O2-NEXT:    sc $9, 0($3)
 ; O2-NEXT:    beqz $9, $BB10_1
 ; O2-NEXT:    nop
 ; O2-NEXT:  # %bb.2: # %entry
-; O2-NEXT:    and $1, $7, $5
-; O2-NEXT:    srlv $1, $1, $3
-; O2-NEXT:    sll $1, $1, 24
-; O2-NEXT:    sra $1, $1, 24
+; O2-NEXT:    and $2, $7, $5
+; O2-NEXT:    srlv $2, $2, $1
+; O2-NEXT:    sll $2, $2, 24
+; O2-NEXT:    sra $2, $2, 24
 ; O2-NEXT:  # %bb.3: # %entry
-; O2-NEXT:    sll $1, $1, 24
 ; O2-NEXT:    jr $ra
-; O2-NEXT:    sra $2, $1, 24
+; O2-NEXT:    nop
 ;
 ; O3-LABEL: AtomicLoadNand8:
 ; O3:       # %bb.0: # %entry
 ; O3-NEXT:    lui $2, %hi(_gp_disp)
 ; O3-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O3-NEXT:    addu $1, $2, $25
 ; O3-NEXT:    addiu $2, $zero, -4
 ; O3-NEXT:    lw $1, %got(y)($1)
-; O3-NEXT:    and $2, $1, $2
+; O3-NEXT:    and $3, $1, $2
 ; O3-NEXT:    andi $1, $1, 3
-; O3-NEXT:    sll $3, $1, 3
-; O3-NEXT:    ori $1, $zero, 255
-; O3-NEXT:    sllv $5, $1, $3
-; O3-NEXT:    sllv $4, $4, $3
+; O3-NEXT:    ori $2, $zero, 255
+; O3-NEXT:    sll $1, $1, 3
+; O3-NEXT:    sllv $5, $2, $1
+; O3-NEXT:    sllv $4, $4, $1
 ; O3-NEXT:    nor $6, $zero, $5
 ; O3-NEXT:  $BB10_1: # %entry
 ; O3-NEXT:    # =>This Inner Loop Header: Depth=1
-; O3-NEXT:    ll $7, 0($2)
+; O3-NEXT:    ll $7, 0($3)
 ; O3-NEXT:    and $8, $7, $4
 ; O3-NEXT:    nor $8, $zero, $8
 ; O3-NEXT:    and $8, $8, $5
 ; O3-NEXT:    and $9, $7, $6
 ; O3-NEXT:    or $9, $9, $8
-; O3-NEXT:    sc $9, 0($2)
+; O3-NEXT:    sc $9, 0($3)
 ; O3-NEXT:    beqz $9, $BB10_1
 ; O3-NEXT:    nop
 ; O3-NEXT:  # %bb.2: # %entry
-; O3-NEXT:    and $1, $7, $5
-; O3-NEXT:    srlv $1, $1, $3
-; O3-NEXT:    sll $1, $1, 24
-; O3-NEXT:    sra $1, $1, 24
+; O3-NEXT:    and $2, $7, $5
+; O3-NEXT:    srlv $2, $2, $1
+; O3-NEXT:    sll $2, $2, 24
+; O3-NEXT:    sra $2, $2, 24
 ; O3-NEXT:  # %bb.3: # %entry
-; O3-NEXT:    sll $1, $1, 24
 ; O3-NEXT:    jr $ra
-; O3-NEXT:    sra $2, $1, 24
+; O3-NEXT:    nop
 ;
 ; MIPS32EB-LABEL: AtomicLoadNand8:
 ; MIPS32EB:       # %bb.0: # %entry
 ; MIPS32EB-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32EB-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32EB-NEXT:    addu $1, $2, $25
 ; MIPS32EB-NEXT:    lw $1, %got(y)($1)
 ; MIPS32EB-NEXT:    addiu $2, $zero, -4
-; MIPS32EB-NEXT:    and $2, $1, $2
+; MIPS32EB-NEXT:    and $3, $1, $2
 ; MIPS32EB-NEXT:    andi $1, $1, 3
 ; MIPS32EB-NEXT:    xori $1, $1, 3
-; MIPS32EB-NEXT:    sll $3, $1, 3
-; MIPS32EB-NEXT:    ori $1, $zero, 255
-; MIPS32EB-NEXT:    sllv $5, $1, $3
+; MIPS32EB-NEXT:    sll $1, $1, 3
+; MIPS32EB-NEXT:    ori $2, $zero, 255
+; MIPS32EB-NEXT:    sllv $5, $2, $1
 ; MIPS32EB-NEXT:    nor $6, $zero, $5
-; MIPS32EB-NEXT:    sllv $4, $4, $3
+; MIPS32EB-NEXT:    sllv $4, $4, $1
 ; MIPS32EB-NEXT:  $BB10_1: # %entry
 ; MIPS32EB-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32EB-NEXT:    ll $7, 0($2)
+; MIPS32EB-NEXT:    ll $7, 0($3)
 ; MIPS32EB-NEXT:    and $8, $7, $4
 ; MIPS32EB-NEXT:    nor $8, $zero, $8
 ; MIPS32EB-NEXT:    and $8, $8, $5
 ; MIPS32EB-NEXT:    and $9, $7, $6
 ; MIPS32EB-NEXT:    or $9, $9, $8
-; MIPS32EB-NEXT:    sc $9, 0($2)
+; MIPS32EB-NEXT:    sc $9, 0($3)
 ; MIPS32EB-NEXT:    beqz $9, $BB10_1
 ; MIPS32EB-NEXT:    nop
 ; MIPS32EB-NEXT:  # %bb.2: # %entry
-; MIPS32EB-NEXT:    and $1, $7, $5
-; MIPS32EB-NEXT:    srlv $1, $1, $3
-; MIPS32EB-NEXT:    sll $1, $1, 24
-; MIPS32EB-NEXT:    sra $1, $1, 24
+; MIPS32EB-NEXT:    and $2, $7, $5
+; MIPS32EB-NEXT:    srlv $2, $2, $1
+; MIPS32EB-NEXT:    sll $2, $2, 24
+; MIPS32EB-NEXT:    sra $2, $2, 24
 ; MIPS32EB-NEXT:  # %bb.3: # %entry
-; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    jr $ra
-; MIPS32EB-NEXT:    sra $2, $1, 24
+; MIPS32EB-NEXT:    nop
 entry:
   %0 = atomicrmw nand i8* @y, i8 %incr monotonic
   ret i8 %0
 
 }
 
 define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
 ; MIPS32-LABEL: AtomicSwap8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32-NEXT:    addu $1, $2, $25
 ; MIPS32-NEXT:    lw $1, %got(y)($1)
 ; MIPS32-NEXT:    addiu $2, $zero, -4
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    and $3, $1, $2
 ; MIPS32-NEXT:    andi $1, $1, 3
-; MIPS32-NEXT:    sll $3, $1, 3
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    sllv $5, $1, $3
+; MIPS32-NEXT:    sll $1, $1, 3
+; MIPS32-NEXT:    ori $2, $zero, 255
+; MIPS32-NEXT:    sllv $5, $2, $1
 ; MIPS32-NEXT:    nor $6, $zero, $5
-; MIPS32-NEXT:    sllv $4, $4, $3
+; MIPS32-NEXT:    sllv $4, $4, $1
 ; MIPS32-NEXT:  $BB11_1: # %entry
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32-NEXT:    ll $7, 0($2)
+; MIPS32-NEXT:    ll $7, 0($3)
 ; MIPS32-NEXT:    and $8, $4, $5
 ; MIPS32-NEXT:    and $9, $7, $6
 ; MIPS32-NEXT:    or $9, $9, $8
-; MIPS32-NEXT:    sc $9, 0($2)
+; MIPS32-NEXT:    sc $9, 0($3)
 ; MIPS32-NEXT:    beqz $9, $BB11_1
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %entry
-; MIPS32-NEXT:    and $1, $7, $5
-; MIPS32-NEXT:    srlv $1, $1, $3
-; MIPS32-NEXT:    sll $1, $1, 24
-; MIPS32-NEXT:    sra $1, $1, 24
+; MIPS32-NEXT:    and $2, $7, $5
+; MIPS32-NEXT:    srlv $2, $2, $1
+; MIPS32-NEXT:    sll $2, $2, 24
+; MIPS32-NEXT:    sra $2, $2, 24
 ; MIPS32-NEXT:  # %bb.3: # %entry
-; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    jr $ra
-; MIPS32-NEXT:    sra $2, $1, 24
+; MIPS32-NEXT:    nop
 ;
 ; MIPS32O0-LABEL: AtomicSwap8:
 ; MIPS32O0:       # %bb.0: # %entry
 ; MIPS32O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32O0-NEXT:    addu $1, $2, $25
 ; MIPS32O0-NEXT:    lw $1, %got(y)($1)

 ;
 ; MIPS32R2-LABEL: AtomicSwap8:
 ; MIPS32R2:       # %bb.0: # %entry
 ; MIPS32R2-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R2-NEXT:    addu $1, $2, $25
 ; MIPS32R2-NEXT:    lw $1, %got(y)($1)
 ; MIPS32R2-NEXT:    addiu $2, $zero, -4
-; MIPS32R2-NEXT:    and $2, $1, $2
+; MIPS32R2-NEXT:    and $3, $1, $2
 ; MIPS32R2-NEXT:    andi $1, $1, 3
-; MIPS32R2-NEXT:    sll $3, $1, 3
-; MIPS32R2-NEXT:    ori $1, $zero, 255
-; MIPS32R2-NEXT:    sllv $5, $1, $3
+; MIPS32R2-NEXT:    sll $1, $1, 3
+; MIPS32R2-NEXT:    ori $2, $zero, 255
+; MIPS32R2-NEXT:    sllv $5, $2, $1
 ; MIPS32R2-NEXT:    nor $6, $zero, $5
-; MIPS32R2-NEXT:    sllv $4, $4, $3
+; MIPS32R2-NEXT:    sllv $4, $4, $1
 ; MIPS32R2-NEXT:  $BB11_1: # %entry
 ; MIPS32R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R2-NEXT:    ll $7, 0($2)
+; MIPS32R2-NEXT:    ll $7, 0($3)
 ; MIPS32R2-NEXT:    and $8, $4, $5
 ; MIPS32R2-NEXT:    and $9, $7, $6
 ; MIPS32R2-NEXT:    or $9, $9, $8
-; MIPS32R2-NEXT:    sc $9, 0($2)
+; MIPS32R2-NEXT:    sc $9, 0($3)
 ; MIPS32R2-NEXT:    beqz $9, $BB11_1
 ; MIPS32R2-NEXT:    nop
 ; MIPS32R2-NEXT:  # %bb.2: # %entry
-; MIPS32R2-NEXT:    and $1, $7, $5
-; MIPS32R2-NEXT:    srlv $1, $1, $3
-; MIPS32R2-NEXT:    seb $1, $1
+; MIPS32R2-NEXT:    and $2, $7, $5
+; MIPS32R2-NEXT:    srlv $2, $2, $1
+; MIPS32R2-NEXT:    seb $2, $2
 ; MIPS32R2-NEXT:  # %bb.3: # %entry
 ; MIPS32R2-NEXT:    jr $ra
-; MIPS32R2-NEXT:    seb $2, $1
+; MIPS32R2-NEXT:    nop
 ;
 ; MIPS32R6-LABEL: AtomicSwap8:
 ; MIPS32R6:       # %bb.0: # %entry
 ; MIPS32R6-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6-NEXT:    addu $1, $2, $25
 ; MIPS32R6-NEXT:    lw $1, %got(y)($1)
 ; MIPS32R6-NEXT:    addiu $2, $zero, -4
-; MIPS32R6-NEXT:    and $2, $1, $2
+; MIPS32R6-NEXT:    and $3, $1, $2
 ; MIPS32R6-NEXT:    andi $1, $1, 3
-; MIPS32R6-NEXT:    sll $3, $1, 3
-; MIPS32R6-NEXT:    ori $1, $zero, 255
-; MIPS32R6-NEXT:    sllv $5, $1, $3
+; MIPS32R6-NEXT:    sll $1, $1, 3
+; MIPS32R6-NEXT:    ori $2, $zero, 255
+; MIPS32R6-NEXT:    sllv $5, $2, $1
 ; MIPS32R6-NEXT:    nor $6, $zero, $5
-; MIPS32R6-NEXT:    sllv $4, $4, $3
+; MIPS32R6-NEXT:    sllv $4, $4, $1
 ; MIPS32R6-NEXT:  $BB11_1: # %entry
 ; MIPS32R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R6-NEXT:    ll $7, 0($2)
+; MIPS32R6-NEXT:    ll $7, 0($3)
 ; MIPS32R6-NEXT:    and $8, $4, $5
 ; MIPS32R6-NEXT:    and $9, $7, $6
 ; MIPS32R6-NEXT:    or $9, $9, $8
-; MIPS32R6-NEXT:    sc $9, 0($2)
+; MIPS32R6-NEXT:    sc $9, 0($3)
 ; MIPS32R6-NEXT:    beqzc $9, $BB11_1
 ; MIPS32R6-NEXT:  # %bb.2: # %entry
-; MIPS32R6-NEXT:    and $1, $7, $5
-; MIPS32R6-NEXT:    srlv $1, $1, $3
-; MIPS32R6-NEXT:    seb $1, $1
+; MIPS32R6-NEXT:    and $2, $7, $5
+; MIPS32R6-NEXT:    srlv $2, $2, $1
+; MIPS32R6-NEXT:    seb $2, $2
 ; MIPS32R6-NEXT:  # %bb.3: # %entry
-; MIPS32R6-NEXT:    jr $ra
-; MIPS32R6-NEXT:    seb $2, $1
+; MIPS32R6-NEXT:    jrc $ra
 ;
 ; MIPS32R6O0-LABEL: AtomicSwap8:
 ; MIPS32R6O0:       # %bb.0: # %entry
 ; MIPS32R6O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32R6O0-NEXT:    addu $1, $2, $25
 ; MIPS32R6O0-NEXT:    # kill: def $v0 killed $a0

 ; MIPS32R6O0-NEXT:    beqzc $4, $BB11_1
 ; MIPS32R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS32R6O0-NEXT:    and $1, $2, $7
 ; MIPS32R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS32R6O0-NEXT:    seb $1, $1
 ; MIPS32R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS32R6O0-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
 ; MIPS32R6O0-NEXT:  # %bb.4: # %entry
-; MIPS32R6O0-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
-; MIPS32R6O0-NEXT:    seb $2, $1
+; MIPS32R6O0-NEXT:    lw $2, 4($sp) # 4-byte Folded Reload
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, 8
 ; MIPS32R6O0-NEXT:    jrc $ra
 ;
 ; MIPS4-LABEL: AtomicSwap8:
 ; MIPS4:       # %bb.0: # %entry
 ; MIPS4-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS4-NEXT:    daddu $1, $1, $25
 ; MIPS4-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS4-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS4-NEXT:    daddiu $2, $zero, -4
-; MIPS4-NEXT:    and $2, $1, $2
+; MIPS4-NEXT:    and $3, $1, $2
 ; MIPS4-NEXT:    andi $1, $1, 3
-; MIPS4-NEXT:    sll $3, $1, 3
-; MIPS4-NEXT:    ori $1, $zero, 255
-; MIPS4-NEXT:    sllv $5, $1, $3
+; MIPS4-NEXT:    sll $1, $1, 3
+; MIPS4-NEXT:    ori $2, $zero, 255
+; MIPS4-NEXT:    sllv $5, $2, $1
 ; MIPS4-NEXT:    nor $6, $zero, $5
-; MIPS4-NEXT:    sllv $4, $4, $3
+; MIPS4-NEXT:    sllv $4, $4, $1
 ; MIPS4-NEXT:  .LBB11_1: # %entry
 ; MIPS4-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS4-NEXT:    ll $7, 0($2)
+; MIPS4-NEXT:    ll $7, 0($3)
 ; MIPS4-NEXT:    and $8, $4, $5
 ; MIPS4-NEXT:    and $9, $7, $6
 ; MIPS4-NEXT:    or $9, $9, $8
-; MIPS4-NEXT:    sc $9, 0($2)
+; MIPS4-NEXT:    sc $9, 0($3)
 ; MIPS4-NEXT:    beqz $9, .LBB11_1
 ; MIPS4-NEXT:    nop
 ; MIPS4-NEXT:  # %bb.2: # %entry
-; MIPS4-NEXT:    and $1, $7, $5
-; MIPS4-NEXT:    srlv $1, $1, $3
-; MIPS4-NEXT:    sll $1, $1, 24
-; MIPS4-NEXT:    sra $1, $1, 24
+; MIPS4-NEXT:    and $2, $7, $5
+; MIPS4-NEXT:    srlv $2, $2, $1
+; MIPS4-NEXT:    sll $2, $2, 24
+; MIPS4-NEXT:    sra $2, $2, 24
 ; MIPS4-NEXT:  # %bb.3: # %entry
-; MIPS4-NEXT:    sll $1, $1, 24
 ; MIPS4-NEXT:    jr $ra
-; MIPS4-NEXT:    sra $2, $1, 24
+; MIPS4-NEXT:    nop
 ;
 ; MIPS64-LABEL: AtomicSwap8:
 ; MIPS64:       # %bb.0: # %entry
 ; MIPS64-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS64-NEXT:    daddu $1, $1, $25
 ; MIPS64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS64-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64-NEXT:    daddiu $2, $zero, -4
-; MIPS64-NEXT:    and $2, $1, $2
+; MIPS64-NEXT:    and $3, $1, $2
 ; MIPS64-NEXT:    andi $1, $1, 3
-; MIPS64-NEXT:    sll $3, $1, 3
-; MIPS64-NEXT:    ori $1, $zero, 255
-; MIPS64-NEXT:    sllv $5, $1, $3
+; MIPS64-NEXT:    sll $1, $1, 3
+; MIPS64-NEXT:    ori $2, $zero, 255
+; MIPS64-NEXT:    sllv $5, $2, $1
 ; MIPS64-NEXT:    nor $6, $zero, $5
-; MIPS64-NEXT:    sllv $4, $4, $3
+; MIPS64-NEXT:    sllv $4, $4, $1
 ; MIPS64-NEXT:  .LBB11_1: # %entry
 ; MIPS64-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64-NEXT:    ll $7, 0($2)
+; MIPS64-NEXT:    ll $7, 0($3)
 ; MIPS64-NEXT:    and $8, $4, $5
 ; MIPS64-NEXT:    and $9, $7, $6
 ; MIPS64-NEXT:    or $9, $9, $8
-; MIPS64-NEXT:    sc $9, 0($2)
+; MIPS64-NEXT:    sc $9, 0($3)
 ; MIPS64-NEXT:    beqz $9, .LBB11_1
 ; MIPS64-NEXT:    nop
 ; MIPS64-NEXT:  # %bb.2: # %entry
-; MIPS64-NEXT:    and $1, $7, $5
-; MIPS64-NEXT:    srlv $1, $1, $3
-; MIPS64-NEXT:    sll $1, $1, 24
-; MIPS64-NEXT:    sra $1, $1, 24
+; MIPS64-NEXT:    and $2, $7, $5
+; MIPS64-NEXT:    srlv $2, $2, $1
+; MIPS64-NEXT:    sll $2, $2, 24
+; MIPS64-NEXT:    sra $2, $2, 24
 ; MIPS64-NEXT:  # %bb.3: # %entry
-; MIPS64-NEXT:    sll $1, $1, 24
 ; MIPS64-NEXT:    jr $ra
-; MIPS64-NEXT:    sra $2, $1, 24
+; MIPS64-NEXT:    nop
 ;
 ; MIPS64R2-LABEL: AtomicSwap8:
 ; MIPS64R2:       # %bb.0: # %entry
 ; MIPS64R2-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS64R2-NEXT:    daddu $1, $1, $25
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS64R2-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64R2-NEXT:    daddiu $2, $zero, -4
-; MIPS64R2-NEXT:    and $2, $1, $2
+; MIPS64R2-NEXT:    and $3, $1, $2
 ; MIPS64R2-NEXT:    andi $1, $1, 3
-; MIPS64R2-NEXT:    sll $3, $1, 3
-; MIPS64R2-NEXT:    ori $1, $zero, 255
-; MIPS64R2-NEXT:    sllv $5, $1, $3
+; MIPS64R2-NEXT:    sll $1, $1, 3
+; MIPS64R2-NEXT:    ori $2, $zero, 255
+; MIPS64R2-NEXT:    sllv $5, $2, $1
 ; MIPS64R2-NEXT:    nor $6, $zero, $5
-; MIPS64R2-NEXT:    sllv $4, $4, $3
+; MIPS64R2-NEXT:    sllv $4, $4, $1
 ; MIPS64R2-NEXT:  .LBB11_1: # %entry
 ; MIPS64R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R2-NEXT:    ll $7, 0($2)
+; MIPS64R2-NEXT:    ll $7, 0($3)
 ; MIPS64R2-NEXT:    and $8, $4, $5
 ; MIPS64R2-NEXT:    and $9, $7, $6
 ; MIPS64R2-NEXT:    or $9, $9, $8
-; MIPS64R2-NEXT:    sc $9, 0($2)
+; MIPS64R2-NEXT:    sc $9, 0($3)
 ; MIPS64R2-NEXT:    beqz $9, .LBB11_1
 ; MIPS64R2-NEXT:    nop
 ; MIPS64R2-NEXT:  # %bb.2: # %entry
-; MIPS64R2-NEXT:    and $1, $7, $5
-; MIPS64R2-NEXT:    srlv $1, $1, $3
-; MIPS64R2-NEXT:    seb $1, $1
+; MIPS64R2-NEXT:    and $2, $7, $5
+; MIPS64R2-NEXT:    srlv $2, $2, $1
+; MIPS64R2-NEXT:    seb $2, $2
 ; MIPS64R2-NEXT:  # %bb.3: # %entry
 ; MIPS64R2-NEXT:    jr $ra
-; MIPS64R2-NEXT:    seb $2, $1
+; MIPS64R2-NEXT:    nop
 ;
 ; MIPS64R6-LABEL: AtomicSwap8:
 ; MIPS64R6:       # %bb.0: # %entry
 ; MIPS64R6-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(y)($1)
 ; MIPS64R6-NEXT:    daddiu $2, $zero, -4
-; MIPS64R6-NEXT:    and $2, $1, $2
+; MIPS64R6-NEXT:    and $3, $1, $2
 ; MIPS64R6-NEXT:    andi $1, $1, 3
-; MIPS64R6-NEXT:    sll $3, $1, 3
-; MIPS64R6-NEXT:    ori $1, $zero, 255
-; MIPS64R6-NEXT:    sllv $5, $1, $3
+; MIPS64R6-NEXT:    sll $1, $1, 3
+; MIPS64R6-NEXT:    ori $2, $zero, 255
+; MIPS64R6-NEXT:    sllv $5, $2, $1
 ; MIPS64R6-NEXT:    nor $6, $zero, $5
-; MIPS64R6-NEXT:    sllv $4, $4, $3
+; MIPS64R6-NEXT:    sllv $4, $4, $1
 ; MIPS64R6-NEXT:  .LBB11_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R6-NEXT:    ll $7, 0($2)
+; MIPS64R6-NEXT:    ll $7, 0($3)
 ; MIPS64R6-NEXT:    and $8, $4, $5
 ; MIPS64R6-NEXT:    and $9, $7, $6
 ; MIPS64R6-NEXT:    or $9, $9, $8
-; MIPS64R6-NEXT:    sc $9, 0($2)
+; MIPS64R6-NEXT:    sc $9, 0($3)
 ; MIPS64R6-NEXT:    beqzc $9, .LBB11_1
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
-; MIPS64R6-NEXT:    and $1, $7, $5
-; MIPS64R6-NEXT:    srlv $1, $1, $3
-; MIPS64R6-NEXT:    seb $1, $1
+; MIPS64R6-NEXT:    and $2, $7, $5
+; MIPS64R6-NEXT:    srlv $2, $2, $1
+; MIPS64R6-NEXT:    seb $2, $2
 ; MIPS64R6-NEXT:  # %bb.3: # %entry
-; MIPS64R6-NEXT:    jr $ra
-; MIPS64R6-NEXT:    seb $2, $1
+; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicSwap8:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $2, $1, %lo(%neg(%gp_rel(AtomicSwap8)))
 ; MIPS64R6O0-NEXT:    move $1, $4

 ; MIPS64R6O0-NEXT:    beqzc $4, .LBB11_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    and $1, $2, $7
 ; MIPS64R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS64R6O0-NEXT:    seb $1, $1
 ; MIPS64R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS64R6O0-NEXT:    sw $1, 12($sp) # 4-byte Folded Spill
 ; MIPS64R6O0-NEXT:  # %bb.4: # %entry
-; MIPS64R6O0-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
-; MIPS64R6O0-NEXT:    seb $2, $1
+; MIPS64R6O0-NEXT:    lw $2, 12($sp) # 4-byte Folded Reload
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; MM32-LABEL: AtomicSwap8:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    lui $2, %hi(_gp_disp)
 ; MM32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MM32-NEXT:    addu $2, $2, $25
 ; MM32-NEXT:    lw $1, %got(y)($2)
 ; MM32-NEXT:    addiu $2, $zero, -4
-; MM32-NEXT:    and $2, $1, $2
+; MM32-NEXT:    and $3, $1, $2
 ; MM32-NEXT:    andi $1, $1, 3
-; MM32-NEXT:    sll $3, $1, 3
-; MM32-NEXT:    ori $1, $zero, 255
-; MM32-NEXT:    sllv $5, $1, $3
+; MM32-NEXT:    sll $1, $1, 3
+; MM32-NEXT:    ori $2, $zero, 255
+; MM32-NEXT:    sllv $5, $2, $1
 ; MM32-NEXT:    nor $6, $zero, $5
-; MM32-NEXT:    sllv $4, $4, $3
+; MM32-NEXT:    sllv $4, $4, $1
 ; MM32-NEXT:  $BB11_1: # %entry
 ; MM32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MM32-NEXT:    ll $7, 0($2)
+; MM32-NEXT:    ll $7, 0($3)
 ; MM32-NEXT:    and $8, $4, $5
 ; MM32-NEXT:    and $9, $7, $6
 ; MM32-NEXT:    or $9, $9, $8
-; MM32-NEXT:    sc $9, 0($2)
+; MM32-NEXT:    sc $9, 0($3)
 ; MM32-NEXT:    beqzc $9, $BB11_1
 ; MM32-NEXT:  # %bb.2: # %entry
-; MM32-NEXT:    and $1, $7, $5
-; MM32-NEXT:    srlv $1, $1, $3
-; MM32-NEXT:    seb $1, $1
+; MM32-NEXT:    and $2, $7, $5
+; MM32-NEXT:    srlv $2, $2, $1
+; MM32-NEXT:    seb $2, $2
 ; MM32-NEXT:  # %bb.3: # %entry
-; MM32-NEXT:    jr $ra
-; MM32-NEXT:    seb $2, $1
+; MM32-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicSwap8:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $2, %hi(_gp_disp)
 ; O1-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O1-NEXT:    addu $1, $2, $25
 ; O1-NEXT:    lw $1, %got(y)($1)
 ; O1-NEXT:    addiu $2, $zero, -4
-; O1-NEXT:    and $2, $1, $2
+; O1-NEXT:    and $3, $1, $2
 ; O1-NEXT:    andi $1, $1, 3
-; O1-NEXT:    sll $3, $1, 3
-; O1-NEXT:    ori $1, $zero, 255
-; O1-NEXT:    sllv $5, $1, $3
+; O1-NEXT:    sll $1, $1, 3
+; O1-NEXT:    ori $2, $zero, 255
+; O1-NEXT:    sllv $5, $2, $1
 ; O1-NEXT:    nor $6, $zero, $5
-; O1-NEXT:    sllv $4, $4, $3
+; O1-NEXT:    sllv $4, $4, $1
 ; O1-NEXT:  $BB11_1: # %entry
 ; O1-NEXT:    # =>This Inner Loop Header: Depth=1
-; O1-NEXT:    ll $7, 0($2)
+; O1-NEXT:    ll $7, 0($3)
 ; O1-NEXT:    and $8, $4, $5
 ; O1-NEXT:    and $9, $7, $6
 ; O1-NEXT:    or $9, $9, $8
-; O1-NEXT:    sc $9, 0($2)
+; O1-NEXT:    sc $9, 0($3)
 ; O1-NEXT:    beqz $9, $BB11_1
 ; O1-NEXT:    nop
 ; O1-NEXT:  # %bb.2: # %entry
-; O1-NEXT:    and $1, $7, $5
-; O1-NEXT:    srlv $1, $1, $3
-; O1-NEXT:    sll $1, $1, 24
-; O1-NEXT:    sra $1, $1, 24
+; O1-NEXT:    and $2, $7, $5
+; O1-NEXT:    srlv $2, $2, $1
+; O1-NEXT:    sll $2, $2, 24
+; O1-NEXT:    sra $2, $2, 24
 ; O1-NEXT:  # %bb.3: # %entry
-; O1-NEXT:    sll $1, $1, 24
 ; O1-NEXT:    jr $ra
-; O1-NEXT:    sra $2, $1, 24
+; O1-NEXT:    nop
 ;
 ; O2-LABEL: AtomicSwap8:
 ; O2:       # %bb.0: # %entry
 ; O2-NEXT:    lui $2, %hi(_gp_disp)
 ; O2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O2-NEXT:    addu $1, $2, $25
 ; O2-NEXT:    lw $1, %got(y)($1)
 ; O2-NEXT:    addiu $2, $zero, -4
-; O2-NEXT:    and $2, $1, $2
+; O2-NEXT:    and $3, $1, $2
 ; O2-NEXT:    andi $1, $1, 3
-; O2-NEXT:    sll $3, $1, 3
-; O2-NEXT:    ori $1, $zero, 255
-; O2-NEXT:    sllv $5, $1, $3
+; O2-NEXT:    sll $1, $1, 3
+; O2-NEXT:    ori $2, $zero, 255
+; O2-NEXT:    sllv $5, $2, $1
 ; O2-NEXT:    nor $6, $zero, $5
-; O2-NEXT:    sllv $4, $4, $3
+; O2-NEXT:    sllv $4, $4, $1
 ; O2-NEXT:  $BB11_1: # %entry
 ; O2-NEXT:    # =>This Inner Loop Header: Depth=1
-; O2-NEXT:    ll $7, 0($2)
+; O2-NEXT:    ll $7, 0($3)
 ; O2-NEXT:    and $8, $4, $5
 ; O2-NEXT:    and $9, $7, $6
 ; O2-NEXT:    or $9, $9, $8
-; O2-NEXT:    sc $9, 0($2)
+; O2-NEXT:    sc $9, 0($3)
 ; O2-NEXT:    beqz $9, $BB11_1
 ; O2-NEXT:    nop
 ; O2-NEXT:  # %bb.2: # %entry
-; O2-NEXT:    and $1, $7, $5
-; O2-NEXT:    srlv $1, $1, $3
-; O2-NEXT:    sll $1, $1, 24
-; O2-NEXT:    sra $1, $1, 24
+; O2-NEXT:    and $2, $7, $5
+; O2-NEXT:    srlv $2, $2, $1
+; O2-NEXT:    sll $2, $2, 24
+; O2-NEXT:    sra $2, $2, 24
 ; O2-NEXT:  # %bb.3: # %entry
-; O2-NEXT:    sll $1, $1, 24
 ; O2-NEXT:    jr $ra
-; O2-NEXT:    sra $2, $1, 24
+; O2-NEXT:    nop
 ;
 ; O3-LABEL: AtomicSwap8:
 ; O3:       # %bb.0: # %entry
 ; O3-NEXT:    lui $2, %hi(_gp_disp)
 ; O3-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O3-NEXT:    addu $1, $2, $25
 ; O3-NEXT:    addiu $2, $zero, -4
 ; O3-NEXT:    lw $1, %got(y)($1)
-; O3-NEXT:    and $2, $1, $2
+; O3-NEXT:    and $3, $1, $2
 ; O3-NEXT:    andi $1, $1, 3
-; O3-NEXT:    sll $3, $1, 3
-; O3-NEXT:    ori $1, $zero, 255
-; O3-NEXT:    sllv $5, $1, $3
-; O3-NEXT:    sllv $4, $4, $3
+; O3-NEXT:    ori $2, $zero, 255
+; O3-NEXT:    sll $1, $1, 3
+; O3-NEXT:    sllv $5, $2, $1
+; O3-NEXT:    sllv $4, $4, $1
 ; O3-NEXT:    nor $6, $zero, $5
 ; O3-NEXT:  $BB11_1: # %entry
 ; O3-NEXT:    # =>This Inner Loop Header: Depth=1
-; O3-NEXT:    ll $7, 0($2)
+; O3-NEXT:    ll $7, 0($3)
 ; O3-NEXT:    and $8, $4, $5
 ; O3-NEXT:    and $9, $7, $6
 ; O3-NEXT:    or $9, $9, $8
-; O3-NEXT:    sc $9, 0($2)
+; O3-NEXT:    sc $9, 0($3)
 ; O3-NEXT:    beqz $9, $BB11_1
 ; O3-NEXT:    nop
 ; O3-NEXT:  # %bb.2: # %entry
-; O3-NEXT:    and $1, $7, $5
-; O3-NEXT:    srlv $1, $1, $3
-; O3-NEXT:    sll $1, $1, 24
-; O3-NEXT:    sra $1, $1, 24
+; O3-NEXT:    and $2, $7, $5
+; O3-NEXT:    srlv $2, $2, $1
+; O3-NEXT:    sll $2, $2, 24
+; O3-NEXT:    sra $2, $2, 24
 ; O3-NEXT:  # %bb.3: # %entry
-; O3-NEXT:    sll $1, $1, 24
 ; O3-NEXT:    jr $ra
-; O3-NEXT:    sra $2, $1, 24
+; O3-NEXT:    nop
 ;
 ; MIPS32EB-LABEL: AtomicSwap8:
 ; MIPS32EB:       # %bb.0: # %entry
 ; MIPS32EB-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32EB-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32EB-NEXT:    addu $1, $2, $25
 ; MIPS32EB-NEXT:    lw $1, %got(y)($1)
 ; MIPS32EB-NEXT:    addiu $2, $zero, -4
-; MIPS32EB-NEXT:    and $2, $1, $2
+; MIPS32EB-NEXT:    and $3, $1, $2
 ; MIPS32EB-NEXT:    andi $1, $1, 3
 ; MIPS32EB-NEXT:    xori $1, $1, 3
-; MIPS32EB-NEXT:    sll $3, $1, 3
-; MIPS32EB-NEXT:    ori $1, $zero, 255
-; MIPS32EB-NEXT:    sllv $5, $1, $3
+; MIPS32EB-NEXT:    sll $1, $1, 3
+; MIPS32EB-NEXT:    ori $2, $zero, 255
+; MIPS32EB-NEXT:    sllv $5, $2, $1
 ; MIPS32EB-NEXT:    nor $6, $zero, $5
-; MIPS32EB-NEXT:    sllv $4, $4, $3
+; MIPS32EB-NEXT:    sllv $4, $4, $1
 ; MIPS32EB-NEXT:  $BB11_1: # %entry
 ; MIPS32EB-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32EB-NEXT:    ll $7, 0($2)
+; MIPS32EB-NEXT:    ll $7, 0($3)
 ; MIPS32EB-NEXT:    and $8, $4, $5
 ; MIPS32EB-NEXT:    and $9, $7, $6
 ; MIPS32EB-NEXT:    or $9, $9, $8
-; MIPS32EB-NEXT:    sc $9, 0($2)
+; MIPS32EB-NEXT:    sc $9, 0($3)
 ; MIPS32EB-NEXT:    beqz $9, $BB11_1
 ; MIPS32EB-NEXT:    nop
 ; MIPS32EB-NEXT:  # %bb.2: # %entry
-; MIPS32EB-NEXT:    and $1, $7, $5
-; MIPS32EB-NEXT:    srlv $1, $1, $3
-; MIPS32EB-NEXT:    sll $1, $1, 24
-; MIPS32EB-NEXT:    sra $1, $1, 24
+; MIPS32EB-NEXT:    and $2, $7, $5
+; MIPS32EB-NEXT:    srlv $2, $2, $1
+; MIPS32EB-NEXT:    sll $2, $2, 24
+; MIPS32EB-NEXT:    sra $2, $2, 24
 ; MIPS32EB-NEXT:  # %bb.3: # %entry
-; MIPS32EB-NEXT:    sll $1, $1, 24
 ; MIPS32EB-NEXT:    jr $ra
-; MIPS32EB-NEXT:    sra $2, $1, 24
+; MIPS32EB-NEXT:    nop
 entry:
   %0 = atomicrmw xchg i8* @y, i8 %newval monotonic
   ret i8 %0
 }
 
 define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
 ; MIPS32-LABEL: AtomicCmpSwap8:
 ; MIPS32:       # %bb.0: # %entry

 define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind {
 ; MIPS32-LABEL: AtomicLoadAdd16:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32-NEXT:    addu $1, $2, $25
 ; MIPS32-NEXT:    lw $1, %got(z)($1)
 ; MIPS32-NEXT:    addiu $2, $zero, -4
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    and $3, $1, $2
 ; MIPS32-NEXT:    andi $1, $1, 3
-; MIPS32-NEXT:    sll $3, $1, 3
-; MIPS32-NEXT:    ori $1, $zero, 65535
-; MIPS32-NEXT:    sllv $5, $1, $3
+; MIPS32-NEXT:    sll $1, $1, 3
+; MIPS32-NEXT:    ori $2, $zero, 65535
+; MIPS32-NEXT:    sllv $5, $2, $1
 ; MIPS32-NEXT:    nor $6, $zero, $5
-; MIPS32-NEXT:    sllv $4, $4, $3
+; MIPS32-NEXT:    sllv $4, $4, $1
 ; MIPS32-NEXT:  $BB14_1: # %entry
 ; MIPS32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32-NEXT:    ll $7, 0($2)
+; MIPS32-NEXT:    ll $7, 0($3)
 ; MIPS32-NEXT:    addu $8, $7, $4
 ; MIPS32-NEXT:    and $8, $8, $5
 ; MIPS32-NEXT:    and $9, $7, $6
 ; MIPS32-NEXT:    or $9, $9, $8
-; MIPS32-NEXT:    sc $9, 0($2)
+; MIPS32-NEXT:    sc $9, 0($3)
 ; MIPS32-NEXT:    beqz $9, $BB14_1
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %entry
-; MIPS32-NEXT:    and $1, $7, $5
-; MIPS32-NEXT:    srlv $1, $1, $3
-; MIPS32-NEXT:    sll $1, $1, 16
-; MIPS32-NEXT:    sra $1, $1, 16
+; MIPS32-NEXT:    and $2, $7, $5
+; MIPS32-NEXT:    srlv $2, $2, $1
+; MIPS32-NEXT:    sll $2, $2, 16
+; MIPS32-NEXT:    sra $2, $2, 16
 ; MIPS32-NEXT:  # %bb.3: # %entry
-; MIPS32-NEXT:    sll $1, $1, 16
 ; MIPS32-NEXT:    jr $ra
-; MIPS32-NEXT:    sra $2, $1, 16
+; MIPS32-NEXT:    nop
 ;
 ; MIPS32O0-LABEL: AtomicLoadAdd16:
 ; MIPS32O0:       # %bb.0: # %entry
 ; MIPS32O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32O0-NEXT:    addu $1, $2, $25
 ; MIPS32O0-NEXT:    lw $1, %got(z)($1)

 ;
 ; MIPS32R2-LABEL: AtomicLoadAdd16:
 ; MIPS32R2:       # %bb.0: # %entry
 ; MIPS32R2-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R2-NEXT:    addu $1, $2, $25
 ; MIPS32R2-NEXT:    lw $1, %got(z)($1)
 ; MIPS32R2-NEXT:    addiu $2, $zero, -4
-; MIPS32R2-NEXT:    and $2, $1, $2
+; MIPS32R2-NEXT:    and $3, $1, $2
 ; MIPS32R2-NEXT:    andi $1, $1, 3
-; MIPS32R2-NEXT:    sll $3, $1, 3
-; MIPS32R2-NEXT:    ori $1, $zero, 65535
-; MIPS32R2-NEXT:    sllv $5, $1, $3
+; MIPS32R2-NEXT:    sll $1, $1, 3
+; MIPS32R2-NEXT:    ori $2, $zero, 65535
+; MIPS32R2-NEXT:    sllv $5, $2, $1
 ; MIPS32R2-NEXT:    nor $6, $zero, $5
-; MIPS32R2-NEXT:    sllv $4, $4, $3
+; MIPS32R2-NEXT:    sllv $4, $4, $1
 ; MIPS32R2-NEXT:  $BB14_1: # %entry
 ; MIPS32R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R2-NEXT:    ll $7, 0($2)
+; MIPS32R2-NEXT:    ll $7, 0($3)
 ; MIPS32R2-NEXT:    addu $8, $7, $4
 ; MIPS32R2-NEXT:    and $8, $8, $5
 ; MIPS32R2-NEXT:    and $9, $7, $6
 ; MIPS32R2-NEXT:    or $9, $9, $8
-; MIPS32R2-NEXT:    sc $9, 0($2)
+; MIPS32R2-NEXT:    sc $9, 0($3)
 ; MIPS32R2-NEXT:    beqz $9, $BB14_1
 ; MIPS32R2-NEXT:    nop
 ; MIPS32R2-NEXT:  # %bb.2: # %entry
-; MIPS32R2-NEXT:    and $1, $7, $5
-; MIPS32R2-NEXT:    srlv $1, $1, $3
-; MIPS32R2-NEXT:    seh $1, $1
+; MIPS32R2-NEXT:    and $2, $7, $5
+; MIPS32R2-NEXT:    srlv $2, $2, $1
+; MIPS32R2-NEXT:    seh $2, $2
 ; MIPS32R2-NEXT:  # %bb.3: # %entry
 ; MIPS32R2-NEXT:    jr $ra
-; MIPS32R2-NEXT:    seh $2, $1
+; MIPS32R2-NEXT:    nop
 ;
 ; MIPS32R6-LABEL: AtomicLoadAdd16:
 ; MIPS32R6:       # %bb.0: # %entry
 ; MIPS32R6-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6-NEXT:    addu $1, $2, $25
 ; MIPS32R6-NEXT:    lw $1, %got(z)($1)
 ; MIPS32R6-NEXT:    addiu $2, $zero, -4
-; MIPS32R6-NEXT:    and $2, $1, $2
+; MIPS32R6-NEXT:    and $3, $1, $2
 ; MIPS32R6-NEXT:    andi $1, $1, 3
-; MIPS32R6-NEXT:    sll $3, $1, 3
-; MIPS32R6-NEXT:    ori $1, $zero, 65535
-; MIPS32R6-NEXT:    sllv $5, $1, $3
+; MIPS32R6-NEXT:    sll $1, $1, 3
+; MIPS32R6-NEXT:    ori $2, $zero, 65535
+; MIPS32R6-NEXT:    sllv $5, $2, $1
 ; MIPS32R6-NEXT:    nor $6, $zero, $5
-; MIPS32R6-NEXT:    sllv $4, $4, $3
+; MIPS32R6-NEXT:    sllv $4, $4, $1
 ; MIPS32R6-NEXT:  $BB14_1: # %entry
 ; MIPS32R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32R6-NEXT:    ll $7, 0($2)
+; MIPS32R6-NEXT:    ll $7, 0($3)
 ; MIPS32R6-NEXT:    addu $8, $7, $4
 ; MIPS32R6-NEXT:    and $8, $8, $5
 ; MIPS32R6-NEXT:    and $9, $7, $6
 ; MIPS32R6-NEXT:    or $9, $9, $8
-; MIPS32R6-NEXT:    sc $9, 0($2)
+; MIPS32R6-NEXT:    sc $9, 0($3)
 ; MIPS32R6-NEXT:    beqzc $9, $BB14_1
 ; MIPS32R6-NEXT:  # %bb.2: # %entry
-; MIPS32R6-NEXT:    and $1, $7, $5
-; MIPS32R6-NEXT:    srlv $1, $1, $3
-; MIPS32R6-NEXT:    seh $1, $1
+; MIPS32R6-NEXT:    and $2, $7, $5
+; MIPS32R6-NEXT:    srlv $2, $2, $1
+; MIPS32R6-NEXT:    seh $2, $2
 ; MIPS32R6-NEXT:  # %bb.3: # %entry
-; MIPS32R6-NEXT:    jr $ra
-; MIPS32R6-NEXT:    seh $2, $1
+; MIPS32R6-NEXT:    jrc $ra
 ;
 ; MIPS32R6O0-LABEL: AtomicLoadAdd16:
 ; MIPS32R6O0:       # %bb.0: # %entry
 ; MIPS32R6O0-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, -8
 ; MIPS32R6O0-NEXT:    addu $1, $2, $25
 ; MIPS32R6O0-NEXT:    # kill: def $v0 killed $a0

 ; MIPS32R6O0-NEXT:    beqzc $4, $BB14_1
 ; MIPS32R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS32R6O0-NEXT:    and $1, $2, $7
 ; MIPS32R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS32R6O0-NEXT:    seh $1, $1
 ; MIPS32R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS32R6O0-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
 ; MIPS32R6O0-NEXT:  # %bb.4: # %entry
-; MIPS32R6O0-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
-; MIPS32R6O0-NEXT:    seh $2, $1
+; MIPS32R6O0-NEXT:    lw $2, 4($sp) # 4-byte Folded Reload
 ; MIPS32R6O0-NEXT:    addiu $sp, $sp, 8
 ; MIPS32R6O0-NEXT:    jrc $ra
 ;
 ; MIPS4-LABEL: AtomicLoadAdd16:
 ; MIPS4:       # %bb.0: # %entry
 ; MIPS4-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS4-NEXT:    daddu $1, $1, $25
 ; MIPS4-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS4-NEXT:    ld $1, %got_disp(z)($1)
 ; MIPS4-NEXT:    daddiu $2, $zero, -4
-; MIPS4-NEXT:    and $2, $1, $2
+; MIPS4-NEXT:    and $3, $1, $2
 ; MIPS4-NEXT:    andi $1, $1, 3
-; MIPS4-NEXT:    sll $3, $1, 3
-; MIPS4-NEXT:    ori $1, $zero, 65535
-; MIPS4-NEXT:    sllv $5, $1, $3
+; MIPS4-NEXT:    sll $1, $1, 3
+; MIPS4-NEXT:    ori $2, $zero, 65535
+; MIPS4-NEXT:    sllv $5, $2, $1
 ; MIPS4-NEXT:    nor $6, $zero, $5
-; MIPS4-NEXT:    sllv $4, $4, $3
+; MIPS4-NEXT:    sllv $4, $4, $1
 ; MIPS4-NEXT:  .LBB14_1: # %entry
 ; MIPS4-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS4-NEXT:    ll $7, 0($2)
+; MIPS4-NEXT:    ll $7, 0($3)
 ; MIPS4-NEXT:    addu $8, $7, $4
 ; MIPS4-NEXT:    and $8, $8, $5
 ; MIPS4-NEXT:    and $9, $7, $6
 ; MIPS4-NEXT:    or $9, $9, $8
-; MIPS4-NEXT:    sc $9, 0($2)
+; MIPS4-NEXT:    sc $9, 0($3)
 ; MIPS4-NEXT:    beqz $9, .LBB14_1
 ; MIPS4-NEXT:    nop
 ; MIPS4-NEXT:  # %bb.2: # %entry
-; MIPS4-NEXT:    and $1, $7, $5
-; MIPS4-NEXT:    srlv $1, $1, $3
-; MIPS4-NEXT:    sll $1, $1, 16
-; MIPS4-NEXT:    sra $1, $1, 16
+; MIPS4-NEXT:    and $2, $7, $5
+; MIPS4-NEXT:    srlv $2, $2, $1
+; MIPS4-NEXT:    sll $2, $2, 16
+; MIPS4-NEXT:    sra $2, $2, 16
 ; MIPS4-NEXT:  # %bb.3: # %entry
-; MIPS4-NEXT:    sll $1, $1, 16
 ; MIPS4-NEXT:    jr $ra
-; MIPS4-NEXT:    sra $2, $1, 16
+; MIPS4-NEXT:    nop
 ;
 ; MIPS64-LABEL: AtomicLoadAdd16:
 ; MIPS64:       # %bb.0: # %entry
 ; MIPS64-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS64-NEXT:    daddu $1, $1, $25
 ; MIPS64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS64-NEXT:    ld $1, %got_disp(z)($1)
 ; MIPS64-NEXT:    daddiu $2, $zero, -4
-; MIPS64-NEXT:    and $2, $1, $2
+; MIPS64-NEXT:    and $3, $1, $2
 ; MIPS64-NEXT:    andi $1, $1, 3
-; MIPS64-NEXT:    sll $3, $1, 3
-; MIPS64-NEXT:    ori $1, $zero, 65535
-; MIPS64-NEXT:    sllv $5, $1, $3
+; MIPS64-NEXT:    sll $1, $1, 3
+; MIPS64-NEXT:    ori $2, $zero, 65535
+; MIPS64-NEXT:    sllv $5, $2, $1
 ; MIPS64-NEXT:    nor $6, $zero, $5
-; MIPS64-NEXT:    sllv $4, $4, $3
+; MIPS64-NEXT:    sllv $4, $4, $1
 ; MIPS64-NEXT:  .LBB14_1: # %entry
 ; MIPS64-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64-NEXT:    ll $7, 0($2)
+; MIPS64-NEXT:    ll $7, 0($3)
 ; MIPS64-NEXT:    addu $8, $7, $4
 ; MIPS64-NEXT:    and $8, $8, $5
 ; MIPS64-NEXT:    and $9, $7, $6
 ; MIPS64-NEXT:    or $9, $9, $8
-; MIPS64-NEXT:    sc $9, 0($2)
+; MIPS64-NEXT:    sc $9, 0($3)
 ; MIPS64-NEXT:    beqz $9, .LBB14_1
 ; MIPS64-NEXT:    nop
 ; MIPS64-NEXT:  # %bb.2: # %entry
-; MIPS64-NEXT:    and $1, $7, $5
-; MIPS64-NEXT:    srlv $1, $1, $3
-; MIPS64-NEXT:    sll $1, $1, 16
-; MIPS64-NEXT:    sra $1, $1, 16
+; MIPS64-NEXT:    and $2, $7, $5
+; MIPS64-NEXT:    srlv $2, $2, $1
+; MIPS64-NEXT:    sll $2, $2, 16
+; MIPS64-NEXT:    sra $2, $2, 16
 ; MIPS64-NEXT:  # %bb.3: # %entry
-; MIPS64-NEXT:    sll $1, $1, 16
 ; MIPS64-NEXT:    jr $ra
-; MIPS64-NEXT:    sra $2, $1, 16
+; MIPS64-NEXT:    nop
 ;
 ; MIPS64R2-LABEL: AtomicLoadAdd16:
 ; MIPS64R2:       # %bb.0: # %entry
 ; MIPS64R2-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS64R2-NEXT:    daddu $1, $1, $25
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS64R2-NEXT:    ld $1, %got_disp(z)($1)
 ; MIPS64R2-NEXT:    daddiu $2, $zero, -4
-; MIPS64R2-NEXT:    and $2, $1, $2
+; MIPS64R2-NEXT:    and $3, $1, $2
 ; MIPS64R2-NEXT:    andi $1, $1, 3
-; MIPS64R2-NEXT:    sll $3, $1, 3
-; MIPS64R2-NEXT:    ori $1, $zero, 65535
-; MIPS64R2-NEXT:    sllv $5, $1, $3
+; MIPS64R2-NEXT:    sll $1, $1, 3
+; MIPS64R2-NEXT:    ori $2, $zero, 65535
+; MIPS64R2-NEXT:    sllv $5, $2, $1
 ; MIPS64R2-NEXT:    nor $6, $zero, $5
-; MIPS64R2-NEXT:    sllv $4, $4, $3
+; MIPS64R2-NEXT:    sllv $4, $4, $1
 ; MIPS64R2-NEXT:  .LBB14_1: # %entry
 ; MIPS64R2-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R2-NEXT:    ll $7, 0($2)
+; MIPS64R2-NEXT:    ll $7, 0($3)
 ; MIPS64R2-NEXT:    addu $8, $7, $4
 ; MIPS64R2-NEXT:    and $8, $8, $5
 ; MIPS64R2-NEXT:    and $9, $7, $6
 ; MIPS64R2-NEXT:    or $9, $9, $8
-; MIPS64R2-NEXT:    sc $9, 0($2)
+; MIPS64R2-NEXT:    sc $9, 0($3)
 ; MIPS64R2-NEXT:    beqz $9, .LBB14_1
 ; MIPS64R2-NEXT:    nop
 ; MIPS64R2-NEXT:  # %bb.2: # %entry
-; MIPS64R2-NEXT:    and $1, $7, $5
-; MIPS64R2-NEXT:    srlv $1, $1, $3
-; MIPS64R2-NEXT:    seh $1, $1
+; MIPS64R2-NEXT:    and $2, $7, $5
+; MIPS64R2-NEXT:    srlv $2, $2, $1
+; MIPS64R2-NEXT:    seh $2, $2
 ; MIPS64R2-NEXT:  # %bb.3: # %entry
 ; MIPS64R2-NEXT:    jr $ra
-; MIPS64R2-NEXT:    seh $2, $1
+; MIPS64R2-NEXT:    nop
 ;
 ; MIPS64R6-LABEL: AtomicLoadAdd16:
 ; MIPS64R6:       # %bb.0: # %entry
 ; MIPS64R6-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS64R6-NEXT:    daddu $1, $1, $25
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS64R6-NEXT:    ld $1, %got_disp(z)($1)
 ; MIPS64R6-NEXT:    daddiu $2, $zero, -4
-; MIPS64R6-NEXT:    and $2, $1, $2
+; MIPS64R6-NEXT:    and $3, $1, $2
 ; MIPS64R6-NEXT:    andi $1, $1, 3
-; MIPS64R6-NEXT:    sll $3, $1, 3
-; MIPS64R6-NEXT:    ori $1, $zero, 65535
-; MIPS64R6-NEXT:    sllv $5, $1, $3
+; MIPS64R6-NEXT:    sll $1, $1, 3
+; MIPS64R6-NEXT:    ori $2, $zero, 65535
+; MIPS64R6-NEXT:    sllv $5, $2, $1
 ; MIPS64R6-NEXT:    nor $6, $zero, $5
-; MIPS64R6-NEXT:    sllv $4, $4, $3
+; MIPS64R6-NEXT:    sllv $4, $4, $1
 ; MIPS64R6-NEXT:  .LBB14_1: # %entry
 ; MIPS64R6-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS64R6-NEXT:    ll $7, 0($2)
+; MIPS64R6-NEXT:    ll $7, 0($3)
 ; MIPS64R6-NEXT:    addu $8, $7, $4
 ; MIPS64R6-NEXT:    and $8, $8, $5
 ; MIPS64R6-NEXT:    and $9, $7, $6
 ; MIPS64R6-NEXT:    or $9, $9, $8
-; MIPS64R6-NEXT:    sc $9, 0($2)
+; MIPS64R6-NEXT:    sc $9, 0($3)
 ; MIPS64R6-NEXT:    beqzc $9, .LBB14_1
 ; MIPS64R6-NEXT:  # %bb.2: # %entry
-; MIPS64R6-NEXT:    and $1, $7, $5
-; MIPS64R6-NEXT:    srlv $1, $1, $3
-; MIPS64R6-NEXT:    seh $1, $1
+; MIPS64R6-NEXT:    and $2, $7, $5
+; MIPS64R6-NEXT:    srlv $2, $2, $1
+; MIPS64R6-NEXT:    seh $2, $2
 ; MIPS64R6-NEXT:  # %bb.3: # %entry
-; MIPS64R6-NEXT:    jr $ra
-; MIPS64R6-NEXT:    seh $2, $1
+; MIPS64R6-NEXT:    jrc $ra
 ;
 ; MIPS64R6O0-LABEL: AtomicLoadAdd16:
 ; MIPS64R6O0:       # %bb.0: # %entry
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, -16
 ; MIPS64R6O0-NEXT:    lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS64R6O0-NEXT:    daddu $1, $1, $25
 ; MIPS64R6O0-NEXT:    daddiu $2, $1, %lo(%neg(%gp_rel(AtomicLoadAdd16)))
 ; MIPS64R6O0-NEXT:    move $1, $4

 ; MIPS64R6O0-NEXT:    beqzc $4, .LBB14_1
 ; MIPS64R6O0-NEXT:  # %bb.2: # %entry
 ; MIPS64R6O0-NEXT:    and $1, $2, $7
 ; MIPS64R6O0-NEXT:    srlv $1, $1, $9
 ; MIPS64R6O0-NEXT:    seh $1, $1
 ; MIPS64R6O0-NEXT:  # %bb.3: # %entry
 ; MIPS64R6O0-NEXT:    sw $1, 12($sp) # 4-byte Folded Spill
 ; MIPS64R6O0-NEXT:  # %bb.4: # %entry
-; MIPS64R6O0-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
-; MIPS64R6O0-NEXT:    seh $2, $1
+; MIPS64R6O0-NEXT:    lw $2, 12($sp) # 4-byte Folded Reload
 ; MIPS64R6O0-NEXT:    daddiu $sp, $sp, 16
 ; MIPS64R6O0-NEXT:    jrc $ra
 ;
 ; MM32-LABEL: AtomicLoadAdd16:
 ; MM32:       # %bb.0: # %entry
 ; MM32-NEXT:    lui $2, %hi(_gp_disp)
 ; MM32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MM32-NEXT:    addu $2, $2, $25
 ; MM32-NEXT:    lw $1, %got(z)($2)
 ; MM32-NEXT:    addiu $2, $zero, -4
-; MM32-NEXT:    and $2, $1, $2
+; MM32-NEXT:    and $3, $1, $2
 ; MM32-NEXT:    andi $1, $1, 3
-; MM32-NEXT:    sll $3, $1, 3
-; MM32-NEXT:    ori $1, $zero, 65535
-; MM32-NEXT:    sllv $5, $1, $3
+; MM32-NEXT:    sll $1, $1, 3
+; MM32-NEXT:    ori $2, $zero, 65535
+; MM32-NEXT:    sllv $5, $2, $1
 ; MM32-NEXT:    nor $6, $zero, $5
-; MM32-NEXT:    sllv $4, $4, $3
+; MM32-NEXT:    sllv $4, $4, $1
 ; MM32-NEXT:  $BB14_1: # %entry
 ; MM32-NEXT:    # =>This Inner Loop Header: Depth=1
-; MM32-NEXT:    ll $7, 0($2)
+; MM32-NEXT:    ll $7, 0($3)
 ; MM32-NEXT:    addu $8, $7, $4
 ; MM32-NEXT:    and $8, $8, $5
 ; MM32-NEXT:    and $9, $7, $6
 ; MM32-NEXT:    or $9, $9, $8
-; MM32-NEXT:    sc $9, 0($2)
+; MM32-NEXT:    sc $9, 0($3)
 ; MM32-NEXT:    beqzc $9, $BB14_1
 ; MM32-NEXT:  # %bb.2: # %entry
-; MM32-NEXT:    and $1, $7, $5
-; MM32-NEXT:    srlv $1, $1, $3
-; MM32-NEXT:    seh $1, $1
+; MM32-NEXT:    and $2, $7, $5
+; MM32-NEXT:    srlv $2, $2, $1
+; MM32-NEXT:    seh $2, $2
 ; MM32-NEXT:  # %bb.3: # %entry
-; MM32-NEXT:    jr $ra
-; MM32-NEXT:    seh $2, $1
+; MM32-NEXT:    jrc $ra
 ;
 ; O1-LABEL: AtomicLoadAdd16:
 ; O1:       # %bb.0: # %entry
 ; O1-NEXT:    lui $2, %hi(_gp_disp)
 ; O1-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O1-NEXT:    addu $1, $2, $25
 ; O1-NEXT:    lw $1, %got(z)($1)
 ; O1-NEXT:    addiu $2, $zero, -4
-; O1-NEXT:    and $2, $1, $2
+; O1-NEXT:    and $3, $1, $2
 ; O1-NEXT:    andi $1, $1, 3
-; O1-NEXT:    sll $3, $1, 3
-; O1-NEXT:    ori $1, $zero, 65535
-; O1-NEXT:    sllv $5, $1, $3
+; O1-NEXT:    sll $1, $1, 3
+; O1-NEXT:    ori $2, $zero, 65535
+; O1-NEXT:    sllv $5, $2, $1
 ; O1-NEXT:    nor $6, $zero, $5
-; O1-NEXT:    sllv $4, $4, $3
+; O1-NEXT:    sllv $4, $4, $1
 ; O1-NEXT:  $BB14_1: # %entry
 ; O1-NEXT:    # =>This Inner Loop Header: Depth=1
-; O1-NEXT:    ll $7, 0($2)
+; O1-NEXT:    ll $7, 0($3)
 ; O1-NEXT:    addu $8, $7, $4
 ; O1-NEXT:    and $8, $8, $5
 ; O1-NEXT:    and $9, $7, $6
 ; O1-NEXT:    or $9, $9, $8
-; O1-NEXT:    sc $9, 0($2)
+; O1-NEXT:    sc $9, 0($3)
 ; O1-NEXT:    beqz $9, $BB14_1
 ; O1-NEXT:    nop
 ; O1-NEXT:  # %bb.2: # %entry
-; O1-NEXT:    and $1, $7, $5
-; O1-NEXT:    srlv $1, $1, $3
-; O1-NEXT:    sll $1, $1, 16
-; O1-NEXT:    sra $1, $1, 16
+; O1-NEXT:    and $2, $7, $5
+; O1-NEXT:    srlv $2, $2, $1
+; O1-NEXT:    sll $2, $2, 16
+; O1-NEXT:    sra $2, $2, 16
 ; O1-NEXT:  # %bb.3: # %entry
-; O1-NEXT:    sll $1, $1, 16
 ; O1-NEXT:    jr $ra
-; O1-NEXT:    sra $2, $1, 16
+; O1-NEXT:    nop
 ;
 ; O2-LABEL: AtomicLoadAdd16:
 ; O2:       # %bb.0: # %entry
 ; O2-NEXT:    lui $2, %hi(_gp_disp)
 ; O2-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O2-NEXT:    addu $1, $2, $25
 ; O2-NEXT:    lw $1, %got(z)($1)
 ; O2-NEXT:    addiu $2, $zero, -4
-; O2-NEXT:    and $2, $1, $2
+; O2-NEXT:    and $3, $1, $2
 ; O2-NEXT:    andi $1, $1, 3
-; O2-NEXT:    sll $3, $1, 3
-; O2-NEXT:    ori $1, $zero, 65535
-; O2-NEXT:    sllv $5, $1, $3
+; O2-NEXT:    sll $1, $1, 3
+; O2-NEXT:    ori $2, $zero, 65535
+; O2-NEXT:    sllv $5, $2, $1
 ; O2-NEXT:    nor $6, $zero, $5
-; O2-NEXT:    sllv $4, $4, $3
+; O2-NEXT:    sllv $4, $4, $1
 ; O2-NEXT:  $BB14_1: # %entry
 ; O2-NEXT:    # =>This Inner Loop Header: Depth=1
-; O2-NEXT:    ll $7, 0($2)
+; O2-NEXT:    ll $7, 0($3)
 ; O2-NEXT:    addu $8, $7, $4
 ; O2-NEXT:    and $8, $8, $5
 ; O2-NEXT:    and $9, $7, $6
 ; O2-NEXT:    or $9, $9, $8
-; O2-NEXT:    sc $9, 0($2)
+; O2-NEXT:    sc $9, 0($3)
 ; O2-NEXT:    beqz $9, $BB14_1
 ; O2-NEXT:    nop
 ; O2-NEXT:  # %bb.2: # %entry
-; O2-NEXT:    and $1, $7, $5
-; O2-NEXT:    srlv $1, $1, $3
-; O2-NEXT:    sll $1, $1, 16
-; O2-NEXT:    sra $1, $1, 16
+; O2-NEXT:    and $2, $7, $5
+; O2-NEXT:    srlv $2, $2, $1
+; O2-NEXT:    sll $2, $2, 16
+; O2-NEXT:    sra $2, $2, 16
 ; O2-NEXT:  # %bb.3: # %entry
-; O2-NEXT:    sll $1, $1, 16
 ; O2-NEXT:    jr $ra
-; O2-NEXT:    sra $2, $1, 16
+; O2-NEXT:    nop
 ;
 ; O3-LABEL: AtomicLoadAdd16:
 ; O3:       # %bb.0: # %entry
 ; O3-NEXT:    lui $2, %hi(_gp_disp)
 ; O3-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O3-NEXT:    addu $1, $2, $25
 ; O3-NEXT:    addiu $2, $zero, -4
 ; O3-NEXT:    lw $1, %got(z)($1)
-; O3-NEXT:    and $2, $1, $2
+; O3-NEXT:    and $3, $1, $2
 ; O3-NEXT:    andi $1, $1, 3
-; O3-NEXT:    sll $3, $1, 3
-; O3-NEXT:    ori $1, $zero, 65535
-; O3-NEXT:    sllv $5, $1, $3
-; O3-NEXT:    sllv $4, $4, $3
+; O3-NEXT:    ori $2, $zero, 65535
+; O3-NEXT:    sll $1, $1, 3
+; O3-NEXT:    sllv $5, $2, $1
+; O3-NEXT:    sllv $4, $4, $1
 ; O3-NEXT:    nor $6, $zero, $5
 ; O3-NEXT:  $BB14_1: # %entry
 ; O3-NEXT:    # =>This Inner Loop Header: Depth=1
-; O3-NEXT:    ll $7, 0($2)
+; O3-NEXT:    ll $7, 0($3)
 ; O3-NEXT:    addu $8, $7, $4
 ; O3-NEXT:    and $8, $8, $5
 ; O3-NEXT:    and $9, $7, $6
 ; O3-NEXT:    or $9, $9, $8
-; O3-NEXT:    sc $9, 0($2)
+; O3-NEXT:    sc $9, 0($3)
 ; O3-NEXT:    beqz $9, $BB14_1
 ; O3-NEXT:    nop
 ; O3-NEXT:  # %bb.2: # %entry
-; O3-NEXT:    and $1, $7, $5
-; O3-NEXT:    srlv $1, $1, $3
-; O3-NEXT:    sll $1, $1, 16
-; O3-NEXT:    sra $1, $1, 16
+; O3-NEXT:    and $2, $7, $5
+; O3-NEXT:    srlv $2, $2, $1
+; O3-NEXT:    sll $2, $2, 16
+; O3-NEXT:    sra $2, $2, 16
 ; O3-NEXT:  # %bb.3: # %entry
-; O3-NEXT:    sll $1, $1, 16
 ; O3-NEXT:    jr $ra
-; O3-NEXT:    sra $2, $1, 16
+; O3-NEXT:    nop
 ;
 ; MIPS32EB-LABEL: AtomicLoadAdd16:
 ; MIPS32EB:       # %bb.0: # %entry
 ; MIPS32EB-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32EB-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32EB-NEXT:    addu $1, $2, $25
 ; MIPS32EB-NEXT:    lw $1, %got(z)($1)
 ; MIPS32EB-NEXT:    addiu $2, $zero, -4
-; MIPS32EB-NEXT:    and $2, $1, $2
+; MIPS32EB-NEXT:    and $3, $1, $2
 ; MIPS32EB-NEXT:    andi $1, $1, 3
 ; MIPS32EB-NEXT:    xori $1, $1, 2
-; MIPS32EB-NEXT:    sll $3, $1, 3
-; MIPS32EB-NEXT:    ori $1, $zero, 65535
-; MIPS32EB-NEXT:    sllv $5, $1, $3
+; MIPS32EB-NEXT:    sll $1, $1, 3
+; MIPS32EB-NEXT:    ori $2, $zero, 65535
+; MIPS32EB-NEXT:    sllv $5, $2, $1
 ; MIPS32EB-NEXT:    nor $6, $zero, $5
-; MIPS32EB-NEXT:    sllv $4, $4, $3
+; MIPS32EB-NEXT:    sllv $4, $4, $1
 ; MIPS32EB-NEXT:  $BB14_1: # %entry
 ; MIPS32EB-NEXT:    # =>This Inner Loop Header: Depth=1
-; MIPS32EB-NEXT:    ll $7, 0($2)
+; MIPS32EB-NEXT:    ll $7, 0($3)
 ; MIPS32EB-NEXT:    addu $8, $7, $4
 ; MIPS32EB-NEXT:    and $8, $8, $5
 ; MIPS32EB-NEXT:    and $9, $7, $6
 ; MIPS32EB-NEXT:    or $9, $9, $8
-; MIPS32EB-NEXT:    sc $9, 0($2)
+; MIPS32EB-NEXT:    sc $9, 0($3)
 ; MIPS32EB-NEXT:    beqz $9, $BB14_1
 ; MIPS32EB-NEXT:    nop
 ; MIPS32EB-NEXT:  # %bb.2: # %entry
-; MIPS32EB-NEXT:    and $1, $7, $5
-; MIPS32EB-NEXT:    srlv $1, $1, $3
-; MIPS32EB-NEXT:    sll $1, $1, 16
-; MIPS32EB-NEXT:    sra $1, $1, 16
+; MIPS32EB-NEXT:    and $2, $7, $5
+; MIPS32EB-NEXT:    srlv $2, $2, $1
+; MIPS32EB-NEXT:    sll $2, $2, 16
+; MIPS32EB-NEXT:    sra $2, $2, 16
 ; MIPS32EB-NEXT:  # %bb.3: # %entry
-; MIPS32EB-NEXT:    sll $1, $1, 16
 ; MIPS32EB-NEXT:    jr $ra
-; MIPS32EB-NEXT:    sra $2, $1, 16
+; MIPS32EB-NEXT:    nop
 entry:
   %0 = atomicrmw add i16* @z, i16 %incr monotonic
   ret i16 %0
 
 }
 
 ; Test that the i16 return value from cmpxchg is recognised as signed,
 ; so that setCC doesn't end up comparing an unsigned value to a signed

llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll

 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_0_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_align16_int16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_align32_int16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_align64_int16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_reg_int16_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_or_int16_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i16
   ret i16 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_not_disjoint16_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_disjoint_align16_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_not_disjoint32_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_disjoint_align32_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int16_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 56
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 56
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_not_disjoint64_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_disjoint_align64_int16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_cst_align16_int16_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_cst_align32_int16_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_int16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i16 @ld_cst_align64_int16_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_0_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align16_uint16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align32_uint16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align64_uint16_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_reg_uint16_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_or_uint16_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i16
   ret i16 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 56
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 56
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align16_uint16_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align32_uint16_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_uint16_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint16_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i16
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i16 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_0_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align16_uint16_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align32_uint16_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_align64_uint16_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_reg_uint16_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_or_uint16_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 48
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 48
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   ret i16 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align16_uint16_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   ret i16 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align32_uint16_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_uint16_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   ret i16 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint16_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   ret i16 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i16 @ld_0_uint16_t_uint32_t(i64 %ptr) {

llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll

 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_0_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align16_int32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align32_int32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align64_int32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_reg_int32_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_or_int32_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint16_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align16_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint32_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align32_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 56
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 56
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint64_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align64_int32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align16_int32_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align32_int32_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_int32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align64_int32_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_0_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align16_int32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align32_int32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_align64_int32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_reg_int32_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_or_int32_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv1 = zext i16 %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint16_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align16_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint32_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align32_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 48
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 48
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_not_disjoint64_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_disjoint_align64_int32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align16_int32_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align32_int32_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_int32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local signext i32 @ld_cst_align64_int32_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_0_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align16_uint32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align32_uint32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align64_uint32_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_reg_uint32_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_or_uint32_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 56
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 56
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_uint32_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_0_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align16_uint32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align32_uint32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_align64_uint32_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_reg_uint32_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_or_uint32_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv1 = zext i16 %1 to i32
   ret i32 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 48
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 48
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   %conv = zext i16 %1 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_uint32_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint32_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   %conv = zext i16 %0 to i32
   ret i32 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn

llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll

 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREP10,CHECK-P8
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_int64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_int64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_int64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_int64_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_int64_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align32_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int64_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 56
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 56
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_int64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_int64_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_int64_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_int64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_int64_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_int64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_int64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_int64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_int64_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_int64_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv1 = zext i16 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align32_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_int64_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 48
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 48
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_int64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_int64_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_int64_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_int64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_int64_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_int64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i64 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_uint64_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_uint64_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_uint64_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv1 = zext i8 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align32_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint64_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 56
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 56
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_uint64_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   %conv = zext i8 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_uint64_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_uint64_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_uint64_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_uint64_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint64_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   %conv = zext i8 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
entry:
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_0_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align16_uint64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align32_uint64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_align64_uint64_t_uint16_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_reg_uint64_t_uint16_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = bitcast i8* %add.ptr to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_or_uint64_t_uint16_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv1 = zext i16 %1 to i64
   ret i64 %conv1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint16_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align16_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lhz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 8
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint32_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lhz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align32_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint64_t_uint16_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lhzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 48
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint16_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lhzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 48
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 16
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_not_disjoint64_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 2
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_disjoint_align64_uint64_t_uint16_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lhzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lhzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i16*
   %1 = load atomic i16, i16* %0 monotonic, align 4096
   %conv = zext i16 %1 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align16_uint64_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align16_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lhz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align32_uint64_t_uint16_t() {
 ; CHECK-LABEL: ld_cst_align32_uint64_t_uint16_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lhz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local i64 @ld_cst_align64_uint64_t_uint16_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint64_t_uint16_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lhz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 48
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint16_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lhz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 48
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096
   %conv = zext i16 %0 to i64
   ret i64 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn

llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll

entry:
   ret i8 %conv
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_0_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_0_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = inttoptr i64 %ptr to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_align16_uint8_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-LABEL: ld_align16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 8(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_align32_uint8_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align32_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 99999000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align32_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 1525
 ; CHECK-PREP10-NEXT:    ori r4, r4, 56600
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_align64_uint8_t_uint8_t(i8* nocapture readonly %ptr) {
 ; CHECK-P10-LABEL: ld_align64_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_align64_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_reg_uint8_t_uint8_t(i8* nocapture readonly %ptr, i64 %off) {
 ; CHECK-LABEL: ld_reg_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbzx r3, r3, r4
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off
   %0 = load atomic i8, i8* %add.ptr monotonic, align 1
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_or_uint8_t_uint8_t(i64 %ptr, i8 zeroext %off) {
 ; CHECK-LABEL: ld_or_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %conv = zext i8 %off to i64
   %or = or i64 %conv, %ptr
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 6
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 6
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_disjoint_align16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rldicr r3, r3, 0, 51
 ; CHECK-NEXT:    lbz r3, 24(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %and = and i64 %ptr, -4096
   %or = or i64 %and, 24
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 8
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-LABEL: ld_not_disjoint32_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ori r3, r3, 34463
 ; CHECK-NEXT:    oris r3, r3, 1
 ; CHECK-NEXT:    lbz r3, 0(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %ptr, 99999
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    lis r4, -15264
 ; CHECK-P10-NEXT:    and r3, r3, r4
 ; CHECK-P10-NEXT:    pli r4, 999990000
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r4, -15264
 ; CHECK-P9-NEXT:    and r3, r3, r4
 ; CHECK-P9-NEXT:    lis r4, 15258
 ; CHECK-P9-NEXT:    ori r4, r4, 41712
 ; CHECK-P9-NEXT:    lbzx r3, r3, r4
-; CHECK-P9-NEXT:    clrldi r3, r3, 56
+; CHECK-P9-NEXT:    clrldi r3, r3, 32
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint8_t:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    lis r4, -15264
 ; CHECK-P8-NEXT:    lis r5, 15258
 ; CHECK-P8-NEXT:    and r3, r3, r4
 ; CHECK-P8-NEXT:    ori r4, r5, 41712
 ; CHECK-P8-NEXT:    lbzx r3, r3, r4
-; CHECK-P8-NEXT:    clrldi r3, r3, 56
+; CHECK-P8-NEXT:    clrldi r3, r3, 32
 ; CHECK-P8-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1000341504
   %or = or i64 %and, 999990000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 16
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_not_disjoint64_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 232
 ; CHECK-P10-NEXT:    pli r5, 3567587329
 ; CHECK-P10-NEXT:    rldimi r5, r4, 32, 0
 ; CHECK-P10-NEXT:    or r3, r3, r5
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    li r4, 29
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 35, 24
 ; CHECK-PREP10-NEXT:    oris r4, r4, 54437
 ; CHECK-PREP10-NEXT:    ori r4, r4, 4097
 ; CHECK-PREP10-NEXT:    or r3, r3, r4
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %or = or i64 %ptr, 1000000000001
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 1
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_uint8_t(i64 %ptr) {
 ; CHECK-P10-LABEL: ld_disjoint_align64_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r4, 244140625
 ; CHECK-P10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-P10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-P10-NEXT:    lbzx r3, r3, r4
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r4, 3725
 ; CHECK-PREP10-NEXT:    rldicr r3, r3, 0, 23
 ; CHECK-PREP10-NEXT:    ori r4, r4, 19025
 ; CHECK-PREP10-NEXT:    rldic r4, r4, 12, 24
 ; CHECK-PREP10-NEXT:    lbzx r3, r3, r4
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %and = and i64 %ptr, -1099511627776
   %or = or i64 %and, 1000000000000
   %0 = inttoptr i64 %or to i8*
   %1 = load atomic i8, i8* %0 monotonic, align 4096
   ret i8 %1
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align16_uint8_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align16_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lbz r3, 4080(0)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align32_uint8_t_uint8_t() {
 ; CHECK-LABEL: ld_cst_align32_uint8_t_uint8_t:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lis r3, 153
 ; CHECK-NEXT:    lbz r3, -27108(r3)
-; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_cst_align64_uint8_t_uint8_t() {
 ; CHECK-P10-LABEL: ld_cst_align64_uint8_t_uint8_t:
 ; CHECK-P10:       # %bb.0: # %entry
 ; CHECK-P10-NEXT:    pli r3, 244140625
 ; CHECK-P10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-P10-NEXT:    lbz r3, 0(r3)
-; CHECK-P10-NEXT:    clrldi r3, r3, 56
+; CHECK-P10-NEXT:    clrldi r3, r3, 32
 ; CHECK-P10-NEXT:    blr
 ;
 ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_uint8_t:
 ; CHECK-PREP10:       # %bb.0: # %entry
 ; CHECK-PREP10-NEXT:    lis r3, 3725
 ; CHECK-PREP10-NEXT:    ori r3, r3, 19025
 ; CHECK-PREP10-NEXT:    rldic r3, r3, 12, 24
 ; CHECK-PREP10-NEXT:    lbz r3, 0(r3)
-; CHECK-PREP10-NEXT:    clrldi r3, r3, 56
+; CHECK-PREP10-NEXT:    clrldi r3, r3, 32
 ; CHECK-PREP10-NEXT:    blr
 entry:
   %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096
   ret i8 %0
 }
 
 ; Function Attrs: nofree norecurse nounwind uwtable willreturn
 define dso_local zeroext i8 @ld_0_uint8_t_uint16_t(i64 %ptr) {

llvm/test/CodeGen/PowerPC/ppc-partword-atomic.ll

 ; PWR9-NEXT:    sync
 ; PWR9-NEXT:    addi 5, 4, value8@toc@l
 ; PWR9-NEXT:  .LBB0_1: # %entry
 ; PWR9-NEXT:    #
 ; PWR9-NEXT:    lbarx 4, 0, 5
 ; PWR9-NEXT:    stbcx. 3, 0, 5
 ; PWR9-NEXT:    bne 0, .LBB0_1
 ; PWR9-NEXT:  # %bb.2: # %entry
-; PWR9-NEXT:    clrlwi 3, 4, 24
-; PWR9-NEXT:    addis 4, 2, global_int@toc@ha
+; PWR9-NEXT:    addis 3, 2, global_int@toc@ha
 ; PWR9-NEXT:    lwsync
-; PWR9-NEXT:    stw 3, global_int@toc@l(4)
+; PWR9-NEXT:    stw 4, global_int@toc@l(3)
 ; PWR9-NEXT:    li 3, 55
 ; PWR9-NEXT:    blr
 entry:
   %0 = atomicrmw xchg i8* getelementptr inbounds ({ i8 }, { i8 }* @value8, i64 0, i32 0), i8 %val seq_cst, align 1
   %conv = zext i8 %0 to i32
   store i32 %conv, i32* @global_int, align 4
   ret i32 55
 }

 ; PWR9-NEXT:    sync
 ; PWR9-NEXT:    addi 5, 4, value16@toc@l
 ; PWR9-NEXT:  .LBB1_1: # %entry
 ; PWR9-NEXT:    #
 ; PWR9-NEXT:    lharx 4, 0, 5
 ; PWR9-NEXT:    sthcx. 3, 0, 5
 ; PWR9-NEXT:    bne 0, .LBB1_1
 ; PWR9-NEXT:  # %bb.2: # %entry
-; PWR9-NEXT:    clrlwi 3, 4, 16
-; PWR9-NEXT:    addis 4, 2, global_int@toc@ha
+; PWR9-NEXT:    addis 3, 2, global_int@toc@ha
 ; PWR9-NEXT:    lwsync
-; PWR9-NEXT:    stw 3, global_int@toc@l(4)
+; PWR9-NEXT:    stw 4, global_int@toc@l(3)
 ; PWR9-NEXT:    li 3, 55
 ; PWR9-NEXT:    blr
 entry:
   %0 = atomicrmw xchg i16* getelementptr inbounds ({ i16 }, { i16 }* @value16, i64 0, i32 0), i16 %val seq_cst, align 2
   %conv = zext i16 %0 to i32
   store i32 %conv, i32* @global_int, align 4
   ret i32 55
 }
 
 attributes #0 = { nounwind }

llvm/test/CodeGen/RISCV/atomic-signext.ll

 define signext i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
 ; RV32I-LABEL: atomic_load_i8_unordered:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    call __atomic_load_1@plt
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_load_i8_unordered:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    lb a0, 0(a0)
-; RV32IA-NEXT:    slli a0, a0, 24
-; RV32IA-NEXT:    srai a0, a0, 24
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomic_load_i8_unordered:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv a1, zero
 ; RV64I-NEXT:    call __atomic_load_1@plt
 ; RV64I-NEXT:    slli a0, a0, 56
 ; RV64I-NEXT:    srai a0, a0, 56
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomic_load_i8_unordered:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    lb a0, 0(a0)
-; RV64IA-NEXT:    slli a0, a0, 56
-; RV64IA-NEXT:    srai a0, a0, 56
 ; RV64IA-NEXT:    ret
   %1 = load atomic i8, i8* %a unordered, align 1
   ret i8 %1
 }
 
 define signext i16 @atomic_load_i16_unordered(i16 *%a) nounwind {
 ; RV32I-LABEL: atomic_load_i16_unordered:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    call __atomic_load_2@plt
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomic_load_i16_unordered:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    lh a0, 0(a0)
-; RV32IA-NEXT:    slli a0, a0, 16
-; RV32IA-NEXT:    srai a0, a0, 16
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomic_load_i16_unordered:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv a1, zero
 ; RV64I-NEXT:    call __atomic_load_2@plt
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomic_load_i16_unordered:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    lh a0, 0(a0)
-; RV64IA-NEXT:    slli a0, a0, 48
-; RV64IA-NEXT:    srai a0, a0, 48
 ; RV64IA-NEXT:    ret
   %1 = load atomic i16, i16* %a unordered, align 2
   ret i16 %1
 }
 
 define signext i32 @atomic_load_i32_unordered(i32 *%a) nounwind {
 ; RV32I-LABEL: atomic_load_i32_unordered:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomic_load_i32_unordered:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    lw a0, 0(a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = load atomic i32, i32* %a unordered, align 4
   ret i32 %1
 }
 
 
 define signext i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i8_monotonic:

 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xchg_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    amoswap.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_add_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_add_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    amoadd.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw add i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_sub_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    neg a1, a1
 ; RV64IA-NEXT:    amoadd.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_and_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_and_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    amoand.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw and i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:  .LBB29_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a2, (a0)
 ; RV64IA-NEXT:    and a3, a2, a1
 ; RV64IA-NEXT:    not a3, a3
 ; RV64IA-NEXT:    sc.w a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB29_1
 ; RV64IA-NEXT:  # %bb.2:
-; RV64IA-NEXT:    sext.w a0, a2
+; RV64IA-NEXT:    mv a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_or_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_or_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    amoor.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw or i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xor_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xor_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    amoxor.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    amomax.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    amomin.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umax_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umax_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    amomaxu.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_umin_i32_monotonic:
 ; RV32I:       # %bb.0:

 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_umin_i32_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    amominu.w a0, a1, (a0)
-; RV64IA-NEXT:    sext.w a0, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i32* %a, i32 %b monotonic
   ret i32 %1
 }
 
 define signext i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i64_monotonic:
 ; RV32I:       # %bb.0: