[DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines

[frasercrmck]

Summary

This patch adds incrementally-better support for SPLAT_VECTOR in a
handful of vector combines by changing a few more
isBuildVectorAllOnes/isBuildVectorAllZeros to the equivalent
isConstantSplatVectorAllOnes/Zeros calls.

[frasercrmck]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

10053–10054

I wasn't sure if I should reword this comment. Unsure how it could be done without just making it more verbose.

[paulwalker-arm]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

10053–10054

Perhaps just drop build_vector?

[frasercrmck]

• update comment according to feedback

[frasercrmck]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

10053–10054

Aye that looks pretty good, thanks.

[frasercrmck]

• rebase
• update SVE test case to account for optimizations

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (ISD::isConstantSplatVectorAllZeros(N0.getNode()))
       return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
                              SDLoc(N), N0.getValueType());
     if (ISD::isConstantSplatVectorAllZeros(N1.getNode()))
       // do not return N1, because undef node may exist in N1
       return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
                              SDLoc(N), N1.getValueType());
 
     // fold (and x, -1) -> x, vector edition
-    if (ISD::isBuildVectorAllOnes(N0.getNode()))
+    if (ISD::isConstantSplatVectorAllOnes(N0.getNode()))
       return N1;
-    if (ISD::isBuildVectorAllOnes(N1.getNode()))
+    if (ISD::isConstantSplatVectorAllOnes(N1.getNode()))
       return N0;
 
     // fold (and (masked_load) (build_vec (x, ...))) to zext_masked_load
     auto *MLoad = dyn_cast<MaskedLoadSDNode>(N0);
     auto *BVec = dyn_cast<BuildVectorSDNode>(N1);
     if (MLoad && BVec && MLoad->getExtensionType() == ISD::EXTLOAD &&
         N0.hasOneUse() && N1.hasOneUse()) {
       EVT LoadVT = MLoad->getMemoryVT();
if (VT.isVector()) {
 
     // fold (or x, 0) -> x, vector edition
     if (ISD::isConstantSplatVectorAllZeros(N0.getNode()))
       return N1;
     if (ISD::isConstantSplatVectorAllZeros(N1.getNode()))
       return N0;
 
     // fold (or x, -1) -> -1, vector edition
-    if (ISD::isBuildVectorAllOnes(N0.getNode()))
+    if (ISD::isConstantSplatVectorAllOnes(N0.getNode()))
       // do not return N0, because undef node may exist in N0
       return DAG.getAllOnesConstant(SDLoc(N), N0.getValueType());
-    if (ISD::isBuildVectorAllOnes(N1.getNode()))
+    if (ISD::isConstantSplatVectorAllOnes(N1.getNode()))
       // do not return N1, because undef node may exist in N1
       return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType());
 
     // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
     // Do this only if the resulting shuffle is legal.
     if (isa<ShuffleVectorSDNode>(N0) &&
         isa<ShuffleVectorSDNode>(N1) &&
         // Avoid folding a node with illegal type.
if (hasOperation(ISD::USUBSAT, VT)) {
           }
         }
       }
     }
   }
 
   if (SimplifySelectOps(N, N1, N2))
     return SDValue(N, 0);  // Don't revisit N.
 
-  // Fold (vselect (build_vector all_ones), N1, N2) -> N1
-  if (ISD::isBuildVectorAllOnes(N0.getNode()))
+  // Fold (vselect all_ones, N1, N2) -> N1
+  if (ISD::isConstantSplatVectorAllOnes(N0.getNode()))
     return N1;
-  // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
-  if (ISD::isBuildVectorAllZeros(N0.getNode()))
+  // Fold (vselect all_zeros, N1, N2) -> N2
+  if (ISD::isConstantSplatVectorAllZeros(N0.getNode()))
     return N2;
 
   // The ConvertSelectToConcatVector function is assuming both the above
   // checks for (vselect (build_vector all{ones,zeros) ...) have been made
   // and addressed.
   if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
       N2.getOpcode() == ISD::CONCAT_VECTORS &&
       ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {

llvm/test/CodeGen/AArch64/sve-expand-div.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
 
 ; Check that expensive divides are expanded into a more performant sequence
 
 ;
 ; SDIV
 ;
 
 define <vscale x 16 x i8> @sdiv_i8(<vscale x 16 x i8> %a) #0 {
 ; CHECK-LABEL: sdiv_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z1.b, #86 // =0x56
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    smulh z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT:    lsr z1.b, z0.b, #7
-; CHECK-NEXT:    mov z2.b, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
 ; CHECK-NEXT:    add z0.b, z0.b, z1.b
 ; CHECK-NEXT:    ret
   %div = sdiv <vscale x 16 x i8> %a, shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> undef, i8 3, i32 0), <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer)
   ret <vscale x 16 x i8> %div
 }
 
 define <vscale x 8 x i16> @sdiv_i16(<vscale x 8 x i16> %a) #0 {
 ; CHECK-LABEL: sdiv_i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #21846
-; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    mov z1.h, w8
+; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    smulh z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    lsr z1.h, z0.h, #15
-; CHECK-NEXT:    mov z2.h, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
 ; CHECK-NEXT:    add z0.h, z0.h, z1.h
 ; CHECK-NEXT:    ret
   %div = sdiv <vscale x 8 x i16> %a, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 3, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer)
   ret <vscale x 8 x i16> %div
 }
 
 define <vscale x 4 x i32> @sdiv_i32(<vscale x 4 x i32> %a) #0 {
 ; CHECK-LABEL: sdiv_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #21846
 ; CHECK-NEXT:    movk w8, #21845, lsl #16
-; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    mov z1.s, w8
+; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    smulh z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    lsr z1.s, z0.s, #31
-; CHECK-NEXT:    mov z2.s, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
 ; CHECK-NEXT:    add z0.s, z0.s, z1.s
 ; CHECK-NEXT:    ret
   %div = sdiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
   ret <vscale x 4 x i32> %div
 }
 
 define <vscale x 2 x i64> @sdiv_i64(<vscale x 2 x i64> %a) #0 {
 ; CHECK-LABEL: sdiv_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #6148914691236517205
 ; CHECK-NEXT:    movk x8, #21846
-; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    mov z1.d, x8
+; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    smulh z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT:    lsr z1.d, z0.d, #63
-; CHECK-NEXT:    mov z2.d, #-1 // =0xffffffffffffffff
-; CHECK-NEXT:    and z1.d, z1.d, z2.d
 ; CHECK-NEXT:    add z0.d, z0.d, z1.d
 ; CHECK-NEXT:    ret
   %div = sdiv <vscale x 2 x i64> %a, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 3, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer)
   ret <vscale x 2 x i64> %div
 }
 
 ;
 ; UDIV

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vrsub.vi v28, v8, 0
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vrsub.vi v8, v8, 0
 ; CHECK-NEXT:    vadd.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v8, v28, 7
-; CHECK-NEXT:    vand.vi v8, v8, -1
 ; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vrsub.vi v8, v8, 0
 ; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    vsra.vi v8, v8, 2
 ; CHECK-NEXT:    vsrl.vi v16, v8, 7
-; CHECK-NEXT:    vand.vi v16, v16, -1
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = sdiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsra.vi v26, v26, 1
 ; CHECK-NEXT:    vsrl.vi v28, v26, 15
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsra.vi v28, v28, 1
 ; CHECK-NEXT:    vsrl.vi v8, v28, 15
-; CHECK-NEXT:    vand.vi v8, v8, -1
 ; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v8, v8, a0
 ; CHECK-NEXT:    vsra.vi v8, v8, 1
 ; CHECK-NEXT:    vsrl.vi v16, v8, 15
-; CHECK-NEXT:    vand.vi v16, v16, -1
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 

 define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
-; CHECK-NEXT:    vsra.vi v26, v25, 2
-; CHECK-NEXT:    vsrl.vi v25, v25, 31
-; CHECK-NEXT:    vand.vi v25, v25, -1
-; CHECK-NEXT:    vadd.vv v8, v26, v25
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdiv_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {

 define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
-; CHECK-NEXT:    vsra.vi v26, v25, 2
-; CHECK-NEXT:    vsrl.vi v25, v25, 31
-; CHECK-NEXT:    vand.vi v25, v25, -1
-; CHECK-NEXT:    vadd.vv v8, v26, v25
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdiv_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {

 define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsub.vv v26, v26, v8
-; CHECK-NEXT:    vsra.vi v28, v26, 2
-; CHECK-NEXT:    vsrl.vi v26, v26, 31
-; CHECK-NEXT:    vand.vi v26, v26, -1
-; CHECK-NEXT:    vadd.vv v8, v28, v26
+; CHECK-NEXT:    vsrl.vi v28, v26, 31
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdiv_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {

 define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsub.vv v28, v28, v8
-; CHECK-NEXT:    vsra.vi v8, v28, 2
-; CHECK-NEXT:    vsrl.vi v28, v28, 31
-; CHECK-NEXT:    vand.vi v28, v28, -1
-; CHECK-NEXT:    vadd.vv v8, v8, v28
+; CHECK-NEXT:    vsrl.vi v8, v28, 31
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdiv_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {

 define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsub.vv v8, v16, v8
-; CHECK-NEXT:    vsra.vi v16, v8, 2
-; CHECK-NEXT:    vsrl.vi v8, v8, 31
-; CHECK-NEXT:    vand.vi v8, v8, -1
-; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsrl.vi v16, v8, 31
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vdiv_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {

 ; CHECK-NEXT:    vsll.vx v25, v25, a0
 ; CHECK-NEXT:    lui a1, 898779
 ; CHECK-NEXT:    addi a1, a1, 1755
 ; CHECK-NEXT:    vmv.v.x v26, a1
 ; CHECK-NEXT:    vsll.vx v26, v26, a0
 ; CHECK-NEXT:    vsrl.vx v26, v26, a0
 ; CHECK-NEXT:    vor.vv v25, v26, v25
 ; CHECK-NEXT:    vmulh.vv v25, v8, v25
-; CHECK-NEXT:    vsra.vi v26, v25, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v25, v25, a0
-; CHECK-NEXT:    vand.vi v25, v25, -1
-; CHECK-NEXT:    vadd.vv v8, v26, v25
+; CHECK-NEXT:    vsrl.vx v26, v25, a0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdiv_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {

 ; CHECK-NEXT:    vsll.vx v26, v26, a0
 ; CHECK-NEXT:    lui a1, 898779
 ; CHECK-NEXT:    addi a1, a1, 1755
 ; CHECK-NEXT:    vmv.v.x v28, a1
 ; CHECK-NEXT:    vsll.vx v28, v28, a0
 ; CHECK-NEXT:    vsrl.vx v28, v28, a0
 ; CHECK-NEXT:    vor.vv v26, v28, v26
 ; CHECK-NEXT:    vmulh.vv v26, v8, v26
-; CHECK-NEXT:    vsra.vi v28, v26, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v26, v26, a0
-; CHECK-NEXT:    vand.vi v26, v26, -1
-; CHECK-NEXT:    vadd.vv v8, v28, v26
+; CHECK-NEXT:    vsrl.vx v28, v26, a0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdiv_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {

 ; CHECK-NEXT:    vsll.vx v28, v28, a0
 ; CHECK-NEXT:    lui a1, 898779
 ; CHECK-NEXT:    addi a1, a1, 1755
 ; CHECK-NEXT:    vmv.v.x v12, a1
 ; CHECK-NEXT:    vsll.vx v12, v12, a0
 ; CHECK-NEXT:    vsrl.vx v12, v12, a0
 ; CHECK-NEXT:    vor.vv v28, v12, v28
 ; CHECK-NEXT:    vmulh.vv v28, v8, v28
-; CHECK-NEXT:    vsra.vi v8, v28, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v28, v28, a0
-; CHECK-NEXT:    vand.vi v28, v28, -1
-; CHECK-NEXT:    vadd.vv v8, v8, v28
+; CHECK-NEXT:    vsrl.vx v8, v28, a0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdiv_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {

 ; CHECK-NEXT:    vsll.vx v16, v16, a0
 ; CHECK-NEXT:    lui a1, 898779
 ; CHECK-NEXT:    addi a1, a1, 1755
 ; CHECK-NEXT:    vmv.v.x v24, a1
 ; CHECK-NEXT:    vsll.vx v24, v24, a0
 ; CHECK-NEXT:    vsrl.vx v24, v24, a0
 ; CHECK-NEXT:    vor.vv v16, v24, v16
 ; CHECK-NEXT:    vmulh.vv v8, v8, v16
-; CHECK-NEXT:    vsra.vi v16, v8, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v8, v8, a0
-; CHECK-NEXT:    vand.vi v8, v8, -1
-; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsrl.vx v16, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vrsub.vi v28, v8, 0
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vrsub.vi v8, v8, 0
 ; CHECK-NEXT:    vadd.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v8, v28, 7
-; CHECK-NEXT:    vand.vi v8, v8, -1
 ; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vrsub.vi v8, v8, 0
 ; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    vsra.vi v8, v8, 2
 ; CHECK-NEXT:    vsrl.vi v16, v8, 7
-; CHECK-NEXT:    vand.vi v16, v16, -1
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = sdiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsra.vi v26, v26, 1
 ; CHECK-NEXT:    vsrl.vi v28, v26, 15
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsra.vi v28, v28, 1
 ; CHECK-NEXT:    vsrl.vi v8, v28, 15
-; CHECK-NEXT:    vand.vi v8, v8, -1
 ; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 

 ; CHECK-LABEL: vdiv_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v8, v8, a0
 ; CHECK-NEXT:    vsra.vi v8, v8, 1
 ; CHECK-NEXT:    vsrl.vi v16, v8, 15
-; CHECK-NEXT:    vand.vi v16, v16, -1
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vrsub.vi v28, v8, 0
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 31
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vrsub.vi v8, v8, 0
 ; CHECK-NEXT:    vadd.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v8, v28, 31
-; CHECK-NEXT:    vand.vi v8, v8, -1
 ; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vrsub.vi v8, v8, 0
 ; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    vsra.vi v8, v8, 2
 ; CHECK-NEXT:    vsrl.vi v16, v8, 31
-; CHECK-NEXT:    vand.vi v16, v16, -1
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 

 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vsra.vi v26, v25, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v25, v25, a0
-; CHECK-NEXT:    vand.vi v25, v25, -1
-; CHECK-NEXT:    vadd.vv v8, v26, v25
+; CHECK-NEXT:    vsrl.vx v26, v25, a0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdiv_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {

 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
-; CHECK-NEXT:    vsra.vi v28, v26, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v26, v26, a0
-; CHECK-NEXT:    vand.vi v26, v26, -1
-; CHECK-NEXT:    vadd.vv v8, v28, v26
+; CHECK-NEXT:    vsrl.vx v28, v26, a0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdiv_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {

 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
-; CHECK-NEXT:    vsra.vi v8, v28, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v28, v28, a0
-; CHECK-NEXT:    vand.vi v28, v28, -1
-; CHECK-NEXT:    vadd.vv v8, v8, v28
+; CHECK-NEXT:    vsrl.vx v8, v28, a0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdiv_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {

 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v8, v8, a0
-; CHECK-NEXT:    vsra.vi v16, v8, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v8, v8, a0
-; CHECK-NEXT:    vand.vi v8, v8, -1
-; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsrl.vx v16, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll

; CHECK-NEXT:    ret
   %vc = or <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vor_vx_nxv8i64_3(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vor_vx_nxv8i64_3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vor.vi v8, v8, -1
+; CHECK-NEXT:    vmv.v.i v8, -1
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = or <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }

llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll

; CHECK-NEXT:    ret
   ret <vscale x 8 x i64> %vc
 }
 
 
 define <vscale x 8 x i64> @vor_vx_nxv8i64_3(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vor_vx_nxv8i64_3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vor.vi v8, v8, -1
+; CHECK-NEXT:    vmv.v.i v8, -1
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = or <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vrsub.vi v28, v8, 0
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vrsub.vi v12, v8, 0
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v12, v28, 7
-; CHECK-NEXT:    vand.vi v12, v12, -1
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vrsub.vi v24, v8, 0
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vsrl.vi v24, v16, 7
-; CHECK-NEXT:    vand.vi v24, v24, -1
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = srem <vscale x 64 x i8> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsra.vi v26, v26, 1
 ; CHECK-NEXT:    vsrl.vi v28, v26, 15
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsra.vi v28, v28, 1
 ; CHECK-NEXT:    vsrl.vi v12, v28, 15
-; CHECK-NEXT:    vand.vi v12, v12, -1
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsra.vi v16, v16, 1
 ; CHECK-NEXT:    vsrl.vi v24, v16, 15
-; CHECK-NEXT:    vand.vi v24, v24, -1
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat

 define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
-; CHECK-NEXT:    vsra.vi v26, v25, 2
-; CHECK-NEXT:    vsrl.vi v25, v25, 31
-; CHECK-NEXT:    vand.vi v25, v25, -1
-; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc

 define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsub.vv v25, v25, v8
-; CHECK-NEXT:    vsra.vi v26, v25, 2
-; CHECK-NEXT:    vsrl.vi v25, v25, 31
-; CHECK-NEXT:    vand.vi v25, v25, -1
-; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc

 define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsub.vv v26, v26, v8
-; CHECK-NEXT:    vsra.vi v28, v26, 2
-; CHECK-NEXT:    vsrl.vi v26, v26, 31
-; CHECK-NEXT:    vand.vi v26, v26, -1
-; CHECK-NEXT:    vadd.vv v26, v28, v26
+; CHECK-NEXT:    vsrl.vi v28, v26, 31
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc

 define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsub.vv v28, v28, v8
-; CHECK-NEXT:    vsra.vi v12, v28, 2
-; CHECK-NEXT:    vsrl.vi v28, v28, 31
-; CHECK-NEXT:    vand.vi v28, v28, -1
-; CHECK-NEXT:    vadd.vv v28, v12, v28
+; CHECK-NEXT:    vsrl.vi v12, v28, 31
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc

 define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsub.vv v16, v16, v8
-; CHECK-NEXT:    vsra.vi v24, v16, 2
-; CHECK-NEXT:    vsrl.vi v16, v16, 31
-; CHECK-NEXT:    vand.vi v16, v16, -1
-; CHECK-NEXT:    vadd.vv v16, v24, v16
+; CHECK-NEXT:    vsrl.vi v24, v16, 31
+; CHECK-NEXT:    vsra.vi v16, v16, 2
+; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc

 ; CHECK-NEXT:    vsll.vx v25, v25, a0
 ; CHECK-NEXT:    lui a1, 898779
 ; CHECK-NEXT:    addi a1, a1, 1755
 ; CHECK-NEXT:    vmv.v.x v26, a1
 ; CHECK-NEXT:    vsll.vx v26, v26, a0
 ; CHECK-NEXT:    vsrl.vx v26, v26, a0
 ; CHECK-NEXT:    vor.vv v25, v26, v25
 ; CHECK-NEXT:    vmulh.vv v25, v8, v25
-; CHECK-NEXT:    vsra.vi v26, v25, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v25, v25, a0
-; CHECK-NEXT:    vand.vi v25, v25, -1
-; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    vsrl.vx v26, v25, a0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc

 ; CHECK-NEXT:    vsll.vx v26, v26, a0
 ; CHECK-NEXT:    lui a1, 898779
 ; CHECK-NEXT:    addi a1, a1, 1755
 ; CHECK-NEXT:    vmv.v.x v28, a1
 ; CHECK-NEXT:    vsll.vx v28, v28, a0
 ; CHECK-NEXT:    vsrl.vx v28, v28, a0
 ; CHECK-NEXT:    vor.vv v26, v28, v26
 ; CHECK-NEXT:    vmulh.vv v26, v8, v26
-; CHECK-NEXT:    vsra.vi v28, v26, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v26, v26, a0
-; CHECK-NEXT:    vand.vi v26, v26, -1
-; CHECK-NEXT:    vadd.vv v26, v28, v26
+; CHECK-NEXT:    vsrl.vx v28, v26, a0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc

 ; CHECK-NEXT:    vsll.vx v28, v28, a0
 ; CHECK-NEXT:    lui a1, 898779
 ; CHECK-NEXT:    addi a1, a1, 1755
 ; CHECK-NEXT:    vmv.v.x v12, a1
 ; CHECK-NEXT:    vsll.vx v12, v12, a0
 ; CHECK-NEXT:    vsrl.vx v12, v12, a0
 ; CHECK-NEXT:    vor.vv v28, v12, v28
 ; CHECK-NEXT:    vmulh.vv v28, v8, v28
-; CHECK-NEXT:    vsra.vi v12, v28, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v28, v28, a0
-; CHECK-NEXT:    vand.vi v28, v28, -1
-; CHECK-NEXT:    vadd.vv v28, v12, v28
+; CHECK-NEXT:    vsrl.vx v12, v28, a0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc

 ; CHECK-NEXT:    vsll.vx v16, v16, a0
 ; CHECK-NEXT:    lui a1, 898779
 ; CHECK-NEXT:    addi a1, a1, 1755
 ; CHECK-NEXT:    vmv.v.x v24, a1
 ; CHECK-NEXT:    vsll.vx v24, v24, a0
 ; CHECK-NEXT:    vsrl.vx v24, v24, a0
 ; CHECK-NEXT:    vor.vv v16, v24, v16
 ; CHECK-NEXT:    vmulh.vv v16, v8, v16
-; CHECK-NEXT:    vsra.vi v24, v16, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v16, v16, a0
-; CHECK-NEXT:    vand.vi v16, v16, -1
-; CHECK-NEXT:    vadd.vv v16, v24, v16
+; CHECK-NEXT:    vsrl.vx v24, v16, a0
+; CHECK-NEXT:    vsra.vi v16, v16, 1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vrsub.vi v28, v8, 0
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vrsub.vi v12, v8, 0
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v12, v28, 7
-; CHECK-NEXT:    vand.vi v12, v12, -1
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i8> %va, %splat

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vrsub.vi v24, v8, 0
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vsrl.vi v24, v16, 7
-; CHECK-NEXT:    vand.vi v24, v24, -1
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = srem <vscale x 64 x i8> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vsra.vi v25, v25, 1
 ; CHECK-NEXT:    vsrl.vi v26, v25, 15
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vsra.vi v26, v26, 1
 ; CHECK-NEXT:    vsrl.vi v28, v26, 15
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vsra.vi v28, v28, 1
 ; CHECK-NEXT:    vsrl.vi v12, v28, 15
-; CHECK-NEXT:    vand.vi v12, v12, -1
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat

 ; CHECK-LABEL: vrem_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 1048571
 ; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vsra.vi v16, v16, 1
 ; CHECK-NEXT:    vsrl.vi v24, v16, 15
-; CHECK-NEXT:    vand.vi v24, v24, -1
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
 ; CHECK-NEXT:    vrsub.vi v26, v8, 0
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
-; CHECK-NEXT:    vand.vi v26, v26, -1
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
 ; CHECK-NEXT:    vrsub.vi v28, v8, 0
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 31
-; CHECK-NEXT:    vand.vi v28, v28, -1
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
 ; CHECK-NEXT:    vrsub.vi v12, v8, 0
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v12, v28, 31
-; CHECK-NEXT:    vand.vi v12, v12, -1
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat

 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
 ; CHECK-NEXT:    vrsub.vi v24, v8, 0
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vsrl.vi v24, v16, 31
-; CHECK-NEXT:    vand.vi v24, v24, -1
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat

 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vsra.vi v26, v25, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v25, v25, a0
-; CHECK-NEXT:    vand.vi v25, v25, -1
-; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    vsrl.vx v26, v25, a0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc

 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
-; CHECK-NEXT:    vsra.vi v28, v26, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v26, v26, a0
-; CHECK-NEXT:    vand.vi v26, v26, -1
-; CHECK-NEXT:    vadd.vv v26, v28, v26
+; CHECK-NEXT:    vsrl.vx v28, v26, a0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc

 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
-; CHECK-NEXT:    vsra.vi v12, v28, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v28, v28, a0
-; CHECK-NEXT:    vand.vi v28, v28, -1
-; CHECK-NEXT:    vadd.vv v28, v12, v28
+; CHECK-NEXT:    vsrl.vx v12, v28, a0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc

 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    slli a0, a0, 12
 ; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
-; CHECK-NEXT:    vsra.vi v24, v16, 1
 ; CHECK-NEXT:    addi a0, zero, 63
-; CHECK-NEXT:    vsrl.vx v16, v16, a0
-; CHECK-NEXT:    vand.vi v16, v16, -1
-; CHECK-NEXT:    vadd.vv v16, v24, v16
+; CHECK-NEXT:    vsrl.vx v24, v16, a0
+; CHECK-NEXT:    vsra.vi v16, v16, 1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
   %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %splat, <vscale x 8 x half> %va
   ret <vscale x 8 x half> %vc
 }
 
 define <vscale x 8 x half> @vmerge_truelhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
 ; CHECK-LABEL: vmerge_truelhs_nxv8f16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vmset.m v0
-; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
 ; CHECK-NEXT:    ret
   %mhead = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <vscale x 8 x i1> %mhead, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
   %vc = select <vscale x 8 x i1> %mtrue, <vscale x 8 x half> %va, <vscale x 8 x half> %vb
   ret <vscale x 8 x half> %vc
 }
 
 define <vscale x 8 x half> @vmerge_falselhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
 ; CHECK-LABEL: vmerge_falselhs_nxv8f16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vmclr.m v0
-; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
+; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
   %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x half> %va, <vscale x 8 x half> %vb
   ret <vscale x 8 x half> %vc
 }
 
 define <vscale x 16 x half> @vfmerge_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %cond) {
 ; CHECK-LABEL: vfmerge_vv_nxv16f16:
 ; CHECK:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
   %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %splat, <vscale x 8 x half> %va
   ret <vscale x 8 x half> %vc
 }
 
 define <vscale x 8 x half> @vmerge_truelhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
 ; CHECK-LABEL: vmerge_truelhs_nxv8f16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vmset.m v0
-; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
 ; CHECK-NEXT:    ret
   %mhead = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <vscale x 8 x i1> %mhead, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
   %vc = select <vscale x 8 x i1> %mtrue, <vscale x 8 x half> %va, <vscale x 8 x half> %vb
   ret <vscale x 8 x half> %vc
 }
 
 define <vscale x 8 x half> @vmerge_falselhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
 ; CHECK-LABEL: vmerge_falselhs_nxv8f16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vmclr.m v0
-; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
+; CHECK-NEXT:    vmv2r.v v8, v10
 ; CHECK-NEXT:    ret
   %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x half> %va, <vscale x 8 x half> %vb
   ret <vscale x 8 x half> %vc
 }
 
 define <vscale x 16 x half> @vfmerge_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %cond) {
 ; CHECK-LABEL: vfmerge_vv_nxv16f16:
 ; CHECK:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> %splat, <vscale x 8 x i64> %va
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vmerge_truelhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
 ; CHECK-LABEL: vmerge_truelhs_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vmset.m v0
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %mhead = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <vscale x 8 x i1> %mhead, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
   %vc = select <vscale x 8 x i1> %mtrue, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vmerge_falselhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
 ; CHECK-LABEL: vmerge_falselhs_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vmclr.m v0
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    ret
   %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
   ret <vscale x 8 x i64> %vc
 }

llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> %splat, <vscale x 8 x i64> %va
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vmerge_truelhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
 ; CHECK-LABEL: vmerge_truelhs_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vmset.m v0
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %mhead = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
   %mtrue = shufflevector <vscale x 8 x i1> %mhead, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
   %vc = select <vscale x 8 x i1> %mtrue, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vmerge_falselhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
 ; CHECK-LABEL: vmerge_falselhs_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vmclr.m v0
-; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT:    vmv8r.v v8, v16
 ; CHECK-NEXT:    ret
   %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
   ret <vscale x 8 x i64> %vc
 }