[SelectionDAG] Add Target-Independent Compiler Barrier

[lenary]

Summary

Several different target backends end up implementing compiler-only
barrier pseudo-instructions which eventually expand into an assembly
comment.

These come from for example C's atomic_signal_fence, C++'s
std::atomic_signal_fence, or Rust's compiler_barrier which are all
documented to not result in assembly instructions. While emitting a
fence instruction (or equivalent) is not incorrect within usual memory
models, it is inefficient. Depending on the target configuration, these
usually turn into atomic_fence before SelectionDAG (with syncscope of
"singlethread"), where they are then turned first into a target-specific
ISD node, and then into a pseudo-instruction which prints as a comment.

Most LLVM Target backends seem to have copied a MEMBARRIER
target-specific ISD node, so every new LLVM target needs to replicate
all these parts to get the same behaviour. Some targets don't do this,
and end up emitting fence instructions without paying attention to the
syncscope fence argument.

LLVM, however, has target-independent machine opcodes, which have a
variety of uses in LLVM's backend code. This patch adds a
COMPILER_BARRIER target-independent opcode to represent a compiler-only
barrier, which does not generate instructions. This opcode still
contains information about the syncscope and ordering of the original
atomic_fence, so that backend-specific optimisations still have this
information.

This patch also refactors existing instances of target-specific
MEMBARRIERs to use the new target-independent COMPILER_BARRIER.

[lenary]

RFC Thread on llvm-dev: http://lists.llvm.org/pipermail/llvm-dev/2020-December/147318.html

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

28637

Would it make sense to have a SelectionDAG::getCompilerBarrier method that would hide most of the boilerplate for creating these nodes?

[lenary]

llvm/lib/Target/X86/X86ISelLowering.cpp

28637

Almost certainly.

One thing I did run into was I wanted to keep the ordering in the barrier around for later passes - but I ran into issues on x86 where the immediate I was using to represent it was getting allocated into a register and that caused instruction verification to fail. I could look at bringing that back if people thought it was useful (for instance, later Machine Passes may want to know if they can hoist/sink loads and stores past a barrier with more granularity than just "No").

[arsenm]

llvm/include/llvm/Support/TargetOpcodes.def

212–215

I think the scope should also be parameterized. This also does not match the description of the defined instruction which is missing the ordering operand

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

28637

Can you use getTargetConstant? That should never end up in a register.

[lenary]

llvm/include/llvm/Support/TargetOpcodes.def

212–215

The documentation about ordering is out of date, I did include it before, but then ran into x86 issues, so removed it. I'm looking at bringing it back with @craig.topper's suggestions.

Because this barrier explicitly does not translate to machine code (that would be a place where you used a target-dependent fence or similar), I don't want to suggest this has any syncscope that is not singlethread, but maybe that's wrong?

llvm/lib/Target/X86/X86ISelLowering.cpp

28637

I'll try again, I cannot remember exactly what I used for that version of the code.

[lenary]

• Include Ordering Again (using getTargetConstant)
• Add Helper for creating DAG nodes

[jrtc27]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

279

I don't think this should be reached any more?

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

607

The change to emitFunctionBody should render this dead?

llvm/test/CodeGen/X86/atomic-idempotent.ll

384

What's up with this change?

[craig.topper]

llvm/test/CodeGen/X86/atomic-idempotent.ll

384

I'm guessing that TargetOpcode::COMPILER_BARRIER is giving a different value from TargetSchedMode::computeInstrLatency() that X86::MEMBARRIER did which changed how X86PadShortFunctions.cpp computed how many NOPs to add before the return.

[jrtc27]

llvm/test/CodeGen/X86/atomic-idempotent.ll

384

I guess the question then is "which is better?".

[craig.topper]

llvm/test/CodeGen/X86/atomic-idempotent.ll

384

I think we were counting a "compiler barrier" that doesn't generate code as having a non-zero or multiple cycle latency before. So this change is probably better.

[lenary]

• Address Minor Review Comments, Method Naming issues.

[jrtc27]

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

610

"both" no longer applies

[lenary]

• Comments and Whitespace

[lenary]

Ping

@arsenm Please may you clarify why you think the scope is still useful to represent this late?

[skan]

FYI, this patch also fix the bug that "X86::Int_MemBarrier should be a MetaInstruction".

[skan]

@lenary Do you need to update something? There are three tests fail according to the log.

[lenary]

In D92842#2533053, @skan wrote:

@lenary Do you need to update something? There are three tests fail according to the log.

I'm waiting for some confirmation that people are happy with the approach. I've had a little feedback but not much, and hardly any actual code review.

Can you link to the bug you are referencing? With a bug to point to, it'll be easier to push for this to land.

[skan]

In D92842#2561721, @lenary wrote:

Can you link to the bug you are referencing? With a bug to point to, it'll be easier to push for this to land.

The failed LIT tests in the remote tests are "x64 debian > LLVM.CodeGen/RISCV::atomic-fence.ll", "x64 windows > LLVM.CodeGen/RISCV::atomic-fence.ll", "x64 windows > LLVM.CodeGen/XCore::threads.ll", I think you can see them on this page.

The bug "X86::Int_MemBarrier should be a MetaInstruction" is an internal bug, I found it when I was doing some development work about debug info personally. Although I could not give a failed test, here is a way to trigger that:

define dso_local i32 @main() !dbg !7 {
entry:
  fence acquire, !dbg !9
  fence release, !dbg !9
  %retval = alloca i32, align 4
  store i32 0, i32* %retval, align 4
  ret i32 0, !dbg !9
}

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5}
!llvm.ident = !{!6}

!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: DebugDirectivesOnly, enums: !2, splitDebugInlining: false, nameTableKind: None)
!1 = !DIFile(filename: "none.c", directory: "/temp")
!2 = !{}
!3 = !{i32 2, !"PersonalFlag", i32 1}
!4 = !{i32 2, !"Debug Info Version", i32 3}
!5 = !{i32 1, !"wchar_size", i32 4}
!6 = !{!"clang version 11.0.0"}
!7 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 1, type: !8, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
!8 = !DISubroutineType(types: !2)
!9 = !DILocation(line: 1, column: 14, scope: !7)

llc -O0 -mtriple x86_64-linux-gnu  test.ll

IR fence acquire and fence release is lowered to X86::Int_MemBarrier, and the interface bool isMetaInstruction() const returns false for it. So if you add an assert
for this, the program will crash.

[lenary]

Updated based on review feedback:

• Migrated more targets to COMPILER_BARRIER
• Added syncscope argument to COMPILER_BARRIER

[lenary]

llvm/include/llvm/Support/TargetOpcodes.def

212

Sorry, I missed this comment

[lenary]

I'm looking for reviewers from the following targets for this change:

• VE - @simoll would you be willing to?
• XCore - @nigelp-xmos would you be willing to?

[nigelp-xmos]

Yes, I will look at this for the XCore target.

[nigelp-xmos]

XCore change LGTM. (Commenting on XCore only.)

[nigelp-xmos]

llvm/include/llvm/Target/TargetSelectionDAG.td defines SDTMemBarrier. This seems to have been introduced in 9b254eed32028 for ISD::MEMBARRIER, which was removed some time ago. I can't find a use of it and I can build without it. Could SDTMemBarrier be removed and would it belong in this patch?

[lenary]

In D92842#2821463, @nigelp-xmos wrote:

llvm/include/llvm/Target/TargetSelectionDAG.td defines SDTMemBarrier. This seems to have been introduced in 9b254eed32028 for ISD::MEMBARRIER, which was removed some time ago. I can't find a use of it and I can build without it. Could SDTMemBarrier be removed and would it belong in this patch?

Yes, that makes sense to me, I think I removed some target-specific TypeProfiles which were now unused, so it makes sense to remove this too.

[pengfei]

Reverse ping. Is there any blocker issue for this patch landing?

[skan]

In D92842#2570304, @skan wrote:

In D92842#2561721, @lenary wrote:

Can you link to the bug you are referencing? With a bug to point to, it'll be easier to push for this to land.

The failed LIT tests in the remote tests are "x64 debian > LLVM.CodeGen/RISCV::atomic-fence.ll", "x64 windows > LLVM.CodeGen/RISCV::atomic-fence.ll", "x64 windows > LLVM.CodeGen/XCore::threads.ll", I think you can see them on this page.

The bug "X86::Int_MemBarrier should be a MetaInstruction" is an internal bug, I found it when I was doing some development work about debug info personally. Although I could not give a failed test, here is a way to trigger that:

define dso_local i32 @main() !dbg !7 {
entry:
  fence acquire, !dbg !9
  fence release, !dbg !9
  %retval = alloca i32, align 4
  store i32 0, i32* %retval, align 4
  ret i32 0, !dbg !9
}

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5}
!llvm.ident = !{!6}

!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: DebugDirectivesOnly, enums: !2, splitDebugInlining: false, nameTableKind: None)
!1 = !DIFile(filename: "none.c", directory: "/temp")
!2 = !{}
!3 = !{i32 2, !"PersonalFlag", i32 1}
!4 = !{i32 2, !"Debug Info Version", i32 3}
!5 = !{i32 1, !"wchar_size", i32 4}
!6 = !{!"clang version 11.0.0"}
!7 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 1, type: !8, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
!8 = !DISubroutineType(types: !2)
!9 = !DILocation(line: 1, column: 14, scope: !7)

llc -O0 -mtriple x86_64-linux-gnu  test.ll

IR fence acquire and fence release is lowered to X86::Int_MemBarrier, and the interface bool isMetaInstruction() const returns false for it. So if you add an assert
for this, the program will crash.

A LIT test is provided at D121879.

[lenary]

In D92842#3388199, @pengfei wrote:

Reverse ping. Is there any blocker issue for this patch landing?

iirc, I have some planned changes and haven't got back to them recently. In the meantime, hopefully @skan's patch tides you over.

[pengfei]

In D92842#3388658, @lenary wrote:

In D92842#3388199, @pengfei wrote:

Reverse ping. Is there any blocker issue for this patch landing?

iirc, I have some planned changes and haven't got back to them recently. In the meantime, hopefully @skan's patch tides you over.

Thanks! I personally prefer this patch. But yes, we can land @skan's patch first.

[lenary]

Superseded by work from @reames

[reames]

Replying here mostly so I can find the information later.

Over the last few days, I have submitted a couple of changes which factor out a target independent MEMBARRIER node. At this point, all targets except ARM, AArch64, AMDGPU, and WebAssembly have been migrated. The former two are on review, the third I don't plan to touch as it uses a late expansion of atomic_fence instead, and has some target specific logic based on that which is hard to follow without architecture context I don't have. The fourth I haven't looked at closely as I just found the alternate spelling of the barrier name it uses.

The choice of MEMBARRIER vs COMPILER_BARRIER naming was arbitrary. I went with what more targets seemed to have used to minimize test churn.

I didn't find an in tree example which required the ordering on the generic instruction. Given that, I left it out. I am not opposed to adding it, but would like to see a justification before we add complexity.

As far as I can tell, the scope argument in this patch is purely spurious. A MEMBARRIER can only have a single scope - SingleThread. This is definitely true for all the targets I've looked at closely. AMDGPU *might* be a counter example, but I don't understand the semantics of it's scopes closely well enough to know for sure.

Finally, this patch contains two functional changes to the x86 backend. I did not include those. Separating those out - with tests! - would likely be valuable. I'd be happy to review if you wanted to do that.

llvm/include/llvm/CodeGen/MachineInstr.h

bool isMetaInstruction() const {
     case TargetOpcode::EH_LABEL:
     case TargetOpcode::GC_LABEL:
     case TargetOpcode::DBG_VALUE:
     case TargetOpcode::DBG_INSTR_REF:
     case TargetOpcode::DBG_LABEL:
     case TargetOpcode::LIFETIME_START:
     case TargetOpcode::LIFETIME_END:
     case TargetOpcode::PSEUDO_PROBE:
+    case TargetOpcode::COMPILER_BARRIER:
       return true;
     }
   }
 
   /// Return true if this is a transient instruction that is either very likely
   /// to be eliminated during register allocation (such as copy-like
   /// instructions), or if this instruction doesn't have an execution-time cost.
   bool isTransient() const {

llvm/include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL)
 
 /// Wraps a typed logging call and its argument with nop sleds. At runtime, this
 /// can be patched to insert instrumentation instructions.
 HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL)
 
 HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL)
 
+// This is a fence with the singlethread scope. It has a single operand, which
+// is the ordering requested. This instruction has `mayLoad` and `mayStore`, so
+// that memory operations are not moved around it.
+HANDLE_TARGET_OPCODE(COMPILER_BARRIER)
+
 /// The following generic opcodes are not supposed to appear after ISel.
 /// This is something we might want to relax, but for now, this is convenient
 /// to produce diagnostics.
 
 /// Generic ADD instruction. This is an integer add.
 HANDLE_TARGET_OPCODE(G_ADD)
 HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
 

llvm/include/llvm/Target/Target.td

def FENTRY_CALL : StandardPseudoInstruction {
   let hasSideEffects = true;
 }
 def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
   let hasSideEffects = true;
 }
+def COMPILER_BARRIER : StandardPseudoInstruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+  let AsmString = "# Compiler Barrier";
+  let hasSideEffects = true;
+  let Size = 0;
+}
 
 // Generic opcodes used in GlobalISel.
 include "llvm/Target/GenericOpcodes.td"
 
 //===----------------------------------------------------------------------===//
 // AsmParser - This class can be implemented by targets that wish to implement
 // .s file parsing.
 //

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

for (auto &MI : MBB) {
         }
         break;
       case TargetOpcode::IMPLICIT_DEF:
         if (isVerbose()) emitImplicitDef(&MI);
         break;
       case TargetOpcode::KILL:
         if (isVerbose()) emitKill(&MI, *this);
         break;
+      case TargetOpcode::COMPILER_BARRIER:
+        OutStreamer->emitRawComment(" Compiler Barrier");
+        break;
       default:
         emitInstruction(&MI);
         if (CanDoExtraAnalysis) {
           MCInst MCI;
           MCI.setOpcode(MI.getOpcode());
           auto Name = OutStreamer->getMnemonic(MCI);
           auto I = MnemonicCounts.insert({Name, 0u});
           I.first->second++;

llvm/lib/CodeGen/PatchableFunction.cpp

static bool doesNotGeneratecode(const MachineInstr &MI) {
   default: return false;
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
   case TargetOpcode::CFI_INSTRUCTION:
   case TargetOpcode::EH_LABEL:
   case TargetOpcode::GC_LABEL:
   case TargetOpcode::DBG_VALUE:
   case TargetOpcode::DBG_LABEL:
+  case TargetOpcode::COMPILER_BARRIER:
     return true;
   }
 }
 
 bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) {
   if (MF.getFunction().hasFnAttribute("patchable-function-entry")) {
     MachineBasicBlock &FirstMBB = *MF.begin();
     const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the SelectionDAG::Legalize method.
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
     SDValue Success =
         DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
 
     Results.push_back(ExtRes.getValue(0));
     Results.push_back(Success);
     Results.push_back(Res.getValue(1));
     break;
   }
+  case ISD::ATOMIC_FENCE: {
+    if (Node->getConstantOperandVal(2) == SyncScope::SingleThread) {
+      SDValue Chain = Node->getOperand(0);
+      SDValue N(DAG.getMachineNode(TargetOpcode::COMPILER_BARRIER, dl, MVT::Other, Chain), 0);
+      Results.push_back(N);
+    }
+    break;
+  }
   case ISD::DYNAMIC_STACKALLOC:
     ExpandDYNAMIC_STACKALLOC(Node, Results);
     break;
   case ISD::MERGE_VALUES:
     for (unsigned i = 0; i < Node->getNumValues(); i++)
       Results.push_back(Node->getOperand(i));
     break;
   case ISD::UNDEF: {

llvm/lib/Target/AArch64/AArch64InstrAtomics.td

 //=- AArch64InstrAtomics.td - AArch64 Atomic codegen support -*- tablegen -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // AArch64 Atomic operand code-gen constructs.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------
 // Atomic fences
 //===----------------------------------
-let AddedComplexity = 15, Size = 0 in
-def CompilerBarrier : Pseudo<(outs), (ins i32imm:$ordering),
-                             [(atomic_fence timm:$ordering, 0)]>, Sched<[]>;
+let AddedComplexity = 15 in
+def : Pat<(atomic_fence (timm), 0), (COMPILER_BARRIER)>;
 def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>;
 def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>;
 
 //===----------------------------------
 // Atomic loads
 //===----------------------------------
 
 // When they're actually atomic, only one addressing mode (GPR64sp) is

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

uint64_t Value = AArch64_AM::decodeLogicalImmediate(
         MI->getOperand(2).getImm(), RegWidth);
     if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
       O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
         << formatImm(SignExtend64(Value, RegWidth));
       return;
     }
   }
 
-  if (Opcode == AArch64::CompilerBarrier) {
+  if (Opcode == AArch64::COMPILER_BARRIER) {
     O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
     printAnnotation(O, Annot);
     return;
   }
 
   if (Opcode == AArch64::SPACE) {
     O << '\t' << MAI.getCommentString() << " SPACE "
       << MI->getOperand(1).getImm();

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

if (MI.getOpcode() == AArch64::TLSDESCCALL) {
     // This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
     // following (BLR) instruction. It doesn't emit any code itself so it
     // doesn't go through the normal TableGenerated channels.
     MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
     Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
     return;
   }
 
-  if (MI.getOpcode() == AArch64::CompilerBarrier ||
+  if (MI.getOpcode() == AArch64::COMPILER_BARRIER ||
       MI.getOpcode() == AArch64::SPACE) {
     // CompilerBarrier just prevents the compiler from reordering accesses, and
     // SPACE just increases basic block size, in both cases no actual code.
     return;
   }
 
   uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
   support::endian::write<uint32_t>(OS, Binary, support::little);
   ++MCNumEmitted; // Keep track of the # of mi's emitted.
 }
 

llvm/lib/Target/ARM/ARMInstrInfo.td

def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
                              (ins GPR:$addr, GPR:$desired, GPR:$new),
                              NoItinerary, []>, Sched<[]>;
 
 def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),
                              (ins GPR:$addr, GPRPair:$desired, GPRPair:$new),
                              NoItinerary, []>, Sched<[]>;
 }
 
-def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary,
-                                 [(atomic_fence timm:$ordering, 0)]> {
-  let hasSideEffects = 1;
-  let Size = 0;
-  let AsmString = "@ COMPILER BARRIER";
-  let hasNoSchedulingInfo = 1;
-}
+def : Pat<(atomic_fence (timm), 0), (COMPILER_BARRIER)>;

llvm/lib/Target/ARM/ARMScheduleA57.td

 
 // To have "CompleteModel = 1", support of pseudos and special instructions
 def : InstRW<[WriteNoop], (instregex "(t)?BKPT$", "(t2)?CDP(2)?$",
   "(t2)?CLREX$", "CONSTPOOL_ENTRY$", "COPY_STRUCT_BYVAL_I32$",
   "(t2)?CPS[123]p$", "(t2)?DBG$", "(t2)?DMB$", "(t2)?DSB$", "ERET$",
   "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",
   "(t2)?RFE(DA|DB|IA|IB)", "(t)?SETEND", "(t2)?SETPAN", "(t2)?SMC", "SPACE",
   "(t2)?SRS(DA|DB|IA|IB)", "SWP(B)?", "t?TRAP", "(t2|t)?UDF$", "t2DCPS", "t2SG",
-  "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "CompilerBarrier",
-  "t__brkdiv0")>;
+  "t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "t__brkdiv0")>;
 
 def : InstRW<[WriteNoop], (instregex "VMRS", "VMSR", "FMSTAT")>;
 
 // Specific memory instrs
 def : InstRW<[WriteNoop, WriteNoop], (instregex "(t2)?LDA", "(t2)?LDC", "(t2)?STC",
   "(t2)?STL", "(t2)?LDREX", "(t2)?STREX", "MEMCPY")>;
 
 // coprocessor moves

 def : SchedAlias<WriteBrTbl, A57Write_1cyc_1B_1I>;
 def : SchedAlias<WritePreLd, A57Write_4cyc_1L>;
 
 def : SchedAlias<WriteLd, A57Write_4cyc_1L>;
 def : SchedAlias<WriteST, A57Write_1cyc_1S>;
 def : ReadAdvance<ReadALU, 0>;
 
 } // SchedModel = CortexA57Model
-

llvm/lib/Target/AVR/AVRInstrInfo.cpp

unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   default: {
     const MCInstrDesc &Desc = get(Opcode);
     return Desc.getSize();
   }
   case TargetOpcode::EH_LABEL:
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
   case TargetOpcode::DBG_VALUE:
+  case TargetOpcode::COMPILER_BARRIER:
     return 0;
   case TargetOpcode::INLINEASM:
   case TargetOpcode::INLINEASM_BR: {
     const MachineFunction &MF = *MI.getParent()->getParent();
     const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget());
     const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
     const TargetInstrInfo &TII = *STI.getInstrInfo();
 
unsigned AVRInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
     // See lib/CodeGen/RegisterRelaxation.cpp for details.
     // We end up here when a jump is too long for a RJMP instruction.
     auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
 
     return getInstSizeInBytes(MI);
 }
 
 } // end of namespace llvm
-

llvm/lib/Target/MSP430/MSP430InstrInfo.cpp

unsigned MSP430InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   const MCInstrDesc &Desc = MI.getDesc();
 
   switch (Desc.getOpcode()) {
   case TargetOpcode::CFI_INSTRUCTION:
   case TargetOpcode::EH_LABEL:
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
   case TargetOpcode::DBG_VALUE:
+  case TargetOpcode::COMPILER_BARRIER:
     return 0;
   case TargetOpcode::INLINEASM:
   case TargetOpcode::INLINEASM_BR: {
     const MachineFunction *MF = MI.getParent()->getParent();
     const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
     return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
                                   *MF->getTarget().getMCAsmInfo());
   }
   }
 
   return Desc.getSize();
 }

llvm/lib/Target/Mips/MipsInstrInfo.cpp

case Mips::DADDiu: {
     // Value is sum of register and immediate. Immediate value could be
     // global string address which is not supported.
     if (Dop.isReg() && Sop1.isReg() && Sop2.isImm())
       return RegImmPair{Sop1.getReg(), Sop2.getImm()};
     // TODO: Handle case where Sop1 is a frame-index.
   }
   }
   return None;
-}
+}
 

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

if (MI.getParent() && MI.getParent()->getParent()) {
         return 2;
     }
     return get(Opcode).getSize();
   }
   case TargetOpcode::EH_LABEL:
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
   case TargetOpcode::DBG_VALUE:
+  case TargetOpcode::COMPILER_BARRIER:
     return 0;
   // These values are determined based on RISCVExpandAtomicPseudoInsts,
   // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the
   // pseudos are expanded.
   case RISCV::PseudoCALLReg:
   case RISCV::PseudoCALL:
   case RISCV::PseudoJump:
   case RISCV::PseudoTAIL:

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 // A parameterized register class alternative to i32imm/i64imm from Target.td.
 def ixlenimm : Operand<XLenVT>;
 
 def ixlenimm_li : Operand<XLenVT> {
   let ParserMatchClass = ImmXLenAsmOperand<"", "LI">;
 }
 
+def xlentimm_nonzero : TImmLeaf<XLenVT, [{return Imm != 0;}]>;
+
 // Standalone (codegen-only) immleaf patterns.
 def simm32     : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
 def simm32hi20 : ImmLeaf<XLenVT, [{return isShiftedInt<20, 12>(Imm);}]>;
 // A mask value that won't affect significant shift bits.
 def immbottomxlenset : ImmLeaf<XLenVT, [{
   if (Subtarget->is64Bit())
     return countTrailingOnes<uint64_t>(Imm) >= 6;
   return countTrailingOnes<uint64_t>(Imm) >= 5;

 defm : StPat<truncstorei16, SH, GPR>;
 defm : StPat<store, SW, GPR>, Requires<[IsRV32]>;
 
 /// Fences
 
 // Refer to Table A.6 in the version 2.3 draft of the RISC-V Instruction Set
 // Manual: Volume I.
 
+def : Pat<(atomic_fence (timm), 0), (COMPILER_BARRIER)>;
+
 // fence acquire -> fence r, rw
-def : Pat<(atomic_fence (XLenVT 4), (timm)), (FENCE 0b10, 0b11)>;
+def : Pat<(atomic_fence (XLenVT 4), (xlentimm_nonzero)), (FENCE 0b10, 0b11)>;
 // fence release -> fence rw, w
-def : Pat<(atomic_fence (XLenVT 5), (timm)), (FENCE 0b11, 0b1)>;
+def : Pat<(atomic_fence (XLenVT 5), (xlentimm_nonzero)), (FENCE 0b11, 0b1)>;
 // fence acq_rel -> fence.tso
-def : Pat<(atomic_fence (XLenVT 6), (timm)), (FENCE_TSO)>;
+def : Pat<(atomic_fence (XLenVT 6), (xlentimm_nonzero)), (FENCE_TSO)>;
 // fence seq_cst -> fence rw, rw
-def : Pat<(atomic_fence (XLenVT 7), (timm)), (FENCE 0b11, 0b11)>;
+def : Pat<(atomic_fence (XLenVT 7), (xlentimm_nonzero)), (FENCE 0b11, 0b11)>;
 
 // Lowering for atomic load and store is defined in RISCVInstrInfoA.td.
 // Although these are lowered to fence+load/store instructions defined in the
 // base RV32I/RV64I ISA, this lowering is only used when the A extension is
 // present. This is necessary as it isn't valid to mix __atomic_* libcalls
 // with inline atomic operations for the same object.
 
 /// Other pseudo-instructions

llvm/lib/Target/X86/X86ISelLowering.h

enum NodeType : unsigned {
     // falls back to heap allocation if not.
     SEG_ALLOCA,
 
     // For allocating stack space when using stack clash protector.
     // Allocation is performed by block, and each block is probed.
     PROBED_ALLOCA,
 
     // Memory barriers.
-    MEMBARRIER,
     MFENCE,
 
     // Get a random integer and indicate whether it is valid in CF.
     RDRAND,
 
     // Get a NIST SP800-90B & C compliant random integer and
     // indicate whether it is valid in CF.
     RDSEED,

llvm/lib/Target/X86/X86ISelLowering.cpp

if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
       FenceSSID == SyncScope::System) {
     if (Subtarget.hasMFence())
       return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
 
     SDValue Chain = Op.getOperand(0);
     return emitLockedStackOp(DAG, Subtarget, Chain, dl);
   }
 
-  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
-  return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
+  // COMPILER_BARRIER codegens to a 0-byte instruction.
+  return SDValue(DAG.getMachineNode(TargetOpcode::COMPILER_BARRIER, dl, MVT::Other, Op.getOperand(0)), 0);
 }
 
 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget &Subtarget,
                              SelectionDAG &DAG) {
   MVT T = Op.getSimpleValueType();
   SDLoc DL(Op);
   unsigned Reg = 0;
   unsigned size = 0;
if (AN->getOrdering() == AtomicOrdering::SequentiallyConsistent &&
       // traffic.  This assumes that stack locations are very likely to be
       // accessed only by the owning thread.
       SDValue NewChain = emitLockedStackOp(DAG, Subtarget, Chain, DL);
       assert(!N->hasAnyUseOfValue(0));
       // NOTE: The getUNDEF is needed to give something for the unused result 0.
       return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
                          DAG.getUNDEF(VT), NewChain);
     }
-    // MEMBARRIER is a compiler barrier; it codegens to a no-op.
-    SDValue NewChain = DAG.getNode(X86ISD::MEMBARRIER, DL, MVT::Other, Chain);
+
+    // COMPILER_BARRIER is a compiler barrier; it codegens to a no-op.
+    SDValue NewChain(DAG.getMachineNode(TargetOpcode::COMPILER_BARRIER, DL, MVT::Other, Chain), 0);
     assert(!N->hasAnyUseOfValue(0));
     // NOTE: The getUNDEF is needed to give something for the unused result 0.
     return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(),
                        DAG.getUNDEF(VT), NewChain);
   }
 
   SDValue LockOp = lowerAtomicArithWithLOCK(N, DAG, Subtarget);
   // RAUW the chain, but don't worry about the result, as it's unused.
#define NODE_NAME_CASE(NODE) case X86ISD::NODE: return "X86ISD::" #NODE;
   NODE_NAME_CASE(VRANGES_SAE)
   NODE_NAME_CASE(PMULUDQ)
   NODE_NAME_CASE(PMULDQ)
   NODE_NAME_CASE(PSADBW)
   NODE_NAME_CASE(DBPSADBW)
   NODE_NAME_CASE(VASTART_SAVE_XMM_REGS)
   NODE_NAME_CASE(VAARG_64)
   NODE_NAME_CASE(WIN_ALLOCA)
-  NODE_NAME_CASE(MEMBARRIER)
   NODE_NAME_CASE(MFENCE)
   NODE_NAME_CASE(SEG_ALLOCA)
   NODE_NAME_CASE(PROBED_ALLOCA)
   NODE_NAME_CASE(RDRAND)
   NODE_NAME_CASE(RDSEED)
   NODE_NAME_CASE(RDPKRU)
   NODE_NAME_CASE(WRPKRU)
   NODE_NAME_CASE(VPMADDUBSW)

llvm/lib/Target/X86/X86InstrCompiler.td

 // Memory barriers
 
 let isCodeGenOnly = 1, Defs = [EFLAGS] in
 def OR32mi8Locked  : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero),
                          "or{l}\t{$zero, $dst|$dst, $zero}", []>,
                          Requires<[Not64BitMode]>, OpSize32, LOCK,
                          Sched<[WriteALURMW]>;
 
-let hasSideEffects = 1 in
-def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
-                     "#MEMBARRIER",
-                     [(X86MemBarrier)]>, Sched<[WriteLoad]>;
-
 // RegOpc corresponds to the mr version of the instruction
 // ImmOpc corresponds to the mi version of the instruction
 // ImmOpc8 corresponds to the mi8 version of the instruction
 // ImmMod corresponds to the instruction format of the mi and mi8 versions
 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
                            Format ImmMod, SDNode Op, string mnemonic> {
 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
     SchedRW = [WriteALURMW] in {

llvm/lib/Target/X86/X86InstrInfo.cpp

default:
     // By default, assume that the instruction is not data invariant.
     return false;
 
     // Some target-independent operations that trivially lower to data-invariant
     // instructions.
   case TargetOpcode::COPY:
   case TargetOpcode::INSERT_SUBREG:
   case TargetOpcode::SUBREG_TO_REG:
+  case TargetOpcode::COMPILER_BARRIER:
     return true;
 
   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
   // However, they set flags and are perhaps the most surprisingly constant
   // time operations so we call them out here separately.
   case X86::IMUL16rr:
   case X86::IMUL16rri8:
   case X86::IMUL16rri:

llvm/lib/Target/X86/X86InstrInfo.td

 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
 
 def SDT_X86PROBED_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
 
 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
 
-def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
+def SDT_X86MFENCE : SDTypeProfile<0, 0, []>;
 
 def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
                                          SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>;
 
 def SDT_X86AESENCDECKL : SDTypeProfile<2, 2, [SDTCisVT<0, v2i64>,
                                               SDTCisVT<1, i32>,
                                               SDTCisVT<2, v2i64>,
                                               SDTCisPtrTy<3>]>;
 
-def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
-                            [SDNPHasChain,SDNPSideEffect]>;
-def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
+def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MFENCE,
                         [SDNPHasChain]>;
 
 
 def X86bsf     : SDNode<"X86ISD::BSF",      SDTUnaryArithWithFlags>;
 def X86bsr     : SDNode<"X86ISD::BSR",      SDTUnaryArithWithFlags>;
 def X86fshl    : SDNode<"X86ISD::FSHL",     SDTIntShiftDOp>;
 def X86fshr    : SDNode<"X86ISD::FSHR",     SDTIntShiftDOp>;
 

llvm/lib/Target/X86/X86MCInstLower.cpp

void X86AsmPrinter::emitInstruction(const MachineInstr *MI) {
   // Add comments for values loaded from constant pool.
   if (OutStreamer->isVerboseAsm())
     addConstantComments(MI, *OutStreamer);
 
   switch (MI->getOpcode()) {
   case TargetOpcode::DBG_VALUE:
     llvm_unreachable("Should be handled target independently");
 
-  // Emit nothing here but a comment if we can.
-  case X86::Int_MemBarrier:
-    OutStreamer->emitRawComment("MEMBARRIER");
-    return;
-
   case X86::EH_RETURN:
   case X86::EH_RETURN64: {
     // Lower these as normal, but add some comments.
     Register Reg = MI->getOperand(0).getReg();
     OutStreamer->AddComment(StringRef("eh_return, addr: %") +
                             X86ATTInstPrinter::getRegisterName(Reg));
     break;
   }

llvm/test/CodeGen/AArch64/fence-singlethread.ll

 ; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s --check-prefix=LINUX
 ; RUN: llc -mtriple=aarch64-apple-ios %s -o - | FileCheck %s --check-prefix=IOS
 ; RUN: llc -mtriple=aarch64-linux-gnueabihf %s -filetype=obj -o %t
 ; RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=OBJ
 
 ; OBJ-NOT: dmb
 
 define void @fence_singlethread() {
 ; LINUX-LABEL: fence_singlethread:
 ; LINUX-NOT: dmb
-; LINUX: // COMPILER BARRIER
+; LINUX: // Compiler Barrier
 ; LINUX-NOT: dmb
 
 ; IOS-LABEL: fence_singlethread:
 ; IOS-NOT: dmb
-; IOS: ; COMPILER BARRIER
+; IOS: ; Compiler Barrier
 ; IOS-NOT: dmb
 
   fence syncscope("singlethread") seq_cst
   ret void
 }

llvm/test/CodeGen/ARM/fence-singlethread.ll

 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s
 ; RUN: llc -mtriple=thumbv7-apple-ios %s -o - | FileCheck %s
 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -filetype=obj -o %t
 ; RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=OBJ
 
 ; OBJ-NOT: dmb
 
 define void @fence_singlethread() {
 ; CHECK-LABEL: fence_singlethread:
 ; CHECK-NOT: dmb
-; CHECK: @ COMPILER BARRIER
+; CHECK: @ Compiler Barrier
 ; CHECK-NOT: dmb
 
   fence syncscope("singlethread") seq_cst
   ret void
 }

llvm/test/CodeGen/RISCV/atomic-fence.ll

 ;
 ; RV64I-LABEL: fence_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    fence rw, rw
 ; RV64I-NEXT:    ret
   fence seq_cst
   ret void
 }
+
+define void @fence_st_acquire() nounwind {
+; RV32I-LABEL: fence_st_acquire:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    # Compiler Barrier
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fence_st_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    # Compiler Barrier
+; RV64I-NEXT:    ret
+; RV641-EMPTY:
+  fence syncscope("singlethread") acquire
+  ret void
+}
+
+define void @fence_st_release() nounwind {
+; RV32I-LABEL: fence_st_release:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    # Compiler Barrier
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fence_st_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    # Compiler Barrier
+; RV64I-NEXT:    ret
+  fence syncscope("singlethread") release
+  ret void
+}
+
+define void @fence_st_acq_rel() nounwind {
+; RV32I-LABEL: fence_st_acq_rel:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    # Compiler Barrier
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fence_st_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    # Compiler Barrier
+; RV64I-NEXT:    ret
+  fence syncscope("singlethread") acq_rel
+  ret void
+}
+
+define void @fence_st_seq_cst() nounwind {
+; RV32I-LABEL: fence_st_seq_cst:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    # Compiler Barrier
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: fence_st_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    # Compiler Barrier
+; RV64I-NEXT:    ret
+  fence syncscope("singlethread") seq_cst
+  ret void
+}

llvm/test/CodeGen/X86/atomic-idempotent.ll

 ; X86-ATOM-NEXT:    retl
   %1 = atomicrmw and i32* %p, i32 -1 acq_rel
   ret i32 %1
 }
 
 define void @or32_nouse_monotonic(i32* %p) {
 ; X64-LABEL: or32_nouse_monotonic:
 ; X64:       # %bb.0:
-; X64-NEXT:    #MEMBARRIER
+; X64-NEXT:    # Compiler Barrier
 ; X64-NEXT:    retq
 ;
 ; X86-GENERIC-LABEL: or32_nouse_monotonic:
 ; X86-GENERIC:       # %bb.0:
-; X86-GENERIC-NEXT:    #MEMBARRIER
+; X86-GENERIC-NEXT:    # Compiler Barrier
 ; X86-GENERIC-NEXT:    retl
 ;
 ; X86-ATOM-LABEL: or32_nouse_monotonic:
 ; X86-ATOM:       # %bb.0:
-; X86-ATOM-NEXT:    #MEMBARRIER
+; X86-ATOM-NEXT:    # Compiler Barrier
+; X86-ATOM-NEXT:    nop
+; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    retl
   atomicrmw or i32* %p, i32 0 monotonic
   ret void
 }
 
 
 define void @or32_nouse_acquire(i32* %p) {
 ; X64-LABEL: or32_nouse_acquire:
 ; X64:       # %bb.0:
-; X64-NEXT:    #MEMBARRIER
+; X64-NEXT:    # Compiler Barrier
 ; X64-NEXT:    retq
 ;
 ; X86-GENERIC-LABEL: or32_nouse_acquire:
 ; X86-GENERIC:       # %bb.0:
-; X86-GENERIC-NEXT:    #MEMBARRIER
+; X86-GENERIC-NEXT:    # Compiler Barrier
 ; X86-GENERIC-NEXT:    retl
 ;
 ; X86-ATOM-LABEL: or32_nouse_acquire:
 ; X86-ATOM:       # %bb.0:
-; X86-ATOM-NEXT:    #MEMBARRIER
+; X86-ATOM-NEXT:    # Compiler Barrier
+; X86-ATOM-NEXT:    nop
+; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    retl
   atomicrmw or i32* %p, i32 0 acquire
   ret void
 }
 
 define void @or32_nouse_release(i32* %p) {
 ; X64-LABEL: or32_nouse_release:
 ; X64:       # %bb.0:
-; X64-NEXT:    #MEMBARRIER
+; X64-NEXT:    # Compiler Barrier
 ; X64-NEXT:    retq
 ;
 ; X86-GENERIC-LABEL: or32_nouse_release:
 ; X86-GENERIC:       # %bb.0:
-; X86-GENERIC-NEXT:    #MEMBARRIER
+; X86-GENERIC-NEXT:    # Compiler Barrier
 ; X86-GENERIC-NEXT:    retl
 ;
 ; X86-ATOM-LABEL: or32_nouse_release:
 ; X86-ATOM:       # %bb.0:
-; X86-ATOM-NEXT:    #MEMBARRIER
+; X86-ATOM-NEXT:    # Compiler Barrier
+; X86-ATOM-NEXT:    nop
+; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    retl
   atomicrmw or i32* %p, i32 0 release
   ret void
 }
 
 define void @or32_nouse_acq_rel(i32* %p) {
 ; X64-LABEL: or32_nouse_acq_rel:
 ; X64:       # %bb.0:
-; X64-NEXT:    #MEMBARRIER
+; X64-NEXT:    # Compiler Barrier
 ; X64-NEXT:    retq
 ;
 ; X86-GENERIC-LABEL: or32_nouse_acq_rel:
 ; X86-GENERIC:       # %bb.0:
-; X86-GENERIC-NEXT:    #MEMBARRIER
+; X86-GENERIC-NEXT:    # Compiler Barrier
 ; X86-GENERIC-NEXT:    retl
 ;
 ; X86-ATOM-LABEL: or32_nouse_acq_rel:
 ; X86-ATOM:       # %bb.0:
-; X86-ATOM-NEXT:    #MEMBARRIER
+; X86-ATOM-NEXT:    # Compiler Barrier
+; X86-ATOM-NEXT:    nop
+; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    nop
 ; X86-ATOM-NEXT:    retl
   atomicrmw or i32* %p, i32 0 acq_rel

llvm/test/CodeGen/X86/atomic-unordered.ll

; CHECK-NEXT:    retq
   %ret = add i64 %v, 15
   ret i64 %ret
 }
 
 define i64 @nofold_fence_acquire(i64* %p) {
 ; CHECK-LABEL: nofold_fence_acquire:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq (%rdi), %rax
-; CHECK-NEXT:    #MEMBARRIER
+; CHECK-NEXT:    # Compiler Barrier
 ; CHECK-NEXT:    addq $15, %rax
 ; CHECK-NEXT:    retq
   %v = load atomic i64, i64* %p unordered, align 8
   fence acquire
   %ret = add i64 %v, 15
   ret i64 %ret
 }
 
 
 define i64 @nofold_stfence(i64* %p) {
 ; CHECK-LABEL: nofold_stfence:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq (%rdi), %rax
-; CHECK-NEXT:    #MEMBARRIER
+; CHECK-NEXT:    # Compiler Barrier
 ; CHECK-NEXT:    addq $15, %rax
 ; CHECK-NEXT:    retq
   %v = load atomic i64, i64* %p unordered, align 8
   fence syncscope("singlethread") seq_cst
   %ret = add i64 %v, 15
   ret i64 %ret
 }
 

llvm/test/CodeGen/X86/barrier-sse.ll

 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
 
 define void @test() {
+; CHECK-LABEL: test
   fence acquire
-  ; CHECK: #MEMBARRIER
+  ; CHECK: ## Compiler Barrier
 
   fence release
-  ; CHECK: #MEMBARRIER
+  ; CHECK: ## Compiler Barrier
 
   fence acq_rel
-  ; CHECK: #MEMBARRIER
+  ; CHECK: ## Compiler Barrier
 
   ret void
 }

llvm/test/CodeGen/X86/implicit-null-check.ll

 ;; TODO: We could handle this case as we can lift the fence into the
 ;; previous block before the conditional without changing behavior.
 define i32 @imp_null_check_load_fence1(i32* %x) {
 ; CHECK-LABEL: imp_null_check_load_fence1:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    testq %rdi, %rdi
 ; CHECK-NEXT:    je LBB16_1
 ; CHECK-NEXT:  ## %bb.2: ## %not_null
-; CHECK-NEXT:    ##MEMBARRIER
+; CHECK-NEXT:    ## Compiler Barrier
 ; CHECK-NEXT:    movl (%rdi), %eax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  LBB16_1: ## %is_null
 ; CHECK-NEXT:    movl $42, %eax
 ; CHECK-NEXT:    retq
 
 entry:
   %c = icmp eq i32* %x, null