[MIPS] Add handing of forbidden slot when IR with inline asm

[yingopq]

Summary

Modify:
Add a global variable 'CurForbiddenSlotAttr' to save current instruction`s forbidden slot and whether set reorder.
This is the judgment condition for whether to add nop.
We would add a couple of '.set noreorder' and '.set reorder' to wrap the current instruction and the next instruction.
Then we can get previous instruction`s forbidden slot attribute and whether set reorder by 'CurForbiddenSlotAttr'.
If previous instruction has forbidden slot and .set reorder is active and current instruction is CTI. Then emit a NOP
after it.

Fix scenarios:
1.When inline asm ends with branch instruction:
1.1)then compiler
generate another CTI immediately, CTI lie in forbidden slot.
test: Use function foo1 in new file llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll.
1.2)and next IR line was also inline asm, need insert nop between them.
test: Use function foo2 in new file llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll.
2.When inline asm includes CTI following branch instruction, need
insert nop between them.
test: Use function foo3 in new file llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll.
3.Also add test for scenario that have been realized in pass, when
CTI follow branch instruction.
test: Use function foo0 in new file llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll.
4.When .set reorder is set in handwritten assembly file, nop need
insert between branch instruction and CTI.
test: in new file llvm/test/MC/Mips/forbidden-slot.s

Test result:
$ sudo ./build/bin/llvm-lit -v llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll llvm/test/MC/Mips/forbidden-slot.s llvm/test/MC/Mips/mips32r6/relocations.s llvm/test/MC/Mips/mips64r6/relocations.s llvm/test/MC/Mips/relocation.s
[sudo] password for huangyin:

• Testing: 5 tests, 5 workers --

PASS: LLVM :: MC/Mips/mips32r6/relocations.s (1 of 5)
PASS: LLVM :: MC/Mips/mips64r6/relocations.s (2 of 5)
PASS: LLVM :: MC/Mips/forbidden-slot.s (3 of 5)
PASS: LLVM :: CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll (4 of 5)
PASS: LLVM :: MC/Mips/relocation.s (5 of 5)
Testing Time: 0.25s
Total Discovered Tests: 5

Passed: 5 (100.00%)

Fix https://github.com/llvm/llvm-project/issues/61045

[MaskRay]

I am quite concerned with extra parameters in AsmPrinter::emitInlineAsm, parseStatement, and similar member functions. Do we have a way not adding them?

@FlyGoat

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

95 ↗

(On Diff #552617)

Don't repeat the variable/function name in new code.

96 ↗

(On Diff #552617)

Do we have to have this variable?

llvm/test/MC/Mips/forbidden-slot.s

2

we cannot use clang in llvm tests due to layering reasons https://maskray.me/blog/2021-08-08-toolchain-testing#the-test-checks-at-the-wrong-layer. also, llvm-project may be built with just llvm, not clang, and this would fail.

5

Align instructions for better look

# MIPSELR6:      beqzc	$9, 0x8 <bbb>
# MIPSELR6-NEXT: nop <aaa>
# MIPSELR6:      b	0x8 <bbb>

[jrtc27]

With the exception of 5, these all sound like garbage inline asm input? If you have a dangling delay slot at the end of the inline assembly, that's your problem, not the compiler's. And don't we default to reorder, anyway, so the only way to write that is to first .set noreorder?

[FlyGoat]

In D158589#4612830, @jrtc27 wrote:

With the exception of 5, these all sound like garbage inline asm input? If you have a dangling delay slot at the end of the inline assembly, that's your problem, not the compiler's. And don't we default to reorder, anyway, so the only way to write that is to first .set noreorder?

Well forbidden slot works differs from delay slot. It is introduced in MIPS Release 6.
It does not change execution flow. It simply disallows some CTI instructions (namely branch etc) to be placed after a branch.
Requiring user to fill nop after all inline assembly that ends with those branch instructions sounds appealing.

[wzssyqa]

In D158589#4612830, @jrtc27 wrote:

With the exception of 5, these all sound like garbage inline asm input? If you have a dangling delay slot at the end of the inline assembly, that's your problem, not the compiler's. And don't we default to reorder, anyway, so the only way to write that is to first .set noreorder?

To make this problem more clear, this patch is about forbidden slot, not delay slot.
In MIPSr6, you cannot put a CTI (branch/jump instruction) just after another CTI, even they are compact(no delay slot),
so a nop is needed to insert.

[FlyGoat]

In D158589#4612822, @MaskRay wrote:

I am quite concerned with extra parameters in AsmPrinter::emitInlineAsm, parseStatement, and similar member functions. Do we have a way not adding them?

@FlyGoat

I can't think of another way to achieve similiar functionality.

Another possible method is to let MC process forbidden-slot even with noreorder set.

[FlyGoat]

FYI Github issue I raised for this problem: https://github.com/llvm/llvm-project/issues/61045

Please update into commit message next time.

[MaskRay]

If the patch is related to https://github.com/llvm/llvm-project/issues/61045 , the convention is to add

"Fix https://github.com/llvm/llvm-project/issues/61045" or "Close https://github.com/llvm/llvm-project/issues/61045" to the local commit message and update the summary (arc diff --head=HEAD 'HEAD^' --verbatim amends the summary with the local commit message when uploading a new diff). Personally I prefer "Close" for features.

[yingopq]

Add a global variable 'CurForbiddenSlotAttr' to save current instruction`s forbidden slot and whether set reorder.
This is the judgment condition for whether to add nop.
We would add a couple of '.set noreorder' and '.set reorder' to wrap the current instruction and the next instruction.
Then we can get previous instruction`s forbidden slot attribute and whether set reorder by 'CurForbiddenSlotAttr'.
If previous instruction has forbidden slot and .set reorder is active and current instruction is CTI. Then emit a NOP
after it.

[yingopq]

Fix fail test "lld/test/ELF/mips-pc-relocs.s"

[yingopq]

This comment has been deleted.

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

95 ↗

(On Diff #552617)

Don't repeat the variable/function name in new code.

You mean we should use another name, not MIp?

96 ↗

(On Diff #552617)

Do we have to have this variable?

In function MatchAndEmitInstruction, we use this structure Info.ParsedOperands to pass MI to target backend MIPS which need use MI to get next instruction of MBB.

llvm/test/MC/Mips/forbidden-slot.s

2

OK, thanks, I would use llvm-mc, like this llvm-mc -assemble -mcpu=mips64r6 -arch=mips64el -filetype=obj %s -o tmp.o.

$ ./build/bin/llvm-lit -v llvm/test/MC/Mips/forbidden-slot.s

• Testing: 1 tests, 1 workers --

PASS: LLVM :: MC/Mips/forbidden-slot.s (1 of 1)

Testing Time: 0.07s

Passed: 1

[yingopq]

@craig.topper Could you kindly help review this issue patch at your convenience, thanks！

[yingopq]

Ping,
Thanks

[yingopq]

Hi @MaskRay @craig.topper @jrtc27 @FlyGoat,

Ping,
Thanks.

lld/test/ELF/mips-pc-relocs.s

 
 # CHECK:      Disassembly of section .text:
 # CHECK-EMPTY:
 # CHECK-NEXT: <__start>:
 # CHECK-NEXT:    20000:       lwpc    $6, 32
 #                                         ^-- (0x20020-0x20000)>>2
 # CHECK-NEXT:    20004:       beqc    $5, $6, 0x20020
 #                                             ^-- (0x20020-4-0x20004)>>2
-# CHECK-NEXT:    20008:       beqzc   $9, 0x20020
-#                                         ^-- (0x20020-4-0x20008)>>2
-# CHECK-NEXT:    2000c:       bc      0x20020
-#                                     ^-- (0x20020-4-0x2000c)>>2
-# CHECK-NEXT:    20010:       aluipc  $2, 0
-#                                         ^-- %hi(0x20020-0x20010)
-# CHECK-NEXT:    20014:       addiu   $2, $2, 12
-#                                             ^-- %lo(0x20020-0x20014)
+# CHECK-NEXT:    20008:       nop
+# CHECK-NEXT:    2000c:       beqzc   $9, 0x20020
+#                                         ^-- (0x20020-4-0x2000c)>>2
+# CHECK-NEXT:    20010:       nop
+# CHECK-NEXT:    20014:       bc      0x20020
+#                                     ^-- (0x20020-4-0x200014)>>2
+# CHECK-NEXT:    20018:       aluipc  $2, 0
+#                                         ^-- %hi(0x20020-0x20018)
+# CHECK-NEXT:    2001c:       addiu   $2, $2, 4
+#                                             ^-- %lo(0x20020-0x2001c)

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

class MipsAsmParser : public MCTargetAsmParser {
   SmallVector<std::unique_ptr<MipsAssemblerOptions>, 2> AssemblerOptions;
   MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a
                        // nullptr, which indicates that no function is currently
                        // selected. This usually happens after an '.end func'
                        // directive.
   bool IsLittleEndian;
   bool IsPicEnabled;
   bool IsCpRestoreSet;
+  bool CurForbiddenSlotAttr;
   int CpRestoreOffset;
   unsigned GPReg;
   unsigned CpSaveLocation;
   /// If true, then CpSaveLocation is a register, otherwise it's an offset.
   bool     CpSaveLocationIsRegister;
 
   // Map of register aliases created via the .set directive.
   StringMap<AsmToken> RegisterSets;
MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
 
     getTargetStreamer().updateABIInfo(*this);
 
     if (!isABI_O32() && !useOddSPReg() != 0)
       report_fatal_error("-mno-odd-spreg requires the O32 ABI");
 
     CurrentFn = nullptr;
 
+    CurForbiddenSlotAttr = false;
     IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent();
 
     IsCpRestoreSet = false;
     CpRestoreOffset = -1;
     GPReg = ABI.GetGlobalPtr();
 
     const Triple &TheTriple = sti.getTargetTriple();
     IsLittleEndian = TheTriple.isLittleEndian();
#undef GET_OPERAND_DIAGNOSTIC_TYPES
   bool hasVirt() const {
     return getSTI().hasFeature(Mips::FeatureVirt);
   }
 
   bool hasGINV() const {
     return getSTI().hasFeature(Mips::FeatureGINV);
   }
 
+  bool hasForbiddenSlot(const MCInstrDesc &MCID) const {
+    return !inMicroMipsMode() && (MCID.TSFlags & MipsII::HasForbiddenSlot);
+  }
+
+  bool SafeInForbiddenSlot(const MCInstrDesc &MCID) const {
+    return !(MCID.TSFlags & MipsII::IsCTI);
+  }
+
+  void onEndOfFile() override;
+
   /// Warn if RegIndex is the same as the current AT.
   void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
 
   void warnIfNoMacro(SMLoc Loc);
 
   bool isLittle() const { return IsLittleEndian; }
 
   const MCExpr *createTargetUnaryExpr(const MCExpr *E,
switch (Opcode) {
           return Error(IDLoc, "invalid operand for instruction");
         break;
       }
     }
   }
 
   bool FillDelaySlot =
       MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder();
-  if (FillDelaySlot)
+
+  // Get previous instruction`s forbidden slot attribute and
+  // whether set reorder.
+  // This 'CurForbiddenSlotAttr' is a global variable.
+  bool PrevForbiddenSlotAttr = CurForbiddenSlotAttr;
+
+  // Flag represents we set reorder after nop.
+  bool SetReorderAfterNop = false;
+
+  // If previous instruction has forbidden slot and .set reorder
+  // is active and current instruction is CTI.
+  // Then emit a NOP after it.
+  if (PrevForbiddenSlotAttr && !SafeInForbiddenSlot(MCID)) {
+    TOut.emitEmptyDelaySlot(false, IDLoc, STI);
+    // When 'FillDelaySlot' is true, the existing logic will add
+    // noreorder before instruction and reorder after it. So there
+    // need exclude this case avoiding two '.set reorder'.
+    // The format of the first case is:
+    // .set noreorder
+    // bnezc
+    // nop
+    // .set reorder
+    if (AssemblerOptions.back()->isReorder() && !FillDelaySlot) {
+      SetReorderAfterNop = true;
+      TOut.emitDirectiveSetReorder();
+    }
+  }
+
+  // Save current instruction`s forbidden slot and whether set reorder.
+  // This is the judgment condition for whether to add nop.
+  // We would add a couple of '.set noreorder' and '.set reorder' to
+  // wrap the current instruction and the next instruction.
+  CurForbiddenSlotAttr = hasForbiddenSlot(MCID) &&
+    AssemblerOptions.back()->isReorder();
+
+  if (FillDelaySlot || CurForbiddenSlotAttr)
     TOut.emitDirectiveSetNoReorder();
 
   MacroExpanderResultTy ExpandResult =
       tryExpandInstruction(Inst, IDLoc, Out, STI);
   switch (ExpandResult) {
   case MER_NotAMacro:
     Out.emitInstruction(Inst, *STI);
     break;
   case MER_Success:
     break;
   case MER_Fail:
     return true;
   }
 
+  // When current instruction was not CTI, recover reorder state.
+  // The format of the second case is:
+  // .set noreoder
+  // bnezc
+  // add
+  // .set reorder
+  if (PrevForbiddenSlotAttr && !SetReorderAfterNop && !FillDelaySlot && AssemblerOptions.back()->isReorder()) {
+    TOut.emitDirectiveSetReorder();
+  }
+
   // We know we emitted an instruction on the MER_NotAMacro or MER_Success path.
   // If we're in microMIPS mode then we must also set EF_MIPS_MICROMIPS.
   if (inMicroMipsMode()) {
     TOut.setUsesMicroMips();
     TOut.updateABIInfo(*this);
   }
 
   // If this instruction has a delay slot and .set reorder is active,
   // emit a NOP after it.
+  // The format of the third case is:
+  // .set noreorder
+  // bnezc
+  // nop
+  // .set noreorder
+  // j
+  // nop
+  // .set reorder
   if (FillDelaySlot) {
     TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI);
     TOut.emitDirectiveSetReorder();
   }
 
   if ((Opcode == Mips::JalOneReg || Opcode == Mips::JalTwoReg ||
        ExpandedJalSym) &&
       isPicAndNotNxxAbi()) {
if (IsCpRestoreSet) {
       TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI);
     } else
       Warning(IDLoc, "no .cprestore used in PIC mode");
   }
 
   return false;
 }
 
+void MipsAsmParser::onEndOfFile() {
+  MipsTargetStreamer &TOut = getTargetStreamer();
+  SMLoc IDLoc = SMLoc();
+  // If has pending forbidden slot, fill nop and recover reorder.
+  if (CurForbiddenSlotAttr) {
+    TOut.emitEmptyDelaySlot(false, IDLoc, STI);
+    if (AssemblerOptions.back()->isReorder())
+      TOut.emitDirectiveSetReorder();
+  }
+}
+
 MipsAsmParser::MacroExpanderResultTy
 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                     const MCSubtargetInfo *STI) {
   switch (Inst.getOpcode()) {
   default:
     return MER_NotAMacro;
   case Mips::LoadImm32:
     return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;

llvm/test/CodeGen/Mips/llvm-ir/forbidden-slot-ir.ll

+target triple = "mipsisa32r6el-unknown-linux-gnu"
+
+; RUN: llc -filetype=asm %s -o - | FileCheck %s --check-prefix=MIPSELR6
+; Function Attrs: noinline nounwind optnone uwtable
+define i1 @foo0() nounwind {
+; MIPSELR6:      bnezc  $1, $BB0_2
+; MIPSELR6-NEXT: nop
+; MIPSELR6:      jr $ra
+entry:
+  %0 = icmp eq i32 0, 1
+  br i1 %0, label %2, label %3
+  ret i1 %0
+2:                                                
+  ret i1 %0
+3:                                                
+  ret i1 %0
+}
+
+define i32 @foo1() nounwind {
+; MIPSELR6:      beqzc  $2, $tmp0
+; MIPSELR6-NEXT: nop
+; MIPSELR6:      jrc  $ra
+entry:
+  %0 = tail call i32 asm "1: addiu $0, $0, 1; beqzc $0, 1b", "=r"() nounwind
+  ret i32 %0
+}
+
+define i32 @foo2() nounwind {
+; MIPSELR6:      beqzc  $9, End
+; MIPSELR6-NEXT: nop
+; MIPSELR6:      addiu  $9, $9, 1
+entry:
+  %0 = tail call i32 asm "beqzc $$t1, End", "=r"() nounwind
+  %1 = tail call i32 asm "addiu $$t1, $$t1, 1", "=r"() nounwind
+  %2 = add nsw i32 %1, %0
+  ret i32 %2
+}
+
+define i32 @foo3() nounwind {
+; MIPSELR6:      beqzc  $2, $tmp1
+; MIPSELR6-NEXT: nop
+; MIPSELR6:      j  End
+entry:
+  %0 = tail call i32 asm "1: addiu $0, $0, 1; beqzc $0, 1b; j End", "=r"() nounwind
+  ret i32 %0
+}

llvm/test/MC/Mips/forbidden-slot.s

+# RUN: llvm-mc -assemble -mcpu=mips64r6 -arch=mips64el -filetype=obj %s -o tmp.o
+# RUN: llvm-objdump -d tmp.o | FileCheck %s --check-prefix=MIPSELR6
+
+# MIPSELR6:      beqzc  $13, 0x0 <aaa>
+# MIPSELR6-NEXT: b  0x0 <aaa>
+# MIPSELR6:      beqzc  $13, 0x8 <bbb>
+# MIPSELR6-NEXT: nop    <aaa>
+# MIPSELR6:      b  0x8 <bbb>
+  .set noreorder
+aaa:
+  beqzc $t1, aaa
+  b aaa
+  .set reorder
+bbb:
+  beqzc $t1, bbb
+  b bbb

llvm/test/MC/Mips/mips32r6/relocations.s

 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_Mips_LO16
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
 # CHECK-ELF: Relocations [
 # CHECK-ELF:     0x0 R_MIPS_PC19_S2 bar
 # CHECK-ELF:     0x4 R_MIPS_PC16 bar
-# CHECK-ELF:     0x8 R_MIPS_PC16 bar
-# CHECK-ELF:     0xC R_MIPS_PC21_S2 bar
-# CHECK-ELF:     0x10 R_MIPS_PC21_S2 bar
-# CHECK-ELF:     0x14 R_MIPS_PC26_S2 bar
-# CHECK-ELF:     0x18 R_MIPS_PC26_S2 bar
-# CHECK-ELF:     0x1C R_MIPS_PCHI16 bar
-# CHECK-ELF:     0x20 R_MIPS_PCLO16 bar
-# CHECK-ELF:     0x24 R_MIPS_PC19_S2 bar
-# CHECK-ELF:     0x28 R_MIPS_PC19_S2 bar
-# CHECK-ELF:     0x2C R_MIPS_LO16 bar
-# CHECK-ELF:     0x30 R_MIPS_LO16 bar
+# CHECK-ELF:     0xC R_MIPS_PC16 bar
+# CHECK-ELF:     0x14 R_MIPS_PC21_S2 bar
+# CHECK-ELF:     0x1C R_MIPS_PC21_S2 bar
+# CHECK-ELF:     0x24 R_MIPS_PC26_S2 bar
+# CHECK-ELF:     0x28 R_MIPS_PC26_S2 bar
+# CHECK-ELF:     0x2C R_MIPS_PCHI16 bar
+# CHECK-ELF:     0x30 R_MIPS_PCLO16 bar
+# CHECK-ELF:     0x34 R_MIPS_PC19_S2 bar
+# CHECK-ELF:     0x38 R_MIPS_PC19_S2 bar
+# CHECK-ELF:     0x3C R_MIPS_LO16 bar
+# CHECK-ELF:     0x40 R_MIPS_LO16 bar
 # CHECK-ELF: ]
 
   addiupc   $2,bar
   beqc  $5, $6, bar
   bnec  $5, $6, bar
   beqzc $9, bar
   bnezc $9, bar
   balc  bar
   bc    bar
   aluipc $2, %pcrel_hi(bar)
   addiu  $2, $2, %pcrel_lo(bar)
   lapc      $2,bar
   lwpc      $2,bar
   jialc  $5, bar
   jic    $5, bar

llvm/test/MC/Mips/mips64r6/relocations.s

 # CHECK-FIXUP:                  #   fixup A - offset: 0,
 # CHECK-FIXUP:                      value: bar, kind: fixup_Mips_LO16
 #------------------------------------------------------------------------------
 # Check that the appropriate relocations were created.
 #------------------------------------------------------------------------------
 # CHECK-ELF: Relocations [
 # CHECK-ELF:     0x0 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
 # CHECK-ELF:     0x4 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
-# CHECK-ELF:     0x8 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
-# CHECK-ELF:     0xC R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
-# CHECK-ELF:     0x10 R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
-# CHECK-ELF:     0x14 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
-# CHECK-ELF:     0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
-# CHECK-ELF:     0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
-# CHECK-ELF:     0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
-# CHECK-ELF:     0x24 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
-# CHECK-ELF:     0x28 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0
-# CHECK-ELF:     0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
-# CHECK-ELF:     0x30 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
-# CHECK-ELF:     0x34 R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
-# CHECK-ELF:     0x38 R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0xC R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
+# CHECK-ELF:     0x14 R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
+# CHECK-ELF:     0x1C R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
+# CHECK-ELF:     0x24 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
+# CHECK-ELF:     0x28 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0xFFFFFFFFFFFFFFFC
+# CHECK-ELF:     0x2C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x30 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x34 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x38 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x3C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x40 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x44 R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
+# CHECK-ELF:     0x48 R_MIPS_LO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0
 # CHECK-ELF: ]
 
   addiupc   $2,bar
   beqc  $5, $6, bar
   bnec  $5, $6, bar
   beqzc $9, bar
   bnezc $9, bar
   balc  bar

llvm/test/MC/Mips/relocation.s

// DATA-NEXT:  00B0: 00000000 00000000 24620000 24620000
                                            // ENCLE: addiu $2, $3, %tprel_hi(foo) # encoding: [A,A,0x62,0x24]
                                            // FIXUP: # fixup A - offset: 0, value: %tprel_hi(foo), kind: fixup_Mips_TPREL_HI
 
         addiu $2, $3, %tprel_lo(foo)       // RELOC: R_MIPS_TLS_TPREL_LO16 foo
                                            // ENCBE: addiu $2, $3, %tprel_lo(foo) # encoding: [0x24,0x62,A,A]
                                            // ENCLE: addiu $2, $3, %tprel_lo(foo) # encoding: [A,A,0x62,0x24]
                                            // FIXUP: # fixup A - offset: 0, value: %tprel_lo(foo), kind: fixup_Mips_TPREL_LO
 
-// DATA-NEXT:  00C0: D85FFFFF CBFFFFFF EC580000 EC480000
+// DATA-NEXT:  00C0: D85FFFFF 00000000 CBFFFFFF EC580000
                                            // ?????: R_MIPS_GLOB_DAT foo
         .set mips32r6
         beqzc $2, foo                      // RELOC: R_MIPS_PC21_S2 foo
                                            // ENCBE: beqzc $2, foo # encoding: [0xd8,0b010AAAAA,A,A]
                                            // ENCLE: beqzc $2, foo # encoding: [A,A,0b010AAAAA,0xd8]
                                            // FIXUP: # fixup A - offset: 0, value: foo-4, kind: fixup_MIPS_PC21_S2
 
         bc foo                             // RELOC: R_MIPS_PC26_S2 foo
                                            // ENCBE: bc foo # encoding: [0b110010AA,A,A,A]
                                            // ENCLE: bc foo # encoding: [A,A,A,0b110010AA]
                                            // FIXUP: # fixup A - offset: 0, value: foo-4, kind: fixup_MIPS_PC26_S2
 
         .set mips64r6
         ldpc $2, foo                       // RELOC: R_MIPS_PC18_S3 foo
                                            // ENCBE: ldpc $2, foo # encoding: [0xec,0b010110AA,A,A]
                                            // ENCLE: ldpc $2, foo # encoding: [A,A,0b010110AA,0xec]
                                            // FIXUP: # fixup A - offset: 0, value: foo, kind: fixup_Mips_PC18_S3
 
         .set mips32r6
         lwpc $2, foo                       // RELOC: R_MIPS_PC19_S2 foo
                                            // ENCBE: lwpc $2, foo # encoding: [0xec,0b01001AAA,A,A]
                                            // ENCLE: lwpc $2, foo # encoding: [A,A,0b01001AAA,0xec]
                                            // FIXUP: # fixup A - offset: 0, value: foo, kind: fixup_MIPS_PC19_S2
 
-// DATA-NEXT:  00D0: 24620000 24620000 00000000
+// DATA-NEXT:  00D0: EC480000 24620000 24620000 00000000
         addiu $2, $3, %pcrel_hi(foo)       // RELOC: R_MIPS_PCHI16 foo
                                            // ENCBE: addiu $2, $3, %pcrel_hi(foo) # encoding: [0x24,0x62,A,A]
                                            // ENCLE: addiu $2, $3, %pcrel_hi(foo) # encoding: [A,A,0x62,0x24]
                                            // FIXUP: # fixup A - offset: 0, value: %pcrel_hi(foo), kind: fixup_MIPS_PCHI16
 
         addiu $2, $3, %pcrel_lo(foo)       // RELOC: R_MIPS_PCLO16 foo
                                            // ENCBE: addiu $2, $3, %pcrel_lo(foo) # encoding: [0x24,0x62,A,A]
                                            // ENCLE: addiu $2, $3, %pcrel_lo(foo) # encoding: [A,A,0x62,0x24]