Remove "Rewrite Symbols" from codegen pipeline

[aeubanks]

Summary

It breaks up the function pass manager in the codegen pipeline.

With empty parameters, it looks at the -mllvm flag -rewrite-map-file.
This is likely not in use.

Add a check that we only have one function pass manager in the codegen
pipeline.

Some tests relied on the fact that we had a module pass somewhere in the
codegen pipeline.

addr-label.ll crashes on ARM due to this change. This is because a
ARMConstantPoolConstant containing a BasicBlock to represent a
blockaddress may hold an invalid pointer to a BasicBlock if the
blockaddress is invalidated by its BasicBlock getting removed. In that
case all referencing blockaddresses are RAUW a constant int. Making
ARMConstantPoolConstant::CVal a WeakVH fixes the crash, but I'm not sure
that's the right fix. As a workaround, create a barrier right before
ISel so that IR optimizations can't happen while a
ARMConstantPoolConstant has been created.

[rnk]

+@compnerd

With empty parameters, it's a no-op and also breaks up the function pass manager.

I'm not sure it's actually a no-op, see the constructor which parses a cl::opt provided file:
https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Transforms/Utils/SymbolRewriter.h#L122

RewriteSymbolPass() { loadAndParseMapFiles(); }

To preserve the functionality, we would need to make adding the pass conditional on the cl::opt being empty. OTOH, I'm not convinced that anyone is actually using this functionality. The top search hits for the command line flag are the Doxygen for the source files.

When this lands, please split it into a straight revert of the function symbol patch the pipeline adjustment change.

[aeubanks]

Yeah it's not technically no-op, but that flag should only be used for testing.
There is a clang flag to enable this pass in the optimization pipeline: -frewrite-map-file. Although actually it's not implemented for the new PM...

[MaskRay]

I think people who need symbol rename are mostly using #pragma redefine_extname or asm labels... (others are using objcopy --redefine-sym/--redefine-syms)

[aeubanks]

Will update the commit message and add a check that we only have one function pass manager in the codegen pipeline

[aeubanks]

add test for only one function pass manager

[aeubanks]

I'll submit the revert separately when landing

[rnk]

lgtm, thanks

[MaskRay]

@compnerd ^^

[aeubanks]

rebase after revert

[aeubanks]

rebase and handle ARM

[aeubanks]

adding some ARM people to look at the ARMTargetMachine change

[SjoerdMeijer]

llvm/lib/Target/ARM/ARMTargetMachine.cpp

466

Thanks for adding us. I am unfamiliar with this BarriesNoopPass. @dmgreen, do you know more about this by any chance?

[aeubanks]

llvm/lib/Target/ARM/ARMTargetMachine.cpp

466

typically if we have a bunch of function passes in a row, the pass manager will run all of them on one function, then the next function, etc
by adding a module pass somewhere in the middle of the function passes, we'll end up running the first half of the function passes on each function, then the second half. this accomplishes what's mentioned in the description

e.g. if we have two functions f1 and f2, and four function passes FP1-4, normally it'd be
FP1 on f1
FP2 on f1
FP3 on f1
FP4 on f1
FP1 on f2
FP2 on f2
FP3 on f2
FP4 on f2

but with the barrier between FP2 and FP3, we get

FP1 on f1
FP2 on f1
FP1 on f2
FP2 on f2
barrier
FP3 on f1
FP4 on f1
FP3 on f2
FP4 on f2

[rnk]

llvm/lib/Target/ARM/ARMTargetMachine.cpp

466

I think this is a reasonable temporary solution, but please add a comment about what this is doing.

The module pass barrier ensures that we run all pre-ISel passes (IR passes) over all functions before starting instruction selection. IR passes can modify the CFG, which can delete address-taken basic blocks. That invalidates references to block addresses stored in the ARM constant pool. Maybe add // FIXME: Solve this another way or something like that.

[aeubanks]

add FIXME

[rnk]

Looks good to me, but let's wait for an ARM backend person to acknowledge the ARM change.

[aeubanks]

ping

[MaskRay]

Ping @compnerd

[aeubanks]

ping @ an ARM owner

llvm/lib/Target/ARM/ARMTargetMachine.cpp

466

ping @SjoerdMeijer @dmgreen

[rnk]

In the absence of review from ARM, I think we should land this as is.

[SjoerdMeijer]

Sorry for the delay. Looks reasonable to me.

llvm/lib/CodeGen/TargetPassConfig.cpp

void TargetPassConfig::addPassesToHandleExceptions() {
   }
 }
 
 /// Add pass to prepare the LLVM IR for code generation. This should be done
 /// before exception handling preparation passes.
 void TargetPassConfig::addCodeGenPrepare() {
   if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
     addPass(createCodeGenPreparePass());
-  addPass(createRewriteSymbolsPass());
 }
 
 /// Add common passes that perform LLVM IR to IR transforms in preparation for
 /// instruction selection.
 void TargetPassConfig::addISelPrepare() {
   addPreISel();
 
   // Force codegen to run according to the callgraph.

llvm/lib/Target/ARM/ARMTargetMachine.cpp

 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Transforms/CFGuard.h"
+#include "llvm/Transforms/IPO.h"
 #include "llvm/Transforms/Scalar.h"
 #include <cassert>
 #include <memory>
 #include <string>
 
 using namespace llvm;
 
 static cl::opt<bool>
if ((TM->getOptLevel() != CodeGenOpt::None &&
     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
                                   MergeExternalByDefault));
   }
 
   if (TM->getOptLevel() != CodeGenOpt::None) {
     addPass(createHardwareLoopsPass());
     addPass(createMVETailPredicationPass());
+    // FIXME: IR passes can delete address-taken basic blocks, deleting
+    // corresponding blockaddresses. ARMConstantPoolConstant holds references to
+    // address-taken basic blocks which can be invalidated if the function
+    // containing the blockaddress has already been codegen'd and the basic
+    // block is removed. Work around this by forcing all IR passes to run before
+    // any ISel takes place. We should have a more principled way of handling
+    // this. See D99707 for more details.
+    addPass(createBarrierNoopPass());
   }
 
   return false;
 }
 
 bool ARMPassConfig::addInstSelector() {
   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
   return false;

llvm/lib/Target/ARM/CMakeLists.txt

add_llvm_target(ARMCodeGen
 
   LINK_COMPONENTS
   ARMDesc
   ARMInfo
   Analysis
   AsmPrinter
   CodeGen
   Core
+  IPO
   MC
   Scalar
   SelectionDAG
   Support
   Target
   GlobalISel
   ARMUtils
   TransformUtils

llvm/test/CodeGen/AArch64/O0-pipeline.ll

 ; CHECK-NEXT:       Lower Garbage Collection Instructions
 ; CHECK-NEXT:       Shadow Stack GC Lowering
 ; CHECK-NEXT:       Lower constant intrinsics
 ; CHECK-NEXT:       Remove unreachable blocks from the CFG
 ; CHECK-NEXT:       Expand vector predication intrinsics
 ; CHECK-NEXT:       Scalarize Masked Memory Intrinsics
 ; CHECK-NEXT:       Expand reduction intrinsics
 ; CHECK-NEXT:       AArch64 Stack Tagging
-; CHECK-NEXT:     Rewrite Symbols
-; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Exception handling preparation
 ; CHECK-NEXT:       Safe Stack instrumentation pass
 ; CHECK-NEXT:       Insert stack protectors
 ; CHECK-NEXT:       Module Verifier
 ; CHECK-NEXT:       Analysis containing CSE Info
 ; CHECK-NEXT:       IRTranslator
 ; CHECK-NEXT:       Analysis for ComputingKnownBits
 ; CHECK-NEXT:       AArch64O0PreLegalizerCombiner

llvm/test/CodeGen/AArch64/O3-pipeline.ll

 ; CHECK-NEXT:       AArch64 Stack Tagging
 ; CHECK-NEXT:       Function Alias Analysis Results
 ; CHECK-NEXT:       Memory SSA
 ; CHECK-NEXT:       Interleaved Load Combine Pass
 ; CHECK-NEXT:       Dominator Tree Construction
 ; CHECK-NEXT:       Interleaved Access Pass
 ; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       CodeGen Prepare
-; CHECK-NEXT:     Rewrite Symbols
-; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Dominator Tree Construction
 ; CHECK-NEXT:       Exception handling preparation
 ; CHECK-NEXT:     AArch64 Promote Constant
 ; CHECK-NEXT:       FunctionPass Manager
 ; CHECK-NEXT:         Dominator Tree Construction
 ; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Merge internal globals
 ; CHECK-NEXT:       Safe Stack instrumentation pass

llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

 ; GCN-O0-NEXT:       Scalarize Masked Memory Intrinsics
 ; GCN-O0-NEXT:       Expand reduction intrinsics
 ; GCN-O0-NEXT:     CallGraph Construction
 ; GCN-O0-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O0-NEXT:       AMDGPU Annotate Kernel Features
 ; GCN-O0-NEXT:       FunctionPass Manager
 ; GCN-O0-NEXT:         AMDGPU Lower Kernel Arguments
 ; GCN-O0-NEXT:       Analysis if a function is memory bound
-; GCN-O0-NEXT:     Rewrite Symbols
-; GCN-O0-NEXT:     FunctionPass Manager
+; GCN-O0-NEXT:       FunctionPass Manager
 ; GCN-O0-NEXT:       Lazy Value Information Analysis
 ; GCN-O0-NEXT:       Lower SwitchInst's to branches
 ; GCN-O0-NEXT:       Lower invoke and unwind, for unwindless code generators
 ; GCN-O0-NEXT:       Remove unreachable blocks from the CFG
 ; GCN-O0-NEXT:       Dominator Tree Construction
 ; GCN-O0-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O0-NEXT:       Function Alias Analysis Results
 ; GCN-O0-NEXT:       Flatten the CFG

 ; GCN-O0-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O0-NEXT:       Function Alias Analysis Results
 ; GCN-O0-NEXT:       Memory SSA
 ; GCN-O0-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O0-NEXT:       SI annotate control flow
 ; GCN-O0-NEXT:       Natural Loop Information
 ; GCN-O0-NEXT:       LCSSA Verifier
 ; GCN-O0-NEXT:       Loop-Closed SSA Form Pass
-; GCN-O0-NEXT:     CallGraph Construction
-; GCN-O0-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O0-NEXT:       DummyCGSCCPass
 ; GCN-O0-NEXT:       FunctionPass Manager
 ; GCN-O0-NEXT:         Safe Stack instrumentation pass
 ; GCN-O0-NEXT:         Insert stack protectors
 ; GCN-O0-NEXT:         Dominator Tree Construction
 ; GCN-O0-NEXT:         Post-Dominator Tree Construction
 ; GCN-O0-NEXT:         Natural Loop Information
 ; GCN-O0-NEXT:         Legacy Divergence Analysis

 ; GCN-O1-NEXT:       AMDGPU Annotate Kernel Features
 ; GCN-O1-NEXT:       FunctionPass Manager
 ; GCN-O1-NEXT:         AMDGPU Lower Kernel Arguments
 ; GCN-O1-NEXT:       Analysis if a function is memory bound
 ; GCN-O1-NEXT:       FunctionPass Manager
 ; GCN-O1-NEXT:         Dominator Tree Construction
 ; GCN-O1-NEXT:         Natural Loop Information
 ; GCN-O1-NEXT:         CodeGen Prepare
-; GCN-O1-NEXT:     Rewrite Symbols
-; GCN-O1-NEXT:     FunctionPass Manager
 ; GCN-O1-NEXT:       Lazy Value Information Analysis
 ; GCN-O1-NEXT:       Lower SwitchInst's to branches
 ; GCN-O1-NEXT:       Lower invoke and unwind, for unwindless code generators
 ; GCN-O1-NEXT:       Remove unreachable blocks from the CFG
 ; GCN-O1-NEXT:       Dominator Tree Construction
 ; GCN-O1-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O1-NEXT:       Function Alias Analysis Results
 ; GCN-O1-NEXT:       Flatten the CFG

 ; GCN-O1-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O1-NEXT:       Function Alias Analysis Results
 ; GCN-O1-NEXT:       Memory SSA
 ; GCN-O1-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O1-NEXT:       SI annotate control flow
 ; GCN-O1-NEXT:       Natural Loop Information
 ; GCN-O1-NEXT:       LCSSA Verifier
 ; GCN-O1-NEXT:       Loop-Closed SSA Form Pass
-; GCN-O1-NEXT:     CallGraph Construction
-; GCN-O1-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O1-NEXT:       DummyCGSCCPass
 ; GCN-O1-NEXT:       FunctionPass Manager
 ; GCN-O1-NEXT:         Safe Stack instrumentation pass
 ; GCN-O1-NEXT:         Insert stack protectors
 ; GCN-O1-NEXT:         Dominator Tree Construction
 ; GCN-O1-NEXT:         Post-Dominator Tree Construction
 ; GCN-O1-NEXT:         Natural Loop Information
 ; GCN-O1-NEXT:         Legacy Divergence Analysis

 ; GCN-O1-OPTS-NEXT:       AMDGPU Annotate Kernel Features
 ; GCN-O1-OPTS-NEXT:       FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:         AMDGPU Lower Kernel Arguments
 ; GCN-O1-OPTS-NEXT:       Analysis if a function is memory bound
 ; GCN-O1-OPTS-NEXT:       FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:         Dominator Tree Construction
 ; GCN-O1-OPTS-NEXT:         Natural Loop Information
 ; GCN-O1-OPTS-NEXT:         CodeGen Prepare
-; GCN-O1-OPTS-NEXT:     Rewrite Symbols
-; GCN-O1-OPTS-NEXT:     FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:       Dominator Tree Construction
 ; GCN-O1-OPTS-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O1-OPTS-NEXT:       Function Alias Analysis Results
 ; GCN-O1-OPTS-NEXT:       Natural Loop Information
 ; GCN-O1-OPTS-NEXT:       Scalar Evolution Analysis
 ; GCN-O1-OPTS-NEXT:       GPU Load and Store Vectorizer
 ; GCN-O1-OPTS-NEXT:       Lazy Value Information Analysis
 ; GCN-O1-OPTS-NEXT:       Lower SwitchInst's to branches

 ; GCN-O1-OPTS-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O1-OPTS-NEXT:       Function Alias Analysis Results
 ; GCN-O1-OPTS-NEXT:       Memory SSA
 ; GCN-O1-OPTS-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O1-OPTS-NEXT:       SI annotate control flow
 ; GCN-O1-OPTS-NEXT:       Natural Loop Information
 ; GCN-O1-OPTS-NEXT:       LCSSA Verifier
 ; GCN-O1-OPTS-NEXT:       Loop-Closed SSA Form Pass
-; GCN-O1-OPTS-NEXT:     CallGraph Construction
-; GCN-O1-OPTS-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O1-OPTS-NEXT:       DummyCGSCCPass
 ; GCN-O1-OPTS-NEXT:       FunctionPass Manager
 ; GCN-O1-OPTS-NEXT:         Safe Stack instrumentation pass
 ; GCN-O1-OPTS-NEXT:         Insert stack protectors
 ; GCN-O1-OPTS-NEXT:         Dominator Tree Construction
 ; GCN-O1-OPTS-NEXT:         Post-Dominator Tree Construction
 ; GCN-O1-OPTS-NEXT:         Natural Loop Information
 ; GCN-O1-OPTS-NEXT:         Legacy Divergence Analysis

 ; GCN-O2-NEXT:       AMDGPU Annotate Kernel Features
 ; GCN-O2-NEXT:       FunctionPass Manager
 ; GCN-O2-NEXT:         AMDGPU Lower Kernel Arguments
 ; GCN-O2-NEXT:       Analysis if a function is memory bound
 ; GCN-O2-NEXT:       FunctionPass Manager
 ; GCN-O2-NEXT:         Dominator Tree Construction
 ; GCN-O2-NEXT:         Natural Loop Information
 ; GCN-O2-NEXT:         CodeGen Prepare
-; GCN-O2-NEXT:     Rewrite Symbols
-; GCN-O2-NEXT:     FunctionPass Manager
 ; GCN-O2-NEXT:       Dominator Tree Construction
 ; GCN-O2-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O2-NEXT:       Function Alias Analysis Results
 ; GCN-O2-NEXT:       Natural Loop Information
 ; GCN-O2-NEXT:       Scalar Evolution Analysis
 ; GCN-O2-NEXT:       GPU Load and Store Vectorizer
 ; GCN-O2-NEXT:       Lazy Value Information Analysis
 ; GCN-O2-NEXT:       Lower SwitchInst's to branches

 ; GCN-O2-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O2-NEXT:       Function Alias Analysis Results
 ; GCN-O2-NEXT:       Memory SSA
 ; GCN-O2-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O2-NEXT:       SI annotate control flow
 ; GCN-O2-NEXT:       Natural Loop Information
 ; GCN-O2-NEXT:       LCSSA Verifier
 ; GCN-O2-NEXT:       Loop-Closed SSA Form Pass
-; GCN-O2-NEXT:     CallGraph Construction
-; GCN-O2-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O2-NEXT:       DummyCGSCCPass
 ; GCN-O2-NEXT:       FunctionPass Manager
 ; GCN-O2-NEXT:         Safe Stack instrumentation pass
 ; GCN-O2-NEXT:         Insert stack protectors
 ; GCN-O2-NEXT:         Dominator Tree Construction
 ; GCN-O2-NEXT:         Post-Dominator Tree Construction
 ; GCN-O2-NEXT:         Natural Loop Information
 ; GCN-O2-NEXT:         Legacy Divergence Analysis

 ; GCN-O3-NEXT:       AMDGPU Annotate Kernel Features
 ; GCN-O3-NEXT:       FunctionPass Manager
 ; GCN-O3-NEXT:         AMDGPU Lower Kernel Arguments
 ; GCN-O3-NEXT:       Analysis if a function is memory bound
 ; GCN-O3-NEXT:       FunctionPass Manager
 ; GCN-O3-NEXT:         Dominator Tree Construction
 ; GCN-O3-NEXT:         Natural Loop Information
 ; GCN-O3-NEXT:         CodeGen Prepare
-; GCN-O3-NEXT:     Rewrite Symbols
-; GCN-O3-NEXT:     FunctionPass Manager
 ; GCN-O3-NEXT:       Dominator Tree Construction
 ; GCN-O3-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O3-NEXT:       Function Alias Analysis Results
 ; GCN-O3-NEXT:       Natural Loop Information
 ; GCN-O3-NEXT:       Scalar Evolution Analysis
 ; GCN-O3-NEXT:       GPU Load and Store Vectorizer
 ; GCN-O3-NEXT:       Lazy Value Information Analysis
 ; GCN-O3-NEXT:       Lower SwitchInst's to branches

 ; GCN-O3-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O3-NEXT:       Function Alias Analysis Results
 ; GCN-O3-NEXT:       Memory SSA
 ; GCN-O3-NEXT:       AMDGPU Annotate Uniform Values
 ; GCN-O3-NEXT:       SI annotate control flow
 ; GCN-O3-NEXT:       Natural Loop Information
 ; GCN-O3-NEXT:       LCSSA Verifier
 ; GCN-O3-NEXT:       Loop-Closed SSA Form Pass
-; GCN-O3-NEXT:     CallGraph Construction
-; GCN-O3-NEXT:     Call Graph SCC Pass Manager
 ; GCN-O3-NEXT:       DummyCGSCCPass
 ; GCN-O3-NEXT:       FunctionPass Manager
 ; GCN-O3-NEXT:         Safe Stack instrumentation pass
 ; GCN-O3-NEXT:         Insert stack protectors
 ; GCN-O3-NEXT:         Dominator Tree Construction
 ; GCN-O3-NEXT:         Post-Dominator Tree Construction
 ; GCN-O3-NEXT:         Natural Loop Information
 ; GCN-O3-NEXT:         Legacy Divergence Analysis

llvm/test/CodeGen/ARM/O3-pipeline.ll

 ; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
 ; CHECK-NEXT:      Function Alias Analysis Results
 ; CHECK-NEXT:      Transform functions to use DSP intrinsics
 ; CHECK-NEXT:      Interleaved Access Pass
 ; CHECK-NEXT:      Type Promotion
 ; CHECK-NEXT:      Dominator Tree Construction
 ; CHECK-NEXT:      Natural Loop Information
 ; CHECK-NEXT:      CodeGen Prepare
-; CHECK-NEXT:    Rewrite Symbols
-; CHECK-NEXT:    FunctionPass Manager
 ; CHECK-NEXT:      Dominator Tree Construction
 ; CHECK-NEXT:      Exception handling preparation
 ; CHECK-NEXT:      Merge internal globals
 ; CHECK-NEXT:      Natural Loop Information
 ; CHECK-NEXT:      Scalar Evolution Analysis
 ; CHECK-NEXT:      Lazy Branch Probability Analysis
 ; CHECK-NEXT:      Lazy Block Frequency Analysis
 ; CHECK-NEXT:      Optimization Remark Emitter
 ; CHECK-NEXT:      Hardware Loop Insertion
 ; CHECK-NEXT:      Scalar Evolution Analysis
 ; CHECK-NEXT:      Loop Pass Manager
 ; CHECK-NEXT:        Transform predicated vector loops to use MVE tail predication
+; CHECK-NEXT:      A No-Op Barrier Pass
+; CHECK-NEXT:      FunctionPass Manager
 ; CHECK-NEXT:      Safe Stack instrumentation pass
 ; CHECK-NEXT:      Insert stack protectors
 ; CHECK-NEXT:      Module Verifier
+; CHECK-NEXT:      Dominator Tree Construction
 ; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
 ; CHECK-NEXT:      Function Alias Analysis Results
 ; CHECK-NEXT:      Natural Loop Information
 ; CHECK-NEXT:      Post-Dominator Tree Construction
 ; CHECK-NEXT:      Branch Probability Analysis
 ; CHECK-NEXT:      Lazy Branch Probability Analysis
 ; CHECK-NEXT:      Lazy Block Frequency Analysis
 ; CHECK-NEXT:      ARM Instruction Selection

llvm/test/CodeGen/Generic/addr-label.ll

+; RUN: llc %s -o - -mtriple=thumbv7-apple-darwin10
 ; RUN: llc %s -o -
 
 ;; Reference to a label that gets deleted.
 define i8* @test1() nounwind {
 entry:
   ret i8* blockaddress(@test1b, %test_label)
 }
 
 define i32 @test1b() nounwind {
 entry:
   ret i32 -1
 test_label:
   br label %ret
 ret:
   ret i32 -1
 }
 
 
-;; Issues with referring to a label that gets RAUW'd later.
+; Issues with referring to a label that gets RAUW'd later.
 define i32 @test2a() nounwind {
 entry:
         %target = bitcast i8* blockaddress(@test2b, %test_label) to i8*
 
         call i32 @test2b(i8* %target)
 
         ret i32 0
 }

llvm/test/CodeGen/X86/O0-pipeline.ll

 ; CHECK-NEXT:       Lower Garbage Collection Instructions
 ; CHECK-NEXT:       Shadow Stack GC Lowering
 ; CHECK-NEXT:       Lower constant intrinsics
 ; CHECK-NEXT:       Remove unreachable blocks from the CFG
 ; CHECK-NEXT:       Expand vector predication intrinsics
 ; CHECK-NEXT:       Scalarize Masked Memory Intrinsics
 ; CHECK-NEXT:       Expand reduction intrinsics
 ; CHECK-NEXT:       Expand indirectbr instructions
-; CHECK-NEXT:     Rewrite Symbols
-; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Exception handling preparation
 ; CHECK-NEXT:       Safe Stack instrumentation pass
 ; CHECK-NEXT:       Insert stack protectors
 ; CHECK-NEXT:       Module Verifier
 ; CHECK-NEXT:       X86 DAG->DAG Instruction Selection
 ; CHECK-NEXT:       X86 PIC Global Base Reg Initialization
 ; CHECK-NEXT:       Finalize ISel and expand pseudo-instructions
 ; CHECK-NEXT:       Local Stack Slot Allocation

llvm/test/CodeGen/X86/opt-pipeline.ll

 ; When EXPENSIVE_CHECKS are enabled, the machine verifier appears between each
 ; pass. Ignore it with 'grep -v'.
 ; RUN: llc -mtriple=x86_64-- -O1 -debug-pass=Structure < %s -o /dev/null 2>&1 \
 ; RUN:   | grep -v 'Verify generated machine code' | FileCheck %s
 ; RUN: llc -mtriple=x86_64-- -O2 -debug-pass=Structure < %s -o /dev/null 2>&1 \
 ; RUN:   | grep -v 'Verify generated machine code' | FileCheck %s
 ; RUN: llc -mtriple=x86_64-- -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 \
 ; RUN:   | grep -v 'Verify generated machine code' | FileCheck %s
+; RUN: llc -mtriple=x86_64-- -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 \
+; RUN:   | FileCheck %s --check-prefix=FPM
 
 ; REQUIRES: asserts
 
 ; CHECK-LABEL: Pass Arguments:
 ; CHECK-NEXT: Target Library Information
 ; CHECK-NEXT: Target Pass Configuration
 ; CHECK-NEXT: Machine Module Information
 ; CHECK-NEXT: Target Transform Information

 ; CHECK-NEXT:       Expand vector predication intrinsics
 ; CHECK-NEXT:       Scalarize Masked Memory Intrinsics
 ; CHECK-NEXT:       Expand reduction intrinsics
 ; CHECK-NEXT:       Interleaved Access Pass
 ; CHECK-NEXT:       X86 Partial Reduction
 ; CHECK-NEXT:       Expand indirectbr instructions
 ; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       CodeGen Prepare
-; CHECK-NEXT:     Rewrite Symbols
-; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Dominator Tree Construction
 ; CHECK-NEXT:       Exception handling preparation
 ; CHECK-NEXT:       Safe Stack instrumentation pass
 ; CHECK-NEXT:       Insert stack protectors
 ; CHECK-NEXT:       Module Verifier
 ; CHECK-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; CHECK-NEXT:       Function Alias Analysis Results
 ; CHECK-NEXT:       Natural Loop Information

 ; CHECK-NEXT:       X86 Indirect Thunks
 ; CHECK-NEXT:       Check CFA info and insert CFI instructions if needed
 ; CHECK-NEXT:       X86 Load Value Injection (LVI) Ret-Hardening
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       X86 Assembly Printer
 ; CHECK-NEXT:       Free MachineFunction
 
+; We should only have one function pass manager.
+; In the past, module passes have accidentally been added into the middle of
+; the codegen pipeline, implicitly creating new function pass managers.
+; FPM: FunctionPass Manager
+; FPM-NOT: FunctionPass Manager
+
 define void @f() {
   ret void
 }

llvm/test/CodeGen/X86/select_meta.ll

-; RUN: llc -mtriple=x86_64-unknown-unknown -print-after-all < %s 2>&1 | FileCheck %s
+; RUN: opt -mtriple=x86_64-unknown-unknown -codegenprepare -S < %s 2>&1 | FileCheck %s
 
 ; Function Attrs: norecurse nounwind readnone uwtable
 define i32 @foo(i32, i32, i32) {
   %4 = and i32 %0, 3
   %5 = icmp eq i32 %4, 1
   %6 = select i1 %5, i32 %1, i32 %2, !prof  !1
 ; CHECK: br {{.*}}label{{.*}}, label{{.*}}, !prof ![[WT:.*]]
   ret i32 %6
 }
 
 !llvm.ident = !{!0}
 
 !0 = !{!"clang version 4.0.0 (trunk 279683)"}
 !1 = !{!"branch_weights", i32 1000, i32 1 }
 ; CHECK: ![[WT]] = !{!"branch_weights", i32 1000, i32 1}

llvm/test/Other/2010-05-06-Printer.ll

 ; RUN: llc -O2 -print-after-all < %s 2>/dev/null
 ; RUN: llc -O2 -print-after-all < %s 2>&1 | FileCheck %s --check-prefix=ALL
 ; RUN: llc -O2 -print-after-all -filter-print-funcs=foo < %s 2>&1 | FileCheck %s --check-prefix=FOO
 ; REQUIRES: default_triple
 define void @tester(){
   ret void
 }
 
 define void @foo(){
   ret void
 }
 
-;ALL-NOT: IR Dump After {{.*}}; ModuleID =
 ;ALL: define void @tester()
 ;ALL: define void @foo()
-;ALL: ModuleID =
 
 ;FOO: IR Dump After
 ;FOO-NEXT: define void @foo()
 ;FOO-NOT: define void @tester

llvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn

deps = [
     "//llvm/lib/CodeGen/GlobalISel",
     "//llvm/lib/CodeGen/SelectionDAG",
     "//llvm/lib/IR",
     "//llvm/lib/MC",
     "//llvm/lib/Support",
     "//llvm/lib/Target",
     "//llvm/lib/Transforms/CFGuard",
     "//llvm/lib/Transforms/Utils",
+    "//llvm/lib/Transforms/IPO",
   ]
   include_dirs = [ "." ]
   sources = [
     "A15SDOptimizer.cpp",
     "ARMAsmPrinter.cpp",
     "ARMBaseInstrInfo.cpp",
     "ARMBaseRegisterInfo.cpp",
     "ARMBasicBlockInfo.cpp",