[RISCV] Fix up stale VECREDUCE comments. NFC.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case ISD::VECREDUCE_AND:
     return RISCVISD::VECREDUCE_AND_VL;
   case ISD::VECREDUCE_OR:
     return RISCVISD::VECREDUCE_OR_VL;
   case ISD::VECREDUCE_XOR:
     return RISCVISD::VECREDUCE_XOR_VL;
   }
 }
 
-// Take a (supported) standard ISD reduction opcode and transform it to a RISCV
-// reduction opcode. Note that this returns a vector type, which must be
-// further processed to access the scalar result in element 0.
 SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
                                             SelectionDAG &DAG) const {
   SDLoc DL(Op);
   SDValue Vec = Op.getOperand(0);
   EVT VecEVT = Vec.getValueType();
 
   unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Op.getOpcode());
 
void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
   case ISD::VECREDUCE_ADD:
   case ISD::VECREDUCE_AND:
   case ISD::VECREDUCE_OR:
   case ISD::VECREDUCE_XOR:
   case ISD::VECREDUCE_SMAX:
   case ISD::VECREDUCE_UMAX:
   case ISD::VECREDUCE_SMIN:
   case ISD::VECREDUCE_UMIN:
-    // The custom-lowering for these nodes returns a vector whose first element
-    // is the result of the reduction. Extract its first element and let the
-    // legalization for EXTRACT_VECTOR_ELT do the rest of the job.
     if (SDValue V = lowerVECREDUCE(SDValue(N, 0), DAG))
       Results.push_back(V);
     break;
   }
 }
 
 // A structure to hold one of the bit-manipulation patterns below. Together, a
 // SHL and non-SHL pattern may form a bit-manipulation pair on a single source: