[NFC] Use generic name for scalable vector stack ID.

[HsiangKai]

Summary

ARM SVE and RISC-V V-extension both support scalable vector types. We need to put scalable vector frame objects on the stack. It needs special handling for scalable vector types. Instead of creating stack ID for these two targets, we prefer to use an unified name for stack ID for scalable vector types.

[david-arm]

LGTM! Seems like a sensible rename to me.

[frasercrmck]

LGTM

llvm/include/llvm/CodeGen/MIRYamlMapping.h

struct ScalarEnumerationTraits<FixedMachineStackObject::ObjectType> {
   }
 };
 
 template <>
 struct ScalarEnumerationTraits<TargetStackID::Value> {
   static void enumeration(yaml::IO &IO, TargetStackID::Value &ID) {
     IO.enumCase(ID, "default", TargetStackID::Default);
     IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
-    IO.enumCase(ID, "sve-vec", TargetStackID::SVEVector);
+    IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector);
     IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
   }
 };
 
 template <> struct MappingTraits<FixedMachineStackObject> {
   static void mapping(yaml::IO &YamlIO, FixedMachineStackObject &Object) {
     YamlIO.mapRequired("id", Object.ID);
     YamlIO.mapOptional(

llvm/include/llvm/CodeGen/TargetFrameLowering.h

namespace llvm {
   class CalleeSavedInfo;
   class MachineFunction;
   class RegScavenger;
 
 namespace TargetStackID {
   enum Value {
     Default = 0,
     SGPRSpill = 1,
-    SVEVector = 2,
+    ScalableVector = 2,
     NoAlloc = 255
   };
 }
 
 /// Information about stack frame layout on the target.  It holds the direction
 /// of stack growth, the known stack alignment on entry to each function, and
 /// the offset to the locals area.
 ///

llvm/lib/Target/AArch64/AArch64FrameLowering.h

StackOffset getNonLocalFrameIndexReference(const MachineFunction &MF,
                                              int FI) const override;
   int getSEHFrameIndexOffset(const MachineFunction &MF, int FI) const;
 
   bool isSupportedStackID(TargetStackID::Value ID) const override {
     switch (ID) {
     default:
       return false;
     case TargetStackID::Default:
-    case TargetStackID::SVEVector:
+    case TargetStackID::ScalableVector:
     case TargetStackID::NoAlloc:
       return true;
     }
   }
 
   bool isStackIdSafeForLocalArea(unsigned StackId) const override {
     // We don't support putting SVE objects into the pre-allocated local
     // frame block at the moment.
-    return StackId != TargetStackID::SVEVector;
+    return StackId != TargetStackID::ScalableVector;
   }
 
   void
   orderFrameObjects(const MachineFunction &MF,
                     SmallVectorImpl<int> &ObjectsToAllocate) const override;
 
 private:
   bool shouldCombineCSRLocalStackBump(MachineFunction &MF,

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

for (MachineInstr &MI : MBB) {
       }
     }
   }
   return DefaultSafeSPDisplacement;
 }
 
 TargetStackID::Value
 AArch64FrameLowering::getStackIDForScalableVectors() const {
-  return TargetStackID::SVEVector;
+  return TargetStackID::ScalableVector;
 }
 
 /// Returns the size of the fixed object area (allocated next to sp on entry)
 /// On Win64 this may include a var args area and an UnwindHelp object for EH.
 static unsigned getFixedObjectSize(const MachineFunction &MF,
                                    const AArch64FunctionInfo *AFI, bool IsWin64,
                                    bool IsFunclet) {
   if (!IsWin64 || IsFunclet) {
for (const auto &Info : CSI) {
     // common demoninator.
     unsigned NewReg;
     if (static_cast<const AArch64RegisterInfo *>(TRI)->regNeedsCFI(Reg, NewReg))
       Reg = NewReg;
     else
       continue;
 
     StackOffset Offset;
-    if (MFI.getStackID(Info.getFrameIdx()) == TargetStackID::SVEVector) {
+    if (MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector) {
       AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
       Offset =
           StackOffset::getScalable(MFI.getObjectOffset(Info.getFrameIdx())) -
           StackOffset::getFixed(AFI->getCalleeSavedStackSize(MFI));
     } else {
       Offset = StackOffset::getFixed(MFI.getObjectOffset(Info.getFrameIdx()) -
                                      getOffsetOfLocalArea());
     }

 }
 
 StackOffset AArch64FrameLowering::resolveFrameIndexReference(
     const MachineFunction &MF, int FI, Register &FrameReg, bool PreferFP,
     bool ForSimm) const {
   const auto &MFI = MF.getFrameInfo();
   int64_t ObjectOffset = MFI.getObjectOffset(FI);
   bool isFixed = MFI.isFixedObjectIndex(FI);
-  bool isSVE = MFI.getStackID(FI) == TargetStackID::SVEVector;
+  bool isSVE = MFI.getStackID(FI) == TargetStackID::ScalableVector;
   return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg,
                                      PreferFP, ForSimm);
 }
 
 StackOffset AArch64FrameLowering::resolveFrameOffsetReference(
     const MachineFunction &MF, int64_t ObjectOffset, bool isFixed, bool isSVE,
     Register &FrameReg, bool PreferFP, bool ForSimm) const {
   const auto &MFI = MF.getFrameInfo();
MIB.addMemOperand(MF.getMachineMemOperand(
         MachinePointerInfo::getFixedStack(MF, FrameIdxReg1),
         MachineMemOperand::MOStore, Size, Alignment));
     if (NeedsWinCFI)
       InsertSEH(MIB, TII, MachineInstr::FrameSetup);
 
     // Update the StackIDs of the SVE stack slots.
     MachineFrameInfo &MFI = MF.getFrameInfo();
     if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR)
-      MFI.setStackID(RPI.FrameIdx, TargetStackID::SVEVector);
+      MFI.setStackID(RPI.FrameIdx, TargetStackID::ScalableVector);
 
   }
   return true;
 }
 
 bool AArch64FrameLowering::restoreCalleeSavedRegisters(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
     MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

 // Returns the size of the stack.
 static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
                                               int &MinCSFrameIndex,
                                               int &MaxCSFrameIndex,
                                               bool AssignOffsets) {
 #ifndef NDEBUG
   // First process all fixed stack objects.
   for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
-    assert(MFI.getStackID(I) != TargetStackID::SVEVector &&
+    assert(MFI.getStackID(I) != TargetStackID::ScalableVector &&
            "SVE vectors should never be passed on the stack by value, only by "
            "reference.");
 #endif
 
   auto Assign = [&MFI](int FI, int64_t Offset) {
     LLVM_DEBUG(dbgs() << "alloc FI(" << FI << ") at SP[" << Offset << "]\n");
     MFI.setObjectOffset(FI, Offset);
   };
#endif
 
   // Ensure that the Callee-save area is aligned to 16bytes.
   Offset = alignTo(Offset, Align(16U));
 
   // Create a buffer of SVE objects to allocate and sort it.
   SmallVector<int, 8> ObjectsToAllocate;
   for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
     unsigned StackID = MFI.getStackID(I);
-    if (StackID != TargetStackID::SVEVector)
+    if (StackID != TargetStackID::ScalableVector)
       continue;
     if (MaxCSFrameIndex >= I && I >= MinCSFrameIndex)
       continue;
     if (MFI.isDeadObjectIndex(I))
       continue;
 
     ObjectsToAllocate.push_back(I);
   }

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

case CCValAssign::Indirect:
           ++NumParts;
         StoreSize *= NumParts;
       }
 
       MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
       Type *Ty = EVT(VA.getValVT()).getTypeForEVT(*DAG.getContext());
       Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty);
       int FI = MFI.CreateStackObject(StoreSize, Alignment, false);
-      MFI.setStackID(FI, TargetStackID::SVEVector);
+      MFI.setStackID(FI, TargetStackID::ScalableVector);
 
       MachinePointerInfo MPI =
           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
       SDValue Ptr = DAG.getFrameIndex(
           FI, DAG.getTargetLoweringInfo().getFrameIndexTy(DAG.getDataLayout()));
       SDValue SpillSlot = Ptr;
 
       // Ensure we generate all stores for each tuple part, whilst updating the

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

if (AArch64::FPR8RegClass.hasSubClassEq(RC))
       Opc = AArch64::STRBui;
     break;
   case 2:
     if (AArch64::FPR16RegClass.hasSubClassEq(RC))
       Opc = AArch64::STRHui;
     else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
       Opc = AArch64::STR_PXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 4:
     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
       Opc = AArch64::STRWui;
       if (Register::isVirtualRegister(SrcReg))
         MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
       else
case 16:
     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
       storeRegPairToStackSlot(getRegisterInfo(), MBB, MBBI,
                               get(AArch64::STPXi), SrcReg, isKill,
                               AArch64::sube64, AArch64::subo64, FI, MMO);
       return;
     } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
       Opc = AArch64::STR_ZXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 24:
     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
       Opc = AArch64::ST1Threev1d;
       Offset = false;
     }
     break;
   case 32:
     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
       Opc = AArch64::ST1Fourv1d;
       Offset = false;
     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
       Opc = AArch64::ST1Twov2d;
       Offset = false;
     } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
       Opc = AArch64::STR_ZZXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 48:
     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
       Opc = AArch64::ST1Threev2d;
       Offset = false;
     } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
       Opc = AArch64::STR_ZZZXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 64:
     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
       Opc = AArch64::ST1Fourv2d;
       Offset = false;
     } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
       Opc = AArch64::STR_ZZZZXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   }
   assert(Opc && "Unknown register class");
   MFI.setStackID(FI, StackID);
 
   const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
                                      .addReg(SrcReg, getKillRegState(isKill))
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
       Opc = AArch64::LDRBui;
     break;
   case 2:
     if (AArch64::FPR16RegClass.hasSubClassEq(RC))
       Opc = AArch64::LDRHui;
     else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
       Opc = AArch64::LDR_PXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 4:
     if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
       Opc = AArch64::LDRWui;
       if (Register::isVirtualRegister(DestReg))
         MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
       else
case 16:
     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
       loadRegPairFromStackSlot(getRegisterInfo(), MBB, MBBI,
                                get(AArch64::LDPXi), DestReg, AArch64::sube64,
                                AArch64::subo64, FI, MMO);
       return;
     } else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
       Opc = AArch64::LDR_ZXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 24:
     if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
       Opc = AArch64::LD1Threev1d;
       Offset = false;
     }
     break;
   case 32:
     if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
       Opc = AArch64::LD1Fourv1d;
       Offset = false;
     } else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
       Opc = AArch64::LD1Twov2d;
       Offset = false;
     } else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
       Opc = AArch64::LDR_ZZXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 48:
     if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
       Opc = AArch64::LD1Threev2d;
       Offset = false;
     } else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
       Opc = AArch64::LDR_ZZZXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 64:
     if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
       Opc = AArch64::LD1Fourv2d;
       Offset = false;
     } else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
       Opc = AArch64::LDR_ZZZZXI;
-      StackID = TargetStackID::SVEVector;
+      StackID = TargetStackID::ScalableVector;
     }
     break;
   }
 
   assert(Opc && "Unknown register class");
   MFI.setStackID(FI, StackID);
 
   const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

 }
 
 bool SIFrameLowering::isSupportedStackID(TargetStackID::Value ID) const {
   switch (ID) {
   case TargetStackID::Default:
   case TargetStackID::NoAlloc:
   case TargetStackID::SGPRSpill:
     return true;
-  case TargetStackID::SVEVector:
+  case TargetStackID::ScalableVector:
     return false;
   }
   llvm_unreachable("Invalid TargetStackID::Value");
 }
 
 // Activate all lanes, returns saved exec.
 static Register buildScratchExecCopy(LivePhysRegs &LiveRegs,
                                      MachineFunction &MF,

llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir

liveins:
   - { reg: '$w0' }
 frameInfo:
   maxAlignment:    16
   adjustsStack:    true
   hasCalls:        true
   maxCallFrameSize: 0
   localFrameSize:  8
 stack:
-  - { id: 0, name: z0.addr, size: 16, alignment: 16, stack-id: sve-vec,
+  - { id: 0, name: z0.addr, size: 16, alignment: 16, stack-id: scalable-vector,
       debug-info-variable: '!29', debug-info-expression: '!DIExpression()',
       debug-info-location: '!30' }
-  - { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: sve-vec,
+  - { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: scalable-vector,
       debug-info-variable: '!31', debug-info-expression: '!DIExpression()',
       debug-info-location: '!32' }
-  - { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: sve-vec,
+  - { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-vector,
       debug-info-variable: '!33', debug-info-expression: '!DIExpression()',
       debug-info-location: '!34' }
-  - { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: sve-vec,
+  - { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-vector,
       debug-info-variable: '!35', debug-info-expression: '!DIExpression()',
       debug-info-location: '!36' }
   - { id: 4, name: w0.addr, size: 4, alignment: 4, local-offset: -4, debug-info-variable: '!37',
       debug-info-expression: '!DIExpression()', debug-info-location: '!38' }
   - { id: 5, name: local_gpr0, size: 4, alignment: 4, local-offset: -8,
       debug-info-variable: '!39', debug-info-expression: '!DIExpression()',
       debug-info-location: '!40' }
-  - { id: 6, name: localv0, size: 16, alignment: 16, stack-id: sve-vec,
+  - { id: 6, name: localv0, size: 16, alignment: 16, stack-id: scalable-vector,
       debug-info-variable: '!42', debug-info-expression: '!DIExpression()',
       debug-info-location: '!43' }
-  - { id: 7, name: localv1, size: 16, alignment: 16, stack-id: sve-vec,
+  - { id: 7, name: localv1, size: 16, alignment: 16, stack-id: scalable-vector,
       debug-info-variable: '!45', debug-info-expression: '!DIExpression()',
       debug-info-location: '!46' }
-  - { id: 8, name: localp0, size: 2, alignment: 2, stack-id: sve-vec,
+  - { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-vector,
       debug-info-variable: '!48', debug-info-expression: '!DIExpression()',
       debug-info-location: '!49' }
-  - { id: 9, name: localp1, size: 2, alignment: 2, stack-id: sve-vec,
+  - { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-vector,
       debug-info-variable: '!51', debug-info-expression: '!DIExpression()',
       debug-info-location: '!52' }
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $z0, $z1, $p0, $p1, $w0
 
     renamable $p2 = COPY killed $p0

llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

frameInfo:
   maxAlignment:    16
   adjustsStack:    true
   hasCalls:        true
   maxCallFrameSize: 0
   localFrameSize:  4
 stack:
   - { id: 0, size: 8,  alignment: 8 }
   - { id: 1, size: 8,  alignment: 8 }
-  - { id: 2, size: 16, alignment: 16, stack-id: sve-vec }
-  - { id: 3, size: 16, alignment: 16, stack-id: sve-vec }
-  - { id: 4, size: 2,  alignment: 2,  stack-id: sve-vec }
-  - { id: 5, size: 2,  alignment: 2,  stack-id: sve-vec }
+  - { id: 2, size: 16, alignment: 16, stack-id: scalable-vector }
+  - { id: 3, size: 16, alignment: 16, stack-id: scalable-vector }
+  - { id: 4, size: 2,  alignment: 2,  stack-id: scalable-vector }
+  - { id: 5, size: 2,  alignment: 2,  stack-id: scalable-vector }
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     liveins: $p0, $p1, $w0, $x1, $z0, $z1
 
     ; Avoid stack slot scavenging.
     $lr = IMPLICIT_DEF
 

llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir

 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog -mattr=+sve %s -o - | FileCheck %s
 ---
 # This test verifies that the basepointer is available in presence of SVE stack objects.
 name: hasBasepointer
 # CHECK-LABEL: name: hasBasepointer
 # CHECK: bb.0:
 # CHECK:      $sp = frame-setup ADDVL_XXI $sp, -1
 # CHECK-NEXT: $sp = frame-setup SUBXri $sp, 16, 0
 # CHECK-NEXT: $x19 = ADDXri $sp, 0, 0
 # CHECK:      STRXui $x0, $x19, 0
 tracksRegLiveness: true
 frameInfo:
   isFrameAddressTaken: true
 stack:
   - { id: 0, type: variable-sized,  alignment: 1 }
   - { id: 1, name: '', size: 16, alignment: 8 }
-  - { id: 2, stack-id: sve-vec, size: 16, alignment: 16 }
+  - { id: 2, stack-id: scalable-vector, size: 16, alignment: 16 }
 body: |
   bb.0:
     liveins: $x0
     STRXui $x0, %stack.1, 0
     RET_ReallyLR
 ...

llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir

--- |
   ; CHECK-NEXT:    ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
   ; CHECK-NEXT:    ldr z8, [sp, #1, mul vl] // 16-byte Folded Reload
   ; CHECK-NEXT:    addvl sp, sp, #2
   ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
   ; CHECK-NEXT:    ret
 ...
 name: fix_restorepoint_p4
 stack:
-  - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 }
+  - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 }
 body:             |
   bb.0.entry:
     $z8 = IMPLICIT_DEF
     $p4 = IMPLICIT_DEF
     B %bb.1
 
   bb.1.entry:
     RET_ReallyLR
 ---

llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir

 # CHECK-NEXT: $[[SCRATCH]] = ADDVL_XXI $fp, -1
 # CHECK-NEXT: STRXui $x0, killed $[[SCRATCH]], 0
 # CHECK: bb.1:
 tracksRegLiveness: true
 frameInfo:
   isFrameAddressTaken: true
 stack:
   - { id: 0, name: '', size: 32761, alignment: 8 }
-  - { id: 1, stack-id: sve-vec, size: 16, alignment: 16 }
+  - { id: 1, stack-id: scalable-vector, size: 16, alignment: 16 }
 body: |
   bb.0:
     liveins: $x0, $x8
     STRXui $x0, %stack.1, 0
     B %bb.1
   bb.1:
     liveins: $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $lr
     RET_ReallyLR implicit $x19, implicit $x20, implicit $x21, implicit $x22, implicit $x23, implicit $x24, implicit $x25, implicit $x26, implicit $x27, implicit $x28, implicit $lr
 ...

llvm/test/CodeGen/AArch64/framelayout-sve.mir

 # ASM-LABEL: test_allocate_sve:
 # ASM:       .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 32 + 16 * VG
 # ASM-NEXT:  .cfi_offset w29, -16
 #
 # UNWINDINFO:       DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +32, DW_OP_plus, DW_OP_consts +16, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT:  DW_CFA_offset: reg29 -16
 name:            test_allocate_sve
 stack:
-  - { id: 0, stack-id: sve-vec, size: 18, alignment: 2 }
+  - { id: 0, stack-id: scalable-vector, size: 18, alignment: 2 }
   - { id: 1, stack-id: default, size: 16, alignment: 8 }
 body:             |
   bb.0.entry:
     RET_ReallyLR
 ---
 ...
 # +----------+
 # | x20, x21 |  // callee saves

 # ASM-NEXT:  .cfi_offset w29, -32
 #
 # UNWINDINFO:       DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +48, DW_OP_plus, DW_OP_consts +16, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT:  DW_CFA_offset: reg20 -8
 # UNWINDINFO-NEXT:  DW_CFA_offset: reg21 -16
 # UNWINDINFO-NEXT:  DW_CFA_offset: reg29 -32
 name:            test_allocate_sve_gpr_callee_saves
 stack:
-  - { id: 0, stack-id: sve-vec, size: 18, alignment: 2 }
+  - { id: 0, stack-id: scalable-vector, size: 18, alignment: 2 }
   - { id: 1, stack-id: default, size: 16, alignment: 8 }
 body:             |
   bb.0.entry:
     $x20 = IMPLICIT_DEF
     $x21 = IMPLICIT_DEF
     RET_ReallyLR
 ---
 ...

 # ASM-NEXT:  .cfi_offset w29, -16
 #
 # UNWINDINFO:       DW_CFA_def_cfa: reg29 +16
 # UNWINDINFO-NEXT:  DW_CFA_offset: reg30 -8
 # UNWINDINFO-NEXT:  DW_CFA_offset: reg29 -16
 
 name:            test_allocate_sve_gpr_realigned
 stack:
-  - { id: 0, stack-id: sve-vec, size: 18, alignment: 2  }
+  - { id: 0, stack-id: scalable-vector, size: 18, alignment: 2  }
   - { id: 1, stack-id: default, size: 16, alignment: 32 }
 body:             |
   bb.0.entry:
     RET_ReallyLR
 ---
 ...
 # +----------+
 # | x20, x21 |  // callee saves

 #
 # UNWINDINFO:       DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +32, DW_OP_plus, DW_OP_consts +24, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT:  DW_CFA_offset: reg29 -16
 
 name:            test_address_sve
 frameInfo:
   maxAlignment:  16
 stack:
-  - { id: 0, stack-id: sve-vec, size: 16, alignment: 8 }
-  - { id: 1, stack-id: sve-vec, size: 16, alignment: 8 }
-  - { id: 2, stack-id: sve-vec, size:  2, alignment: 2 }
+  - { id: 0, stack-id: scalable-vector, size: 16, alignment: 8 }
+  - { id: 1, stack-id: scalable-vector, size: 16, alignment: 8 }
+  - { id: 2, stack-id: scalable-vector, size:  2, alignment: 2 }
   - { id: 3, stack-id: default, size: 16, alignment: 8 }
 body:             |
   bb.0.entry:
     liveins: $z0, $z1, $p0
 
     STR_ZXI $z0, %stack.0, 0
     STR_ZXI $z1, %stack.1, 0
     STR_PXI $p0, %stack.2, 0

 # UNWINDINFO:      DW_CFA_def_cfa: reg29 +16
 # UNWINDINFO-NEXT: DW_CFA_offset: reg30 -8
 # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
 name:            test_address_sve_fp
 frameInfo:
   maxAlignment:  16
   isFrameAddressTaken: true
 stack:
-  - { id: 0, stack-id: sve-vec, size: 16, alignment: 8 }
-  - { id: 1, stack-id: sve-vec, size: 16, alignment: 8 }
-  - { id: 2, stack-id: sve-vec, size:  2, alignment: 2 }
+  - { id: 0, stack-id: scalable-vector, size: 16, alignment: 8 }
+  - { id: 1, stack-id: scalable-vector, size: 16, alignment: 8 }
+  - { id: 2, stack-id: scalable-vector, size:  2, alignment: 2 }
   - { id: 3, stack-id: default, size: 16, alignment: 8 }
 body:             |
   bb.0.entry:
     liveins: $z0, $z1, $p0
 
     STR_ZXI $z0, %stack.0, 0
     STR_ZXI $z1, %stack.1, 0
     STR_PXI $p0, %stack.2, 0

 #
 # UNWINDINFO:      DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +32, DW_OP_plus, DW_OP_consts +8, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
 
 name:             test_stack_arg_sve
 fixedStack:
   - { id: 0, stack-id: default, size: 16, alignment: 16, offset: 0 }
 stack:
-  - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 }
+  - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 }
   - { id: 1, stack-id: default, size: 16, alignment: 16 }
 body:             |
   bb.0.entry:
     liveins: $x0
 
     $x0 = LDRXui %fixed-stack.0, 0
     RET_ReallyLR
 ---

 # ASM-NEXT:  .cfi_offset w29, -16
 #
 # UNWINDINFO:      DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +16, DW_OP_plus, DW_OP_consts +2056, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
 name:            test_address_sve_out_of_range
 frameInfo:
   maxAlignment:  16
 stack:
-  - { id: 0, stack-id: sve-vec, size:   16, alignment: 16 }
-  - { id: 1, stack-id: sve-vec, size: 3584, alignment: 16 }
-  - { id: 2, stack-id: sve-vec, size:  512, alignment: 16 }
+  - { id: 0, stack-id: scalable-vector, size:   16, alignment: 16 }
+  - { id: 1, stack-id: scalable-vector, size: 3584, alignment: 16 }
+  - { id: 2, stack-id: scalable-vector, size:  512, alignment: 16 }
 
 body:             |
   bb.0.entry:
     liveins: $z0, $p0
 
     STR_ZXI $z0, %stack.0, 0
     STR_PXI $p0, %stack.1, 0
 

 # UNWINDINFO:      DW_CFA_def_cfa: reg29 +32
 # UNWINDINFO-NEXT: DW_CFA_offset: reg19 -16
 # UNWINDINFO-NEXT: DW_CFA_offset: reg30 -24
 # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -32
 name:            test_address_gpr_vla
 frameInfo:
   maxAlignment:  16
 stack:
-  - { id: 0, stack-id: sve-vec, size: 16, alignment: 8 }
+  - { id: 0, stack-id: scalable-vector, size: 16, alignment: 8 }
   - { id: 1, stack-id: default, size: 16, alignment: 8 }
   - { id: 2, stack-id: default, type: variable-sized }
 body:             |
   bb.0.entry:
     liveins: $xzr
 
     STRXui $xzr, %stack.1, 0
 

 # UNWINDINFO-NEXT: DW_CFA_expression: reg79 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -64, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT: DW_CFA_offset: reg19 -8
 # UNWINDINFO-NEXT: DW_CFA_offset: reg20 -16
 # UNWINDINFO-NEXT: DW_CFA_offset: reg21 -24
 # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -32
 
 name: save_restore_sve
 stack:
-  - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 }
+  - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 }
   - { id: 1, stack-id: default, size: 32, alignment: 16 }
 body:             |
   bb.0.entry:
 
     $z8_z9_z10_z11   = IMPLICIT_DEF
     $z12_z13_z14_z15 = IMPLICIT_DEF
     $z16_z17_z18_z19 = IMPLICIT_DEF
     $z20_z21_z22_z23 = IMPLICIT_DEF

 # UNWINDINFO-NEXT: DW_CFA_expression: reg76 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT: DW_CFA_expression: reg77 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT: DW_CFA_expression: reg78 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -56, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT: DW_CFA_expression: reg79 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -64, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT: DW_CFA_offset: reg30 -8
 # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
 name: save_restore_sve_realign
 stack:
-  - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 }
+  - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 }
   - { id: 1, stack-id: default, size: 16, alignment: 32 }
 body:             |
   bb.0.entry:
 
     $z8_z9_z10_z11   = IMPLICIT_DEF
     $z12_z13_z14_z15 = IMPLICIT_DEF
     $z16_z17_z18_z19 = IMPLICIT_DEF
     $z20_z21_z22_z23 = IMPLICIT_DEF

 # | id #2 (size 16)     |@ -112
 # | id #3 (size 2)      |@ -114
 # | id #4 (size 16)     |@ -144
 # | id #5 (size 2)      |@ -146
 # +- - - - - - - - - - -+ <- New SP @-160
 # CHECK-LABEL: name: frame_layout
 # CHECK:       stack:
 # CHECK:        - { id: 0, name: '', type: default, offset: -80, size: 32, alignment: 16,
-# CHECK-NEXT:       stack-id: sve-vec,
+# CHECK-NEXT:       stack-id: scalable-vector,
 # CHECK:        - { id: 1, name: '', type: default, offset: -84, size: 4, alignment: 2,
-# CHECK-NEXT:       stack-id: sve-vec,
+# CHECK-NEXT:       stack-id: scalable-vector,
 # CHECK:        - { id: 2, name: '', type: default, offset: -112, size: 16, alignment: 16,
-# CHECK-NEXT:       stack-id: sve-vec,
+# CHECK-NEXT:       stack-id: scalable-vector,
 # CHECK:        - { id: 3, name: '', type: default, offset: -114, size: 2, alignment: 2,
-# CHECK-NEXT:       stack-id: sve-vec,
+# CHECK-NEXT:       stack-id: scalable-vector,
 # CHECK:        - { id: 4, name: '', type: spill-slot, offset: -144, size: 16, alignment: 16,
-# CHECK-NEXT:       stack-id: sve-vec,
+# CHECK-NEXT:       stack-id: scalable-vector,
 # CHECK:        - { id: 5, name: '', type: spill-slot, offset: -146, size: 2, alignment: 2,
-# CHECK-NEXT:       stack-id: sve-vec,
+# CHECK-NEXT:       stack-id: scalable-vector,
 # CHECK:        - { id: 6, name: '', type: spill-slot, offset: -16, size: 16, alignment: 16,
-# CHECK-NEXT:       stack-id: sve-vec, callee-saved-register: '$z8',
+# CHECK-NEXT:       stack-id: scalable-vector, callee-saved-register: '$z8',
 # CHECK:        - { id: 7, name: '', type: spill-slot, offset: -32, size: 16, alignment: 16,
-# CHECK-NEXT:       stack-id: sve-vec, callee-saved-register: '$z23',
+# CHECK-NEXT:       stack-id: scalable-vector, callee-saved-register: '$z23',
 # CHECK:        - { id: 8, name: '', type: spill-slot, offset: -34, size: 2, alignment: 2,
-# CHECK-NEXT:       stack-id: sve-vec, callee-saved-register: '$p4',
+# CHECK-NEXT:       stack-id: scalable-vector, callee-saved-register: '$p4',
 # CHECK:        - { id: 9, name: '', type: spill-slot, offset: -36, size: 2, alignment: 2,
-# CHECK-NEXT:       stack-id: sve-vec, callee-saved-register: '$p15',
+# CHECK-NEXT:       stack-id: scalable-vector, callee-saved-register: '$p15',
 # CHECK:        - { id: 10, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
 # CHECK-NEXT:       stack-id: default, callee-saved-register: '$fp',
 #
 # CHECK:      bb.0.entry:
 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
 # CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -3
 # CHECK-NEXT: STR_PXI killed $p15, $sp, 6
 # CHECK-NEXT: STR_PXI killed $p4, $sp, 7
 # CHECK-NEXT: STR_ZXI killed $z23, $sp, 1
 # CHECK-NEXT: STR_ZXI killed $z8, $sp, 2
 # CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -7
 # CHECK-COUNT-3: frame-setup CFI_INSTRUCTION
 # ASM-LABEL: frame_layout:
 # ASM:       .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xd0, 0x00, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 80 * VG
 # ASM-NEXT:  .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8  @ cfa - 16 - 8 * VG
 # ASM-NEXT:  .cfi_offset w29, -16
 #
 # UNWINDINFO:      DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +16, DW_OP_plus, DW_OP_consts +80, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT: DW_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
 # UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
 name: frame_layout
 stack:
-  - { id: 0, type: default,    size:  32, alignment: 16, stack-id: sve-vec }
-  - { id: 1, type: default,    size:   4, alignment:  2, stack-id: sve-vec }
-  - { id: 2, type: default,    size:  16, alignment: 16, stack-id: sve-vec }
-  - { id: 3, type: default,    size:   2, alignment:  2, stack-id: sve-vec }
-  - { id: 4, type: spill-slot, size:  16, alignment: 16, stack-id: sve-vec }
-  - { id: 5, type: spill-slot, size:   2, alignment:  2, stack-id: sve-vec }
+  - { id: 0, type: default,    size:  32, alignment: 16, stack-id: scalable-vector }
+  - { id: 1, type: default,    size:   4, alignment:  2, stack-id: scalable-vector }
+  - { id: 2, type: default,    size:  16, alignment: 16, stack-id: scalable-vector }
+  - { id: 3, type: default,    size:   2, alignment:  2, stack-id: scalable-vector }
+  - { id: 4, type: spill-slot, size:  16, alignment: 16, stack-id: scalable-vector }
+  - { id: 5, type: spill-slot, size:   2, alignment:  2, stack-id: scalable-vector }
 body:             |
   bb.0.entry:
 
     ; Trigger some callee saves
     $z8  = IMPLICIT_DEF
     $z23 = IMPLICIT_DEF
     $p4  = IMPLICIT_DEF
     $p15 = IMPLICIT_DEF
 
     RET_ReallyLR
 
 ---
 # Make sure we account for the offset between the fp and the sve area, if it exists.
 # FIXME: Should there be an offset?
 # CHECK-LABEL: name: fp_relative_index_with_float_save
 # CHECK:        - { id: 0, name: '', type: default, offset: -16, size: 16, alignment: 16,
-# CHECK-NEXT:       stack-id: sve-vec
+# CHECK-NEXT:       stack-id: scalable-vector
 # CHECK:        - { id: 1, name: '', type: default, offset: -64, size: 16, alignment: 32,
 # CHECK-NEXT:      stack-id: default
 # CHECK:        - { id: 2, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
 # CHECK-NEXT:      stack-id: default, callee-saved-register: '$lr'
 # CHECK:        - { id: 3, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
 # CHECK-NEXT:      stack-id: default, callee-saved-register: '$fp'
 # CHECK:        - { id: 4, name: '', type: spill-slot, offset: -32, size: 8, alignment: 16,
 # CHECK-NEXT:      stack-id: default, callee-saved-register: '$d8'
 
 # CHECK: $x8 = SUBXri $fp, 16, 0
 # CHECK: STR_ZXI $z0, killed $x8, -1
 
 name: fp_relative_index_with_float_save
 stack:
-  - { id: 0, stack-id: sve-vec, size: 16, alignment: 16 }
+  - { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 }
   - { id: 1, stack-id: default, size: 16, alignment: 32 }
 frameInfo:
   maxAlignment:  16
   isFrameAddressTaken: true
 body:             |
   bb.0.entry:
     liveins: $z0
 
     $d8 = IMPLICIT_DEF
 
     STR_ZXI $z0, %stack.0, 0
 
     RET_ReallyLR
 ---

llvm/test/CodeGen/AArch64/live-debugvalues-sve.mir

 frameInfo:
   maxAlignment:    16
   adjustsStack:    true
   hasCalls:        true
   maxCallFrameSize: 0
   savePoint:       '%bb.1'
   restorePoint:    '%bb.1'
 stack:
-  - { id: 0, size: 16, alignment: 16, stack-id: sve-vec }
+  - { id: 0, size: 16, alignment: 16, stack-id: scalable-vector }
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.2(0x30000000), %bb.1(0x50000000)
     liveins: $w0, $z0, $z1
 
     DBG_VALUE $z0, $noreg, !27, !DIExpression(), debug-location !30
     DBG_VALUE $z1, $noreg, !28, !DIExpression(), debug-location !30

llvm/test/CodeGen/AArch64/spillfill-sve.mir

liveins:
   - { reg: '$p0', virtual-reg: '%0' }
 body:             |
   bb.0.entry:
     liveins: $p0
 
     ; CHECK-LABEL: name: spills_fills_stack_id_ppr
     ; CHECK: stack:
     ; CHECK:      - { id: 0, name: '', type: spill-slot, offset: 0, size: 2, alignment: 2
-    ; CHECK-NEXT:     stack-id: sve-vec, callee-saved-register: ''
+    ; CHECK-NEXT:     stack-id: scalable-vector, callee-saved-register: ''
 
     ; EXPAND-LABEL: name: spills_fills_stack_id_ppr
     ; EXPAND: STR_PXI $p0, $sp, 7
     ; EXPAND: $p0 = LDR_PXI $sp, 7
 
     %0:ppr = COPY $p0
 
     $p0 = IMPLICIT_DEF
liveins:
   - { reg: '$z0', virtual-reg: '%0' }
 body:             |
   bb.0.entry:
     liveins: $z0
 
     ; CHECK-LABEL: name: spills_fills_stack_id_zpr
     ; CHECK: stack:
     ; CHECK:      - { id: 0, name: '', type: spill-slot, offset: 0, size: 16, alignment: 16
-    ; CHECK-NEXT:     stack-id: sve-vec, callee-saved-register: ''
+    ; CHECK-NEXT:     stack-id: scalable-vector, callee-saved-register: ''
 
     ; EXPAND-LABEL: name: spills_fills_stack_id_zpr
     ; EXPAND: STR_ZXI $z0, $sp, 0
     ; EXPAND: $z0 = LDR_ZXI $sp, 0
 
     %0:zpr = COPY $z0
 
     $z0_z1_z2_z3     = IMPLICIT_DEF
liveins:
   - { reg: '$z0_z1', virtual-reg: '%0' }
 body:             |
   bb.0.entry:
     liveins: $z0_z1
 
     ; CHECK-LABEL: name: spills_fills_stack_id_zpr2
     ; CHECK: stack:
     ; CHECK:      - { id: 0, name: '', type: spill-slot, offset: 0, size: 32, alignment: 16
-    ; CHECK-NEXT:     stack-id: sve-vec
+    ; CHECK-NEXT:     stack-id: scalable-vector
 
     ; EXPAND-LABEL: name: spills_fills_stack_id_zpr2
     ; EXPAND: STR_ZXI $z0, $sp, 0
     ; EXPAND: STR_ZXI $z1, $sp, 1
     ; EXPAND: $z0 = LDR_ZXI $sp, 0
     ; EXPAND: $z1 = LDR_ZXI $sp, 1
 
     %0:zpr2 = COPY $z0_z1
liveins:
   - { reg: '$z0_z1_z2', virtual-reg: '%0' }
 body:             |
   bb.0.entry:
     liveins: $z0_z1_z2
 
     ; CHECK-LABEL: name: spills_fills_stack_id_zpr3
     ; CHECK: stack:
     ; CHECK:      - { id: 0, name: '', type: spill-slot, offset: 0, size: 48, alignment: 16
-    ; CHECK-NEXT:     stack-id: sve-vec
+    ; CHECK-NEXT:     stack-id: scalable-vector
 
     ; EXPAND-LABEL: name: spills_fills_stack_id_zpr3
     ; EXPAND: STR_ZXI $z0, $sp, 0
     ; EXPAND: STR_ZXI $z1, $sp, 1
     ; EXPAND: STR_ZXI $z2, $sp, 2
     ; EXPAND: $z0 = LDR_ZXI $sp, 0
     ; EXPAND: $z1 = LDR_ZXI $sp, 1
     ; EXPAND: $z2 = LDR_ZXI $sp, 2
liveins:
   - { reg: '$z0_z1_z2_z3', virtual-reg: '%0' }
 body:             |
   bb.0.entry:
     liveins: $z0_z1_z2_z3
 
     ; CHECK-LABEL: name: spills_fills_stack_id_zpr4
     ; CHECK: stack:
     ; CHECK:      - { id: 0, name: '', type: spill-slot, offset: 0, size: 64, alignment: 16
-    ; CHECK-NEXT:     stack-id: sve-vec
+    ; CHECK-NEXT:     stack-id: scalable-vector
 
     ; EXPAND-LABEL: name: spills_fills_stack_id_zpr4
     ; EXPAND: STR_ZXI $z0, $sp, 0
     ; EXPAND: STR_ZXI $z1, $sp, 1
     ; EXPAND: STR_ZXI $z2, $sp, 2
     ; EXPAND: STR_ZXI $z3, $sp, 3
     ; EXPAND: $z0 = LDR_ZXI $sp, 0
     ; EXPAND: $z1 = LDR_ZXI $sp, 1

llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll

 ; RUN: llc -mtriple=aarch64 -mattr=+sve < %s 2>%t | FileCheck %s --check-prefix=CHECKCG
 ; RUN: llc -mtriple=aarch64 -mattr=+sve -stop-after=finalize-isel < %s | FileCheck %s --check-prefix=CHECKISEL
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
 ; WARN-NOT: warning
 
 ; CHECKCG-LABEL: foo:
 ; CHECKCG: addvl   sp, sp, #-1
 
 ; CHECKISEL-LABEL: name: foo
 ; CHECKISEL:       stack:
 ; CHECKISEL:       id: 0, name: ptr, type: default, offset: 0, size: 16, alignment: 16,
-; CHECKISEL-NEXT:  stack-id: sve-vec
+; CHECKISEL-NEXT:  stack-id: scalable-vector
 define i32 @foo(<vscale x 16 x i8> %val) {
   %ptr = alloca <vscale x 16 x i8>
   %res = call i32 @bar(<vscale x 16 x i8>* %ptr)
   ret i32 %res
 }
 
 declare i32 @bar(<vscale x 16 x i8>* %ptr);
 
 ; CHECKCG-LABEL: foo2:
 ; CHECKCG: addvl   sp, sp, #-2
 
 ; CHECKISEL-LABEL: name: foo2
 ; CHECKISEL:       stack:
 ; CHECKISEL:       id: 0, name: ptr, type: default, offset: 0, size: 32, alignment: 16,
-; CHECKISEL-NEXT:  stack-id: sve-vec
+; CHECKISEL-NEXT:  stack-id: scalable-vector
 
 define i32 @foo2(<vscale x 32 x i8> %val) {
   %ptr = alloca <vscale x 32 x i8>, align 16
   %res = call i32 @bar2(<vscale x 32 x i8>* %ptr)
   ret i32 %res
 }
 declare i32 @bar2(<vscale x 32 x i8>* %ptr);

llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll

; CHECK:     RET_ReallyLR implicit $z0
   ret <vscale x 4 x i32> %z9
 }
 
 ; Test that z8 and z9 are passed by reference.
 define aarch64_sve_vector_pcs <vscale x 4 x i32> @caller_with_many_sve_arg(<vscale x 4 x i32> %z) {
 ; CHECK: name: caller_with_many_sve_arg
 ; CHECK: stack:
 ; CHECK:      - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16,
-; CHECK-NEXT:     stack-id: sve-vec
+; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK:      - { id: 1, name: '', type: default, offset: 0, size: 16, alignment: 16,
-; CHECK-NEXT:     stack-id: sve-vec
+; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK-DAG:  [[PTRUE:%[0-9]+]]:ppr_3b = PTRUE_S 31
 ; CHECK-DAG:  ST1W_IMM %{{[0-9]+}}, [[PTRUE]], %stack.1, 0
 ; CHECK-DAG:  ST1W_IMM %{{[0-9]+}}, [[PTRUE]], %stack.0, 0
 ; CHECK-DAG:  [[BASE2:%[0-9]+]]:gpr64sp = ADDXri %stack.1, 0
 ; CHECK-DAG:  [[BASE1:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0
 ; CHECK-DAG:  $x0 = COPY [[BASE1]]
 ; CHECK-DAG:  $x1 = COPY [[BASE2]]
 ; CHECK-NEXT: BL @callee_with_many_sve_arg
; CHECK:     RET_ReallyLR implicit $p0
   ret <vscale x 4 x i1> %p5
 }
 
 ; Test that p4 and p5 are passed by reference.
 define aarch64_sve_vector_pcs <vscale x 4 x i1> @caller_with_many_svepred_arg(<vscale x 4 x i1> %p) {
 ; CHECK: name: caller_with_many_svepred_arg
 ; CHECK: stack:
 ; CHECK:      - { id: 0, name: '', type: default, offset: 0, size: 1, alignment: 4,
-; CHECK-NEXT:     stack-id: sve-vec
+; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK:      - { id: 1, name: '', type: default, offset: 0, size: 1, alignment: 4,
-; CHECK-NEXT:     stack-id: sve-vec
+; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK-DAG: STR_PXI %{{[0-9]+}}, %stack.0, 0
 ; CHECK-DAG: STR_PXI %{{[0-9]+}}, %stack.1, 0
 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0
 ; CHECK-DAG: [[BASE2:%[0-9]+]]:gpr64sp = ADDXri %stack.1, 0
 ; CHECK-DAG: $x0 = COPY [[BASE1]]
 ; CHECK-DAG: $x1 = COPY [[BASE2]]
 ; CHECK-NEXT: BL @callee_with_many_svepred_arg
 ; CHECK:     RET_ReallyLR implicit $p0
; CHECK: RET_ReallyLR implicit $z0
   ret <vscale x 4 x i32> %z9
 }
 
 ; Test that z8 and z9 are passed by reference, where reference is passed on the stack.
 define aarch64_sve_vector_pcs <vscale x 4 x i32> @caller_with_many_gpr_sve_arg(i64 %x, <vscale x 4 x i32> %z, <vscale x 2 x i64> %z2) {
 ; CHECK: name: caller_with_many_gpr_sve_arg
 ; CHECK: stack:
 ; CHECK:      - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16,
-; CHECK-NEXT:     stack-id: sve-vec
+; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK:      - { id: 1, name: '', type: default, offset: 0, size: 16, alignment: 16,
-; CHECK-NEXT:     stack-id: sve-vec
+; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK-DAG: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31
 ; CHECK-DAG: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31
 ; CHECK-DAG: ST1D_IMM %{{[0-9]+}}, killed [[PTRUE_D]], %stack.0, 0
 ; CHECK-DAG: ST1W_IMM %{{[0-9]+}}, killed [[PTRUE_S]], %stack.1, 0
 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64common = ADDXri %stack.0, 0
 ; CHECK-DAG: [[BASE2:%[0-9]+]]:gpr64common = ADDXri %stack.1, 0
 ; CHECK-DAG: [[SP:%[0-9]+]]:gpr64sp = COPY $sp
 ; CHECK-DAG: STRXui killed [[BASE1]], [[SP]], 0
 ; CHECK-DAG: STRXui killed [[BASE2]], [[SP]], 1
 ; CHECK:     BL @callee_with_many_gpr_sve_arg
 ; CHECK:     RET_ReallyLR implicit $z0
   %ret = call aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_gpr_sve_arg(i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 4 x i32> %z, <vscale x 2 x i64> %z2, <vscale x 4 x i32> %z)
   ret <vscale x 4 x i32> %ret
 }

llvm/test/CodeGen/AArch64/sve-localstackalloc.mir

liveins:
   - { reg: '$w0', virtual-reg: '%2' }
 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 # CHECK-LABEL: name: insert_32i8_idx
 # CHECK: localFrameSize:  0
 stack:
   - { id: 0, name: '', type: default, offset: 0, size: 32, alignment: 16,
-      stack-id: sve-vec, callee-saved-register: '', callee-saved-restored: true,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 machineFunctionInfo: {}
 body:             |
   bb.0 (%ir-block.0):
     liveins: $z0, $z1, $w0
 
     %2:gpr32 = COPY $w0
     %1:zpr = COPY $z1