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[RISCV] Spilling for RISC-V V extension. (2nd version)
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Authored by HsiangKai on Jan 21 2021, 9:28 AM.

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Summary

This version does not expect frame pointer will be used for vector frame.

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Event Timeline

HsiangKai created this revision.Jan 21 2021, 9:28 AM
HsiangKai requested review of this revision.Jan 21 2021, 9:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 21 2021, 9:28 AM
Herald added a subscriber: MaskRay. · View Herald Transcript

Is this dependent on the frame lowering patch to emit the csrr vlenb?

Is this patch dependent on https://reviews.llvm.org/D93614?

Yes, D93614 is landed.

Is this dependent on the frame lowering patch to emit the csrr vlenb?

I have added the parent commit.

This revision is now accepted and ready to land.Jan 22 2021, 4:57 PM
frasercrmck added inline comments.Jan 25 2021, 2:20 AM
llvm/test/CodeGen/RISCV/rvv/spill-vector-csr.ll
1 ↗(On Diff #318240)

Might be good to have RV32 tests too

This revision was automatically updated to reflect the committed changes.