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Differential D93707

[FPEnv] Allow fneg + strict_fsub -> strict_fadd in DAGCombiner
Needs ReviewPublic

Authored by ajwock on Dec 22 2020, 7:27 AM.

Details

Reviewers
qiucf
uweigand
craig.topper
andrew.w.kaylor
kpn
RKSimon
Summary

A complimentary change to D85548. This change allows strict_fsub x, (fneg y) to become strict_fadd x, y while preserving chain ordering outside of these operations.

A number of tests were changed significantly because DAGCombiner optimizations cannot be disabled.

Diff Detail

Event Timeline

ajwock created this revision.Dec 22 2020, 7:27 AM
Herald added subscribers: steven.zhang, pengfei, hiraditya, nemanjai. · View Herald TranscriptDec 22 2020, 7:27 AM
ajwock requested review of this revision.Dec 22 2020, 7:27 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 22 2020, 7:27 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B83278: Diff 313339.Dec 22 2020, 8:24 AM
craig.topper added inline comments.Dec 22 2020, 9:42 AM
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
13416

Can we use SelectionDAG::FlagInserter like visitFSUB instead of passing Flags?

llvm/test/CodeGen/X86/fp-intrinsics.ll
70

Why did this get worse?

llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
680

The checks line are normally generated by a script update_llc_test_checks.py. The next time someone reruns that script on this file, theses lines will disappear.

craig.topper added a reviewer: RKSimon.Dec 22 2020, 9:42 AM
RKSimon added inline comments.Dec 23 2020, 4:31 AM
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
13416

+1

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
1062

Was this added by update_llc_test_checks.py ? I'm worried if someone comes along and regenerates it we'll lose this line - what about moving it above the define (update_llc_test_checks.py shouldn't touch it then).

llvm/test/CodeGen/X86/strict-fsub-combines.ll
1

pre-commit this test file with current codegen and use update_llc_test_checks.py

nemanjai added inline comments.Dec 28 2020, 7:40 AM
llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
1062

The equivalent of this can be achieved by adding a RUN line with -mcpu=pwr10 (or a respective target feature attribute for these specific functions). On Power10, we have instructions for materializing floating point constants in registers rather than loading from the constant pool.

RKSimon mentioned this in rGa328ee657798: [X86] Add tests from D93707 for fsub_strict(x,fneg(y)) -> fadd_strict(x,y)….Jul 10 2021, 7:10 AM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
21 lines
test/
CodeGen/
PowerPC/
122 lines
SystemZ/
95 lines
X86/
20 lines
18 lines
76 lines

Diff 313339

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 464 Lines • ▼ Show 20 Lines private:
SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N); SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
SDValue visitTRUNCATE(SDNode *N); SDValue visitTRUNCATE(SDNode *N);
SDValue visitBITCAST(SDNode *N); SDValue visitBITCAST(SDNode *N);
SDValue visitFREEZE(SDNode *N); SDValue visitFREEZE(SDNode *N);
SDValue visitBUILD_PAIR(SDNode *N); SDValue visitBUILD_PAIR(SDNode *N);
SDValue visitFADD(SDNode *N); SDValue visitFADD(SDNode *N);
SDValue visitSTRICT_FADD(SDNode *N); SDValue visitSTRICT_FADD(SDNode *N);
SDValue visitFSUB(SDNode *N); SDValue visitFSUB(SDNode *N);
SDValue visitSTRICT_FSUB(SDNode *N);
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for function 'visitSTRICT_FSUB' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for function 'visitSTRICT_FSUB' [readability-identifier…
SDValue visitFMUL(SDNode *N); SDValue visitFMUL(SDNode *N);
SDValue visitFMA(SDNode *N); SDValue visitFMA(SDNode *N);
SDValue visitFDIV(SDNode *N); SDValue visitFDIV(SDNode *N);
SDValue visitFREM(SDNode *N); SDValue visitFREM(SDNode *N);
SDValue visitFSQRT(SDNode *N); SDValue visitFSQRT(SDNode *N);
SDValue visitFCOPYSIGN(SDNode *N); SDValue visitFCOPYSIGN(SDNode *N);
SDValue visitFPOW(SDNode *N); SDValue visitFPOW(SDNode *N);
SDValue visitSINT_TO_FP(SDNode *N); SDValue visitSINT_TO_FP(SDNode *N);
▲ Show 20 Lines • Show All 1,205 Lines • ▼ Show 20 LinesSDValue DAGCombiner::visit(SDNode *N) {
case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N); case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N); case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
case ISD::TRUNCATE: return visitTRUNCATE(N); case ISD::TRUNCATE: return visitTRUNCATE(N);
case ISD::BITCAST: return visitBITCAST(N); case ISD::BITCAST: return visitBITCAST(N);
case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
case ISD::FADD: return visitFADD(N); case ISD::FADD: return visitFADD(N);
case ISD::STRICT_FADD: return visitSTRICT_FADD(N); case ISD::STRICT_FADD: return visitSTRICT_FADD(N);
case ISD::FSUB: return visitFSUB(N); case ISD::FSUB: return visitFSUB(N);
case ISD::STRICT_FSUB: return visitSTRICT_FSUB(N);
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  case ISD::STRICT_FSUB:        return visitSTRICT_FSUB(N);
+  case ISD::STRICT_FSUB:
+    return visitSTRICT_FSUB(N);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - case ISD::STRICT_FSUB: return…
case ISD::FMUL: return visitFMUL(N); case ISD::FMUL: return visitFMUL(N);
case ISD::FMA: return visitFMA(N); case ISD::FMA: return visitFMA(N);
case ISD::FDIV: return visitFDIV(N); case ISD::FDIV: return visitFDIV(N);
case ISD::FREM: return visitFREM(N); case ISD::FREM: return visitFREM(N);
case ISD::FSQRT: return visitFSQRT(N); case ISD::FSQRT: return visitFSQRT(N);
case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
case ISD::FPOW: return visitFPOW(N); case ISD::FPOW: return visitFPOW(N);
case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
▲ Show 20 Lines • Show All 11,690 Lines • ▼ Show 20 LinesSDValue DAGCombiner::visitFSUB(SDNode *N) {
if (SDValue Fused = visitFSUBForFMACombine(N)) { if (SDValue Fused = visitFSUBForFMACombine(N)) {
AddToWorklist(Fused.getNode()); AddToWorklist(Fused.getNode());
return Fused; return Fused;
} }
return SDValue(); return SDValue();
} }
SDValue DAGCombiner::visitSTRICT_FSUB(SDNode *N) {
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for function 'visitSTRICT_FSUB' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for function 'visitSTRICT_FSUB' [readability-identifier…
SDValue Chain = N->getOperand(0);
SDValue N0 = N->getOperand(1);
SDValue N1 = N->getOperand(2);
EVT VT = N->getValueType(0);
EVT ChainVT = N->getValueType(1);
SDLoc DL(N);
const SDNodeFlags Flags = N->getFlags();
// fold (strict_fsub A, (fneg B)) -> (strict_fadd A, B)
if (SDValue NegN1 =
TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize))
return DAG.getNode(ISD::STRICT_FADD, DL, DAG.getVTList(VT, ChainVT),
{Chain, N0, NegN1}, Flags);
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Can we use SelectionDAG::FlagInserter like visitFSUB instead of passing Flags?

craig.topper: Can we use SelectionDAG::FlagInserter like visitFSUB instead of passing Flags?
RKSimonUnsubmitted
Not Done
ReplyInline Actions

+1

RKSimon: +1
return SDValue();
}
SDValue DAGCombiner::visitFMUL(SDNode *N) { SDValue DAGCombiner::visitFMUL(SDNode *N) {
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1); SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, true); ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, true);
ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true); ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDLoc DL(N); SDLoc DL(N);
const TargetOptions &Options = DAG.getTarget().Options; const TargetOptions &Options = DAG.getTarget().Options;
▲ Show 20 Lines • Show All 9,302 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,053 Lines • ▼ Show 20 Lines %add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64(
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <4 x double> %add ret <4 x double> %add
} }
define <1 x float> @constrained_vector_fsub_v1f32() #0 { define <1 x float> @constrained_vector_fsub_v1f32() #0 {
; PC64LE: # float -1
RKSimonUnsubmitted
Not Done
ReplyInline Actions

Was this added by update_llc_test_checks.py ? I'm worried if someone comes along and regenerates it we'll lose this line - what about moving it above the define (update_llc_test_checks.py shouldn't touch it then).

RKSimon: Was this added by update_llc_test_checks.py ? I'm worried if someone comes along and…
nemanjaiUnsubmitted
Not Done
ReplyInline Actions

The equivalent of this can be achieved by adding a RUN line with -mcpu=pwr10 (or a respective target feature attribute for these specific functions). On Power10, we have instructions for materializing floating point constants in registers rather than loading from the constant pool.

nemanjai: The equivalent of this can be achieved by adding a RUN line with `-mcpu=pwr10` (or a respective…
; PC64LE-LABEL: constrained_vector_fsub_v1f32: ; PC64LE-LABEL: constrained_vector_fsub_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI20_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI20_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI20_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI20_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI20_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI20_0@toc@l(3)
; PC64LE-NEXT: lfs 1, .LCPI20_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI20_1@toc@l(4)
; PC64LE-NEXT: xssubsp 1, 1, 0 ; PC64LE-NEXT: xsaddsp 1, 1, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9: # float -1
; PC64LE9-LABEL: constrained_vector_fsub_v1f32: ; PC64LE9-LABEL: constrained_vector_fsub_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI20_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI20_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI20_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI20_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI20_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI20_1@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI20_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI20_1@toc@l(3)
; PC64LE9-NEXT: xssubsp 1, 1, 0 ; PC64LE9-NEXT: xsaddsp 1, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32( %sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32(
<1 x float> <float 0x7FF0000000000000>, <1 x float> <float 0x7FF0000000000000>,
<1 x float> <float 1.000000e+00>, <1 x float> <float 1.000000e+00>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <1 x float> %sub ret <1 x float> %sub
} }
define <2 x double> @constrained_vector_fsub_v2f64() #0 { define <2 x double> @constrained_vector_fsub_v2f64() #0 {
; PC64LE: # double -1
; PC64LE: # double -0.10000000000000001
; PC64LE-LABEL: constrained_vector_fsub_v2f64: ; PC64LE-LABEL: constrained_vector_fsub_v2f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI21_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI21_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI21_1@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI21_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI21_0@toc@l
; PC64LE-NEXT: addi 4, 4, .LCPI21_1@toc@l ; PC64LE-NEXT: addi 4, 4, .LCPI21_1@toc@l
; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: lxvd2x 1, 0, 4 ; PC64LE-NEXT: lxvd2x 1, 0, 4
; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 0, 0
; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 1, 1
; PC64LE-NEXT: xvsubdp 34, 1, 0 ; PC64LE-NEXT: xvadddp 34, 1, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9: # double -1
; PC64LE9: # double -0.10000000000000001
; PC64LE9-LABEL: constrained_vector_fsub_v2f64: ; PC64LE9-LABEL: constrained_vector_fsub_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI21_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI21_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI21_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI21_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI21_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI21_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI21_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxvx 1, 0, 3
; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: xvadddp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64( %sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64(
<2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, <2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<2 x double> <double 1.000000e+00, double 1.000000e-01>, <2 x double> <double 1.000000e+00, double 1.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %sub ret <2 x double> %sub
} }
define <3 x float> @constrained_vector_fsub_v3f32() #0 { define <3 x float> @constrained_vector_fsub_v3f32() #0 {
; PC64LE: # float -0
; PC64LE: # float -1
; PC64LE: # float -2
; PC64LE-LABEL: constrained_vector_fsub_v3f32: ; PC64LE-LABEL: constrained_vector_fsub_v3f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI22_1@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI22_3@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI22_2@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI22_1@toc@l(3)
; PC64LE-NEXT: lfs 1, .LCPI22_3@toc@l(4)
; PC64LE-NEXT: lfs 2, .LCPI22_2@toc@l(5)
; PC64LE-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI22_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI22_2@toc@ha ; PC64LE-NEXT: xsaddsp 1, 0, 1
; PC64LE-NEXT: addis 5, 2, .LCPI22_1@toc@ha ; PC64LE-NEXT: lfs 3, .LCPI22_0@toc@l(3)
; PC64LE-NEXT: xxlxor 3, 3, 3 ; PC64LE-NEXT: addis 3, 2, .LCPI22_4@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI22_0@toc@l(3) ; PC64LE-NEXT: xsaddsp 2, 0, 2
; PC64LE-NEXT: lfs 1, .LCPI22_2@toc@l(4) ; PC64LE-NEXT: addi 3, 3, .LCPI22_4@toc@l
; PC64LE-NEXT: lfs 2, .LCPI22_1@toc@l(5)
; PC64LE-NEXT: addis 3, 2, .LCPI22_3@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI22_3@toc@l
; PC64LE-NEXT: xssubsp 1, 0, 1
; PC64LE-NEXT: lvx 4, 0, 3 ; PC64LE-NEXT: lvx 4, 0, 3
; PC64LE-NEXT: xssubsp 2, 0, 2 ; PC64LE-NEXT: xsaddsp 0, 0, 3
; PC64LE-NEXT: xssubsp 0, 0, 3
; PC64LE-NEXT: xscvdpspn 1, 1 ; PC64LE-NEXT: xscvdpspn 1, 1
; PC64LE-NEXT: xscvdpspn 2, 2 ; PC64LE-NEXT: xscvdpspn 2, 2
; PC64LE-NEXT: xscvdpspn 0, 0 ; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 1, 1, 3 ; PC64LE-NEXT: xxsldwi 34, 1, 1, 3
; PC64LE-NEXT: xxsldwi 35, 2, 2, 3 ; PC64LE-NEXT: xxsldwi 35, 2, 2, 3
; PC64LE-NEXT: vmrghw 2, 3, 2 ; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: vperm 2, 3, 2, 4
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9: # float -0
; PC64LE9: # float -1
; PC64LE9: # float -2
; PC64LE9-LABEL: constrained_vector_fsub_v3f32: ; PC64LE9-LABEL: constrained_vector_fsub_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_0@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: lfs 0, .LCPI22_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI22_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI22_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_1@toc@ha
; PC64LE9-NEXT: lfs 2, .LCPI22_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI22_1@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI22_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_2@toc@ha
; PC64LE9-NEXT: lfs 3, .LCPI22_2@toc@l(3) ; PC64LE9-NEXT: xsaddsp 0, 1, 0
; PC64LE9-NEXT: lfs 2, .LCPI22_2@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI22_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI22_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI22_3@toc@l ; PC64LE9-NEXT: lfs 3, .LCPI22_3@toc@l(3)
; PC64LE9-NEXT: xssubsp 1, 0, 1 ; PC64LE9-NEXT: addis 3, 2, .LCPI22_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI22_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: xssubsp 2, 0, 2 ; PC64LE9-NEXT: xsaddsp 2, 1, 2
; PC64LE9-NEXT: xssubsp 0, 0, 3 ; PC64LE9-NEXT: xsaddsp 1, 1, 3
; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 1, 1
; PC64LE9-NEXT: xscvdpspn 0, 2 ; PC64LE9-NEXT: xxsldwi 34, 1, 1, 3
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xscvdpspn 1, 2
; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xxsldwi 35, 1, 1, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2 ; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32( %sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32(
<3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, <3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000,
float 0xFFFFFFFFE0000000>, float 0xFFFFFFFFE0000000>,
<3 x float> <float 2.0, float 1.0, float 0.0>, <3 x float> <float 2.0, float 1.0, float 0.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %sub ret <3 x float> %sub
} }
define <3 x double> @constrained_vector_fsub_v3f64() #0 { define <3 x double> @constrained_vector_fsub_v3f64() #0 {
; PC64LE: # double -2
; PC64LE: # double -1
; PC64LE-LABEL: constrained_vector_fsub_v3f64: ; PC64LE-LABEL: constrained_vector_fsub_v3f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI23_1@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI23_2@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI23_2@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI23_3@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI23_1@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI23_2@toc@l
; PC64LE-NEXT: addi 4, 4, .LCPI23_2@toc@l ; PC64LE-NEXT: addi 4, 4, .LCPI23_3@toc@l
; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: lxvd2x 1, 0, 4 ; PC64LE-NEXT: lxvd2x 1, 0, 4
; PC64LE-NEXT: addis 3, 2, .LCPI23_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI23_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI23_1@toc@ha
; PC64LE-NEXT: lfd 3, .LCPI23_0@toc@l(3) ; PC64LE-NEXT: lfd 3, .LCPI23_0@toc@l(3)
; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 0, 0
; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 1, 1
; PC64LE-NEXT: xvsubdp 2, 1, 0 ; PC64LE-NEXT: xvadddp 2, 1, 0
; PC64LE-NEXT: xxlxor 0, 0, 0 ; PC64LE-NEXT: lfs 0, .LCPI23_1@toc@l(4)
; PC64LE-NEXT: xssubdp 3, 3, 0 ; PC64LE-NEXT: xsadddp 3, 3, 0
; PC64LE-NEXT: xxswapd 1, 2 ; PC64LE-NEXT: xxswapd 1, 2
; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9: # double -2
; PC64LE9: # double -1
; PC64LE9-LABEL: constrained_vector_fsub_v3f64: ; PC64LE9-LABEL: constrained_vector_fsub_v3f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI23_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI23_0@toc@ha
; PC64LE9-NEXT: xxlxor 1, 1, 1
; PC64LE9-NEXT: lfd 0, .LCPI23_0@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI23_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI23_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI23_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI23_1@toc@l ; PC64LE9-NEXT: lfs 1, .LCPI23_1@toc@l(3)
; PC64LE9-NEXT: xssubdp 3, 0, 1
; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI23_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI23_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI23_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI23_2@toc@l
; PC64LE9-NEXT: xsadddp 3, 0, 1
; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI23_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI23_3@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxvx 1, 0, 3
; PC64LE9-NEXT: xvsubdp 2, 1, 0 ; PC64LE9-NEXT: xvadddp 2, 1, 0
; PC64LE9-NEXT: xxswapd 1, 2 ; PC64LE9-NEXT: xxswapd 1, 2
; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 killed $vsl1
; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2 ; PC64LE9-NEXT: # kill: def $f2 killed $f2 killed $vsl2
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64( %sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64(
<3 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF, <3 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF>, double 0xFFEFFFFFFFFFFFFF>,
<3 x double> <double 2.0, double 1.0, double 0.0>, <3 x double> <double 2.0, double 1.0, double 0.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x double> %sub ret <3 x double> %sub
} }
define <4 x double> @constrained_vector_fsub_v4f64() #0 { define <4 x double> @constrained_vector_fsub_v4f64() #0 {
; PC64LE: # double -2
; PC64LE: # double -0.20000000000000001
; PC64LE: # double -1
; PC64LE: # double -0.10000000000000001
; PC64LE-LABEL: constrained_vector_fsub_v4f64: ; PC64LE-LABEL: constrained_vector_fsub_v4f64:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI24_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI24_0@toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI24_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI24_1@toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI24_2@toc@ha ; PC64LE-NEXT: addis 5, 2, .LCPI24_2@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI24_0@toc@l ; PC64LE-NEXT: addi 3, 3, .LCPI24_0@toc@l
; PC64LE-NEXT: addi 4, 4, .LCPI24_1@toc@l ; PC64LE-NEXT: addi 4, 4, .LCPI24_1@toc@l
; PC64LE-NEXT: lxvd2x 0, 0, 3 ; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: addi 3, 5, .LCPI24_2@toc@l ; PC64LE-NEXT: addi 3, 5, .LCPI24_2@toc@l
; PC64LE-NEXT: lxvd2x 1, 0, 4 ; PC64LE-NEXT: lxvd2x 1, 0, 4
; PC64LE-NEXT: lxvd2x 2, 0, 3 ; PC64LE-NEXT: lxvd2x 2, 0, 3
; PC64LE-NEXT: xxswapd 0, 0 ; PC64LE-NEXT: xxswapd 0, 0
; PC64LE-NEXT: xxswapd 1, 1 ; PC64LE-NEXT: xxswapd 1, 1
; PC64LE-NEXT: xxswapd 2, 2 ; PC64LE-NEXT: xxswapd 2, 2
; PC64LE-NEXT: xvsubdp 35, 1, 0 ; PC64LE-NEXT: xvadddp 35, 1, 0
; PC64LE-NEXT: xvsubdp 34, 1, 2 ; PC64LE-NEXT: xvadddp 34, 1, 2
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9: # double -2
; PC64LE9: # double -0.20000000000000001
; PC64LE9: # double -1
; PC64LE9: # double -0.10000000000000001
; PC64LE9-LABEL: constrained_vector_fsub_v4f64: ; PC64LE9-LABEL: constrained_vector_fsub_v4f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI24_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI24_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI24_0@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI24_0@toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI24_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI24_1@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI24_1@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI24_1@toc@l
; PC64LE9-NEXT: lxvx 1, 0, 3 ; PC64LE9-NEXT: lxvx 1, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI24_2@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI24_2@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI24_2@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI24_2@toc@l
; PC64LE9-NEXT: xvsubdp 35, 1, 0 ; PC64LE9-NEXT: xvadddp 35, 1, 0
; PC64LE9-NEXT: lxvx 0, 0, 3 ; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: xvsubdp 34, 1, 0 ; PC64LE9-NEXT: xvadddp 34, 1, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64( %sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64(
<4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF, <4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
▲ Show 20 Lines • Show All 7,857 Lines • Show Last 20 Lines

llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll

Show First 20 Lines • Show All 903 Lines • ▼ Show 20 Lines
} }
define <1 x float> @constrained_vector_fsub_v1f32() #0 { define <1 x float> @constrained_vector_fsub_v1f32() #0 {
; S390X-LABEL: constrained_vector_fsub_v1f32: ; S390X-LABEL: constrained_vector_fsub_v1f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI20_0 ; S390X-NEXT: larl %r1, .LCPI20_0
; S390X-NEXT: le %f0, 0(%r1) ; S390X-NEXT: le %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI20_1 ; S390X-NEXT: larl %r1, .LCPI20_1
; S390X-NEXT: seb %f0, 0(%r1) ; S390X-NEXT: aeb %f0, 0(%r1)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fsub_v1f32: ; SZ13-LABEL: constrained_vector_fsub_v1f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vgmf %v0, 2, 8 ; SZ13-NEXT: larl %r1, .LCPI20_0
; SZ13-NEXT: vgmf %v1, 1, 8 ; SZ13-NEXT: vgmf %v0, 1, 8
; SZ13-NEXT: sebr %f1, %f0 ; SZ13-NEXT: aeb %f0, 0(%r1)
; SZ13-NEXT: vlr %v24, %v1 ; SZ13-NEXT: vlr %v24, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32( %sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32(
<1 x float> <float 0x7FF0000000000000>, <1 x float> <float 0x7FF0000000000000>,
<1 x float> <float 1.000000e+00>, <1 x float> <float 1.000000e+00>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <1 x float> %sub ret <1 x float> %sub
} }
define <2 x double> @constrained_vector_fsub_v2f64() #0 { define <2 x double> @constrained_vector_fsub_v2f64() #0 {
; S390X-LABEL: constrained_vector_fsub_v2f64: ; S390X-LABEL: constrained_vector_fsub_v2f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI21_0 ; S390X-NEXT: larl %r1, .LCPI21_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI21_2 ; S390X-NEXT: larl %r1, .LCPI21_2
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI21_1 ; S390X-NEXT: larl %r1, .LCPI21_1
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f1
; S390X-NEXT: sdb %f2, 0(%r1) ; S390X-NEXT: adb %f2, 0(%r1)
; S390X-NEXT: sdbr %f0, %f1 ; S390X-NEXT: adbr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fsub_v2f64: ; SZ13-LABEL: constrained_vector_fsub_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI21_0 ; SZ13-NEXT: larl %r1, .LCPI21_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vgmg %v1, 12, 10 ; SZ13-NEXT: vgmg %v1, 12, 10
; SZ13-NEXT: vfsdb %v24, %v1, %v0 ; SZ13-NEXT: vfadb %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64( %sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64(
<2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, <2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<2 x double> <double 1.000000e+00, double 1.000000e-01>, <2 x double> <double 1.000000e+00, double 1.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x double> %sub ret <2 x double> %sub
} }
define <3 x float> @constrained_vector_fsub_v3f32() #0 { define <3 x float> @constrained_vector_fsub_v3f32() #0 {
; S390X-LABEL: constrained_vector_fsub_v3f32: ; S390X-LABEL: constrained_vector_fsub_v3f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI22_0 ; S390X-NEXT: larl %r1, .LCPI22_0
; S390X-NEXT: le %f0, 0(%r1) ; S390X-NEXT: le %f0, 0(%r1)
; S390X-NEXT: ler %f4, %f0 ; S390X-NEXT: lzer %f1
; S390X-NEXT: lcdfr %f4, %f1
; S390X-NEXT: aebr %f4, %f0
; S390X-NEXT: larl %r1, .LCPI22_1 ; S390X-NEXT: larl %r1, .LCPI22_1
; S390X-NEXT: ler %f2, %f0 ; S390X-NEXT: ler %f2, %f0
; S390X-NEXT: seb %f2, 0(%r1) ; S390X-NEXT: aeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI22_2 ; S390X-NEXT: larl %r1, .LCPI22_2
; S390X-NEXT: seb %f0, 0(%r1) ; S390X-NEXT: aeb %f0, 0(%r1)
; S390X-NEXT: lzer %f1
; S390X-NEXT: sebr %f4, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fsub_v3f32: ; SZ13-LABEL: constrained_vector_fsub_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vgbm %v2, 61440 ; SZ13-NEXT: lzer %f0
; SZ13-NEXT: lzer %f1 ; SZ13-NEXT: vgbm %v1, 61440
; SZ13-NEXT: sebr %f2, %f1 ; SZ13-NEXT: vgmf %v2, 0, 1
; SZ13-NEXT: vgmf %v1, 1, 1 ; SZ13-NEXT: lcdfr %f0, %f0
; SZ13-NEXT: vgbm %v3, 61440 ; SZ13-NEXT: larl %r1, .LCPI22_0
; SZ13-NEXT: vgbm %v0, 61440 ; SZ13-NEXT: aebr %f0, %f1
; SZ13-NEXT: sebr %f3, %f1 ; SZ13-NEXT: aebr %f2, %f1
; SZ13-NEXT: vgmf %v1, 2, 8 ; SZ13-NEXT: aeb %f1, 0(%r1)
; SZ13-NEXT: sebr %f0, %f1 ; SZ13-NEXT: vmrhf %v1, %v2, %v1
; SZ13-NEXT: vmrhf %v0, %v3, %v0 ; SZ13-NEXT: vrepf %v0, %v0, 0
; SZ13-NEXT: vrepf %v1, %v2, 0 ; SZ13-NEXT: vmrhg %v24, %v1, %v0
; SZ13-NEXT: vmrhg %v24, %v0, %v1
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32( %sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32(
<3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, <3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000,
float 0xFFFFFFFFE0000000>, float 0xFFFFFFFFE0000000>,
<3 x float> <float 2.0, float 1.0, float 0.0>, <3 x float> <float 2.0, float 1.0, float 0.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x float> %sub ret <3 x float> %sub
Show All 11 Lines
; S390X-NEXT: sdb %f1, 16(%r2) ; S390X-NEXT: sdb %f1, 16(%r2)
; S390X-NEXT: std %f0, 0(%r2) ; S390X-NEXT: std %f0, 0(%r2)
; S390X-NEXT: std %f2, 8(%r2) ; S390X-NEXT: std %f2, 8(%r2)
; S390X-NEXT: std %f1, 16(%r2) ; S390X-NEXT: std %f1, 16(%r2)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fsub_v3f64: ; SZ13-LABEL: constrained_vector_fsub_v3f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vl %v0, 0(%r2), 4 ; SZ13-NEXT: vl %v0, 0(%r2), 4
; SZ13-NEXT: vgmg %v2, 12, 10 ; SZ13-NEXT: vgmg %v2, 12, 10
; SZ13-NEXT: sdb %f2, 16(%r2) ; SZ13-NEXT: sdb %f2, 16(%r2)
; SZ13-NEXT: vgmg %v1, 12, 10 ; SZ13-NEXT: vgmg %v1, 12, 10
; SZ13-NEXT: vfsdb %v0, %v1, %v0 ; SZ13-NEXT: vfsdb %v0, %v1, %v0
; SZ13-NEXT: vst %v0, 0(%r2), 4 ; SZ13-NEXT: vst %v0, 0(%r2), 4
; SZ13-NEXT: std %f2, 16(%r2) ; SZ13-NEXT: std %f2, 16(%r2)
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%b = load <3 x double>, <3 x double>* %a %b = load <3 x double>, <3 x double>* %a
%sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64( %sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64(
<3 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF, <3 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF>, double 0xFFEFFFFFFFFFFFFF>,
<3 x double> %b, <3 x double> %b,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
store <3 x double> %sub, <3 x double>* %a store <3 x double> %sub, <3 x double>* %a
ret void ret void
} }
define <4 x double> @constrained_vector_fsub_v4f64() #0 { define <4 x double> @constrained_vector_fsub_v4f64() #0 {
; S390X-LABEL: constrained_vector_fsub_v4f64: ; S390X-LABEL: constrained_vector_fsub_v4f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI24_0 ; S390X-NEXT: larl %r1, .LCPI24_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI24_1 ; S390X-NEXT: larl %r1, .LCPI24_1
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f1
; S390X-NEXT: sdb %f6, 0(%r1) ; S390X-NEXT: ldr %f6, %f1
; S390X-NEXT: adb %f6, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI24_2 ; S390X-NEXT: larl %r1, .LCPI24_2
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f4, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI24_4 ; S390X-NEXT: larl %r1, .LCPI24_4
; S390X-NEXT: ldeb %f3, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI24_3 ; S390X-NEXT: larl %r1, .LCPI24_3
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: adb %f2, 0(%r1)
; S390X-NEXT: sdb %f2, 0(%r1) ; S390X-NEXT: adbr %f4, %f1
; S390X-NEXT: ldr %f4, %f0 ; S390X-NEXT: adbr %f0, %f1
; S390X-NEXT: sdbr %f4, %f1
; S390X-NEXT: sdbr %f0, %f3
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fsub_v4f64: ; SZ13-LABEL: constrained_vector_fsub_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI24_0 ; SZ13-NEXT: larl %r1, .LCPI24_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vgmg %v1, 12, 10 ; SZ13-NEXT: vgmg %v1, 12, 10
; SZ13-NEXT: larl %r1, .LCPI24_1 ; SZ13-NEXT: larl %r1, .LCPI24_1
; SZ13-NEXT: vfsdb %v26, %v1, %v0 ; SZ13-NEXT: vfadb %v26, %v1, %v0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfsdb %v24, %v1, %v0 ; SZ13-NEXT: vfadb %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64( %sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64(
<4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF, <4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
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llvm/test/CodeGen/X86/fp-intrinsics.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; // downward, this shouldn't be simplified. ; // downward, this shouldn't be simplified.
; return a - 0; ; return a - 0;
; } ; }
; ;
define double @f2(double %a) #0 { define double @f2(double %a) #0 {
; X87-LABEL: f2: ; X87-LABEL: f2:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: fldz ; X87-NEXT: fldz
; X87-NEXT: fsubrl {{[0-9]+}}(%esp) ; X87-NEXT: fchs
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; X87-NEXT: faddl 4(%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f2: ; X86-SSE-LABEL: f2:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $12, %esp ; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 16 ; X86-SSE-NEXT: .cfi_def_cfa_offset 16
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorpd %xmm1, %xmm1 ; X86-SSE-NEXT: addsd .LCPI1_0, %xmm0
; X86-SSE-NEXT: subsd %xmm1, %xmm0
; X86-SSE-NEXT: movsd %xmm0, (%esp) ; X86-SSE-NEXT: movsd %xmm0, (%esp)
; X86-SSE-NEXT: fldl (%esp) ; X86-SSE-NEXT: fldl (%esp)
; X86-SSE-NEXT: wait ; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $12, %esp ; X86-SSE-NEXT: addl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4 ; X86-SSE-NEXT: .cfi_def_cfa_offset 4
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; SSE-LABEL: f2: ; SSE-LABEL: f2:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: xorpd %xmm1, %xmm1 ; SSE-NEXT: addsd .LCPI1_0(%rip), %xmm0
; SSE-NEXT: subsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: f2: ; AVX-LABEL: f2:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vaddsd .LCPI1_0(%rip), %xmm0, %xmm0
; AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry-f2:
%sub = call double @llvm.experimental.constrained.fsub.f64( %sub = call double @llvm.experimental.constrained.fsub.f64(
double %a, double %a,
double 0.000000e+00, double 0.000000e+00,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret double %sub ret double %sub
} }
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llvm/test/CodeGen/X86/strict-fsub-combines.ll

  • This file was added.
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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pre-commit this test file with current codegen and use update_llc_test_checks.py

RKSimon: pre-commit this test file with current codegen and use update_llc_test_checks.py
define float @fneg_strict_fsub_to_strict_fadd(float %x, float %y) {
; CHECK: addss %{{.*}}, %{{.*}}
%neg = fneg float %y
%sub = call float @llvm.experimental.constrained.fsub.f32(float %x, float %neg, metadata!"round.dynamic", metadata!"fpexcept.strict")
ret float %sub
}
define double @fneg_strict_fsub_to_strict_fadd_d(double %x, double %y) {
; CHECK: addsd %{{.*}}, %{{.*}}
%neg = fneg double %y
%sub = call double @llvm.experimental.constrained.fsub.f64(double %x, double %neg, metadata!"round.dynamic", metadata!"fpexcept.strict")
ret double %sub
}
declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata)
declare double @llvm.experimental.constrained.fsub.f64(double, double, metadata, metadata)

llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 671 Lines • ▼ Show 20 Lines %add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64(
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x double> %add ret <4 x double> %add
} }
define <1 x float> @constrained_vector_fsub_v1f32() #0 { define <1 x float> @constrained_vector_fsub_v1f32() #0 {
; CHECK: # float -1
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The checks line are normally generated by a script update_llc_test_checks.py. The next time someone reruns that script on this file, theses lines will disappear.

craig.topper: The checks line are normally generated by a script update_llc_test_checks.py. The next time…
; CHECK-LABEL: constrained_vector_fsub_v1f32: ; CHECK-LABEL: constrained_vector_fsub_v1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: subss {{.*}}(%rip), %xmm0 ; CHECK-NEXT: addss {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX: # float -1
; AVX-LABEL: constrained_vector_fsub_v1f32: ; AVX-LABEL: constrained_vector_fsub_v1f32:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-NEXT: vsubss {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32( %sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32(
<1 x float> <float 0x7FF0000000000000>, <1 x float> <float 0x7FF0000000000000>,
<1 x float> <float 1.000000e+00>, <1 x float> <float 1.000000e+00>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <1 x float> %sub ret <1 x float> %sub
} }
define <2 x double> @constrained_vector_fsub_v2f64() #0 { define <2 x double> @constrained_vector_fsub_v2f64() #0 {
; CHECK: # double -1
; CHECK: # double -0.10000000000000001
; CHECK-LABEL: constrained_vector_fsub_v2f64: ; CHECK-LABEL: constrained_vector_fsub_v2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308] ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
; CHECK-NEXT: subpd {{.*}}(%rip), %xmm0 ; CHECK-NEXT: addpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX: # double -1
; AVX: # double -0.10000000000000001
; AVX-LABEL: constrained_vector_fsub_v2f64: ; AVX-LABEL: constrained_vector_fsub_v2f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308] ; AVX-NEXT: vmovapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
; AVX-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vaddpd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64( %sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64(
<2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, <2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<2 x double> <double 1.000000e+00, double 1.000000e-01>, <2 x double> <double 1.000000e+00, double 1.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x double> %sub ret <2 x double> %sub
} }
define <3 x float> @constrained_vector_fsub_v3f32() #0 { define <3 x float> @constrained_vector_fsub_v3f32() #0 {
; CHECK: # float -0
; CHECK: # float -2
; CHECK: # float -1
; CHECK-LABEL: constrained_vector_fsub_v3f32: ; CHECK-LABEL: constrained_vector_fsub_v3f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: movaps %xmm1, %xmm2 ; CHECK-NEXT: addss %xmm1, %xmm2
; CHECK-NEXT: subss %xmm0, %xmm2 ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: addss %xmm1, %xmm0
; CHECK-NEXT: subss {{.*}}(%rip), %xmm0 ; CHECK-NEXT: addss {{.*}}(%rip), %xmm1
; CHECK-NEXT: subss {{.*}}(%rip), %xmm1
; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; CHECK-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_fsub_v3f32: ; AVX-LABEL: constrained_vector_fsub_v3f32:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm1
; AVX-NEXT: vsubss %xmm0, %xmm1, %xmm0 ; AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm2
; AVX-NEXT: vsubss {{.*}}(%rip), %xmm1, %xmm2 ; AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vsubss {{.*}}(%rip), %xmm1, %xmm1 ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[2,3]
; AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32( %sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32(
<3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, <3 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000,
float 0xFFFFFFFFE0000000>, float 0xFFFFFFFFE0000000>,
<3 x float> <float 2.0, float 1.0, float 0.0>, <3 x float> <float 2.0, float 1.0, float 0.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x float> %sub ret <3 x float> %sub
} }
define <3 x double> @constrained_vector_fsub_v3f64() #0 { define <3 x double> @constrained_vector_fsub_v3f64() #0 {
; CHECK: # double -2
; CHECK: # double -1
; CHECK: # double -0
; CHECK-LABEL: constrained_vector_fsub_v3f64: ; CHECK-LABEL: constrained_vector_fsub_v3f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorpd %xmm0, %xmm0 ; CHECK: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
; CHECK-NEXT: addpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: subsd %xmm0, %xmm1 ; CHECK-NEXT: addsd {{.*}}(%rip), %xmm1
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
; CHECK-NEXT: subpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: movapd %xmm0, %xmm1
; CHECK-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; CHECK-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: wait ; CHECK-NEXT: wait
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_fsub_v3f64: ; AVX-LABEL: constrained_vector_fsub_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0
; AVX-NEXT: vmovapd {{.*#+}} xmm1 = [-1.7976931348623157E+308,-1.7976931348623157E+308] ; AVX-NEXT: vmovapd {{.*#+}} xmm1 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
; AVX-NEXT: vsubpd {{.*}}(%rip), %xmm1, %xmm1 ; AVX-NEXT: vaddpd {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64( %sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64(
<3 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF, <3 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF>, double 0xFFEFFFFFFFFFFFFF>,
<3 x double> <double 2.0, double 1.0, double 0.0>, <3 x double> <double 2.0, double 1.0, double 0.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x double> %sub ret <3 x double> %sub
} }
define <4 x double> @constrained_vector_fsub_v4f64() #0 { define <4 x double> @constrained_vector_fsub_v4f64() #0 {
; CHECK: # double -2
; CHECK: # double -0.20000000000000001
; CHECK: # double -1
; CHECK: # double -0.10000000000000001
; CHECK-LABEL: constrained_vector_fsub_v4f64: ; CHECK-LABEL: constrained_vector_fsub_v4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308] ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
; CHECK-NEXT: movapd %xmm0, %xmm1 ; CHECK-NEXT: movapd {{.*#+}} xmm1 = [-2.0E+0,-2.0000000000000001E-1]
; CHECK-NEXT: subpd {{.*}}(%rip), %xmm1 ; CHECK-NEXT: addpd %xmm0, %xmm1
; CHECK-NEXT: subpd {{.*}}(%rip), %xmm0 ; CHECK-NEXT: addpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_fsub_v4f64: ; AVX1-LABEL: constrained_vector_fsub_v4f64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308] ; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308]
; AVX1-NEXT: vsubpd {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: constrained_vector_fsub_v4f64: ; AVX512-LABEL: constrained_vector_fsub_v4f64:
; AVX512: # %bb.0: # %entry ; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vbroadcastsd {{.*#+}} ymm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308] ; AVX512-NEXT: vbroadcastsd {{.*#+}} ymm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308]
; AVX512-NEXT: vsubpd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
entry: entry:
%sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64( %sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64(
<4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF, <4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
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