[InstCombine] Canonicalize SPF to abs intrinc

[lebedev.ri]

Summary

This patch enables canonicalization of SPF_ABS and SPF_ABS to the abs intrinsic. I'll comment in-line for remaining issues...

[nikic]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

1070

I'm wondering what to do about this one use check. Should we canonicalize even if the compare has other uses?

We are folding cmp+sub+select into abs or abs+sub. However, both cmp and sub can potentially have extra uses.

llvm/test/Transforms/InstCombine/abs_abs.ll

94

This is the main remaining problem: What happens here is that we see abs(x) > 0, convert this to abs(x) != 0 (based on abs range) and then to x != 0. The last step happens due to the fold I added in rGada8a17d945c17c5603e24824f642ca199412adf, previously this worked. At that point we are left with something like x != 0 ? abs(x) : -abs(x), which is no longer a proper abs.

What do you think the best way to handle this would be? Should this pattern be added to the SPF_ABS recognition? Just explicitly match it in InstCombine?

[nikic]

Rebase over D87197, update affected clang tests.

[dmgreen]

I would expect the tests in llvm to only be subset of the possible second order effects that can come up from changing this. Perhaps abs is simple enough, but you might want to run the llvm test suite to see if there are any other interesting binary differences.

clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c

3 ↗

(On Diff #290127)

Hmm. These needn't be running -O3. I'll see to removing that. Looks OK though, from what I understand about how these get lowered.

[nikic]

I've looked at some of the diffs on test suite. The main change I'm seeing is that loops containing abs now get unrolled more. I'm not sure whether that's expected/desired or not.

I've also spotted two possible folds (these aren't regressions though, they aren't recognized in select form either):

• abs(x, false) < 0 => x == INT_MIN
• https://alive2.llvm.org/ce/z/Mu93Wx

[nikic]

To give an example of what I mean by more unrolling, https://editor.mergely.com/z5GcKJGU/ is the diff for Bitcode/simd_ops/CMakeFiles/simd_ops_test_op_pabsd_237. This is a loop with llvm.abs.v4i32 operations that now has double the unrolling factor.

[nikic]

Rebase

[nikic]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

1070

Here's how dropping the one use check would look like: https://gist.github.com/nikic/3dece504951cba82415fed2d6aa876bf

Nominally, we are only increasing instruction count for the combination of nabs with extra uses on both icmp and sub.

[spatel]

LGTM - I think we should give this a try as-is (with the one-use check still there), see if anything regresses, then ease/remove the use check as a follow-on.
As noted, we may need to adjust cost models to account for the size/speed difference that's showing up in unrolling/inlining. That's probably because we assume that an intrinsic is expanded to a single instruction vs. the current cmp+sub+select being 3 instructions?

[nikic]

In D87188#2277728, @spatel wrote:

LGTM - I think we should give this a try as-is (with the one-use check still there), see if anything regresses, then ease/remove the use check as a follow-on.

Okay, let's do that.

As noted, we may need to adjust cost models to account for the size/speed difference that's showing up in unrolling/inlining. That's probably because we assume that an intrinsic is expanded to a single instruction vs. the current cmp+sub+select being 3 instructions?

The default abs cost model already uses icmp+select+sub. Though X86 has custom cost model for the vector variants, which is generally cheaper, so it makes sense that more unrolling is seen there. I expect that this part of the change already happened when the vector intrinsics were switched over recently.

[mstorsjo]

This broke a few tests for me (generating code that now gives the fail result at runtime).

I'm not entirely sure which bit is the culprit, but the difference in output (that breaks tests) for one object file is available at https://martin.st/temp/vc1_block-diff-aarch64.txt, and https://martin.st/temp/vc1_block-diff-armv7.txt. For the aarch64 version, it looks like some conditionals are inverted, like these changes:

-	b.ge	.LBB1_124
+	b.hs	.LBB1_124

and

-	csel	w14, w15, w14, gt
+	csel	w14, w15, w14, hi

(with no seemingly related changes that would change the roles of the registers).

The input files for reproducing the issues are available at https://martin.st/temp/vc1_block-aarch64.c and https://martin.st/temp/vc1_block-armv7.c, which can be compiled with clang -target {aarch64,armv7}-w64-mingw32 -c -O2 vc1_block-{aarch64,armv7}.c.

[sanwou01]

I know this has already been reverted but just FYI that I've bisected a ~2% regression in SPEC2017 x264_r on AArch64 to this commit. Presumably this is due to the extra unrolling / cost modelling issue already mentioned?

[spatel]

In D87188#2281957, @sanwou01 wrote:

I know this has already been reverted but just FYI that I've bisected a ~2% regression in SPEC2017 x264_r on AArch64 to this commit. Presumably this is due to the extra unrolling / cost modelling issue already mentioned?

That would be my guess. I'm not familiar with the unroller or inliner, but I don't even see them using the cost model at 1st glance. Are they purely counting IR instructions?

If I missed the cost model calls, the cost model is still not correct for code-size:

$ cat cost.ll
declare i32        @llvm.abs.i32(i32, i1)
define i32 @abs(i32 %x, i32 %y) {
  %I32 = call i32 @llvm.abs.i32(i32 %x, i1 false)
  %negx = sub i32 0, %x
  %cmp = icmp sgt i32 %x, -1
  %sel = select i1 %cmp, i32 %x, i32 %negx 
  ret i32 %I32
}

$ opt  -cost-model -cost-kind=code-size -analyze -mtriple=aarch64--  cost.ll 
Printing analysis 'Cost Model Analysis' for function 'abs':
Cost Model: Found an estimated cost of 1 for instruction:   %I32 = call i32 @llvm.abs.i32(i32 %x, i1 false)
Cost Model: Found an estimated cost of 1 for instruction:   %negx = sub i32 0, %x
Cost Model: Found an estimated cost of 1 for instruction:   %cmp = icmp sgt i32 %x, -1
Cost Model: Found an estimated cost of 1 for instruction:   %sel = select i1 %cmp, i32 %x, i32 %negx

So we're assuming the size cost is either 1 or 3 depending on how we encoded abs() in IR, but neither is correct for AArch64 IIUC:

$ llc -o - -mtriple=aarch64-- cost.ll 
	cmp	w0, #0                          // =0
	cneg	w0, w0, mi
	ret

[nikic]

In D87188#2281093, @mstorsjo wrote:

This broke a few tests for me (generating code that now gives the fail result at runtime).

I'm not entirely sure which bit is the culprit, but the difference in output (that breaks tests) for one object file is available at https://martin.st/temp/vc1_block-diff-aarch64.txt, and https://martin.st/temp/vc1_block-diff-armv7.txt. For the aarch64 version, it looks like some conditionals are inverted, like these changes:

-	b.ge	.LBB1_124
+	b.hs	.LBB1_124

and

-	csel	w14, w15, w14, gt
+	csel	w14, w15, w14, hi

(with no seemingly related changes that would change the roles of the registers).

The input files for reproducing the issues are available at https://martin.st/temp/vc1_block-aarch64.c and https://martin.st/temp/vc1_block-armv7.c, which can be compiled with clang -target {aarch64,armv7}-w64-mingw32 -c -O2 vc1_block-{aarch64,armv7}.c.

Based on an initial look, the changes in comparison predicates here are probably a red herring. If I understand right, those predicates are switching from signed to unsigned comparison (e.g. gt to hi). I also see similar changes in IR. However, all the cases I looked at are actually correct (e.g. abs(x) > abs(y) can be compared signed or unsigned for poisoning abs). Assuming that this code is clean under ubsan, the problem is likely something else.

[mstorsjo]

In D87188#2282502, @nikic wrote:

Based on an initial look, the changes in comparison predicates here are probably a red herring. If I understand right, those predicates are switching from signed to unsigned comparison (e.g. gt to hi). I also see similar changes in IR. However, all the cases I looked at are actually correct (e.g. abs(x) > abs(y) can be compared signed or unsigned for poisoning abs). Assuming that this code is clean under ubsan, the problem is likely something else.

I just checked, and the code is indeed clean under ubsan.

The changes in the asm is more than just a few places, so it's quite a bit of work to dissect which one of them (if the changes are localized into smaller individual changes) is the one that's causing the error...

[nikic]

Reopening this so we don't forget...

I believe @spatel is working on the cost modelling. I did not have much luck tracking down the miscompile, at least did not spot anything incriminating in the llvm-diff.

[spatel]

In D87188#2348326, @nikic wrote:

Reopening this so we don't forget...

I believe @spatel is working on the cost modelling. I did not have much luck tracking down the miscompile, at least did not spot anything incriminating in the llvm-diff.

Yes, I'm working through the mess of the TTI cost model with things like:
c963bde0152a
It's a slog...

[spatel]

In D87188#2348343, @spatel wrote:

In D87188#2348326, @nikic wrote:

Reopening this so we don't forget...

I believe @spatel is working on the cost modelling. I did not have much luck tracking down the miscompile, at least did not spot anything incriminating in the llvm-diff.

Yes, I'm working through the mess of the TTI cost model with things like:
c963bde0152a
It's a slog...

D90554 / f7eac51b9b
I think that change makes this patch ready to try again. If we do see regressions, then it should now be easy to adjust target-specific cost modeling of abs() intrinsics to fix those.

[lebedev.ri]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

1070

I think we shouldn't have one-use checks here, yes.

[nikic]

In D87188#2385619, @spatel wrote:

D90554 / f7eac51b9b
I think that change makes this patch ready to try again. If we do see regressions, then it should now be easy to adjust target-specific cost modeling of abs() intrinsics to fix those.

We still need to track down the miscompile that @mstorsjo reported before reapplying this patch.

[nikic]

Rebase.

[nikic]

This needs someone with access to AArch64 hardware to look into https://reviews.llvm.org/D87188#2281093 to make progress. I don't have any AArch64 hardware, and judging by the time it takes to build cmake on an AArch64 machine in the GCC compile farm, there's no way I'm going to be doing LLVM builds there.

[lebedev.ri]

@mstorsjo please can you be more specific what kind of tests are starting to fail?
Do those tests just check that the code compiled into an identical assembly?

I reduced vc1_block-aarch64.c, and got:

; ModuleID = 'input.ll'
source_filename = "vc1_block-aarch64.c"
target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-w64-windows-gnu"

define i1 @barney(i8 %arg, i8 %arg9) {
bb:
  %tmp = sext i8 %arg to i32
  %tmp10 = icmp slt i32 %tmp, 0
  %tmp11 = sub nsw i32 0, %tmp
  %tmp12 = select i1 %tmp10, i32 %tmp11, i32 %tmp
  %tmp13 = shl nuw nsw i32 %tmp12, 1
  %tmp14 = zext i8 %arg9 to i32
  %tmp15 = add nuw nsw i32 %tmp13, %tmp14
  %tmp16 = icmp slt i32 %tmp15, 2
  ret i1 %tmp16
}

declare i32 @eggs()

which used to get optimized into

; ModuleID = '<stdin>'
source_filename = "vc1_block-aarch64.c"
target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-w64-windows-gnu"

define i1 @barney(i8 %arg, i8 %arg9) {
bb:
  %tmp = sext i8 %arg to i32
  %tmp10 = icmp slt i32 %tmp, 0
  %tmp11 = sub nsw i32 0, %tmp
  %tmp12 = select i1 %tmp10, i32 %tmp11, i32 %tmp
  %tmp13 = shl nuw nsw i32 %tmp12, 1
  %tmp14 = zext i8 %arg9 to i32
  %tmp15 = add nuw nsw i32 %tmp13, %tmp14
  %tmp16 = icmp slt i32 %tmp15, 2
  ret i1 %tmp16
}

declare i32 @eggs()

and is now optimized into

; ModuleID = '<stdin>'
source_filename = "vc1_block-aarch64.c"
target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-w64-windows-gnu"

define i1 @barney(i8 %arg, i8 %arg9) {
bb:
  %tmp = sext i8 %arg to i32
  %0 = call i32 @llvm.abs.i32(i32 %tmp, i1 true)
  %tmp13 = shl nuw nsw i32 %0, 1
  %tmp14 = zext i8 %arg9 to i32
  %tmp15 = add nuw nsw i32 %tmp13, %tmp14
  %tmp16 = icmp ult i32 %tmp15, 2
  ret i1 %tmp16
}

declare i32 @eggs()

; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
declare i32 @llvm.abs.i32(i32, i1 immarg) #0

attributes #0 = { nofree nosync nounwind readnone speculatable willreturn }

which is not a miscompile:

$ /repositories/alive2/build-Clang-release/alive-tv old.ll new.ll

----------------------------------------
define i1 @barney(i8 %arg, i8 %arg9) {
%bb:
  %tmp = sext i8 %arg to i32
  %tmp10 = icmp slt i32 %tmp, 0
  %tmp11 = sub nsw i32 0, %tmp
  %tmp12 = select i1 %tmp10, i32 %tmp11, i32 %tmp
  %tmp13 = shl nsw nuw i32 %tmp12, 1
  %tmp14 = zext i8 %arg9 to i32
  %tmp15 = add nsw nuw i32 %tmp13, %tmp14
  %tmp16 = icmp slt i32 %tmp15, 2
  ret i1 %tmp16
}
=>
define i1 @barney(i8 %arg, i8 %arg9) {
%bb:
  %tmp = sext i8 %arg to i32
  %0 = abs i32 %tmp, 1
  %tmp13 = shl nsw nuw i32 %0, 1
  %tmp14 = zext i8 %arg9 to i32
  %tmp15 = add nsw nuw i32 %tmp13, %tmp14
  %tmp16 = icmp ult i32 %tmp15, 2
  ret i1 %tmp16
}
Transformation seems to be correct!

Summary:
  1 correct transformations
  0 incorrect transformations
  0 Alive2 errors

The original assembly was:

        .text
        .file   "vc1_block-aarch64.c"
        .def     barney;
        .scl    2;
        .type   32;
        .endef
        .globl  barney                          // -- Begin function barney
        .p2align        2
barney:                                 // @barney
// %bb.0:                               // %bb
        sxtb    w8, w0
        cmp     w8, #0                          // =0
        cneg    w8, w8, mi
        lsl     w8, w8, #1
        add     w8, w8, w1, uxtb
        cmp     w8, #2                          // =2
        cset    w0, lt
        ret
                                        // -- End function

and new one is

        .text
        .file   "vc1_block-aarch64.c"
        .def     barney;
        .scl    2;
        .type   32;
        .endef
        .globl  barney                          // -- Begin function barney
        .p2align        2
barney:                                 // @barney
// %bb.0:                               // %bb
        sxtb    w8, w0
        cmp     w8, #0                          // =0
        cneg    w8, w8, mi
        lsl     w8, w8, #1
        add     w8, w8, w1, uxtb
        cmp     w8, #2                          // =2
        cset    w0, lo
        ret
                                        // -- End function

with diff being

$ diff old.s new.s 
17c17
<       cset    w0, lt
---
>       cset    w0, lo

[mstorsjo]

In D87188#2445414, @lebedev.ri wrote:

@mstorsjo please can you be more specific what kind of tests are starting to fail?
Do those tests just check that the code compiled into an identical assembly?

No, it's video/audio decoding tests, and after that change specific reference input samples produce a different output hash than before.

I can retry the change (I see that the patch is recently rebased and hopefully still should apply on the latest main version) soon and see if I can pinpoint what's going wrong any closer than before.

[lebedev.ri]

Partial rebase (without updating test coverage)

[spatel]

In D87188#2445506, @lebedev.ri wrote:

Partial rebase (without updating test coverage)

Thanks for reducing!
If I'm seeing it correctly, the codegen looks fine - the difference is in the IR icmp predicate changing from slt to ult, and that diff appears to be correct independent of whether or not we use the abs intrinsic:
https://alive2.llvm.org/ce/z/VDDqBj

So either the source/test has an incorrect expectation and/or something outside of this function is wrong?

[craig.topper]

In D87188#2446096, @spatel wrote:

In D87188#2445506, @lebedev.ri wrote:

Partial rebase (without updating test coverage)

Thanks for reducing!
If I'm seeing it correctly, the codegen looks fine - the difference is in the IR icmp predicate changing from slt to ult, and that diff appears to be correct independent of whether or not we use the abs intrinsic:
https://alive2.llvm.org/ce/z/VDDqBj

So either the source/test has an incorrect expectation and/or something outside of this function is wrong?

It's also correct without the nsw/nuw flags since the inputs are i8 and extended to i32 it can't see i32 INT_MIN.

[lebedev.ri]

In D87188#2447025, @craig.topper wrote:

In D87188#2446096, @spatel wrote:

In D87188#2445506, @lebedev.ri wrote:

Partial rebase (without updating test coverage)

Thanks for reducing!
If I'm seeing it correctly, the codegen looks fine - the difference is in the IR icmp predicate changing from slt to ult, and that diff appears to be correct independent of whether or not we use the abs intrinsic:
https://alive2.llvm.org/ce/z/VDDqBj

So either the source/test has an incorrect expectation and/or something outside of this function is wrong?

It's also correct without the nsw/nuw flags since the inputs are i8 and extended to i32 it can't see i32 INT_MIN.

Just to be sure, i just run the entire compilation of vc1_block-aarch64.c through alive2, and as far as i can tell, it did not report any IR-level miscompilations.
So either the original code has bugs/UB's/whatever, or this is an AArch64 backend bug (cc @t.p.northover), or the IR problem is in a place alive2 can't find.

[mstorsjo]

In D87188#2447958, @lebedev.ri wrote:

Just to be sure, i just run the entire compilation of vc1_block-aarch64.c through alive2, and as far as i can tell, it did not report any IR-level miscompilations.
So either the original code has bugs/UB's/whatever, or this is an AArch64 backend bug (cc @t.p.northover), or the IR problem is in a place alive2 can't find.

FWIW, the testcase does run without any remarks in ubsan at least...

I retried the issue now, and I've reduced it down to one standalone function that causes the errors. https://martin.st/temp/vc1_block-p-block2.c is this function separated into a standalone translation unit - that I can run in the test framework. Unfortunately, the rather small difference further up in the optimization chain cascades into quite a lot of differences at the end, and I don't know really where to go from there to pinpoint the issue.

[mstorsjo]

FWIW, the issue is reproducible for an aarch64-linux-gnu target as well. If it would help someone, I could make a prepackaged build for that target, with object files + this single source function that breaks it + sample input files to run it with.

[mstorsjo]

(Also, for studying the effect of this one, on an IR level, the difference is already present in the output of -S -emit-llvm from clang, unless using -Xclang -disable-llvm-passes, but I'm sure you already took that into account.)

[lebedev.ri]

@mstorsjo i've bothered @dmajor to give this a try on some of mozilla's CI, and unfortunately it came back green..
I don't recall if i can reproduce it locally (on vanilla test suite, i'll recheck),
but right now it would seem that you are the only one who can reproduce this :/

Were you able to make any progress on a somewhat more actionable reproducer?

What would be really helpful is a standalone source that can be compiled and run (here by be locally, on linux x86_64)
that produces different result with/without this change.

[mstorsjo]

In D87188#2461497, @lebedev.ri wrote:

@mstorsjo i've bothered @dmajor to give this a try on some of mozilla's CI, and unfortunately it came back green..
I don't recall if i can reproduce it locally (on vanilla test suite, i'll recheck),
but right now it would seem that you are the only one who can reproduce this :/

Were you able to make any progress on a somewhat more actionable reproducer?

What would be really helpful is a standalone source that can be compiled and run (here by be locally, on linux x86_64)
that produces different result with/without this change.

IIRC I'm only able to reproduce this for aarch64 (and possibly arm) targets unfortunately. I can make a kind of standalone testcase with one single file built from source, linked and executed along with a bigger piece of code (either from source or prebuilt object files), but it'd be for aarch64-linux (or aarch64-darwin if that helps - I haven't tried reproducing it there but I'd presume it behaves the same as I noticed the bug first on aarch64 windows).

[mstorsjo]

In D87188#2461510, @mstorsjo wrote:

In D87188#2461497, @lebedev.ri wrote:

@mstorsjo i've bothered @dmajor to give this a try on some of mozilla's CI, and unfortunately it came back green..
I don't recall if i can reproduce it locally (on vanilla test suite, i'll recheck),
but right now it would seem that you are the only one who can reproduce this :/

Were you able to make any progress on a somewhat more actionable reproducer?

What would be really helpful is a standalone source that can be compiled and run (here by be locally, on linux x86_64)
that produces different result with/without this change.

IIRC I'm only able to reproduce this for aarch64 (and possibly arm) targets unfortunately. I can make a kind of standalone testcase with one single file built from source, linked and executed along with a bigger piece of code (either from source or prebuilt object files), but it'd be for aarch64-linux (or aarch64-darwin if that helps - I haven't tried reproducing it there but I'd presume it behaves the same as I noticed the bug first on aarch64 windows).

Ok, here's a reproduction environment, requiring aarch64 linux (tested on ubuntu 18.04, but anything similar or newer should be fine, and AWS and other cloud providers makes it fairly easy to spin up such an instance) - with https://martin.st/temp/ffmpeg-repro.zip downloaded and unzipped:

$ gcc -c vc1_block-debug.c -o vc1_block-debug.o
$ gcc *.o -Wl,--start-group *.a -Wl,--end-group -o ffmpeg -lm -lpthread -lz
$ ./ffmpeg -v quiet -i SA00040.vc1 -f framecrc -
#software: Lavf58.65.100
#tb 0: 1/25
#media_type 0: video
#codec_id 0: rawvideo
#dimensions 0: 176x144
#sar 0: 1/1
0,          0,          0,        1,    38016, 0xa6f15db5
0,          1,          1,        1,    38016, 0xa6f15db5
0,          2,          2,        1,    38016, 0xa6f15db5
0,          4,          4,        1,    38016, 0x5c4ef0e7
0,          5,          5,        1,    38016, 0x53a42d1d
0,          6,          6,        1,    38016, 0x68f7d89e
0,          7,          7,        1,    38016, 0xc15f4368
0,          8,          8,        1,    38016, 0xc15f4368
0,          9,          9,        1,    38016, 0xd1bd47a8
0,         10,         10,        1,    38016, 0xd1bd47a8
0,         11,         11,        1,    38016, 0xe1e821ca
0,         12,         12,        1,    38016, 0xe1e821ca
0,         13,         13,        1,    38016, 0xe1e821ca
0,         14,         14,        1,    38016, 0xe1e821ca
0,         15,         15,        1,    38016, 0xe1e821ca
$ clang -c vc1_block-debug.c -o vc1_block-debug.o -O2 # Recompile the problematic function with clang with this patch included
$ gcc *.o -Wl,--start-group *.a -Wl,--end-group -o ffmpeg -lm -lpthread -lz
$ ./ffmpeg -v quiet -i SA00040.vc1 -f framecrc -
#software: Lavf58.65.100
#tb 0: 1/25
#media_type 0: video
#codec_id 0: rawvideo
#dimensions 0: 176x144
#sar 0: 1/1
0,          0,          0,        1,    38016, 0xa6f15db5
0,          1,          1,        1,    38016, 0xa6f15db5
0,          2,          2,        1,    38016, 0xa6f15db5
0,          4,          4,        1,    38016, 0x5c4ef0e7
0,          5,          5,        1,    38016, 0x53a42d1d
0,          6,          6,        1,    38016, 0x68f7d89e
0,          7,          7,        1,    38016, 0xc15f4368
0,          8,          8,        1,    38016, 0xc15f4368
0,          9,          9,        1,    38016, 0xd1bd47a8
0,         10,         10,        1,    38016, 0xd1bd47a8
0,         11,         11,        1,    38016, 0x3bf00b9a # The hashes from here onwards differ
0,         12,         12,        1,    38016, 0x3bf00b9a
0,         13,         13,        1,    38016, 0x3bf00b9a
0,         14,         14,        1,    38016, 0x3bf00b9a
0,         15,         15,        1,    38016, 0x3bf00b9a

Alternative repro, fully from source:

$ git clone https://github.com/mstorsjo/ffmpeg.git
$ cd ffmpeg
$ git checkout origin/vc1-debug 
$ mkdir ../ffmpeg-build; cd ../ffmpeg-build
$ ../ffmpeg/configure --disable-everything --enable-decoder=vc1 --enable-demuxer=vc1 --enable-encoder=rawvideo --enable-muxer=framecrc --enable-protocol=file --enable-protocol=pipe --enable-parser=vc1 --enable-bsf=extract_extradata --samples=$(pwd)/../samples
$ make -j$(nproc)
$ make fate-rsync # Fetch reference test samples
$ make fate-vc1 # Succeeds
$ clang -c ../ffmpeg/libavcodec/vc1_block-debug.c -o libavcodec/vc1_block-debug.o -O3 -I../ffmpeg -I. # Recompile the problematic function with clang with this patch included
$ make fate-vc1 # Fails
TEST    vc1_sa00040
--- /home/ubuntu/code/ffmpeg/tests/ref/fate/vc1_sa00040	2020-12-18 12:04:27.216500325 +0000
+++ tests/data/fate/vc1_sa00040	2020-12-18 12:10:33.352940826 +0000
@@ -13,8 +13,8 @@
 0,          8,          8,        1,    38016, 0xc15f4368
 0,          9,          9,        1,    38016, 0xd1bd47a8
 0,         10,         10,        1,    38016, 0xd1bd47a8
-0,         11,         11,        1,    38016, 0xe1e821ca
-0,         12,         12,        1,    38016, 0xe1e821ca
-0,         13,         13,        1,    38016, 0xe1e821ca
-0,         14,         14,        1,    38016, 0xe1e821ca
-0,         15,         15,        1,    38016, 0xe1e821ca
+0,         11,         11,        1,    38016, 0x3bf00b9a
+0,         12,         12,        1,    38016, 0x3bf00b9a
+0,         13,         13,        1,    38016, 0x3bf00b9a
+0,         14,         14,        1,    38016, 0x3bf00b9a
+0,         15,         15,        1,    38016, 0x3bf00b9a
Test vc1_sa00040 failed. Look at tests/data/fate/vc1_sa00040.err for details.
/home/ubuntu/code/ffmpeg/tests/Makefile:255: recipe for target 'fate-vc1_sa00040' failed
make: *** [fate-vc1_sa00040] Error 1

[dmgreen]

Thanks for the reproducer. I verified that it does indeed fail with this patch.

It seems to be doing this as a knock-on effect: https://godbolt.org/z/Y4z3je, which does not verify: https://alive2.llvm.org/ce/z/PN7Rv5 ?

[lebedev.ri]

In D87188#2463285, @dmgreen wrote:

Thanks for the reproducer. I verified that it does indeed fail with this patch.

It seems to be doing this as a knock-on effect: https://godbolt.org/z/Y4z3je, which does not verify: https://alive2.llvm.org/ce/z/PN7Rv5 ?

@dmgreen THANK YOU!
That was sufficient information for me, the actual miscompiling fold is D87197.

[dmgreen]

Yeah. The reproducer seems to work OK with a patch something like this:

diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp
index 35c21a0..c517286 100644                                                                     
--- a/llvm/lib/Analysis/InstructionSimplify.cpp                                                   
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp                                                   
@@ -4020,11 +4020,11 @@ static Value *simplifySelectWithICmpCond(Value *CondVal, Value *TrueVal,  
                                                                                                  
     // X == 0 ? abs(X) : -abs(X) --> -abs(X)                                                     
     // X == 0 ? -abs(X) : abs(X) --> abs(X)                                                      
-    if (match(TrueVal, m_Intrinsic<Intrinsic::abs>(m_Value(X))) &&                               
-        match(FalseVal, m_Neg(m_Intrinsic<Intrinsic::abs>(m_Specific(X)))))                      
+    if (match(TrueVal, m_Intrinsic<Intrinsic::abs>(m_Specific(CmpLHS))) &&                       
+        match(FalseVal, m_Neg(m_Intrinsic<Intrinsic::abs>(m_Specific(CmpLHS)))))                 
       return FalseVal;                                                                           
-    if (match(TrueVal, m_Neg(m_Intrinsic<Intrinsic::abs>(m_Value(X)))) &&                        
-        match(FalseVal, m_Intrinsic<Intrinsic::abs>(m_Specific(X))))                             
+    if (match(TrueVal, m_Neg(m_Intrinsic<Intrinsic::abs>(m_Specific(CmpLHS)))) &&                
+        match(FalseVal, m_Intrinsic<Intrinsic::abs>(m_Specific(CmpLHS))))                        
       return FalseVal;                                                                           
   }

(I must admit, was fully expecting this to be something wrong in the AArch64 backend. I'll leave that fix to you if you are happy to add tests and whatnot.)

[lebedev.ri]

In D87188#2463447, @dmgreen wrote:

Yeah. The reproducer seems to work OK with a patch something like this:

diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp
index 35c21a0..c517286 100644                                                                     
--- a/llvm/lib/Analysis/InstructionSimplify.cpp                                                   
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp                                                   
@@ -4020,11 +4020,11 @@ static Value *simplifySelectWithICmpCond(Value *CondVal, Value *TrueVal,  
                                                                                                  
     // X == 0 ? abs(X) : -abs(X) --> -abs(X)                                                     
     // X == 0 ? -abs(X) : abs(X) --> abs(X)                                                      
-    if (match(TrueVal, m_Intrinsic<Intrinsic::abs>(m_Value(X))) &&                               
-        match(FalseVal, m_Neg(m_Intrinsic<Intrinsic::abs>(m_Specific(X)))))                      
+    if (match(TrueVal, m_Intrinsic<Intrinsic::abs>(m_Specific(CmpLHS))) &&                       
+        match(FalseVal, m_Neg(m_Intrinsic<Intrinsic::abs>(m_Specific(CmpLHS)))))                 
       return FalseVal;                                                                           
-    if (match(TrueVal, m_Neg(m_Intrinsic<Intrinsic::abs>(m_Value(X)))) &&                        
-        match(FalseVal, m_Intrinsic<Intrinsic::abs>(m_Specific(X))))                             
+    if (match(TrueVal, m_Neg(m_Intrinsic<Intrinsic::abs>(m_Specific(CmpLHS)))) &&                
+        match(FalseVal, m_Intrinsic<Intrinsic::abs>(m_Specific(CmpLHS))))                        
       return FalseVal;                                                                           
   }

Indeed, that is what i have already committed locally and will push in a sec.

(I must admit, was fully expecting this to be something wrong in the AArch64 backend. I'll leave that fix to you if you are happy to add tests and whatnot.)

Yeah, i also was almost convinced it was :)

[lebedev.ri]

Once again, thank you @mstorsjo and @dmgreen!

[mstorsjo]

In D87188#2463566, @lebedev.ri wrote:

Once again, thank you @mstorsjo and @dmgreen!

Awesome, thanks guys!

I'll let you know tomorrow in the unlikely case if this still caused some other regressions as well (or possibly later, if my nightly build ends up broken for other reasons).

[mstorsjo]

In D87188#2463733, @mstorsjo wrote:

In D87188#2463566, @lebedev.ri wrote:

Once again, thank you @mstorsjo and @dmgreen!

Awesome, thanks guys!

I'll let you know tomorrow in the unlikely case if this still caused some other regressions as well (or possibly later, if my nightly build ends up broken for other reasons).

My tests ran successfully with a version with this applied, so the case can be considered closed now.

[nlopes]

This patch regressed the following test of Transforms/InstCombine/abs-1.ll:
(need to drop NSW in this case).

define i8 @nabs_canonical_3(i8 %x) {
%0:
  %cmp = icmp slt i8 %x, 0
  %neg = sub nsw i8 0, %x
  %abs = select i1 %cmp, i8 %x, i8 %neg
  ret i8 %abs
}
=>
define i8 @nabs_canonical_3(i8 %x) {
%0:
  %1 = abs i8 %x, 1
  %abs = sub nsw i8 0, %1
  ret i8 %abs
}
Transformation doesn't verify!
ERROR: Target is more poisonous than source

Example:
i8 %x = #x80 (128, -128)

Source:
i1 %cmp = #x1 (1)
i8 %neg = poison
i8 %abs = #x80 (128, -128)

Target:
i8 %1 = poison
i8 %abs = poison
Source value: #x80 (128, -128)
Target value: poison

(same bug occurs with @nabs_nabs_x01 in Transforms/InstCombine/abs_abs.ll)

[thakis]

Heads up: Breaks a test for us: https://bugs.chromium.org/p/chromium/issues/detail?id=1161542

(No reduced repro yet, might be UB, just fyi at this point.)

[lebedev.ri]

In D87188#2470392, @thakis wrote:

Heads up: Breaks a test for us: https://bugs.chromium.org/p/chromium/issues/detail?id=1161542

(No reduced repro yet, might be UB, just fyi at this point.)

Thanks for headsup. For now i'll deal with the problem @nlopes pointed out above in a bit..

[lebedev.ri]

In D87188#2467915, @nlopes wrote:

This patch regressed the following test of Transforms/InstCombine/abs-1.ll:
(need to drop NSW in this case).

define i8 @nabs_canonical_3(i8 %x) {
%0:
  %cmp = icmp slt i8 %x, 0
  %neg = sub nsw i8 0, %x
  %abs = select i1 %cmp, i8 %x, i8 %neg
  ret i8 %abs
}
=>
define i8 @nabs_canonical_3(i8 %x) {
%0:
  %1 = abs i8 %x, 1
  %abs = sub nsw i8 0, %1
  ret i8 %abs
}
Transformation doesn't verify!
ERROR: Target is more poisonous than source

Example:
i8 %x = #x80 (128, -128)

Source:
i1 %cmp = #x1 (1)
i8 %neg = poison
i8 %abs = #x80 (128, -128)

Target:
i8 %1 = poison
i8 %abs = poison
Source value: #x80 (128, -128)
Target value: poison

(same bug occurs with @nabs_nabs_x01 in Transforms/InstCombine/abs_abs.ll)

Thanks, fixed in rGf8079355c604fead0f8538548bd7eb51fcc81e31.

[thakis]

In D87188#2470401, @lebedev.ri wrote:

In D87188#2470392, @thakis wrote:

Heads up: Breaks a test for us: https://bugs.chromium.org/p/chromium/issues/detail?id=1161542

(No reduced repro yet, might be UB, just fyi at this point.)

Thanks for headsup. For now i'll deal with the problem @nlopes pointed out above in a bit..

Just to follow up, this ended up being UB on our end (fix: https://android-review.googlesource.com/c/platform/external/perfetto/+/1535483)

[nlopes]

In D87188#2476230, @thakis wrote:

In D87188#2470401, @lebedev.ri wrote:

In D87188#2470392, @thakis wrote:

Heads up: Breaks a test for us: https://bugs.chromium.org/p/chromium/issues/detail?id=1161542

(No reduced repro yet, might be UB, just fyi at this point.)

Thanks for headsup. For now i'll deal with the problem @nlopes pointed out above in a bit..

Just to follow up, this ended up being UB on our end (fix: https://android-review.googlesource.com/c/platform/external/perfetto/+/1535483)

Nice! 😀 Thanks for the update.

clang/test/CodeGen/builtins-wasm.c

u8x16 sub_saturate_u_i8x16(u8x16 x, u8x16 y) {
   return __builtin_wasm_sub_saturate_u_i8x16(x, y);
   // WEBASSEMBLY: call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(
   // WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i8x16 abs_i8x16(i8x16 v) {
   return __builtin_wasm_abs_i8x16(v);
-  // WEBASSEMBLY: %neg = sub <16 x i8> zeroinitializer, %v
-  // WEBASSEMBLY: %abscond = icmp slt <16 x i8> %v, zeroinitializer
-  // WEBASSEMBLY: %abs = select <16 x i1> %abscond, <16 x i8> %neg, <16 x i8> %v
-  // WEBASSEMBLY: ret <16 x i8> %abs
+  // WEBASSEMBLY: call <16 x i8> @llvm.abs.v16i8(<16 x i8> %v, i1 false)
+  // WEBASSEMBLY-NEXT: ret
 }
 
 i16x8 abs_i16x8(i16x8 v) {
   return __builtin_wasm_abs_i16x8(v);
-  // WEBASSEMBLY: %neg = sub <8 x i16> zeroinitializer, %v
-  // WEBASSEMBLY: %abscond = icmp slt <8 x i16> %v, zeroinitializer
-  // WEBASSEMBLY: %abs = select <8 x i1> %abscond, <8 x i16> %neg, <8 x i16> %v
-  // WEBASSEMBLY: ret <8 x i16> %abs
+  // WEBASSEMBLY: call <8 x i16> @llvm.abs.v8i16(<8 x i16> %v, i1 false)
+  // WEBASSEMBLY-NEXT: ret
 }
 
 i32x4 abs_i32x4(i32x4 v) {
   return __builtin_wasm_abs_i32x4(v);
-  // WEBASSEMBLY: %neg = sub <4 x i32> zeroinitializer, %v
-  // WEBASSEMBLY: %abscond = icmp slt <4 x i32> %v, zeroinitializer
-  // WEBASSEMBLY: %abs = select <4 x i1> %abscond, <4 x i32> %neg, <4 x i32> %v
-  // WEBASSEMBLY: ret <4 x i32> %abs
+  // WEBASSEMBLY: call <4 x i32> @llvm.abs.v4i32(<4 x i32> %v, i1 false)
+  // WEBASSEMBLY-NEXT: ret
 }
 
 i8x16 min_s_i8x16(i8x16 x, i8x16 y) {
   return __builtin_wasm_min_s_i8x16(x, y);
   // WEBASSEMBLY: %0 = icmp slt <16 x i8> %x, %y
   // WEBASSEMBLY-NEXT: %1 = select <16 x i1> %0, <16 x i8> %x, <16 x i8> %y
   // WEBASSEMBLY-NEXT: ret <16 x i8> %1
 }

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

static Instruction *canonicalizeMinMaxWithConstant(SelectInst &Sel,
   // If we are swapping the select operands, swap the metadata too.
   assert(Sel.getTrueValue() == RHS && Sel.getFalseValue() == LHS &&
          "Unexpected results from matchSelectPattern");
   Sel.swapValues();
   Sel.swapProfMetadata();
   return &Sel;
 }
 
-/// There are many select variants for each of ABS/NABS.
-/// In matchSelectPattern(), there are different compare constants, compare
-/// predicates/operands and select operands.
-/// In isKnownNegation(), there are different formats of negated operands.
-/// Canonicalize all these variants to 1 pattern.
-/// This makes CSE more likely.
+/// Canonicalize select-based abs/nabs to llvm.abs() intrinsic.
 static Instruction *canonicalizeAbsNabs(SelectInst &Sel, ICmpInst &Cmp,
                                         InstCombinerImpl &IC) {
   if (!Cmp.hasOneUse() || !isa<Constant>(Cmp.getOperand(1)))
     return nullptr;
 
-  // Choose a sign-bit check for the compare (likely simpler for codegen).
-  // ABS:  (X <s 0) ? -X : X
-  // NABS: (X <s 0) ? X : -X
   Value *LHS, *RHS;
   SelectPatternFlavor SPF = matchSelectPattern(&Sel, LHS, RHS).Flavor;
   if (SPF != SelectPatternFlavor::SPF_ABS &&
       SPF != SelectPatternFlavor::SPF_NABS)
     return nullptr;
 
-  Value *TVal = Sel.getTrueValue();
-  Value *FVal = Sel.getFalseValue();
-  assert(isKnownNegation(TVal, FVal) &&
-         "Unexpected result from matchSelectPattern");
-
-  // The compare may use the negated abs()/nabs() operand, or it may use
-  // negation in non-canonical form such as: sub A, B.
-  bool CmpUsesNegatedOp = match(Cmp.getOperand(0), m_Neg(m_Specific(TVal))) ||
-                          match(Cmp.getOperand(0), m_Neg(m_Specific(FVal)));
-
-  bool CmpCanonicalized = !CmpUsesNegatedOp &&
-                          match(Cmp.getOperand(1), m_ZeroInt()) &&
-                          Cmp.getPredicate() == ICmpInst::ICMP_SLT;
-  bool RHSCanonicalized = match(RHS, m_Neg(m_Specific(LHS)));
-
-  // Is this already canonical?
-  if (CmpCanonicalized && RHSCanonicalized)
-    return nullptr;
-
-  // If RHS is not canonical but is used by other instructions, don't
-  // canonicalize it and potentially increase the instruction count.
-  if (!RHSCanonicalized)
-    if (!(RHS->hasOneUse() || (RHS->hasNUses(2) && CmpUsesNegatedOp)))
-      return nullptr;
-
-  // Create the canonical compare: icmp slt LHS 0.
-  if (!CmpCanonicalized) {
-    Cmp.setPredicate(ICmpInst::ICMP_SLT);
-    Cmp.setOperand(1, ConstantInt::getNullValue(Cmp.getOperand(0)->getType()));
-    if (CmpUsesNegatedOp)
-      Cmp.setOperand(0, LHS);
-  }
-
-  // Create the canonical RHS: RHS = sub (0, LHS).
-  if (!RHSCanonicalized) {
-    assert(RHS->hasOneUse() && "RHS use number is not right");
-    RHS = IC.Builder.CreateNeg(LHS);
-    if (TVal == LHS) {
-      // Replace false value.
-      IC.replaceOperand(Sel, 2, RHS);
-      FVal = RHS;
-    } else {
-      // Replace true value.
-      IC.replaceOperand(Sel, 1, RHS);
-      TVal = RHS;
-    }
-  }
+  bool IntMinIsPoison = match(RHS, m_NSWNeg(m_Specific(LHS)));
+  Constant *IntMinIsPoisonC =
+      ConstantInt::get(Type::getInt1Ty(Sel.getContext()), IntMinIsPoison);
+  Instruction *Abs =
+      IC.Builder.CreateBinaryIntrinsic(Intrinsic::abs, LHS, IntMinIsPoisonC);
+
+  if (SPF == SelectPatternFlavor::SPF_NABS)
+    return IntMinIsPoison ? BinaryOperator::CreateNSWNeg(Abs)
+                          : BinaryOperator::CreateNeg(Abs);
 
-  // If the select operands do not change, we're done.
-  if (SPF == SelectPatternFlavor::SPF_NABS) {
-    if (TVal == LHS)
-      return &Sel;
-    assert(FVal == LHS && "Unexpected results from matchSelectPattern");
-  } else {
-    if (FVal == LHS)
-      return &Sel;
-    assert(TVal == LHS && "Unexpected results from matchSelectPattern");
-  }
-
-  // We are swapping the select operands, so swap the metadata too.
-  Sel.swapValues();
-  Sel.swapProfMetadata();
-  return &Sel;
+  return IC.replaceInstUsesWith(Sel, Abs);
 }
 
 /// If we have a select with an equality comparison, then we know the value in
 /// one of the arms of the select. See if substituting this value into an arm
 /// and simplifying the result yields the same value as the other arm.
 ///
 /// To make this transform safe, we must drop poison-generating flags
 /// (nsw, etc) if we simplified to a binop because the select may be guarding

llvm/test/Transforms/InstCombine/abs-1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 
 declare i32 @abs(i32)
 declare i64 @labs(i64)
 declare i64 @llabs(i64)
 
 ; Test that the abs library call simplifier works correctly.
 ; abs(x) -> x <s 0 ? -x : x.
 
 define i32 @test_abs(i32 %x) {
 ; CHECK-LABEL: @test_abs(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[NEG]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %ret = call i32 @abs(i32 %x)
   ret i32 %ret
 }
 
 define i64 @test_labs(i64 %x) {
 ; CHECK-LABEL: @test_labs(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i64 [[X:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i64 0, [[X]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i64 [[NEG]], i64 [[X]]
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.abs.i64(i64 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i64 [[TMP1]]
 ;
   %ret = call i64 @labs(i64 %x)
   ret i64 %ret
 }
 
 define i64 @test_llabs(i64 %x) {
 ; CHECK-LABEL: @test_llabs(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i64 [[X:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i64 0, [[X]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i64 [[NEG]], i64 [[X]]
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.abs.i64(i64 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i64 [[TMP1]]
 ;
   %ret = call i64 @llabs(i64 %x)
   ret i64 %ret
 }
 
 ; We have a canonical form of abs to make CSE easier.
 
 define i8 @abs_canonical_1(i8 %x) {
 ; CHECK-LABEL: @abs_canonical_1(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i8 [[NEG]], i8 [[X]]
-; CHECK-NEXT:    ret i8 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %cmp = icmp sgt i8 %x, 0
   %neg = sub i8 0, %x
   %abs = select i1 %cmp, i8 %x, i8 %neg
   ret i8 %abs
 }
 
 ; Vectors should work too.
 
 define <2 x i8> @abs_canonical_2(<2 x i8> %x) {
 ; CHECK-LABEL: @abs_canonical_2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[NEG]], <2 x i8> [[X]]
-; CHECK-NEXT:    ret <2 x i8> [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.abs.v2i8(<2 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
 ;
   %cmp = icmp sgt <2 x i8> %x, <i8 -1, i8 -1>
   %neg = sub <2 x i8> zeroinitializer, %x
   %abs = select <2 x i1> %cmp, <2 x i8> %x, <2 x i8> %neg
   ret <2 x i8> %abs
 }
 
 ; Even if a constant has undef elements.
 
 define <2 x i8> @abs_canonical_2_vec_undef_elts(<2 x i8> %x) {
 ; CHECK-LABEL: @abs_canonical_2_vec_undef_elts(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[NEG]], <2 x i8> [[X]]
-; CHECK-NEXT:    ret <2 x i8> [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.abs.v2i8(<2 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
 ;
   %cmp = icmp sgt <2 x i8> %x, <i8 undef, i8 -1>
   %neg = sub <2 x i8> zeroinitializer, %x
   %abs = select <2 x i1> %cmp, <2 x i8> %x, <2 x i8> %neg
   ret <2 x i8> %abs
 }
 
 ; NSW should not change.
 
 define i8 @abs_canonical_3(i8 %x) {
 ; CHECK-LABEL: @abs_canonical_3(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i8 0, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i8 [[NEG]], i8 [[X]]
-; CHECK-NEXT:    ret i8 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %cmp = icmp slt i8 %x, 0
   %neg = sub nsw i8 0, %x
   %abs = select i1 %cmp, i8 %neg, i8 %x
   ret i8 %abs
 }
 
 define i8 @abs_canonical_4(i8 %x) {
 ; CHECK-LABEL: @abs_canonical_4(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i8 [[NEG]], i8 [[X]]
-; CHECK-NEXT:    ret i8 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %cmp = icmp slt i8 %x, 1
   %neg = sub i8 0, %x
   %abs = select i1 %cmp, i8 %neg, i8 %x
   ret i8 %abs
 }
 
 define i32 @abs_canonical_5(i8 %x) {
 ; CHECK-LABEL: @abs_canonical_5(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[CONV:%.*]] = sext i8 [[X]] to i32
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i32 0, [[CONV]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[NEG]], i32 [[CONV]]
-; CHECK-NEXT:    ret i32 [[ABS]]
+; CHECK-NEXT:    [[CONV:%.*]] = sext i8 [[X:%.*]] to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[CONV]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i8 %x, 0
   %conv = sext i8 %x to i32
   %neg = sub i32 0, %conv
   %abs = select i1 %cmp, i32 %conv, i32 %neg
   ret i32 %abs
 }
 
 define i32 @abs_canonical_6(i32 %a, i32 %b) {
 ; CHECK-LABEL: @abs_canonical_6(
 ; CHECK-NEXT:    [[T1:%.*]] = sub i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[T1]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[T1]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[TMP1]], i32 [[T1]]
-; CHECK-NEXT:    ret i32 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[T1]], i1 false)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %t1 = sub i32 %a, %b
   %cmp = icmp sgt i32 %t1, -1
   %t2 = sub i32 %b, %a
   %abs = select i1 %cmp, i32 %t1, i32 %t2
   ret i32 %abs
 }
 
 define <2 x i8> @abs_canonical_7(<2 x i8> %a, <2 x i8 > %b) {
 ; CHECK-LABEL: @abs_canonical_7(
 ; CHECK-NEXT:    [[T1:%.*]] = sub <2 x i8> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[T1]], zeroinitializer
-; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i8> zeroinitializer, [[T1]]
-; CHECK-NEXT:    [[ABS:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[TMP1]], <2 x i8> [[T1]]
-; CHECK-NEXT:    ret <2 x i8> [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.abs.v2i8(<2 x i8> [[T1]], i1 false)
+; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
 ;
 
   %t1 = sub <2 x i8> %a, %b
   %cmp = icmp sgt <2 x i8> %t1, <i8 -1, i8 -1>
   %t2 = sub <2 x i8> %b, %a
   %abs = select <2 x i1> %cmp, <2 x i8> %t1, <2 x i8> %t2
   ret <2 x i8> %abs
 }
 
 define i32 @abs_canonical_8(i32 %a) {
 ; CHECK-LABEL: @abs_canonical_8(
-; CHECK-NEXT:    [[T:%.*]] = sub i32 0, [[A:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[A]], 0
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[T]], i32 [[A]]
-; CHECK-NEXT:    ret i32 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A:%.*]], i1 false)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %t = sub i32 0, %a
   %cmp = icmp slt i32 %t, 0
   %abs = select i1 %cmp, i32 %a, i32 %t
   ret i32 %abs
 }
 
 define i32 @abs_canonical_9(i32 %a, i32 %b) {
 ; CHECK-LABEL: @abs_canonical_9(
 ; CHECK-NEXT:    [[T1:%.*]] = sub i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[T1]], -1
 ; CHECK-NEXT:    [[T2:%.*]] = sub i32 [[B]], [[A]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[T1]], i32 [[T2]]
-; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[ABS]], [[T2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[T1]], i1 false)
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[TMP1]], [[T2]]
 ; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %t1 = sub i32 %a, %b
   %cmp = icmp sgt i32 %t1, -1
   %t2 = sub i32 %b, %a
   %abs = select i1 %cmp, i32 %t1, i32 %t2
   %add = add i32 %abs, %t2 ; increase use count for %t2.
   ret i32 %add
 }
 
 define i32 @abs_canonical_10(i32 %a, i32 %b) {
 ; CHECK-LABEL: @abs_canonical_10(
 ; CHECK-NEXT:    [[T1:%.*]] = sub i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[T1]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[T1]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[TMP1]], i32 [[T1]]
-; CHECK-NEXT:    ret i32 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[T1]], i1 false)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %t2 = sub i32 %b, %a
   %t1 = sub i32 %a, %b
   %cmp = icmp sgt i32 %t1, -1
   %abs = select i1 %cmp, i32 %t1, i32 %t2
   ret i32 %abs
 }
 
 ; We have a canonical form of nabs to make CSE easier.
 
 define i8 @nabs_canonical_1(i8 %x) {
 ; CHECK-LABEL: @nabs_canonical_1(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i8 [[X]], i8 [[NEG]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[ABS:%.*]] = sub i8 0, [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[ABS]]
 ;
   %cmp = icmp sgt i8 %x, 0
   %neg = sub i8 0, %x
   %abs = select i1 %cmp, i8 %neg, i8 %x
   ret i8 %abs
 }
 
 ; Vectors should work too.
 
 define <2 x i8> @nabs_canonical_2(<2 x i8> %x) {
 ; CHECK-LABEL: @nabs_canonical_2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[X]], <2 x i8> [[NEG]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.abs.v2i8(<2 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[ABS:%.*]] = sub <2 x i8> zeroinitializer, [[TMP1]]
 ; CHECK-NEXT:    ret <2 x i8> [[ABS]]
 ;
   %cmp = icmp sgt <2 x i8> %x, <i8 -1, i8 -1>
   %neg = sub <2 x i8> zeroinitializer, %x
   %abs = select <2 x i1> %cmp, <2 x i8> %neg, <2 x i8> %x
   ret <2 x i8> %abs
 }
 
 ; Even if a constant has undef elements.
 
 define <2 x i8> @nabs_canonical_2_vec_undef_elts(<2 x i8> %x) {
 ; CHECK-LABEL: @nabs_canonical_2_vec_undef_elts(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[NEG:%.*]] = sub <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[X]], <2 x i8> [[NEG]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.abs.v2i8(<2 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[ABS:%.*]] = sub <2 x i8> zeroinitializer, [[TMP1]]
 ; CHECK-NEXT:    ret <2 x i8> [[ABS]]
 ;
   %cmp = icmp sgt <2 x i8> %x, <i8 -1, i8 undef>
   %neg = sub <2 x i8> zeroinitializer, %x
   %abs = select <2 x i1> %cmp, <2 x i8> %neg, <2 x i8> %x
   ret <2 x i8> %abs
 }
 
 ; NSW should not change.
 
 define i8 @nabs_canonical_3(i8 %x) {
 ; CHECK-LABEL: @nabs_canonical_3(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i8 0, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i8 [[X]], i8 [[NEG]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[ABS:%.*]] = sub nsw i8 0, [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[ABS]]
 ;
   %cmp = icmp slt i8 %x, 0
   %neg = sub nsw i8 0, %x
   %abs = select i1 %cmp, i8 %x, i8 %neg
   ret i8 %abs
 }
 
 define i8 @nabs_canonical_4(i8 %x) {
 ; CHECK-LABEL: @nabs_canonical_4(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i8 [[X]], i8 [[NEG]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[ABS:%.*]] = sub i8 0, [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[ABS]]
 ;
   %cmp = icmp slt i8 %x, 1
   %neg = sub i8 0, %x
   %abs = select i1 %cmp, i8 %x, i8 %neg
   ret i8 %abs
 }
 
 define i32 @nabs_canonical_5(i8 %x) {
 ; CHECK-LABEL: @nabs_canonical_5(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[CONV:%.*]] = sext i8 [[X]] to i32
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i32 0, [[CONV]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[CONV]], i32 [[NEG]]
+; CHECK-NEXT:    [[CONV:%.*]] = sext i8 [[X:%.*]] to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[CONV]], i1 true)
+; CHECK-NEXT:    [[ABS:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[ABS]]
 ;
   %cmp = icmp sgt i8 %x, 0
   %conv = sext i8 %x to i32
   %neg = sub i32 0, %conv
   %abs = select i1 %cmp, i32 %neg, i32 %conv
   ret i32 %abs
 }
 
 define i32 @nabs_canonical_6(i32 %a, i32 %b) {
 ; CHECK-LABEL: @nabs_canonical_6(
 ; CHECK-NEXT:    [[T1:%.*]] = sub i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[T1]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[T1]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[T1]], i32 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[T1]], i1 false)
+; CHECK-NEXT:    [[ABS:%.*]] = sub i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[ABS]]
 ;
   %t1 = sub i32 %a, %b
   %cmp = icmp sgt i32 %t1, -1
   %t2 = sub i32 %b, %a
   %abs = select i1 %cmp, i32 %t2, i32 %t1
   ret i32 %abs
 }
 
 define <2 x i8> @nabs_canonical_7(<2 x i8> %a, <2 x i8 > %b) {
 ; CHECK-LABEL: @nabs_canonical_7(
 ; CHECK-NEXT:    [[T1:%.*]] = sub <2 x i8> [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[T1]], zeroinitializer
-; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i8> zeroinitializer, [[T1]]
-; CHECK-NEXT:    [[ABS:%.*]] = select <2 x i1> [[CMP]], <2 x i8> [[T1]], <2 x i8> [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.abs.v2i8(<2 x i8> [[T1]], i1 false)
+; CHECK-NEXT:    [[ABS:%.*]] = sub <2 x i8> zeroinitializer, [[TMP1]]
 ; CHECK-NEXT:    ret <2 x i8> [[ABS]]
 ;
   %t1 = sub <2 x i8> %a, %b
   %cmp = icmp sgt <2 x i8> %t1, <i8 -1, i8 -1>
   %t2 = sub <2 x i8> %b, %a
   %abs = select <2 x i1> %cmp, <2 x i8> %t2, <2 x i8> %t1
   ret <2 x i8> %abs
 }
 
 define i32 @nabs_canonical_8(i32 %a) {
 ; CHECK-LABEL: @nabs_canonical_8(
-; CHECK-NEXT:    [[T:%.*]] = sub i32 0, [[A:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[A]], 0
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[A]], i32 [[T]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A:%.*]], i1 false)
+; CHECK-NEXT:    [[ABS:%.*]] = sub i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[ABS]]
 ;
   %t = sub i32 0, %a
   %cmp = icmp slt i32 %t, 0
   %abs = select i1 %cmp, i32 %t, i32 %a
   ret i32 %abs
 }
 
 define i32 @nabs_canonical_9(i32 %a, i32 %b) {
 ; CHECK-LABEL: @nabs_canonical_9(
 ; CHECK-NEXT:    [[T1:%.*]] = sub i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[T1]], -1
 ; CHECK-NEXT:    [[T2:%.*]] = sub i32 [[B]], [[A]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[T2]], i32 [[T1]]
-; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[T2]], [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[T1]], i1 false)
+; CHECK-NEXT:    [[ADD:%.*]] = sub i32 [[T2]], [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %t1 = sub i32 %a, %b
   %cmp = icmp sgt i32 %t1, -1
   %t2 = sub i32 %b, %a
   %abs = select i1 %cmp, i32 %t2, i32 %t1
   %add = add i32 %t2, %abs ; increase use count for %t2
   ret i32 %add
 }
 
 define i32 @nabs_canonical_10(i32 %a, i32 %b) {
 ; CHECK-LABEL: @nabs_canonical_10(
 ; CHECK-NEXT:    [[T1:%.*]] = sub i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[T1]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[T1]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP]], i32 [[T1]], i32 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[T1]], i1 false)
+; CHECK-NEXT:    [[ABS:%.*]] = sub i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[ABS]]
 ;
   %t2 = sub i32 %b, %a
   %t1 = sub i32 %a, %b
   %cmp = icmp slt i32 %t1, 1
   %abs = select i1 %cmp, i32 %t1, i32 %t2
   ret i32 %abs
 }
 
 ; The following 5 tests use a shift+add+xor to implement abs():
 ; B = ashr i8 A, 7  -- smear the sign bit.
 ; xor (add A, B), B -- add -1 and flip bits if negative
 
 define i8 @shifty_abs_commute0(i8 %x) {
 ; CHECK-LABEL: @shifty_abs_commute0(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = sub i8 0, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[TMP1]], i8 [[TMP2]], i8 [[X]]
-; CHECK-NEXT:    ret i8 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %signbit = ashr i8 %x, 7
   %add = add i8 %signbit, %x
   %abs = xor i8 %add, %signbit
   ret i8 %abs
 }
 
 define i8 @shifty_abs_commute0_nsw(i8 %x) {
 ; CHECK-LABEL: @shifty_abs_commute0_nsw(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = sub nsw i8 0, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[TMP1]], i8 [[TMP2]], i8 [[X]]
-; CHECK-NEXT:    ret i8 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %signbit = ashr i8 %x, 7
   %add = add nsw i8 %signbit, %x
   %abs = xor i8 %add, %signbit
   ret i8 %abs
 }
 
 ; The nuw flag creates a contradiction. If the shift produces all 1s, the only
 ; way for the add to not wrap is for %x to be 0, but then the shift couldn't
 ; have produced all 1s. We partially optimize this.
 define i8 @shifty_abs_commute0_nuw(i8 %x) {
 ; CHECK-LABEL: @shifty_abs_commute0_nuw(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i8 [[X:%.*]], 0
 ; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 0
 ; CHECK-NEXT:    ret i8 [[ABS]]
 ;
   %signbit = ashr i8 %x, 7
   %add = add nuw i8 %signbit, %x
   %abs = xor i8 %add, %signbit
   ret i8 %abs
 }
 
 define <2 x i8> @shifty_abs_commute1(<2 x i8> %x) {
 ; CHECK-LABEL: @shifty_abs_commute1(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[TMP2:%.*]] = sub <2 x i8> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[ABS:%.*]] = select <2 x i1> [[TMP1]], <2 x i8> [[TMP2]], <2 x i8> [[X]]
-; CHECK-NEXT:    ret <2 x i8> [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.abs.v2i8(<2 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
 ;
   %signbit = ashr <2 x i8> %x, <i8 7, i8 7>
   %add = add <2 x i8> %signbit, %x
   %abs = xor <2 x i8> %signbit, %add
   ret <2 x i8> %abs
 }
 
 define <2 x i8> @shifty_abs_commute2(<2 x i8> %x) {
 ; CHECK-LABEL: @shifty_abs_commute2(
 ; CHECK-NEXT:    [[Y:%.*]] = mul <2 x i8> [[X:%.*]], <i8 3, i8 3>
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i8> [[Y]], zeroinitializer
-; CHECK-NEXT:    [[TMP2:%.*]] = sub <2 x i8> zeroinitializer, [[Y]]
-; CHECK-NEXT:    [[ABS:%.*]] = select <2 x i1> [[TMP1]], <2 x i8> [[TMP2]], <2 x i8> [[Y]]
-; CHECK-NEXT:    ret <2 x i8> [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.abs.v2i8(<2 x i8> [[Y]], i1 false)
+; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
 ;
   %y = mul <2 x i8> %x, <i8 3, i8 3>   ; extra op to thwart complexity-based canonicalization
   %signbit = ashr <2 x i8> %y, <i8 7, i8 7>
   %add = add <2 x i8> %y, %signbit
   %abs = xor <2 x i8> %signbit, %add
   ret <2 x i8> %abs
 }
 
 define i8 @shifty_abs_commute3(i8 %x) {
 ; CHECK-LABEL: @shifty_abs_commute3(
 ; CHECK-NEXT:    [[Y:%.*]] = mul i8 [[X:%.*]], 3
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = sub i8 0, [[Y]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[TMP1]], i8 [[TMP2]], i8 [[Y]]
-; CHECK-NEXT:    ret i8 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[Y]], i1 false)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %y = mul i8 %x, 3                    ; extra op to thwart complexity-based canonicalization
   %signbit = ashr i8 %y, 7
   %add = add i8 %y, %signbit
   %abs = xor i8 %add, %signbit
   ret i8 %abs
 }
 
;
   ret i8 %abs
 }
 
 ; There's another way to make abs() using shift, xor, and subtract.
 ; PR36036 - https://bugs.llvm.org/show_bug.cgi?id=36036
 
 define i8 @shifty_sub(i8 %x) {
 ; CHECK-LABEL: @shifty_sub(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = sub i8 0, [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i8 [[TMP2]], i8 [[X]]
-; CHECK-NEXT:    ret i8 [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %sh = ashr i8 %x, 7
   %xor = xor i8 %x, %sh
   %r = sub i8 %xor, %sh
   ret i8 %r
 }
 
 define i8 @shifty_sub_nsw_commute(i8 %x) {
 ; CHECK-LABEL: @shifty_sub_nsw_commute(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = sub nsw i8 0, [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP1]], i8 [[TMP2]], i8 [[X]]
-; CHECK-NEXT:    ret i8 [[R]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %sh = ashr i8 %x, 7
   %xor = xor i8 %sh, %x
   %r = sub nsw i8 %xor, %sh
   ret i8 %r
 }
 
 define <4 x i32> @shifty_sub_nuw_vec_commute(<4 x i32> %x) {
;
   %sh = ashr i12 %x, 11
   %xor = xor i12 %x, %sh
   %r = sub nsw nuw i12 %xor, %sh
   ret i12 %r
 }
 
 define i8 @negate_abs(i8 %x) {
 ; CHECK-LABEL: @negate_abs(
-; CHECK-NEXT:    [[N:%.*]] = sub i8 0, [[X:%.*]]
-; CHECK-NEXT:    [[C:%.*]] = icmp slt i8 [[X]], 0
-; CHECK-NEXT:    [[S:%.*]] = select i1 [[C]], i8 [[X]], i8 [[N]]
-; CHECK-NEXT:    ret i8 [[S]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[R:%.*]] = sub i8 0, [[TMP1]]
+; CHECK-NEXT:    ret i8 [[R]]
 ;
   %n = sub i8 0, %x
   %c = icmp slt i8 %x, 0
   %s = select i1 %c, i8 %n, i8 %x
   %r = sub i8 0, %s
   ret i8 %r
 }
 
 define <2 x i8> @negate_nabs(<2 x i8> %x) {
 ; CHECK-LABEL: @negate_nabs(
-; CHECK-NEXT:    [[N:%.*]] = sub <2 x i8> zeroinitializer, [[X:%.*]]
-; CHECK-NEXT:    [[C:%.*]] = icmp slt <2 x i8> [[X]], zeroinitializer
-; CHECK-NEXT:    [[S:%.*]] = select <2 x i1> [[C]], <2 x i8> [[N]], <2 x i8> [[X]]
-; CHECK-NEXT:    ret <2 x i8> [[S]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i8> @llvm.abs.v2i8(<2 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT:    ret <2 x i8> [[TMP1]]
 ;
   %n = sub <2 x i8> zeroinitializer, %x
   %c = icmp slt <2 x i8> %x, zeroinitializer
   %s = select <2 x i1> %c, <2 x i8> %x, <2 x i8> %n
   %r = sub <2 x i8> zeroinitializer, %s
   ret <2 x i8> %r
 }
 
 define i1 @abs_must_be_positive(i32 %x) {
 ; CHECK-LABEL: @abs_must_be_positive(
 ; CHECK-NEXT:    ret i1 true
 ;
   %negx = sub nsw i32 0, %x
   %c = icmp sge i32 %x, 0
   %sel = select i1 %c, i32 %x, i32 %negx
   %c2 = icmp sge i32 %sel, 0
   ret i1 %c2
 }
 
 define i8 @abs_swapped(i8 %a) {
 ; CHECK-LABEL: @abs_swapped(
 ; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[A:%.*]]
 ; CHECK-NEXT:    call void @extra_use(i8 [[NEG]])
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i8 [[A]], 0
-; CHECK-NEXT:    [[M1:%.*]] = select i1 [[CMP1]], i8 [[NEG]], i8 [[A]]
-; CHECK-NEXT:    ret i8 [[M1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[A]], i1 false)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %neg = sub i8 0, %a
   call void @extra_use(i8 %neg)
   %cmp1 = icmp sgt i8 %a, 0
   %m1 = select i1 %cmp1, i8 %a, i8 %neg
   ret i8 %m1
 }
 
 define i8 @nabs_swapped(i8 %a) {
 ; CHECK-LABEL: @nabs_swapped(
 ; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[A:%.*]]
 ; CHECK-NEXT:    call void @extra_use(i8 [[NEG]])
-; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i8 [[A]], 0
-; CHECK-NEXT:    [[M2:%.*]] = select i1 [[CMP2]], i8 [[A]], i8 [[NEG]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[A]], i1 false)
+; CHECK-NEXT:    [[M2:%.*]] = sub i8 0, [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[M2]]
 ;
   %neg = sub i8 0, %a
   call void @extra_use(i8 %neg)
   %cmp2 = icmp sgt i8 %a, 0
   %m2 = select i1 %cmp2, i8 %neg, i8 %a
   ret i8 %m2
 }
 
 define i8 @abs_different_constants(i8 %a) {
 ; CHECK-LABEL: @abs_different_constants(
 ; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[A:%.*]]
 ; CHECK-NEXT:    call void @extra_use(i8 [[NEG]])
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i8 [[A]], 0
-; CHECK-NEXT:    [[M1:%.*]] = select i1 [[CMP1]], i8 [[NEG]], i8 [[A]]
-; CHECK-NEXT:    ret i8 [[M1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[A]], i1 false)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %neg = sub i8 0, %a
   call void @extra_use(i8 %neg)
   %cmp1 = icmp sgt i8 %a, -1
   %m1 = select i1 %cmp1, i8 %a, i8 %neg
   ret i8 %m1
 }
 
 define i8 @nabs_different_constants(i8 %a) {
 ; CHECK-LABEL: @nabs_different_constants(
 ; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[A:%.*]]
 ; CHECK-NEXT:    call void @extra_use(i8 [[NEG]])
-; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i8 [[A]], 0
-; CHECK-NEXT:    [[M2:%.*]] = select i1 [[CMP2]], i8 [[A]], i8 [[NEG]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[A]], i1 false)
+; CHECK-NEXT:    [[M2:%.*]] = sub i8 0, [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[M2]]
 ;
   %neg = sub i8 0, %a
   call void @extra_use(i8 %neg)
   %cmp2 = icmp sgt i8 %a, -1
   %m2 = select i1 %cmp2, i8 %neg, i8 %a
   ret i8 %m2
 }
 
 @g = external global i64
 
 ; PR45539 - https://bugs.llvm.org/show_bug.cgi?id=45539
 
 define i64 @infinite_loop_constant_expression_abs(i64 %arg) {
 ; CHECK-LABEL: @infinite_loop_constant_expression_abs(
 ; CHECK-NEXT:    [[T:%.*]] = sub i64 ptrtoint (i64* @g to i64), [[ARG:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = icmp slt i64 [[T]], 0
-; CHECK-NEXT:    [[T2:%.*]] = sub nsw i64 0, [[T]]
-; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T1]], i64 [[T2]], i64 [[T]]
-; CHECK-NEXT:    ret i64 [[T3]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.abs.i64(i64 [[T]], i1 true)
+; CHECK-NEXT:    ret i64 [[TMP1]]
 ;
   %t = sub i64 ptrtoint (i64* @g to i64), %arg
   %t1 = icmp slt i64 %t, 0
   %t2 = sub nsw i64 0, %t
   %t3 = select i1 %t1, i64 %t2, i64 %t
   ret i64 %t3
 }

llvm/test/Transforms/InstCombine/abs_abs.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @abs_abs_x01(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x01(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define <2 x i32> @abs_abs_x01_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @abs_abs_x01_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
   %sub = sub nsw <2 x i32> zeroinitializer, %x
   %cond = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %sub
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16
   ret <2 x i32> %cond18
 }
 
 define i32 @abs_abs_x02(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x02(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x03(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x03(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x04(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x04(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define <2 x i32> @abs_abs_x04_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @abs_abs_x04_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %cmp = icmp slt <2 x i32> %x, <i32 1, i32 1>
   %sub = sub nsw <2 x i32> zeroinitializer, %x
   %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16
   ret <2 x i32> %cond18
 }
 
 define i32 @abs_abs_x05(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x05(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x06(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x06(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x07(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x07(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x08(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x08(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x09(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x09(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x10(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x10(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x11(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x11(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x12(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x12(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x13(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x13(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x14(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x14(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x15(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x15(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_abs_x16(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x16(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 ; abs(abs(-x)) -> abs(-x) -> abs(x)
 define i32 @abs_abs_x17(i32 %x) {
 ; CHECK-LABEL: @abs_abs_x17(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X]], 0
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %sub = sub nsw i32 0, %x
   %cmp = icmp sgt i32 %sub, -1
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 ; abs(abs(x - y)) -> abs(x - y)
 define i32 @abs_abs_x18(i32 %x, i32 %y) {
 ; CHECK-LABEL: @abs_abs_x18(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[A]], 0
-; CHECK-NEXT:    [[NEGA:%.*]] = sub i32 0, [[A]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[NEGA]], i32 [[A]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %a = sub nsw i32 %x, %y
   %b = sub nsw i32 %y, %x
   %cmp = icmp sgt i32 %a, -1
   %cond = select i1 %cmp, i32 %a, i32 %b
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 ; abs(abs(-x)) -> abs(-x) -> abs(x)
 define <2 x i32> @abs_abs_x02_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @abs_abs_x02_vec(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %sub = sub nsw <2 x i32> zeroinitializer, %x
   %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16
   ret <2 x i32> %cond18
 }
 
 ; abs(abs(x - y)) -> abs(x - y)
 define <2 x i32> @abs_abs_x03_vec(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @abs_abs_x03_vec(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[A]], zeroinitializer
-; CHECK-NEXT:    [[NEGA:%.*]] = sub <2 x i32> zeroinitializer, [[A]]
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[NEGA]], <2 x i32> [[A]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[A]], i1 false)
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %a = sub nsw <2 x i32> %x, %y
   %b = sub nsw <2 x i32> %y, %x
   %cmp = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %b
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16
   ret <2 x i32> %cond18
 }
 
 define i32 @nabs_nabs_x01(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x01(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x02(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x02(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x03(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x03(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x04(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x04(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x05(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x05(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x06(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x06(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x07(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x07(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x08(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x08(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x09(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x09(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x10(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x10(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x11(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x11(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x12(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x12(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x13(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x13(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x14(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x14(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x15(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x15(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_nabs_x16(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x16(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 ; nabs(nabs(-x)) -> nabs(-x) -> nabs(x)
 define i32 @nabs_nabs_x17(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x17(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X]], 0
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %sub = sub nsw i32 0, %x
   %cmp = icmp sgt i32 %sub, -1
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub16, i32 %cond
   ret i32 %cond18
 }
 
 ; nabs(nabs(x - y)) -> nabs(x - y)
 define i32 @nabs_nabs_x18(i32 %x, i32 %y) {
 ; CHECK-LABEL: @nabs_nabs_x18(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[A]], 0
-; CHECK-NEXT:    [[NEGA:%.*]] = sub i32 0, [[A]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[A]], i32 [[NEGA]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %a = sub nsw i32 %x, %y
   %b = sub nsw i32 %y, %x
   %cmp = icmp sgt i32 %a, -1
   %cond = select i1 %cmp, i32 %b, i32 %a
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub16, i32 %cond
   ret i32 %cond18
 }
 
 ; nabs(nabs(-x)) -> nabs(-x) -> nabs(x)
 define <2 x i32> @nabs_nabs_x01_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @nabs_nabs_x01_vec(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[X]], <2 x i32> [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[COND:%.*]] = sub nsw <2 x i32> zeroinitializer, [[TMP1]]
 ; CHECK-NEXT:    ret <2 x i32> [[COND]]
 ;
   %sub = sub nsw <2 x i32> zeroinitializer, %x
   %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %sub
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %sub16, <2 x i32> %cond
   ret <2 x i32> %cond18
 }
 
 ; nabs(nabs(x - y)) -> nabs(x - y)
 define <2 x i32> @nabs_nabs_x02_vec(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @nabs_nabs_x02_vec(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[A]], zeroinitializer
-; CHECK-NEXT:    [[NEGA:%.*]] = sub <2 x i32> zeroinitializer, [[A]]
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[A]], <2 x i32> [[NEGA]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[A]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub <2 x i32> zeroinitializer, [[TMP1]]
+; CHECK-NEXT:    ret <2 x i32> [[COND18]]
 ;
   %a = sub nsw <2 x i32> %x, %y
   %b = sub nsw <2 x i32> %y, %x
   %cmp = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %a
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %sub16, <2 x i32> %cond
   ret <2 x i32> %cond18
 }
 
 define i32 @abs_nabs_x01(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x01(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x02(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x02(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x03(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x03(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x04(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x04(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x05(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x05(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x06(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x06(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x07(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x07(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x08(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x08(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x09(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x09(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x10(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x10(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x11(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x11(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x12(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x12(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x13(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x13(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x14(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x14(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x15(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x15(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @abs_nabs_x16(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x16(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 ; abs(nabs(-x)) -> abs(-x) -> abs(x)
 define i32 @abs_nabs_x17(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x17(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X]], 0
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %sub = sub nsw i32 0, %x
   %cmp = icmp sgt i32 %sub, -1
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 ; abs(nabs(x - y)) -> abs(x - y)
 define i32 @abs_nabs_x18(i32 %x, i32 %y) {
 ; CHECK-LABEL: @abs_nabs_x18(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[A]], 0
-; CHECK-NEXT:    [[NEGA:%.*]] = sub i32 0, [[A]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[NEGA]], i32 [[A]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %a = sub nsw i32 %x, %y
   %b = sub nsw i32 %y, %x
   %cmp = icmp sgt i32 %a, -1
   %cond = select i1 %cmp, i32 %b, i32 %a
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 ; abs(nabs(-x)) -> abs(-x) -> abs(x)
 define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @abs_nabs_x01_vec(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %sub = sub nsw <2 x i32> zeroinitializer, %x
   %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %sub
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16
   ret <2 x i32> %cond18
 }
 
 ; abs(nabs(x - y)) -> abs(x - y)
 define <2 x i32> @abs_nabs_x02_vec(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @abs_nabs_x02_vec(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[A]], zeroinitializer
-; CHECK-NEXT:    [[NEGA:%.*]] = sub <2 x i32> zeroinitializer, [[A]]
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[NEGA]], <2 x i32> [[A]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[A]], i1 false)
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %a = sub nsw <2 x i32> %x, %y
   %b = sub nsw <2 x i32> %y, %x
   %cmp = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> %b, <2 x i32> %a
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16
   ret <2 x i32> %cond18
 }
 
 define i32 @nabs_abs_x01(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x01(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB9]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x02(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x02(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB9]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, -1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x03(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x03(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB9]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x04(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x04(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB9]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x05(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x05(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB9]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x06(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x06(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB9]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp sgt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x07(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x07(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB9]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x08(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x08(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB9:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB9]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, 0
   %sub9 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub9, i32 %cond
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x09(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x09(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB16]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x10(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x10(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB16]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x11(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x11(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB16]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x12(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x12(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB16]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 0
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x13(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x13(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB16]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x14(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x14(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB16]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %x, i32 %sub
   %cmp1 = icmp slt i32 %cond, 1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x15(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x15(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB16]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 define i32 @nabs_abs_x16(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x16(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X]]
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB16]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp slt i32 %cond, 1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16
   ret i32 %cond18
 }
 
 ; nabs(abs(-x)) -> nabs(-x) -> nabs(x)
 define i32 @nabs_abs_x17(i32 %x) {
 ; CHECK-LABEL: @nabs_abs_x17(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X]], 0
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[SUB16]]
 ;
   %sub = sub nsw i32 0, %x
   %cmp = icmp sgt i32 %sub, -1
   %cond = select i1 %cmp, i32 %sub, i32 %x
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub16, i32 %cond
   ret i32 %cond18
 }
 
 ; nabs(abs(x - y)) -> nabs(x - y)
 define i32 @nabs_abs_x18(i32 %x, i32 %y) {
 ; CHECK-LABEL: @nabs_abs_x18(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[A]], 0
-; CHECK-NEXT:    [[NEGA:%.*]] = sub i32 0, [[A]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[CMP]], i32 [[A]], i32 [[NEGA]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %a = sub nsw i32 %x, %y
   %b = sub nsw i32 %y, %x
   %cmp = icmp sgt i32 %a, -1
   %cond = select i1 %cmp, i32 %a, i32 %b
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %sub16, i32 %cond
   ret i32 %cond18
 }
 
 ; nabs(abs(-x)) -> nabs(-x) -> nabs(x)
 define <2 x i32> @nabs_abs_x01_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @nabs_abs_x01_vec(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[X]], <2 x i32> [[SUB]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[SUB16:%.*]] = sub nsw <2 x i32> zeroinitializer, [[TMP1]]
+; CHECK-NEXT:    ret <2 x i32> [[SUB16]]
 ;
   %sub = sub nsw <2 x i32> zeroinitializer, %x
   %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %sub16, <2 x i32> %cond
   ret <2 x i32> %cond18
 }
 
 ; nabs(abs(x - y)) -> nabs(x - y)
 define <2 x i32> @nabs_abs_x02_vec(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @nabs_abs_x02_vec(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[A]], zeroinitializer
-; CHECK-NEXT:    [[NEGA:%.*]] = sub <2 x i32> zeroinitializer, [[A]]
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[A]], <2 x i32> [[NEGA]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[A]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub nsw <2 x i32> zeroinitializer, [[TMP1]]
+; CHECK-NEXT:    ret <2 x i32> [[COND18]]
 ;
   %a = sub nsw <2 x i32> %x, %y
   %b = sub nsw <2 x i32> %y, %x
   %cmp = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %b
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %sub16, <2 x i32> %cond
   ret <2 x i32> %cond18
 }

llvm/test/Transforms/InstCombine/call-callconv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 ; Verify that the non-default calling conv doesn't prevent the libcall simplification
 
 @.str = private unnamed_addr constant [4 x i8] c"abc\00", align 1
 
 define arm_aapcscc i32 @_abs(i32 %i) nounwind readnone {
 ; CHECK-LABEL: @_abs(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[I:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i32 0, [[I]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[NEG]], i32 [[I]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[I:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %call = tail call arm_aapcscc i32 @abs(i32 %i) nounwind readnone
   ret i32 %call
 }
 
 declare arm_aapcscc i32 @abs(i32) nounwind readnone
 
 define arm_aapcscc i32 @_labs(i32 %i) nounwind readnone {
 ; CHECK-LABEL: @_labs(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[I:%.*]], 0
-; CHECK-NEXT:    [[NEG:%.*]] = sub nsw i32 0, [[I]]
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[NEG]], i32 [[I]]
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[I:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %call = tail call arm_aapcscc i32 @labs(i32 %i) nounwind readnone
   ret i32 %call
 }
 
 declare arm_aapcscc i32 @labs(i32) nounwind readnone
 
 define arm_aapcscc i32 @_strlen1() {

llvm/test/Transforms/InstCombine/cttz-abs.ll

;
   %s = sub i64 0, %x
   %d = select i1 %c, i64 %s, i64 %x
   %r = tail call i64 @llvm.cttz.i64(i64 %d)
   ret i64 %r
 }
 
 define i32 @cttz_abs_multiuse(i32 %x) {
 ; CHECK-LABEL: @cttz_abs_multiuse(
-; CHECK-NEXT:    [[C:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[S:%.*]] = sub i32 0, [[X]]
-; CHECK-NEXT:    [[D:%.*]] = select i1 [[C]], i32 [[S]], i32 [[X]]
-; CHECK-NEXT:    call void @use_abs(i32 [[D]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    call void @use_abs(i32 [[TMP1]])
 ; CHECK-NEXT:    [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), [[RNG0]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %c = icmp slt i32 %x, 1
   %s = sub i32 0, %x
   %d = select i1 %c, i32 %s, i32 %x
   call void @use_abs(i32 %d)
   %r = tail call i32 @llvm.cttz.i32(i32 %d, i1 true)
   ret i32 %r
 }
 
 define i32 @cttz_nabs_multiuse(i32 %x) {
 ; CHECK-LABEL: @cttz_nabs_multiuse(
-; CHECK-NEXT:    [[C:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[S:%.*]] = sub i32 0, [[X]]
-; CHECK-NEXT:    [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[S]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[D:%.*]] = sub i32 0, [[TMP1]]
 ; CHECK-NEXT:    call void @use_abs(i32 [[D]])
 ; CHECK-NEXT:    [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), [[RNG0]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %c = icmp slt i32 %x, 1
   %s = sub i32 0, %x
   %d = select i1 %c, i32 %x, i32 %s
   call void @use_abs(i32 %d)

llvm/test/Transforms/InstCombine/icmp.ll

;
   ret <2 x i1> %v
 }
 
 define i32 @f5(i8 %a, i8 %b) {
 ; CHECK-LABEL: @f5(
 ; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[CONV3:%.*]] = zext i8 [[B:%.*]] to i32
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[CONV]], [[CONV3]]
-; CHECK-NEXT:    [[CMP4:%.*]] = icmp slt i32 [[SUB]], 0
-; CHECK-NEXT:    [[SUB7:%.*]] = sub nsw i32 0, [[SUB]]
-; CHECK-NEXT:    [[SUB7_SUB:%.*]] = select i1 [[CMP4]], i32 [[SUB7]], i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SUB7_SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[SUB]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %conv = zext i8 %a to i32
   %conv3 = zext i8 %b to i32
   %sub = sub nsw i32 %conv, %conv3
   %cmp4 = icmp slt i32 %sub, 0
   %sub7 = sub nsw i32 0, %sub
   %sub7.sub = select i1 %cmp4, i32 %sub7, i32 %sub
   ret i32 %sub7.sub
;
   %c = icmp sgt i8 %b2, %a2
   ret i1 %c
 }
 
 ; Make sure InstCombine doesn't try too hard to simplify the icmp and break the abs idiom
 define i32 @abs_preserve(i32 %x) {
 ; CHECK-LABEL: @abs_preserve(
 ; CHECK-NEXT:    [[A:%.*]] = shl nsw i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[C:%.*]] = icmp slt i32 [[A]], 0
-; CHECK-NEXT:    [[NEGA:%.*]] = sub i32 0, [[A]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[C]], i32 [[NEGA]], i32 [[A]]
-; CHECK-NEXT:    ret i32 [[ABS]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %a = mul nsw i32 %x, 2
   %c = icmp sge i32 %a, 0
   %nega = sub i32 0, %a
   %abs = select i1 %c, i32 %a, i32 %nega
   ret i32 %abs
 }
 
;
   %cast = ptrtoint <2 x i8*> %0 to <2 x i64>
   %res = icmp eq <2 x i64> %cast, zeroinitializer
   ret <2 x i1> %res
 }
 
 ; fold (icmp pred (sub (0, X)) C1) for vec type
 define <2 x i32> @Op1Negated_Vec(<2 x i32> %x) {
 ; CHECK-LABEL: @Op1Negated_Vec(
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X:%.*]]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer
-; CHECK-NEXT:    [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %sub = sub nsw <2 x i32> zeroinitializer, %x
   %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
   %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x
   ret <2 x i32> %cond
 }
 
 define i1 @signbit_bitcast_fpext(float %x) {

llvm/test/Transforms/InstCombine/max-of-nots.ll

;
   ret i32 %smax96
 }
 
  ; negative test case (i.e. can not simplify) : ABS(MIN(NOT x,y))
 define i32 @abs_of_min_of_not(i32 %x, i32 %y) {
 ; CHECK-LABEL: @abs_of_min_of_not(
 ; CHECK-NEXT:    [[XORD:%.*]] = xor i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[YADD:%.*]] = add i32 [[Y:%.*]], 2
-; CHECK-NEXT:    [[COND_I:%.*]] = icmp slt i32 [[YADD]], [[XORD]]
-; CHECK-NEXT:    [[MIN:%.*]] = select i1 [[COND_I]], i32 [[YADD]], i32 [[XORD]]
-; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[MIN]], 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 0, [[MIN]]
-; CHECK-NEXT:    [[ABS:%.*]] = select i1 [[CMP2]], i32 [[SUB]], i32 [[MIN]]
-; CHECK-NEXT:    ret i32 [[ABS]]
+; CHECK-NEXT:    [[COND_I_NOT:%.*]] = icmp slt i32 [[YADD]], [[XORD]]
+; CHECK-NEXT:    [[MIN:%.*]] = select i1 [[COND_I_NOT]], i32 [[YADD]], i32 [[XORD]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[MIN]], i1 false)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 
   %xord = xor i32 %x, -1
   %yadd = add i32 %y, 2
   %cond.i = icmp sge i32 %yadd, %xord
   %min = select i1 %cond.i, i32 %xord, i32 %yadd
   %cmp2 = icmp sgt i32 %min, -1
   %sub = sub i32 0, %min

llvm/test/Transforms/InstCombine/select_meta.ll

;
   %1 = icmp slt i32 %a, -32768
   %2 = trunc i32 %a to i16
   %3 = select i1 %1, i16 %2, i16 -32768, !prof !1
   ret i16 %3
 }
 
 define i32 @abs_nabs_x01(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x01(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 %x, 0
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 0, %x
-; CHECK-NEXT:    [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 %x, !prof ![[$MD3:[0-9]+]]
-; CHECK-NEXT:    ret i32 [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
   %cond = select i1 %cmp, i32 %sub, i32 %x, !prof !1
   %cmp1 = icmp sgt i32 %cond, -1
   %sub16 = sub nsw i32 0, %cond
   %cond18 = select i1 %cmp1, i32 %cond, i32 %sub16, !prof !2
   ret i32 %cond18
 }
 
 ; Swap predicate / metadata order
 
 define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @abs_nabs_x01_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> %x, zeroinitializer
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, %x
-; CHECK-NEXT:    [[COND1:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> %x, !prof ![[$MD3]]
-; CHECK-NEXT:    ret <2 x i32> [[COND1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
   %sub = sub nsw <2 x i32> zeroinitializer, %x
   %cond = select <2 x i1> %cmp, <2 x i32> %sub, <2 x i32> %x, !prof !1
   %cmp1 = icmp sgt <2 x i32> %cond, <i32 -1, i32 -1>
   %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
   %cond18 = select <2 x i1> %cmp1, <2 x i32> %cond, <2 x i32> %sub16, !prof !2
   ret <2 x i32> %cond18
;
   %retval = select i1 %cmp5, i32 %cond, i32 %x, !prof !2
   ret i32 %retval
 }
 
 ; SMAX(SMAX(75, X), 36) -> SMAX(X, 75)
 define i32 @test70(i32 %x) {
 ; CHECK-LABEL: @test70(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 %x, 75
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[TMP1]], i32 %x, i32 75, !prof ![[$MD3]]
+; CHECK-NEXT:    [[COND:%.*]] = select i1 [[TMP1]], i32 %x, i32 75, !prof ![[$MD3:[0-9]+]]
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp = icmp slt i32 %x, 75
   %cond = select i1 %cmp, i32 75, i32 %x, !prof !1
   %cmp3 = icmp slt i32 %cond, 36
   %retval = select i1 %cmp3, i32 36, i32 %cond, !prof !2
   ret i32 %retval
 }

llvm/test/Transforms/InstCombine/sub-of-negatible.ll

;
   ret i8 %t1
 }
 
 ; abs/nabs can be negated
 define i8 @negate_abs(i8 %x, i8 %y) {
 ; CHECK-LABEL: @negate_abs(
 ; CHECK-NEXT:    [[T0:%.*]] = sub i8 0, [[X:%.*]]
 ; CHECK-NEXT:    call void @use8(i8 [[T0]])
-; CHECK-NEXT:    [[T1:%.*]] = icmp slt i8 [[X]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[T1]], i8 [[X]], i8 [[T0]], !prof !0
-; CHECK-NEXT:    [[T3:%.*]] = add i8 [[TMP1]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X]], i1 false)
+; CHECK-NEXT:    [[T3:%.*]] = sub i8 [[Y:%.*]], [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t0 = sub i8 0, %x
   call void @use8(i8 %t0)
   %t1 = icmp slt i8 %x, 0
   %t2 = select i1 %t1, i8 %t0, i8 %x, !prof !0
   %t3 = sub i8 %y, %t2
   ret i8 %t3
 }
 define i8 @negate_nabs(i8 %x, i8 %y) {
 ; CHECK-LABEL: @negate_nabs(
 ; CHECK-NEXT:    [[T0:%.*]] = sub i8 0, [[X:%.*]]
 ; CHECK-NEXT:    call void @use8(i8 [[T0]])
-; CHECK-NEXT:    [[T1:%.*]] = icmp slt i8 [[X]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[T1]], i8 [[T0]], i8 [[X]], !prof !0
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X]], i1 false)
 ; CHECK-NEXT:    [[T3:%.*]] = add i8 [[TMP1]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i8 [[T3]]
 ;
   %t0 = sub i8 0, %x
   call void @use8(i8 %t0)
   %t1 = icmp slt i8 %x, 0
   %t2 = select i1 %t1, i8 %x, i8 %t0, !prof !0
   %t3 = sub i8 %y, %t2

llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll

 define i32 @TestVectorsEqual(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
 ; CHECK-LABEL: @TestVectorsEqual(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32* [[VEC0:%.*]] to <4 x i32>*
 ; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32* [[VEC1:%.*]] to <4 x i32>*
 ; CHECK-NEXT:    [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
 ; CHECK-NEXT:    [[TMP4:%.*]] = sub nsw <4 x i32> [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = icmp slt <4 x i32> [[TMP4]], zeroinitializer
-; CHECK-NEXT:    [[TMP6:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP4]]
-; CHECK-NEXT:    [[TMP7:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP6]], <4 x i32> [[TMP4]]
-; CHECK-NEXT:    [[TMP8:%.*]] = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> [[TMP7]])
-; CHECK-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP8]], [[TOLERANCE:%.*]]
-; CHECK-NEXT:    [[COND6:%.*]] = zext i1 [[CMP5]] to i32
+; CHECK-NEXT:    [[TMP5:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP4]], i1 true)
+; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])
+; CHECK-NEXT:    [[CMP5_NOT:%.*]] = icmp sle i32 [[TMP6]], [[TOLERANCE:%.*]]
+; CHECK-NEXT:    [[COND6:%.*]] = zext i1 [[CMP5_NOT]] to i32
 ; CHECK-NEXT:    ret i32 [[COND6]]
 ;
 entry:
   br label %for.cond
 
 for.cond:
   %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
   %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]

 ; CHECK-LABEL: @TestVectorsEqual_alt(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32* [[VEC0:%.*]] to <4 x i32>*
 ; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32* [[VEC1:%.*]] to <4 x i32>*
 ; CHECK-NEXT:    [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
 ; CHECK-NEXT:    [[TMP4:%.*]] = sub <4 x i32> [[TMP1]], [[TMP3]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> [[TMP4]])
-; CHECK-NEXT:    [[CMP3:%.*]] = icmp ule i32 [[TMP5]], [[TOLERANCE:%.*]]
-; CHECK-NEXT:    [[COND:%.*]] = zext i1 [[CMP3]] to i32
+; CHECK-NEXT:    [[CMP3_NOT:%.*]] = icmp ule i32 [[TMP5]], [[TOLERANCE:%.*]]
+; CHECK-NEXT:    [[COND:%.*]] = zext i1 [[CMP3_NOT]] to i32
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
 entry:
   br label %for.cond
 
 for.cond:
   %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.inc ]
   %Component.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]

llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll

;
   %r = sub i8 %m2, %m1
   ret i8 %r
 }
 
 ; or (abs a), (abs a) --> abs a
 
 define i8 @abs_swapped(i8 %a) {
 ; CHECK-LABEL: @abs_swapped(
-; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[A:%.*]]
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i8 [[A]], 0
-; CHECK-NEXT:    [[M1:%.*]] = select i1 [[CMP1]], i8 [[NEG]], i8 [[A]]
-; CHECK-NEXT:    ret i8 [[M1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[A:%.*]], i1 false)
+; CHECK-NEXT:    ret i8 [[TMP1]]
 ;
   %neg = sub i8 0, %a
   %cmp1 = icmp sgt i8 %a, 0
   %cmp2 = icmp slt i8 %a, 0
   %m1 = select i1 %cmp1, i8 %a, i8 %neg
   %m2 = select i1 %cmp2, i8 %neg, i8 %a
   %r = or i8 %m2, %m1
   ret i8 %r
;
   %r = xor i8 %m2, %m1
   ret i8 %r
 }
 
 ; or (nabs a), (nabs a) --> nabs a
 
 define i8 @nabs_different_constants(i8 %a) {
 ; CHECK-LABEL: @nabs_different_constants(
-; CHECK-NEXT:    [[NEG:%.*]] = sub i8 0, [[A:%.*]]
-; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i8 [[A]], 0
-; CHECK-NEXT:    [[M1:%.*]] = select i1 [[CMP1]], i8 [[A]], i8 [[NEG]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[A:%.*]], i1 false)
+; CHECK-NEXT:    [[M1:%.*]] = sub i8 0, [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[M1]]
 ;
   %neg = sub i8 0, %a
   %cmp1 = icmp slt i8 %a, 0
   %cmp2 = icmp sgt i8 %a, -1
   %m1 = select i1 %cmp1, i8 %a, i8 %neg
   %m2 = select i1 %cmp2, i8 %neg, i8 %a
   %r = or i8 %m2, %m1
   ret i8 %r
 }