[PowerPC] Fix thunk alignment issue when using pc-rel instruction

[NeHuang]

Summary

Thunk alignment is needed when using pc-rel instructions to avoid crossing the 64 byte boundary.

Patched by @nemanjai

[NeHuang]

• Updated the LIT cases accordingly.
• Create a test case for thunk alignment fix.

[MaskRay]

lld/test/ELF/ppc64-thunk-alignment.s

1 ↗

(On Diff #285706)

I don't think the additional test is necessary. The address differences should be reflected by other tests.

Having too many tests for a feature is also something we should try to avoid.

[MaskRay]

lld/test/ELF/ppc64-toc-call-to-pcrel.s

35 ↗

(On Diff #285706)

Doesn't it have <__toc_save_callee>?

[NeHuang]

Thanks MaskRay. The additional test removed.

[NeHuang]

lld/test/ELF/ppc64-thunk-alignment.s

1 ↗

(On Diff #285706)

Will do.

lld/test/ELF/ppc64-toc-call-to-pcrel.s

35 ↗

(On Diff #285706)

Sorry I did not quite get your point. 0x10020040 is the start address of __toc_save_callee stub.

[MaskRay]

lld/test/ELF/ppc64-toc-call-to-pcrel.s

35 ↗

(On Diff #285706)

For b and bl , objdump -d symbolizes the target address. If it symbolizes bfl and the result is meaningful, please add <__toc_save_callee>

[NeHuang]

lld/test/ELF/ppc64-toc-call-to-pcrel.s

35 ↗

(On Diff #285706)

Thanks for the clarification. Run object dump with llvm-objdump -d --no-show-raw-insn --mcpu=future ppc64-toc-call-to-pcrel.s.tmp and got results as below, I do not think the dis-assembler gives us the stub name for bfl and we can not add <__toc_save_callee> here.

...
1002002c: lwz 3, 32724(30)
10020030: bfl 0, 0x10020040
10020034: ld 2, 24(1)
...

[sfertile]

LGTM.

lld/ELF/SyntheticSections.cpp

return llvm::find_if(exidxSections, [](InputSection *isec) {
          }) != exidxSections.end();
 }
 
 bool ARMExidxSyntheticSection::classof(const SectionBase *d) {
   return d->kind() == InputSectionBase::Synthetic && d->type == SHT_ARM_EXIDX;
 }
 
 ThunkSection::ThunkSection(OutputSection *os, uint64_t off)
-    : SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 4,
-                       ".text.thunk") {
+    : SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS,
+                       config->emachine == EM_PPC64 ? 16 : 4, ".text.thunk") {
   this->parent = os;
   this->outSecOff = off;
 }
 
 size_t ThunkSection::getSize() const {
   if (roundUpSizeForErrata)
     return alignTo(size, 4096);
   return size;

lld/ELF/Thunks.cpp

 };
 
 // PPC64 R12 Setup Stub
 // When a caller that does not maintain a toc-pointer performs a local call to
 // a callee which requires a toc-pointer then we need this stub to place the
 // callee's global entry point into r12 without a save of R2.
 class PPC64R12SetupStub final : public Thunk {
 public:
-  PPC64R12SetupStub(Symbol &dest) : Thunk(dest, 0) {}
+  PPC64R12SetupStub(Symbol &dest) : Thunk(dest, 0) { alignment = 16; }
   uint32_t size() override { return 16; }
   void writeTo(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
 };
 
 // PPC64 PC-relative PLT Stub
 // When a caller that does not maintain a toc-pointer performs an extern call
 // then this stub is needed for:
 // 1) Loading the target functions address from the procedure linkage table into
 //    r12 for use by the target functions global entry point, and into the count
 //    register with pc-relative instructions.
 // 2) Transferring control to the target function through an indirect branch.
 class PPC64PCRelPLTStub final : public Thunk {
 public:
-  PPC64PCRelPLTStub(Symbol &dest) : Thunk(dest, 0) {}
+  PPC64PCRelPLTStub(Symbol &dest) : Thunk(dest, 0) { alignment = 16; }
   uint32_t size() override { return 16; }
   void writeTo(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
   bool isCompatibleWith(const InputSection &isec,
                         const Relocation &rel) const override;
 };
 
 // A bl instruction uses a signed 24 bit offset, with an implicit 4 byte