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dnsampaio (Diogo N. Sampaio)
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User Since
Sep 22 2017, 3:13 PM (157 w, 14 h)

Recent Activity

Aug 19 2020

dnsampaio added a comment to D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.

I'm out in vacations, just have my phone here. I'm surprised I forgot to
preserve de debug information, sorry about that.

Aug 19 2020, 5:46 AM · Restricted Project

Aug 18 2020

dnsampaio updated subscribers of D84923: [ARM] Fix so immediates and pc relative checks.

Feel free to move on this patch, I'm in vacations.

Aug 18 2020, 12:15 AM · Restricted Project

Aug 3 2020

dnsampaio added inline comments to D85101: [AArch64][CodeGen] Restrict bfloat vector operations to what's actually supported.
Aug 3 2020, 2:04 AM · Restricted Project

Jul 30 2020

dnsampaio updated the diff for D84923: [ARM] Fix so immediates and pc relative checks.

Fixed true -> false for isSOImm when checking for reducing to t1 instructions

Jul 30 2020, 8:41 AM · Restricted Project
dnsampaio added inline comments to D84923: [ARM] Fix so immediates and pc relative checks.
Jul 30 2020, 8:40 AM · Restricted Project
dnsampaio added reviewers for D84923: [ARM] Fix so immediates and pc relative checks: samparker, gchatelet.
Jul 30 2020, 4:22 AM · Restricted Project
dnsampaio requested review of D84923: [ARM] Fix so immediates and pc relative checks.
Jul 30 2020, 2:18 AM · Restricted Project
dnsampaio added a comment to D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.

Ping ... ping...

Jul 30 2020, 2:15 AM · Restricted Project, Restricted Project

Jul 24 2020

dnsampaio added a comment to D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.

Ping

Jul 24 2020, 2:25 AM · Restricted Project, Restricted Project

Jul 22 2020

dnsampaio accepted D84169: [Thumb] set code alignment for 16-bit load from constant pool.

Thanks. LGTM.

Jul 22 2020, 1:42 AM · Restricted Project

Jul 21 2020

dnsampaio added a comment to D84169: [Thumb] set code alignment for 16-bit load from constant pool.

Ok, this patch seems to be correct, but it would be nice to have a test.
You can use clang -mllvm -stop-before=arm-cp-islands -mllvm --simplify-mir to obtain a machine IR before the patch, and use llc -run-pass=arm-cp-islands to validate that the alignment for the function is set to 4.

Jul 21 2020, 8:24 AM · Restricted Project
dnsampaio added a comment to D84169: [Thumb] set code alignment for 16-bit load from constant pool.

Sorry, it seems I was looking the wrong instruction, it should be the label variant: vldr.16 s0, .LCPI0_0

Jul 21 2020, 1:24 AM · Restricted Project
dnsampaio added a comment to D84169: [Thumb] set code alignment for 16-bit load from constant pool.

Hi, thanks for working on this.
What exactly are you trying to fix? From what I see from https://developer.arm.com/docs/ddi0597/h/simd-and-floating-point-instructions-alphabetic-order/vldr-immediate-load-simdfp-register-immediate
VLDR.16 s0,{pc}+0x16 requires only a alignment of 2 bytes, as it has only a single zero appended in the case of half (.16):

T1
Half-precision scalar (size == 01)
(Armv8.2)
VLDR{<c>}{<q>}.16 <Sd>, [<Rn> {, #{+/-}<imm>}]
esize = 8 << UInt(size);  add = (U == '1');
imm32 = if esize == 16 then ZeroExtend(imm8:'0', 32) else ZeroExtend(imm8:'00', 32);
Jul 21 2020, 1:06 AM · Restricted Project

Jul 17 2020

dnsampaio updated the diff for D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.

Fixed remaining of inline comments

Jul 17 2020, 8:54 AM · Restricted Project, Restricted Project
dnsampaio added a comment to D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.

Indeed not all of them. Fixed this time.

Jul 17 2020, 8:02 AM · Restricted Project, Restricted Project
dnsampaio updated the summary of D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.
Jul 17 2020, 2:25 AM · Restricted Project, Restricted Project
dnsampaio updated the summary of D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.
Jul 17 2020, 2:25 AM · Restricted Project, Restricted Project

Jul 15 2020

dnsampaio added a comment to D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.

Ping

Jul 15 2020, 6:13 AM · Restricted Project, Restricted Project

Jul 10 2020

dnsampaio committed rG7bf168390fd0: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses (authored by dnsampaio).
[BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses
Jul 10 2020, 12:35 AM
dnsampaio closed D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.
Jul 10 2020, 12:35 AM · Restricted Project
dnsampaio updated the diff for D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.

Preserve name

Jul 10 2020, 12:02 AM · Restricted Project

Jul 9 2020

dnsampaio updated the diff for D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.

Re-fixed test file, now showing only differences

Jul 9 2020, 8:08 AM · Restricted Project
dnsampaio committed rGa0e981c190ff: [NFC] Add SExt multiuses test (authored by dnsampaio).
[NFC] Add SExt multiuses test
Jul 9 2020, 7:31 AM
dnsampaio added a comment to D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.

Fixed test location and command

The file is not moved here in the review, so something may be out-of-sync. The best thing would be to commit that file first with the current CHECK lines, then update it after applying this code patch. That way, we will highlight the test diffs.

Jul 9 2020, 7:19 AM · Restricted Project
dnsampaio added inline comments to D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.
Jul 9 2020, 2:40 AM · Restricted Project
dnsampaio updated the diff for D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.

Clear users assumptions (and test it)

Jul 9 2020, 2:34 AM · Restricted Project

Jul 8 2020

dnsampaio retitled D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses from [BDCE] SExt -> ZExt when no sign bits is used with multiple uses to [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.
Jul 8 2020, 7:14 AM · Restricted Project
dnsampaio retitled D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses from [AggressiveInstCombine] SExt -> ZExt when no sign bits is used with multiple uses to [BDCE] SExt -> ZExt when no sign bits is used with multiple uses.
Jul 8 2020, 7:13 AM · Restricted Project
dnsampaio updated the diff for D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.

Fixed test location and command

Jul 8 2020, 7:13 AM · Restricted Project

Jul 7 2020

dnsampaio updated the diff for D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.

Moved to BDCE.

Jul 7 2020, 6:00 PM · Restricted Project
dnsampaio updated the diff for D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.

Rebased.
Now the AAPCS explicitly avoids conflicts with the C11, by not imposing any restriction
when the natural container will overlap a zero lenght bit-field:
https://github.com/ARM-software/abi-aa/commit/2334fc7611ede31b33e314ddd0dc90579015b322
Both 32 and 64 bit versions were updated on the same way.

Jul 7 2020, 6:17 AM · Restricted Project, Restricted Project
dnsampaio added reviewers for D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses: dmgreen, eli.friedman.
Jul 7 2020, 5:27 AM · Restricted Project
dnsampaio updated the diff for D60413: [BDCE] SExt -> ZExt when no sign bits is used and instruction has multiple uses.

Rebase

Jul 7 2020, 5:25 AM · Restricted Project

Jun 12 2020

dnsampaio added a comment to D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Perhaps we could move to making half a valid type for the arm back-end as follow up patches. Allowing half as argument through the IR is already a step to that direction.
IMO this patch is already quite big and it excels in fixing the bugs it proposed.

Jun 12 2020, 3:12 AM · Restricted Project, Restricted Project

May 27 2020

dnsampaio added a comment to D79378: PR34581: Don't remove an 'if (p)' guarding a call to 'operator delete(p)' under -Oz..

Hi @rsmith,
are you still looking into this?
cheers

May 27 2020, 4:55 PM · Restricted Project, Restricted Project

May 15 2020

dnsampaio committed rG6c68f75ee4d9: Prevent register coalescing in functions whith setjmp (authored by dnsampaio).
Prevent register coalescing in functions whith setjmp
May 15 2020, 4:52 PM
dnsampaio closed D77767: Prevent register coalescing in functions whith setjmp.
May 15 2020, 4:52 PM · Restricted Project
dnsampaio updated the diff for D77767: Prevent register coalescing in functions whith setjmp.

Addressed requests

May 15 2020, 3:14 PM · Restricted Project
dnsampaio added inline comments to D77767: Prevent register coalescing in functions whith setjmp.
May 15 2020, 3:14 PM · Restricted Project

May 14 2020

dnsampaio accepted D79378: PR34581: Don't remove an 'if (p)' guarding a call to 'operator delete(p)' under -Oz..

LGTM, as far @rjmccall 's concern about documentation is addressed.

May 14 2020, 5:20 AM · Restricted Project, Restricted Project
dnsampaio added a comment to D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Why not just make half as an argument do the right thing for that case?

That would be the ideal approach, but currently there's a limitation on the backend's calling convention lowering that gets in the way.
The lowering of calls in SelectionDAGBuilder includes a target-independent step that is responsible for spliting or promoting each argument into "legal registers" and takes place before the targets' calling convention lowering.
As f16 is not a legal type on many of the AAPCS_VFP targets, it gets promoted to f32 before the target's lowering code has a chance to define how to handle it.
Ideally, this stpe should only take place if lowering calling conventions after type legalization - there's a FIXME there already capturing that -, but that would involve a major rewriting that would impact multiple targets.
Inserting a hacky target-dependent fix in this step also didn't look very good.
Do you see other alternatives for handling it? If not, which approach would you suggest?

Would it be possible to pass a half argument and fix-it-up at CodeGenPrepare?

May 14 2020, 5:20 AM · Restricted Project, Restricted Project

May 11 2020

dnsampaio added a comment to D79378: PR34581: Don't remove an 'if (p)' guarding a call to 'operator delete(p)' under -Oz..

From my point it does LGTM.

May 11 2020, 5:19 AM · Restricted Project, Restricted Project

May 5 2020

dnsampaio added a comment to D77767: Prevent register coalescing in functions whith setjmp.

Ping

May 5 2020, 2:36 PM · Restricted Project
dnsampaio added a comment to D79378: PR34581: Don't remove an 'if (p)' guarding a call to 'operator delete(p)' under -Oz..

I believe we can avoid creating some blocks for latter removing them, no?

May 5 2020, 4:48 AM · Restricted Project, Restricted Project

May 1 2020

dnsampaio committed rG081dbd61db8a: [NFC] Try to fix test due asan failure (authored by dnsampaio).
[NFC] Try to fix test due asan failure
May 1 2020, 5:21 PM
dnsampaio added a comment to D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.

Hi, @ldionne
I just submitted a what I think is the test fix. It was the only place I was not using the second element of the string and could generate a underflow.

May 1 2020, 5:08 PM · Restricted Project

Apr 30 2020

dnsampaio committed rGc14ac8043ed1: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol |… (authored by dnsampaio).
[FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol |…
Apr 30 2020, 3:40 PM
dnsampaio closed D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.
Apr 30 2020, 3:40 PM · Restricted Project

Apr 29 2020

dnsampaio added a comment to D37933: Prevent InstCombine from miscompiling `operator delete` .

Hi @davide, do you have any plans to address this issue? Regards.

Apr 29 2020, 10:43 AM

Apr 27 2020

dnsampaio updated the diff for D77767: Prevent register coalescing in functions whith setjmp.

Now testing only simple-register-coalescing

Apr 27 2020, 7:24 PM · Restricted Project
dnsampaio updated the summary of D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.
Apr 27 2020, 9:06 AM · Restricted Project
dnsampaio updated the diff for D77767: Prevent register coalescing in functions whith setjmp.

Fixed x86 test

Apr 27 2020, 8:34 AM · Restricted Project
dnsampaio retitled D77767: Prevent register coalescing in functions whith setjmp from Prevent stack coloring functions whith setjmp / longjmp to Prevent register coalescing in functions whith setjmp.
Apr 27 2020, 8:01 AM · Restricted Project
dnsampaio updated the diff for D77767: Prevent register coalescing in functions whith setjmp.

Do not perform register coalescing

Apr 27 2020, 6:25 AM · Restricted Project

Apr 25 2020

dnsampaio added a comment to D77767: Prevent register coalescing in functions whith setjmp.

Hi @efriedma and @rnk ,

Apr 25 2020, 9:00 AM · Restricted Project

Apr 20 2020

dnsampaio added a comment to D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.

Ping. I would like to move along this small patch.

Apr 20 2020, 9:10 AM · Restricted Project

Apr 14 2020

dnsampaio added a comment to D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.

Ping

Apr 14 2020, 5:25 PM · Restricted Project
dnsampaio added a comment to D77767: Prevent register coalescing in functions whith setjmp.

Hi @rnk and @efriedma, indeed my initial thoughts were as well the register allocator, specially because using the pbqp allocator there are no spills for this example so it does not fail.
From what I see in the code it seems that none of the register allocators know anything about setjmp. There's an ancient llvm-dev post confirming it: https://lists.llvm.org/pipermail/llvm-dev/2011-October/043731.html

Apr 14 2020, 2:39 PM · Restricted Project

Apr 9 2020

dnsampaio accepted D77074: [FPEnv][AArch64] Platform-specific builtin constrained FP enablement.

LGTM, not forgetting to remove the exit comments.

Apr 9 2020, 4:21 PM · Restricted Project
dnsampaio added a comment to D77767: Prevent register coalescing in functions whith setjmp.

Hi @efriedma,
thanks for looking into this.

Apr 9 2020, 4:02 PM · Restricted Project

Apr 8 2020

dnsampaio created D77767: Prevent register coalescing in functions whith setjmp.
Apr 8 2020, 6:29 PM · Restricted Project

Apr 6 2020

dnsampaio added a comment to D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.

Ping

Apr 6 2020, 3:16 PM · Restricted Project

Apr 2 2020

dnsampaio added a comment to D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.

Ping

Apr 2 2020, 2:06 PM · Restricted Project
dnsampaio added inline comments to D77074: [FPEnv][AArch64] Platform-specific builtin constrained FP enablement.
Apr 2 2020, 2:06 PM · Restricted Project

Apr 1 2020

dnsampaio added inline comments to D77074: [FPEnv][AArch64] Platform-specific builtin constrained FP enablement.
Apr 1 2020, 11:48 AM · Restricted Project

Mar 31 2020

dnsampaio added inline comments to D77074: [FPEnv][AArch64] Platform-specific builtin constrained FP enablement.
Mar 31 2020, 4:56 AM · Restricted Project

Mar 27 2020

dnsampaio added a comment to D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.

Gentle Ping. I believe all issues with this fix have been fulfilled.

Mar 27 2020, 4:50 AM · Restricted Project

Mar 23 2020

dnsampaio updated the diff for D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.
  • Fixed tests to use "\\b" instead of "\b".
Mar 23 2020, 4:53 AM · Restricted Project

Mar 18 2020

dnsampaio accepted D74766: [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrdmulhq_lane intrinsics.

LGTM

Mar 18 2020, 11:19 PM · Restricted Project
dnsampaio added a comment to D74619: [ARM] Enabling range checks on Neon intrinsics' lane arguments.

Hi,
thanks for looking into this. The patch LGTM, but regarding the indentation, I don't know what would be the best practice here. We tend to like to preserve the line-git-history, but if we start ignoring the formater check, then it has no sense in they being here.
Perhaps @t.p.northover or @olista01 could share their thoughts here.

Mar 18 2020, 5:57 AM · Restricted Project

Mar 17 2020

dnsampaio added inline comments to D73638: [AST] Move dependence computations into a separate file.
Mar 17 2020, 2:17 AM · Restricted Project

Mar 16 2020

dnsampaio added a comment to D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.

Ping.

Mar 16 2020, 1:40 PM · Restricted Project

Mar 13 2020

dnsampaio committed rG83cdb654e475: [AArch64][Fix] LdSt optimization generate premature stack-popping (authored by dnsampaio).
[AArch64][Fix] LdSt optimization generate premature stack-popping
Mar 13 2020, 7:26 PM
dnsampaio closed D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.
Mar 13 2020, 7:26 PM · Restricted Project
dnsampaio updated the diff for D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.
  • Removed incorrect spacing changes
Mar 13 2020, 10:44 AM · Restricted Project
dnsampaio updated the diff for D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.
  • Removed unecessary changes
Mar 13 2020, 8:33 AM · Restricted Project
dnsampaio updated the diff for D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.
  • Do not allow a instruction that may load or store between the LdSt[SP] and the SP update.
Mar 13 2020, 8:01 AM · Restricted Project

Mar 12 2020

dnsampaio updated the diff for D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.
  • Do not use pseudo-value
Mar 12 2020, 4:30 AM · Restricted Project
dnsampaio added a comment to D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.

Hi @EricWF, thanks for the review.
Indeed there seems to have some other unrelated issue for matching the word boundary \b. Perhaps I wrongly assumed that it should also match line beginning and end.
For example, I would expect all these matches to succeed:

Mar 12 2020, 2:19 AM · Restricted Project

Mar 11 2020

dnsampaio updated the diff for D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.
  • Correct mayAlias to isStack
Mar 11 2020, 6:54 PM · Restricted Project
dnsampaio updated the diff for D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.
  • Fixed tests
  • Avoid optimization when target is Windows with CFI, as we need to correctly update unwind information
Mar 11 2020, 4:30 PM · Restricted Project
dnsampaio added a comment to D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.

Ping.

Mar 11 2020, 5:08 AM · Restricted Project

Mar 10 2020

dnsampaio accepted D74618: [ARM] Creating 'call_mangled' for Neon intrinsics definitions.

LGTM, after a nit inline.

Mar 10 2020, 8:39 AM · Restricted Project

Mar 9 2020

dnsampaio updated the diff for D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.

Do not optimize post-increment SP in windows targets

Mar 9 2020, 4:48 AM · Restricted Project
dnsampaio added inline comments to D74766: [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrdmulhq_lane intrinsics.
Mar 9 2020, 4:48 AM · Restricted Project
dnsampaio added inline comments to D74619: [ARM] Enabling range checks on Neon intrinsics' lane arguments.
Mar 9 2020, 3:11 AM · Restricted Project

Mar 8 2020

dnsampaio added a comment to D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.

I think there's a secondary problem here: if we move an SP adjustment, we might also need to adjust the unwind/debug info. This is particularly nasty on Windows, where messing up the unwind info can actually cause a miscompile.

If you don't want to spend the time to try to figure that out, I'd be happy to just completely forbid optimizing sp adjustments here. It should be rare enough that it doesn't matter much in practice.

Mar 8 2020, 2:56 PM · Restricted Project

Mar 6 2020

dnsampaio created D75755: [AArch64][Fix] LdSt optimization generate premature stack-popping.
Mar 6 2020, 8:46 AM · Restricted Project

Mar 5 2020

dnsampaio added inline comments to D74618: [ARM] Creating 'call_mangled' for Neon intrinsics definitions.
Mar 5 2020, 3:51 AM · Restricted Project
dnsampaio added a comment to D74617: [ARM] Keeping sign information on bitcasts for Neon vdot_lane intrinsics.

Is this missing a test?

Mar 5 2020, 3:18 AM · Restricted Project
dnsampaio accepted D74616: [ARM] Setting missing isLaneQ attribute on Neon Intrisics definitions.

LGTM with a nit: we can save some space using sintax like this:

let isLaneQ = 1 in
def UDOT_LANEQ : SOpInst<"vdot_laneq", "..(<<)(<<Q)I", "iUiQiQUi", OP_DOT_LNQ>;

or concatenating those that are just one after the other:

let isLaneQ = 1 in {
  def VFMLAL_LANEQ_LOW  : SOpInst<"vfmlal_laneq_low",  "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN>;
   def VFMLSL_LANEQ_LOW  : SOpInst<"vfmlsl_laneq_low",  "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN>;
   def VFMLAL_LANEQ_HIGH : SOpInst<"vfmlal_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN_Hi>;
   def VFMLSL_LANEQ_HIGH : SOpInst<"vfmlsl_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN_Hi>;
}
Mar 5 2020, 2:46 AM · Restricted Project

Mar 4 2020

dnsampaio created D75622: [FIX][libc++][Regex] Using regex_constants match_prev_avail | match_not_bol | match_not_bow.
Mar 4 2020, 9:32 AM · Restricted Project

Feb 14 2020

dnsampaio committed rG8bc790f9e6a6: [AArch64][FPenv] Update chain of int to fp conversion (authored by dnsampaio).
[AArch64][FPenv] Update chain of int to fp conversion
Feb 14 2020, 9:11 PM
dnsampaio closed D74597: [AArch64][FPenv] Update chain of int to fp conversion.
Feb 14 2020, 9:11 PM · Restricted Project
dnsampaio updated the diff for D74597: [AArch64][FPenv] Update chain of int to fp conversion.

Changes requested: IR test, chain changed depending on isStrictFPOpcode, signed and unsigned tests

Feb 14 2020, 8:05 AM · Restricted Project
dnsampaio created D74597: [AArch64][FPenv] Update chain of int to fp conversion.
Feb 14 2020, 2:12 AM · Restricted Project

Feb 11 2020

dnsampaio added a comment to D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.

Hi @ostannard, thanks for your review.
I updated the patch so it won't act when the computed volatile bit-field access will overlap a zero length bit-field, avoiding the conflict. We can update it accordingly to future versions of the AAPCS if required.

Feb 11 2020, 7:14 AM · Restricted Project, Restricted Project
dnsampaio updated the diff for D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.
  • Fixing comments and removing some tests changes not required
Feb 11 2020, 7:14 AM · Restricted Project, Restricted Project
dnsampaio updated the diff for D72932: [ARM] Follow AACPS standard for volatile bit-fields access width.
  • Add test that the volatile access does not cross a border defined by a zero lenght bit-field, defined by C11, avoiding race-conditions
Feb 11 2020, 6:55 AM · Restricted Project, Restricted Project

Feb 10 2020

dnsampaio added a comment to D73970: [ARM] Fix non-determenistic behaviour.

Do you think it's worth cherry-picking this to 10.0? CC @hans

Also, it looks like the test got dropped in the commit.

Feb 10 2020, 12:24 AM · Restricted Project