dnsampaio (Diogo N. Sampaio)
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User Since
Sep 22 2017, 3:13 PM (56 w, 2 d)

Recent Activity

Fri, Oct 19

dnsampaio added a comment to D53319: Add support for AArch64 UDF instruction.

Ping.

Fri, Oct 19, 9:07 AM

Tue, Oct 16

dnsampaio updated the diff for D53319: Add support for AArch64 UDF instruction.

No custom decoding is required

Tue, Oct 16, 10:57 AM
dnsampaio added inline comments to D53319: Add support for AArch64 UDF instruction.
Tue, Oct 16, 10:22 AM
dnsampaio updated the diff for D53319: Add support for AArch64 UDF instruction.

Fixed the tests as to check boundaries, and one value in the middle.
Changed tests ordering as they generated empty lines not treated by FileCheck.

Tue, Oct 16, 4:50 AM
dnsampaio added a comment to D53319: Add support for AArch64 UDF instruction.

To send patch....

Tue, Oct 16, 4:29 AM
dnsampaio created D53319: Add support for AArch64 UDF instruction.
Tue, Oct 16, 3:18 AM

Thu, Oct 11

dnsampaio committed rL344248: [AARCH64][FIX] Emit data symbol for constant pool data.
[AARCH64][FIX] Emit data symbol for constant pool data
Thu, Oct 11, 7:13 AM
dnsampaio closed D53132: [AARCH64][FIX] Emit data symbol for constant pool data.
Thu, Oct 11, 7:13 AM
dnsampaio updated the diff for D53132: [AARCH64][FIX] Emit data symbol for constant pool data.

Removed processor and specific triple target from test.

Thu, Oct 11, 6:27 AM
dnsampaio added a reviewer for D53132: [AARCH64][FIX] Emit data symbol for constant pool data: pbarrio.
Thu, Oct 11, 4:34 AM
dnsampaio created D53132: [AARCH64][FIX] Emit data symbol for constant pool data.
Thu, Oct 11, 4:26 AM

Tue, Oct 2

dnsampaio committed rLLD343604: [NFC][BUG-FIX][ARM] Add missing data symbol.
[NFC][BUG-FIX][ARM] Add missing data symbol
Tue, Oct 2, 9:55 AM
dnsampaio committed rL343604: [NFC][BUG-FIX][ARM] Add missing data symbol.
[NFC][BUG-FIX][ARM] Add missing data symbol
Tue, Oct 2, 9:54 AM
dnsampaio committed rL343594: [ARM] Emmit data symbol for constant pool data.
[ARM] Emmit data symbol for constant pool data
Tue, Oct 2, 7:59 AM
dnsampaio closed D52737: [ARM] Emmit data symbol for constant pool data.
Tue, Oct 2, 7:59 AM
dnsampaio updated the diff for D52737: [ARM] Emmit data symbol for constant pool data.

Updated test to use llvm-mc instead of clang.

Tue, Oct 2, 3:39 AM
dnsampaio updated the diff for D52737: [ARM] Emmit data symbol for constant pool data.

Simplified tests. Using the standard function for emitting data symbols, if required.

Tue, Oct 2, 2:54 AM
dnsampaio added inline comments to D52737: [ARM] Emmit data symbol for constant pool data.
Tue, Oct 2, 2:53 AM

Mon, Oct 1

dnsampaio created D52737: [ARM] Emmit data symbol for constant pool data.
Mon, Oct 1, 11:26 AM

Sep 12 2018

dnsampaio committed rL342061: [ARM] Tighten f64<->f16 conversion requirements.
[ARM] Tighten f64<->f16 conversion requirements
Sep 12 2018, 9:26 AM
dnsampaio closed D51631: [ARM] Tighten f64<->f16 conversion requirements.
Sep 12 2018, 9:26 AM

Sep 7 2018

dnsampaio added a comment to D51683: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89.

Correct. The protected name is double underscore as both suffix and prefix.

Sep 7 2018, 2:47 AM
dnsampaio committed rC341644: Replaces __inline by __inline__ / C89 compatible.
Replaces __inline by __inline__ / C89 compatible
Sep 7 2018, 2:41 AM
dnsampaio committed rL341644: Replaces __inline by __inline__ / C89 compatible.
Replaces __inline by __inline__ / C89 compatible
Sep 7 2018, 2:41 AM

Sep 6 2018

dnsampaio committed rL341548: Fix march triple used test from rL341475.
Fix march triple used test from rL341475
Sep 6 2018, 7:14 AM
dnsampaio committed rC341548: Fix march triple used test from rL341475.
Fix march triple used test from rL341475
Sep 6 2018, 7:14 AM
dnsampaio updated the diff for D51683: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89.
Sep 6 2018, 6:10 AM
dnsampaio updated the diff for D51683: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89.

Fix test march triple.

Sep 6 2018, 5:59 AM
dnsampaio added inline comments to D51683: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89.
Sep 6 2018, 3:05 AM

Sep 5 2018

dnsampaio committed rC341475: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89.
Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89
Sep 5 2018, 7:57 AM
dnsampaio committed rL341475: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89.
Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89
Sep 5 2018, 7:57 AM
dnsampaio closed D51683: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89.
Sep 5 2018, 7:57 AM
dnsampaio created D51683: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89.
Sep 5 2018, 7:09 AM

Aug 14 2018

dnsampaio updated the diff for D50704: [Inline-cost] Teach cost function to account for accumulative code-size growth.

Fixed comment explaining the elaborated growth cost-function.

Aug 14 2018, 9:50 AM
dnsampaio added inline comments to D50704: [Inline-cost] Teach cost function to account for accumulative code-size growth.
Aug 14 2018, 9:43 AM
dnsampaio updated the diff for D50704: [Inline-cost] Teach cost function to account for accumulative code-size growth.

Using FileCheck in test file.

Aug 14 2018, 8:50 AM
dnsampaio created D50704: [Inline-cost] Teach cost function to account for accumulative code-size growth.
Aug 14 2018, 6:57 AM
dnsampaio added inline comments to D50432: [DAGCombiner] Reduce load widths of shifted masks.
Aug 14 2018, 2:14 AM
dnsampaio added inline comments to D50432: [DAGCombiner] Reduce load widths of shifted masks.
Aug 14 2018, 2:14 AM

Aug 13 2018

dnsampaio updated the summary of D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Aug 13 2018, 7:30 AM

Aug 8 2018

dnsampaio added inline comments to D50433: A New Divergence Analysis for LLVM.
Aug 8 2018, 6:48 AM

Aug 7 2018

dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Added missing test-file

Aug 7 2018, 9:51 AM
dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Moving this pattern matching to AggressiveInstCombine following a suggestion of @lebedev.ri . Now it searches for minimal required patterns as desired by @spatel.

Aug 7 2018, 9:50 AM

Aug 3 2018

dnsampaio added a comment to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

So all expensive operations have been eliminated, I do not see why it wouldn't fit in InstCombne. We detect a pattern and we reduce it.

Because the pattern that we are matching is larger than it needs to be (as the comment in the test file clearly shows - there is no 'or' in the minimal pattern). This problem of trying to make everything fit in instcombine has been discussed several times on llvm-dev in the last ~year. Eg:
http://lists.llvm.org/pipermail/llvm-dev/2017-September/117151.html

I agree that it won't handle all cases. But one will need to come with a more generic thinking as to create a new pass that handles this. Something like an abstract known bits, that tells that two values hold the same bits coming from a given instruction, or some simplification by demanded bits from the same values. It is feasible, but it is not my intention to do it so now.

Did you look at (new)-GVN to see if it fits in there?

I must confess that I did not quite understand all the work-flow of newGVN, but from what I did see, it mostly wouldn't fit. It seems to behave like InstCombine, expecting to replace the current instruction being visited. And it would require to create one value as to detect if there is a leader of that value and then reuse it. It is not that complicated, but quite awkward IMO.

If this is in instcombine (in addition to missing the pattern when there is no 'or'), I think you have to limit the transform based on uses as Roman mentioned in an earlier comment.

Aug 3 2018, 3:01 AM

Aug 2 2018

dnsampaio added inline comments to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Aug 2 2018, 3:38 AM

Jul 30 2018

dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Added test that the inner and must be replaced by the new shift operation.
Converted the function to bool, as it does not require to create the Or operation after the replaceAll.

Jul 30 2018, 5:07 AM
dnsampaio added inline comments to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Jul 30 2018, 5:03 AM
dnsampaio added a comment to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

As we are replacing all the uses of the DeadAnd, it is not required to create and replace the visiting Or operation. Replace all uses does the job already.

Jul 30 2018, 4:58 AM
dnsampaio added inline comments to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Jul 30 2018, 2:23 AM
dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Replaces all uses of the innermost and with the new shift.

Jul 30 2018, 2:23 AM

Jul 25 2018

dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Jul 25 2018, 8:15 AM
dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Relaxed conditions for which the transformation is applied.
Added more tests for ashr.

Jul 25 2018, 4:53 AM

Jul 24 2018

dnsampaio added inline comments to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Jul 24 2018, 9:19 AM
dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Removed unused arguments.
Early exit.

Jul 24 2018, 9:16 AM
dnsampaio added inline comments to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Jul 24 2018, 9:14 AM
dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

All required values are obtained during the pattern matching.

Jul 24 2018, 8:37 AM
dnsampaio added inline comments to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Jul 24 2018, 8:36 AM
dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Moved to a separated function. Placed function call after knowing more about the operands.
Added ashr case, that was being wrongly treated as lshr.
Added comments, including one that argues that this function would be useless if and instructions are move before any type of shift operations.
Using m_c_Or, and passing operands as arguments.

Jul 24 2018, 4:55 AM
dnsampaio added a comment to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Did most fixes. Just don't how to capture non-leaf nodes of the pattern being matched. Using other match operations would actually be more complicated than just passing the operands as arguments to the new function, now that I already know they are AND operations due the function call placement.

Jul 24 2018, 4:50 AM

Jul 20 2018

dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Jul 20 2018, 6:16 AM
dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Detect desired pattern from the binary operation using the results.

Jul 20 2018, 6:09 AM
dnsampaio added a comment to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
  1. Please always upload all patches with the full context (-U99999)

Sorry, I thought that it being an entire function it wouldn't matter. Lesson learned.

Jul 20 2018, 1:53 AM

Jul 17 2018

dnsampaio updated the diff for D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

Added context.

Jul 17 2018, 12:11 AM

Jul 16 2018

dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Using hasNUses() instead of numUses() ==

Jul 16 2018, 3:28 AM

Jul 14 2018

dnsampaio added inline comments to D48278: [SelectionDAG] Fold redundant masking operations of shifted value.
Jul 14 2018, 2:24 PM
dnsampaio updated the diff for D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

Replaced num_uses by !hasNUsesOfValue as requested.

Jul 14 2018, 2:23 PM

Jul 13 2018

dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Moved test to correct folder

Jul 13 2018, 7:18 AM
dnsampaio updated the diff for D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

Only accepts instructions with 2 uses (AND / SHIFT operations). So that looping through the uses is not expensive, and we avoid it in most cases.
Removed recursive bit value computations(computeKnownBits).

Jul 13 2018, 6:59 AM
dnsampaio added a comment to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Fixed execution costs. See below.

Jul 13 2018, 1:34 AM
dnsampaio updated the diff for D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

Constrain to allow the transformation to happen only when the masked value has only 2 users (an AND and a SHIFT).
Removed value tracking operations.

Jul 13 2018, 1:11 AM
dnsampaio added a comment to D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

It reduces the number of computation operations, from 3 to 2, and the number of constants kept int constants for performing the masking, from 2 to 1.
I don't see how it increases the latency. If you are going to perform the masking and the shift anyway.

Ah, I see that now. But I'm not convinced this is the right approach. Why are we waiting to optimize this in the backend? This is a universally good optimization, so it should be in IR:
https://rise4fun.com/Alive/O04

I'm not sure exactly where that optimization belongs. Ie, is it EarlyCSE, GVN, somewhere else, or is it its own pass? But I don't see any benefit in waiting to do this in the DAG.

This also raises a question that has come up in another review recently - D41233. If we reverse the canonicalization of shl+and, we would solve the most basic case that I showed above:

define i32 @shl_first(i32 %a {
  %t2 = shl i32 %a, 8
  %t3 = and i32 %t2, 44032
  ret i32 %t3
}

define i32 @mask_first(i32 %a) {
  %a2 = and i32 %a, 172
  %a3 = shl i32 %a2, 8
  ret i32 %a3
}
Jul 13 2018, 1:00 AM

Jul 12 2018

dnsampaio created D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Jul 12 2018, 5:44 AM

Jul 11 2018

dnsampaio committed rL336800: [NFC][InstCombine] Converts isLegalNarrowLoad into isLegalNarrowLdSt.
[NFC][InstCombine] Converts isLegalNarrowLoad into isLegalNarrowLdSt
Jul 11 2018, 6:04 AM
dnsampaio closed D48624: [NFC][SelectionDAG] Extending Load width reduction tests to Load and Store.
Jul 11 2018, 6:04 AM

Jul 9 2018

dnsampaio added a reviewer for D48278: [SelectionDAG] Fold redundant masking operations of shifted value: thakis.
Jul 9 2018, 11:47 PM
dnsampaio added a comment to D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

Ah, I see that now. But I'm not convinced this is the right approach. Why are we waiting to optimize this in the backend? This is a universally good optimization, so it should be in IR:

Agree, I also intend to implement this transformation in the IR. But there are cases that this is only seen after some instructions have been combined in the dag, so why not here also? And indeed, it is a requirement for a future patch that detects opportunities to reduce load and store widths.

Jul 9 2018, 7:24 AM
dnsampaio updated the diff for D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

Added checks for shift opcodes as to early exit if not found.
Validate mask widths (although it would be a error in the code if they are of different).

Jul 9 2018, 7:21 AM
dnsampaio added a comment to D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

Like @spatel I'm not clear on what you're really trying to accomplish here - has the arm/arm64 codegen improved?

Jul 9 2018, 3:47 AM
dnsampaio added a comment to D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

This patch was reverted with rL336453 because it caused:
https://bugs.llvm.org/show_bug.cgi?id=38084

Sorry about that.

Beyond that, I don't understand the motivation. The patch increases the latency of a computation. Why is that beneficial? The x86 diff doesn't look like a win to me.

It reduces the number of computation operations, from 3 to 2, and the number of constants kept for performing the masking, from 2 to 1.
I don't see how it increases the latency. If you are going to perform the masking and the shift anyway.

I don't know what the ARM/AArch output looked like before this patch. Always check in the baseline tests before making a code change, so we have that as a reference (and in case the patch is reverted, we won't lose the test coverage that motivated the code patch).

Jul 9 2018, 3:36 AM

Jul 6 2018

dnsampaio committed rL336440: Commit rL336426 cause buildbot failures.
Commit rL336426 cause buildbot failures
Jul 6 2018, 7:46 AM
dnsampaio added a comment to rL336426: [SelectionDAG] https://reviews.llvm.org/D48278.

One bot is failing in the test CodeGen/AArch64/FoldRedundantShiftedMasking.ll
I'm trying to figure out why as it doesn't happen with my debug or release builds.

Jul 6 2018, 7:16 AM
dnsampaio committed rL336428: Added missing semicolon.
Added missing semicolon
Jul 6 2018, 3:14 AM
dnsampaio added an edge to rL336426: [SelectionDAG] https://reviews.llvm.org/D48278: D48278: [SelectionDAG] Fold redundant masking operations of shifted value.
Jul 6 2018, 2:50 AM
dnsampaio added 1 commit(s) for D48278: [SelectionDAG] Fold redundant masking operations of shifted value: rL336426: [SelectionDAG] https://reviews.llvm.org/D48278.
Jul 6 2018, 2:50 AM
dnsampaio committed rL336426: [SelectionDAG] https://reviews.llvm.org/D48278.
[SelectionDAG] https://reviews.llvm.org/D48278
Jul 6 2018, 2:47 AM

Jul 5 2018

dnsampaio committed rL336384: Testing commit permision.
Testing commit permision
Jul 5 2018, 11:54 AM
dnsampaio updated the diff for D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

Give patch more context.

Jul 5 2018, 6:16 AM
dnsampaio updated the diff for D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

AArch64 tests go into the folder AArch64

Jul 5 2018, 6:15 AM
dnsampaio raised a concern with rL336268: NFC - Various typo fixes in tests.

Please see
https://bugs.llvm.org/show_bug.cgi?id=38061

Jul 5 2018, 1:24 AM

Jul 4 2018

dnsampaio updated the diff for D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

Replaced tests as to be not dependent in the load width reduction.
Added 1 positive test per case, and 2 negative tests, one where one mask is not a constant and other the shifted amount is not constant.

Jul 4 2018, 9:00 AM
dnsampaio removed a dependent revision for D46749: [SelectionDAG]Reduce masked data movement chains and memory access widths: D48278: [SelectionDAG] Fold redundant masking operations of shifted value.
Jul 4 2018, 8:47 AM
dnsampaio removed a dependency for D48278: [SelectionDAG] Fold redundant masking operations of shifted value: D46749: [SelectionDAG]Reduce masked data movement chains and memory access widths.
Jul 4 2018, 8:47 AM
dnsampaio accepted D48439: [NEON] Support vldNq intrinsics in AArch32 (LLVM part).

All good.

Jul 4 2018, 8:33 AM
dnsampaio accepted D48920: [NEON] Fix combining of vldx_dup intrinsics with updating of base addresses.

Seems good to me.

Jul 4 2018, 3:56 AM
dnsampaio added a comment to D48920: [NEON] Fix combining of vldx_dup intrinsics with updating of base addresses.

Hi Ivan,
The patch fixes the crash, but I would like to know if the desired updates aren't already done, just needing to copy paste them?
Cheers
Diogo

Jul 4 2018, 2:25 AM

Jul 3 2018

dnsampaio requested changes to D48439: [NEON] Support vldNq intrinsics in AArch32 (LLVM part).

Please add the new intrinsics to the target specific combine function of VLDUP NEON load/store intrinsics
ARMISelLowering.cpp, line 11477. The switch dies on llvm_unreachable.

Jul 3 2018, 4:48 AM
dnsampaio reopened D48439: [NEON] Support vldNq intrinsics in AArch32 (LLVM part).
Jul 3 2018, 4:44 AM

Jun 27 2018

dnsampaio updated the diff for D48624: [NFC][SelectionDAG] Extending Load width reduction tests to Load and Store.

Removed flag as requested.

Jun 27 2018, 4:13 AM
dnsampaio created D48624: [NFC][SelectionDAG] Extending Load width reduction tests to Load and Store.
Jun 27 2018, 1:38 AM

Jun 18 2018

dnsampaio edited dependencies for D47730: [SelectionDAG]Reduce masked data movement chains and memory access widths pt3, added: 1; removed: 1.
Jun 18 2018, 5:36 AM · Restricted Project