[ARM] Add ARMv8.6 Fine Grain Traps system registers

[stuij]

Summary

This patch upstreams support for the ARMv8.6A Fine Grain Traps (FGT)
extension, which adds 5 new system registers.

See ARMv8.6-FGT in the Arm Architecture Reference Manual Armv8 for more
information.

[SjoerdMeijer]

LGTM, with one nit that doesn't need another review.

llvm/test/MC/AArch64/armv8.6a-fgt.s

6

nit: perhaps good to see some other X-registers being used here than only x0.

[stuij]

don't just test x0

llvm/lib/Target/AArch64/AArch64.td

 def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
     "AllowTaggedGlobals",
     "true", "Use an instruction sequence for taking the address of a global "
     "that allows a memory tag in the upper address bits">;
 
 def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
     "true", "Enable BFloat16 Extension" >;
 
+def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
+    "true", "Enable fine grained virtualization traps extension">;
+
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
   FeaturePAN, FeatureLOR, FeatureVH]>;
 

 def HasV8_5aOps : SubtargetFeature<
   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
    FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
    FeatureBranchTargetId]>;
 
 def HasV8_6aOps : SubtargetFeature<
   "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
-  [HasV8_5aOps, FeatureAMVS, FeatureBF16]>;
+
+  [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AArch64RegisterInfo.td"
 include "AArch64RegisterBanks.td"
 include "AArch64CallingConvention.td"

llvm/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasBTI = false;
   bool HasRandGen = false;
   bool HasMTE = false;
   bool HasTME = false;
 
   // Armv8.6-A Extensions
   bool HasBF16 = false;
   bool HasAMVS = false;
+  bool HasFineGrainedTraps = false;
 
   // Arm SVE2 extensions
   bool HasSVE2AES = false;
   bool HasSVE2SM4 = false;
   bool HasSVE2SHA3 = false;
   bool HasSVE2BitPerm = false;
 
   // Future architecture extensions.
public:
   // Arm SVE2 extensions
   bool hasSVE2AES() const { return HasSVE2AES; }
   bool hasSVE2SM4() const { return HasSVE2SM4; }
   bool hasSVE2SHA3() const { return HasSVE2SHA3; }
   bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
 
   // Armv8.6-A Extensions
   bool hasBF16() const { return HasBF16; }
+  bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
 
   bool isLittleEndian() const { return IsLittle; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
   bool isTargetIOS() const { return TargetTriple.isiOS(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }

llvm/lib/Target/AArch64/AArch64SystemOperands.td

def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2",
     0b11, 0b100, 0b1101, 0b1000, 0b000>{
       let Encoding{4} = x;
       let Encoding{3-0} = n;
     }
   }
 }
 }
 
+// v8.6a Fine Grained Virtualization Traps
+//                                 Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in {
+def : RWSysReg<"HFGRTR_EL2",       0b11, 0b100, 0b0001, 0b0001, 0b100>;
+def : RWSysReg<"HFGWTR_EL2",       0b11, 0b100, 0b0001, 0b0001, 0b101>;
+def : RWSysReg<"HFGITR_EL2",       0b11, 0b100, 0b0001, 0b0001, 0b110>;
+def : RWSysReg<"HDFGRTR_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b100>;
+def : RWSysReg<"HDFGWTR_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b101>;
+}
+
 // Cyclone specific system registers
 //                                 Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::ProcAppleA7} }] in
 def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;

llvm/test/MC/AArch64/armv8.6a-fgt.s

+// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+fgt   < %s | FileCheck %s
+// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding  < %s 2>&1         | FileCheck %s --check-prefix=NOFGT
+
+msr HFGRTR_EL2, x0
+msr HFGWTR_EL2, x5
+msr HFGITR_EL2, x10
+msr HDFGRTR_EL2, x15
+msr HDFGWTR_EL2, x20
+// CHECK: msr     HFGRTR_EL2, x0          // encoding: [0x80,0x11,0x1c,0xd5]
+// CHECK: msr     HFGWTR_EL2, x5          // encoding: [0xa5,0x11,0x1c,0xd5]
+// CHECK: msr     HFGITR_EL2, x10         // encoding: [0xca,0x11,0x1c,0xd5]
+// CHECK: msr     HDFGRTR_EL2, x15        // encoding: [0x8f,0x31,0x1c,0xd5]
+// CHECK: msr     HDFGWTR_EL2, x20        // encoding: [0xb4,0x31,0x1c,0xd5]
+// NOFGT: error: expected writable system register or pstate
+// NOFGT: error: expected writable system register or pstate
+// NOFGT: error: expected writable system register or pstate
+// NOFGT: error: expected writable system register or pstate
+// NOFGT: error: expected writable system register or pstate
+
+mrs x30,  HFGRTR_EL2
+mrs x25,  HFGWTR_EL2
+mrs x20,  HFGITR_EL2
+mrs x15,  HDFGRTR_EL2
+mrs x10,  HDFGWTR_EL2
+// CHECK: mrs     x30, HFGRTR_EL2         // encoding: [0x9e,0x11,0x3c,0xd5]
+// CHECK: mrs     x25, HFGWTR_EL2         // encoding: [0xb9,0x11,0x3c,0xd5]
+// CHECK: mrs     x20, HFGITR_EL2         // encoding: [0xd4,0x11,0x3c,0xd5]
+// CHECK: mrs     x15, HDFGRTR_EL2        // encoding: [0x8f,0x31,0x3c,0xd5]
+// CHECK: mrs     x10, HDFGWTR_EL2        // encoding: [0xaa,0x31,0x3c,0xd5]
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register

llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt

+# RUN: llvm-mc -triple=aarch64  -mattr=+fgt -disassemble < %s      | FileCheck %s
+# RUN: llvm-mc -triple=aarch64              -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOFGT
+
+[0x80,0x11,0x1c,0xd5]
+[0xa0,0x11,0x1c,0xd5]
+[0xc0,0x11,0x1c,0xd5]
+[0x80,0x31,0x1c,0xd5]
+[0xa0,0x31,0x1c,0xd5]
+
+# CHECK: msr HFGRTR_EL2, x0
+# CHECK: msr HFGWTR_EL2, x0
+# CHECK: msr HFGITR_EL2, x0
+# CHECK: msr HDFGRTR_EL2, x0
+# CHECK: msr HDFGWTR_EL2, x0
+# NOFGT: msr S3_4_C1_C1_4, x0
+# NOFGT: msr S3_4_C1_C1_5, x0
+# NOFGT: msr S3_4_C1_C1_6, x0
+# NOFGT: msr S3_4_C3_C1_4, x0
+# NOFGT: msr S3_4_C3_C1_5, x0
+
+[0x80,0x11,0x3c,0xd5]
+[0xa0,0x11,0x3c,0xd5]
+[0xc0,0x11,0x3c,0xd5]
+[0x80,0x31,0x3c,0xd5]
+[0xa0,0x31,0x3c,0xd5]
+
+# CHECK: mrs x0, HFGRTR_EL2
+# CHECK: mrs x0, HFGWTR_EL2
+# CHECK: mrs x0, HFGITR_EL2
+# CHECK: mrs x0, HDFGRTR_EL2
+# CHECK: mrs x0, HDFGWTR_EL2
+# NOFGT: mrs x0, S3_4_C1_C1_4
+# NOFGT: mrs x0, S3_4_C1_C1_5
+# NOFGT: mrs x0, S3_4_C1_C1_6
+# NOFGT: mrs x0, S3_4_C3_C1_4
+# NOFGT: mrs x0, S3_4_C3_C1_5