[SVE] Generate overloaded functions for ACLE intrinsics.

[sdesmalen]

Summary

The SVE ACLE allows using a short-form for the intrinsics, e.g.
the following two declarations generate the same code:

  
svuint32_t svld1(svbool_t, uint32_t const *);
svuint32_t svld1_u32(svbool_t, uint32_t const *);

using the attribute:

__clang_arm_builtin_alias

so that any call to svld1(svbool_t, uint32_t const *) will
map to __builtin_sve_svld1_u32.

[sdesmalen]

• Rebased patch on top of D75850.
• Removed __clang_arm_sve_alias in favour of __clang_arm_builtin_alias

[miyuki]

clang/lib/Sema/SemaDeclAttr.cpp

5004–5005

I would suggest splitting the check into Arm-specific and AArch64-specific checks to speed things up (if it is easy to get the current target arch in this context).

[sdesmalen]

• Refactored condition to check for valid builtins (split up checks for Arm and AArch64)

[miyuki]

The clang attribute part LGTM, but I want someone else to check the rest.

[SjoerdMeijer]

clang/include/clang/Basic/Attr.td

363

nit: don't thin we use underscores in names, and looking at examples below, I guess this should be TargetAnyARM

clang/utils/TableGen/SveEmitter.cpp

103

nit: add a comment here too (for consistency)

625–626

Unrelated to this change, I just spotted it because it looked a bit messy, but is this the old copyright header? While we are at it, replace this with the new one? Looks like e.g. in arm_mve.h, we do use the new one.

[SjoerdMeijer]

With the nit addressed, this LGTM

clang/utils/TableGen/SveEmitter.cpp

625–626

Let's ignore this for now, we can fix this later if needed.

[sdesmalen]

Addressed review comments before commititng. Thanks for the review @miyuki and @SjoerdMeijer!

clang/include/clang/Basic/Attr.td

class TargetSpec {
   //   const llvm::Triple &T = Target.getTriple();
   code CustomCode = [{}];
 }
 
 class TargetArch<list<string> arches> : TargetSpec {
   let Arches = arches;
 }
 def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>;
+def TargetAArch64 : TargetArch<["aarch64"]>;
+def TargetAnyArm : TargetArch<!listconcat(TargetARM.Arches, TargetAArch64.Arches)>;
 def TargetAVR : TargetArch<["avr"]>;
 def TargetBPF : TargetArch<["bpfel", "bpfeb"]>;
 def TargetMips32 : TargetArch<["mips", "mipsel"]>;
 def TargetAnyMips : TargetArch<["mips", "mipsel", "mips64", "mips64el"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
 def TargetRISCV : TargetArch<["riscv32", "riscv64"]>;
 def TargetX86 : TargetArch<["x86"]>;
 def TargetAnyX86 : TargetArch<["x86", "x86_64"]>;

 
 def Alias : Attr {
   let Spellings = [GCC<"alias">];
   let Args = [StringArgument<"Aliasee">];
   let Subjects = SubjectList<[Function, GlobalVar], ErrorDiag>;
   let Documentation = [Undocumented];
 }
 
-def ArmBuiltinAlias : InheritableAttr, TargetSpecificAttr<TargetARM> {
+def ArmBuiltinAlias : InheritableAttr, TargetSpecificAttr<TargetAnyArm> {
   let Spellings = [Clang<"__clang_arm_builtin_alias">];
   let Args = [IdentifierArgument<"BuiltinName">];
   let Subjects = SubjectList<[Function], ErrorDiag>;
   let Documentation = [ArmBuiltinAliasDocs];
 }
 
 def Aligned : InheritableAttr {
   let Spellings = [GCC<"aligned">, Declspec<"align">, Keyword<"alignas">,

clang/lib/Sema/SemaDeclAttr.cpp

#include "clang/Basic/arm_mve_builtin_aliases.inc"
   return ArmBuiltinAliasValid(BuiltinID, AliasName, Map, IntrinNames);
 }
 
 static bool ArmCdeAliasValid(unsigned BuiltinID, StringRef AliasName) {
 #include "clang/Basic/arm_cde_builtin_aliases.inc"
   return ArmBuiltinAliasValid(BuiltinID, AliasName, Map, IntrinNames);
 }
 
+static bool ArmSveAliasValid(unsigned BuiltinID, StringRef AliasName) {
+  switch (BuiltinID) {
+  default:
+    return false;
+#define GET_SVE_BUILTINS
+#define BUILTIN(name, types, attr) case SVE::BI##name:
+#include "clang/Basic/arm_sve_builtins.inc"
+    return true;
+  }
+}
+
 static void handleArmBuiltinAliasAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
   if (!AL.isArgIdent(0)) {
     S.Diag(AL.getLoc(), diag::err_attribute_argument_n_type)
         << AL << 1 << AANT_ArgumentIdentifier;
     return;
   }
 
   IdentifierInfo *Ident = AL.getArgAsIdent(0)->Ident;
   unsigned BuiltinID = Ident->getBuiltinID();
   StringRef AliasName = cast<FunctionDecl>(D)->getIdentifier()->getName();
 
-  if (!ArmMveAliasValid(BuiltinID, AliasName) &&
-      !ArmCdeAliasValid(BuiltinID, AliasName)) {
+  bool IsAArch64 = S.Context.getTargetInfo().getTriple().isAArch64();
+  if ((IsAArch64 && !ArmSveAliasValid(BuiltinID, AliasName)) ||
+      (!IsAArch64 && !ArmMveAliasValid(BuiltinID, AliasName) &&
+       !ArmCdeAliasValid(BuiltinID, AliasName))) {
     S.Diag(AL.getLoc(), diag::err_attribute_arm_builtin_alias);
     return;
   }
 
   D->addAttr(::new (S.Context) ArmBuiltinAliasAttr(S.Context, AL, Ident));
 }
 
 //===----------------------------------------------------------------------===//

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1_shortform.c

+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s -D__ARM_FEATURE_SVE | FileCheck %s
+
+#include <arm_sve.h>
+//
+// ld1
+//
+
+svint8_t test_svld1_s8(svbool_t pg, const int8_t *base)
+{
+  // CHECK-LABEL: test_svld1_s8
+  // CHECK: <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %{{.*}}, i32 1, <vscale x 16 x i1> %{{.*}}, <vscale x 16 x i8> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svint16_t test_svld1_s16(svbool_t pg, const int16_t *base)
+{
+  // CHECK-LABEL: test_svld1_s16
+  // CHECK: <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0nxv8i16(<vscale x 8 x i16>* %{{.*}}, i32 1, <vscale x 8 x i1> %{{.*}}, <vscale x 8 x i16> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svint32_t test_svld1_s32(svbool_t pg, const int32_t *base)
+{
+  // CHECK-LABEL: test_svld1_s32
+  // CHECK: <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %{{.*}}, i32 1, <vscale x 4 x i1> %{{.*}}, <vscale x 4 x i32> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svint64_t test_svld1_s64(svbool_t pg, const int64_t *base)
+{
+  // CHECK-LABEL: test_svld1_s64
+  // CHECK: <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* %{{.*}}, i32 1, <vscale x 2 x i1> %{{.*}}, <vscale x 2 x i64> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svuint8_t test_svld1_u8(svbool_t pg, const uint8_t *base)
+{
+  // CHECK-LABEL: test_svld1_u8
+  // CHECK: <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %{{.*}}, i32 1, <vscale x 16 x i1> %{{.*}}, <vscale x 16 x i8> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svuint16_t test_svld1_u16(svbool_t pg, const uint16_t *base)
+{
+  // CHECK-LABEL: test_svld1_u16
+  // CHECK: <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0nxv8i16(<vscale x 8 x i16>* %{{.*}}, i32 1, <vscale x 8 x i1> %{{.*}}, <vscale x 8 x i16> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svuint32_t test_svld1_u32(svbool_t pg, const uint32_t *base)
+{
+  // CHECK-LABEL: test_svld1_u32
+  // CHECK: <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %{{.*}}, i32 1, <vscale x 4 x i1> %{{.*}}, <vscale x 4 x i32> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svuint64_t test_svld1_u64(svbool_t pg, const uint64_t *base)
+{
+  // CHECK-LABEL: test_svld1_u64
+  // CHECK: <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* %{{.*}}, i32 1, <vscale x 2 x i1> %{{.*}}, <vscale x 2 x i64> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svfloat16_t test_svld1_f16(svbool_t pg, const float16_t *base)
+{
+  // CHECK-LABEL: test_svld1_f16
+  // CHECK: <vscale x 8 x half> @llvm.masked.load.nxv8f16.p0nxv8f16(<vscale x 8 x half>* %{{.*}}, i32 1, <vscale x 8 x i1> %{{.*}}, <vscale x 8 x half> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svfloat32_t test_svld1_f32(svbool_t pg, const float32_t *base)
+{
+  // CHECK-LABEL: test_svld1_f32
+  // CHECK: <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0nxv4f32(<vscale x 4 x float>* %{{.*}}, i32 1, <vscale x 4 x i1> %{{.*}}, <vscale x 4 x float> zeroinitializer)
+  return svld1(pg, base);
+}
+
+svfloat64_t test_svld1_f64(svbool_t pg, const float64_t *base)
+{
+  // CHECK-LABEL: test_svld1_f64
+  // CHECK: <vscale x 2 x double> @llvm.masked.load.nxv2f64.p0nxv2f64(<vscale x 2 x double>* %{{.*}}, i32 1, <vscale x 2 x i1> %{{.*}}, <vscale x 2 x double> zeroinitializer)
+  return svld1(pg, base);
+}

clang/utils/TableGen/SveEmitter.cpp

public:
   unsigned getSizeInBits() const {
     return Bitwidth;
   }
 
   /// Return the string representation of a type, which is an encoded
   /// string for passing to the BUILTIN() macro in Builtins.def.
   std::string builtin_str() const;
 
+  /// Return the C/C++ string representation of a type for use in the
+  /// arm_sve.h header file.
+  std::string str() const;
+
 private:
   /// Creates the type based on the typespec string in TS.
   void applyTypespec();
 
   /// Applies a prototype modifier to the type.
   void applyModifier(char Mod);
 };
 
if (isScalar()) {
     if (Pointer) S += "*";
     return S;
   }
 
   assert(isScalableVector() && "Unsupported type");
   return "q" + utostr(getNumElements() * NumVectors) + S;
 }
 
+std::string SVEType::str() const {
+  if (isPredicatePattern())
+    return "sv_pattern";
+
+  if (isPrefetchOp())
+    return "sv_prfop";
+
+  std::string S;
+  if (Void)
+    S += "void";
+  else {
+    if (isScalableVector())
+      S += "sv";
+    if (!Signed && !Float)
+      S += "u";
+
+    if (Float)
+      S += "float";
+    else if (isScalarPredicate())
+      S += "bool";
+    else
+      S += "int";
+
+    if (!isScalarPredicate())
+      S += utostr(ElementBitwidth);
+    if (!isScalableVector() && isVector())
+      S += "x" + utostr(getNumElements());
+    if (NumVectors > 1)
+      S += "x" + utostr(NumVectors);
+    S += "_t";
+  }
+
+  if (Constant)
+    S += " const";
+  if (Pointer)
+    S += " *";
+
+  return S;
+}
 void SVEType::applyTypespec() {
   for (char I : TS) {
     switch (I) {
     case 'P':
       Predicate = true;
       ElementBitwidth = 1;
       break;
     case 'U':

 
 void Intrinsic::emitIntrinsic(raw_ostream &OS) const {
   // Use the preprocessor to 
   if (getClassKind() != ClassG || getProto().size() <= 1) {
     OS << "#define " << mangleName(getClassKind())
        << "(...) __builtin_sve_" << mangleName(ClassS)
        << "(__VA_ARGS__)\n";
   } else {
-    llvm_unreachable("Not yet implemented. Overloaded intrinsics will follow "
-                     "in a future patch");
+    std::string FullName = mangleName(ClassS);
+    std::string ProtoName = mangleName(ClassG);
+
+    OS << "__aio __attribute__((__clang_arm_builtin_alias("
+       << "__builtin_sve_" << FullName << ")))\n";
+
+    OS << getTypes()[0].str() << " " << ProtoName << "(";
+    for (unsigned I = 0; I < getTypes().size() - 1; ++I) {
+      if (I != 0)
+        OS << ", ";
+      OS << getTypes()[I + 1].str();
+    }
+    OS << ");\n";
   }
 }
 
 //===----------------------------------------------------------------------===//
 // SVEEmitter implementation
 //===----------------------------------------------------------------------===//
 void SVEEmitter::createIntrinsic(
     Record *R, SmallVectorImpl<std::unique_ptr<Intrinsic>> &Out) {
void SVEEmitter::createIntrinsic(
   TypeSpecs.erase(std::unique(TypeSpecs.begin(), TypeSpecs.end()),
                   TypeSpecs.end());
 
   // Create an Intrinsic for each type spec.
   for (auto TS : TypeSpecs) {
     Out.push_back(std::make_unique<Intrinsic>(Name, Proto, Merge,
                                               LLVMName, Flags, TS, ClassS,
                                               *this, Guard));
+
+    // Also generate the short-form (e.g. svadd_m) for the given type-spec.
+    if (Intrinsic::isOverloadedIntrinsic(Name))
+      Out.push_back(std::make_unique<Intrinsic>(
+          Name, Proto, Merge, LLVMName, Flags, TS, ClassG, *this, Guard));
   }
 }
 
 void SVEEmitter::createHeader(raw_ostream &OS) {
   OS << "/*===---- arm_sve.h - ARM SVE intrinsics "
         "-----------------------------------===\n"
         " *\n"
         " *\n"
         " * Part of the LLVM Project, under the Apache License v2.0 with LLVM "
         "Exceptions.\n"
         " * See https://llvm.org/LICENSE.txt for license information.\n"
         " * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception\n"
         " *\n"
         " *===-----------------------------------------------------------------"
void SVEEmitter::createHeader(raw_ostream &OS) {
   OS << "typedef __SVUint16_t svuint16_t;\n";
   OS << "typedef __SVUint32_t svuint32_t;\n";
   OS << "typedef __SVUint64_t svuint64_t;\n";
   OS << "typedef __SVFloat16_t svfloat16_t;\n";
   OS << "typedef __SVFloat32_t svfloat32_t;\n";
   OS << "typedef __SVFloat64_t svfloat64_t;\n";
   OS << "typedef __SVBool_t  svbool_t;\n\n";
 
+  OS << "/* Function attributes */\n";
+  OS << "#define __aio static inline __attribute__((__always_inline__, "
+        "__nodebug__, __overloadable__))\n\n";
+
   SmallVector<std::unique_ptr<Intrinsic>, 128> Defs;
   std::vector<Record *> RV = Records.getAllDerivedDefinitions("Inst");
   for (auto *R : RV)
     createIntrinsic(R, Defs);
 
   // Sort intrinsics in header file by following order/priority:
   // - Architectural guard (i.e. does it require SVE2 or SVE2_AES)
   // - Class (is intrinsic overloaded or not)