Don't assume promotable integers are zero/sign-extended already in x86-64 ABI.

[emilio]

Summary

Sign-extension is not guaranteed by the ABI, and thus the callee cannot assume
it.

This fixes PR44228 and PR12207.

With these changes, there are still two tests that need updating:

• CodeGenObjC/optimized-setter.m fails with:

clang: llvm/lib/IR/Instructions.cpp:400: void llvm::CallInst::init(llvm::FunctionType *, llvm::Value *, ArrayRef<llvm::Value *>, ArrayRef<llvm::OperandBundleDef>, const llvm::Twine &): Assertion `(i >= FTy->getNumParams() || FTy->getParamType(i) == Args[i]->getType()) && "Calling a function with a bad signature!"' failed.

• OpenMP/parallel_for_simd_codegen.cpp fails with:

clang: clang/lib/CodeGen/CGCall.cpp:3858: clang::CodeGen::RValue clang::CodeGen::CodeGenFunction::EmitCall(const clang::CodeGen::CGFunctionInfo &, const clang::CodeGen::CGCallee &, clang::CodeGen::ReturnValueSlot, const clang::CodeGen::CallArgList &, llvm::CallBase **, clang::SourceLocation): Assertion `IRFuncTy == TypeFromVal' failed.

These two are probably bad assumptions in some of the ObjC / OpenMP-specific
code, but I want to check this patch is on the right track before digging more.

[lebedev.ri]

Sign-extension is not guaranteed by the ABI, and thus the callee cannot assume it.

This is a bit too vague.
Can you quote specific parts of the appropriate standard/document?

[emilio]

The relevant discussion is here. From the "Parameter Passing" section in https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-1.0.pdf, there's no mention of sign-extension requirements for arguments.

The only related thing is
"When a value of type _Bool is returned or passed in a register or on the stack,
bit 0 contains the truth value and bits 1 to 7 shall be zero."
with a footnote:
"Other bits are left unspecified, hence the consumer side of those values can rely on it being 0 or 1 when truncated to 8 bit."

which says that _Bool has only significant low 8 bits and the rest is unspecified.

Then Michael Matz (one of the editors of that document) clarifies below:

Yes, we (intentionally) haven't required any extensions to happen for arguments

or return values smaller than 64bit (e.g. we haven't even specified that arguments <= 32bit would be zero-extended in the high bits, as would have been
natural with the instruction set). If LLVM relies on that it would be a bug.

There's more information on that bug and related ones, but I think the above should be enough :)

[rnk]

+@chandlerc @rjmccall

Didn't we work this out already when John added the alignment tracking stuff? I remember this bug involving libjpegturbo standalone assembly receiving a 32-bit argument, and then using the full 64-bit RDI register to read it, but clang stopped zero extending it. I thought the ABI doc was ambiguous at the time, and we studied GCC's behavior, and that is how we arrived at clang's current behavior. I am generally skeptical about changing behavior in this area just because the ABI doc says something now. It keeps changing. What did it say in the past? Shouldn't we pay more attention to that?

Found the libjpegturbo thing:
https://github.com/libjpeg-turbo/libjpeg-turbo/commit/498d9bc92fcf39124b6f08e57326944dedd2ddd6

[emilio]

In D72742#1822554, @rnk wrote:

+@chandlerc @rjmccall

Didn't we work this out already when John added the alignment tracking stuff? I remember this bug involving libjpegturbo standalone assembly receiving a 32-bit argument, and then using the full 64-bit RDI register to read it, but clang stopped zero extending it. I thought the ABI doc was ambiguous at the time, and we studied GCC's behavior, and that is how we arrived at clang's current behavior. I am generally skeptical about changing behavior in this area just because the ABI doc says something now. It keeps changing. What did it say in the past? Shouldn't we pay more attention to that?

Found the libjpegturbo thing:
https://github.com/libjpeg-turbo/libjpeg-turbo/commit/498d9bc92fcf39124b6f08e57326944dedd2ddd6

That seems somewhat related. This would be a similar change to the one that clang did back then, but for the bytes in the lower 32-bits when the argument is smaller than that.

The ABI document, afaict, has never defined the inputs to be zero-extended. See https://groups.google.com/forum/?hl=en#!topic/x86-64-abi/E8O33onbnGQ for an old thread discussing this, and the two bugs that are referenced in the commit message (one of them fairly old).

GCC does avoid the zero-extension on the caller sometimes, when not required by the language and when its optimizer finds it suitable.

[rnk]

In D72742#1822709, @emilio wrote:

GCC does avoid the zero-extension on the caller sometimes, when not required by the language and when its optimizer finds it suitable.

I believe at the time, faced with ambiguity in the document, experiments were done to try to uncover what GCC actually did in practice. I guess LLVM settled on the "things are extended to 32-bits" model.

This change seems like it has backwards compatibility concerns with clang. If new clang stops extending things and it calls old clang code, won't that cause breakages? Based on the test code updates, it seems like you are updating both call sites and function prototypes. Won't that be problematic for the users that care about ABI stability over GCC ABI compatibility?

clang/test/CodeGen/2007-06-18-SextAttrAggregate.c

11

This test was originally added for x86_64, see the bug:
https://bugs.llvm.org/show_bug.cgi?id=1513

It needs to be updated.

clang/test/CodeGenCXX/const-init-cxx11.cpp

536

I agree it would be nice to avoid emitting these coercions through memory for such simple cases.

[rjmccall]

Didn't we work this out already when John added the alignment tracking stuff? I remember this bug involving libjpegturbo standalone assembly receiving a 32-bit argument, and then using the full 64-bit RDI register to read it, but clang stopped zero extending it.

So, this is complicated. LLVM IR's zext/sext representation is not explicit about the width to which types are extended. Per the language reference, the choice of extension width is at least target-specific, and I say "at least" because nothing is obviously stopping it from also being type-specific; that is, in theory i1 zeroext could mean an extension to 8-bit but i8 zeroext could mean an extension to 32-bit or beyond. The use of isPromotableIntegerType() here means that this only applies to integer types of lower rank than int, which on x86_64 are all 16-bit or less; that apparently embeds an assumption that the promotion width is 32-bit for this target. libjpegturbo was incorrectly assuming that a formally 32-bit argument was extended to the full 64-bit register width; obviously that's related to what we're talking about here, but it's not actually affected by the proposed patch.

Extending arguments to at least the width of int is necessary if you want unprototyped functions with small arguments to be callable through a prototype. The reverse isn't true, and no such concern applies to return types, so all in all I doubt that this was an influence on Clang's behavior. We should already be explicitly extending arguments to i32 when passing an unprototyped or non-required argument.

This change seems like it has backwards compatibility concerns with clang. If new clang stops extending things and it calls old clang code, won't that cause breakages? Based on the test code updates, it seems like you are updating both call sites and function prototypes. Won't that be problematic for the users that care about ABI stability over GCC ABI compatibility?

What defines the ABI for a particular target is also complicated. For established targets with binary-compatibility requirements, ABI is arguably best defined by what you're not willing to break compatibility with. Clang supports several targets for which the system compiler is not GCC, and therefore GCC's behavior is not particularly relevant to the discussion (for those targets). I suspect that at least PS4 would strongly object to an ABI change here, no matter what the ABI document says; I don't know about Darwin, BSD, etc. So I think it is going to be necessary to make this target-OS-specific.

For targets for which GCC clearly defines the ABI, though, I think we clearly need to take this change.

clang/test/CodeGenCXX/const-init-cxx11.cpp

536

In the short term, yes, we should update the code so that we don't need a coercion through memory to go from i1 to i8.

The right long-term change is that LLVM's zext/sext attributes should encode the width to which the value is extended.

[emilio]

Could anyone update me with how do they want me to proceed here? Is fixing the coercions enough to allow this to land? Do I need to make it target-specific? If so, which targets should keep the current behavior?

Another slightly more backwards-compatible alternative (though hacky, arguably) is to just not use the zext for optimization purposes in the backend. This would be simpler and should keep clang always sign-extending on the caller too, for now. We could then after a while, switch to this approach. D71178 contains such a patch, for comparison.

Thoughts?

[rjmccall]

In D72742#1854594, @emilio wrote:

Could anyone update me with how do they want me to proceed here? Is fixing the coercions enough to allow this to land? Do I need to make it target-specific?

It needs to be target-specific.

If so, which targets should keep the current behavior?

At least Darwin and PS4, maybe some others. BSD?

Another slightly more backwards-compatible alternative (though hacky, arguably) is to just not use the zext for optimization purposes in the backend. This would be simpler and should keep clang always sign-extending on the caller too, for now. We could then after a while, switch to this approach. D71178 contains such a patch, for comparison.

It wouldn't be unreasonable to have a way to request this behavior, but I'm not sure about switching to it for all zext / sext.

[jyknight]

I wrote some stuff on https://bugs.llvm.org/show_bug.cgi?id=44228, probably best to continue the discussion there. I really don't think we should take this patch -- at least not without reopening the ABI discussion first.

[lebedev.ri]

Passing-by remark: i'm not sure it was noted already,
but i believe that the function linkage should be differentiated here,
the ABI mismatch can only exist if the function can actually be called
from the external code, which isn't always the case.

clang/lib/CodeGen/TargetInfo.cpp

GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
   llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
 
   // Verify that the second element is at an 8-byte offset.
   assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
          "Invalid x86-64 argument pair!");
   return Result;
 }
 
-ABIArgInfo X86_64ABIInfo::
-classifyReturnType(QualType RetTy) const {
+ABIArgInfo X86_64ABIInfo::classifyReturnType(QualType RetTy) const {
   // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
   // classification algorithm.
   X86_64ABIInfo::Class Lo, Hi;
   classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
 
   // Check some invariants.
   assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
   assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
case X87Up:
     // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
     // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
     // and %r9 is used.
   case Integer:
     ++neededInt;
 
     // Pick an 8-byte type based on the preferred type.
     ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
-
-    // If we have a sign or zero extended integer, make sure to return Extend
-    // so that the parameter gets the right LLVM IR attributes.
-    if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
-      // Treat an enum type as its underlying type.
-      if (const EnumType *EnumTy = Ty->getAs<EnumType>())
-        Ty = EnumTy->getDecl()->getIntegerType();
-
-      if (Ty->isIntegralOrEnumerationType() &&
-          Ty->isPromotableIntegerType())
-        return ABIArgInfo::getExtend(Ty);
-    }
-
     break;
 
     // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
     // available SSE register is used, the registers are taken in the
     // order from %xmm0 to %xmm7.
   case SSE: {
     llvm::Type *IRType = CGT.ConvertType(Ty);
     ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);

clang/test/CodeGen/2007-06-18-SextAttrAggregate.c

 // RUN: %clang_cc1 %s -o - -emit-llvm | FileCheck %s
-// XFAIL: aarch64, arm64, x86_64-pc-windows-msvc, x86_64-w64-windows-gnu, x86_64-pc-windows-gnu
+// XFAIL: x86_64, aarch64, arm64, x86_64-pc-windows-msvc, x86_64-w64-windows-gnu, x86_64-pc-windows-gnu
 
 // PR1513
 
 // AArch64 ABI actually requires the reverse of what this is testing: the callee
 // does any extensions and remaining bits are unspecified.
 
 // Win64 ABI does expect extensions for type smaller than 64bits.
 
+// Same for AMD64's PSABI
+
 // Technically this test wasn't written to test that feature, but it's a
 // valuable check nevertheless.
 
 struct s{
 long a;
 long b;
 };
 
 void f(struct s a, char *b, signed char C) {
   // CHECK: i8 signext
 
 }

clang/test/CodeGen/avx512-reduceMinMaxIntrin.c

 // CHECK-NEXT:    store <2 x double> [[TMP21]], <2 x double>* [[__T8_I]], align 16
 // CHECK-NEXT:    [[TMP22:%.*]] = load <2 x double>, <2 x double>* [[__T8_I]], align 16
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <2 x double> [[TMP22]], i32 0
 // CHECK-NEXT:    ret double [[VECEXT_I]]
 double test_mm512_reduce_min_pd(__m512d __W){
   return _mm512_reduce_min_pd(__W); 
 }
 
-// CHECK-LABEL: define i64 @test_mm512_mask_reduce_max_epi64(i8 zeroext %__M, <8 x i64> %__W) #0 {
+// CHECK-LABEL: define i64 @test_mm512_mask_reduce_max_epi64(i8 %__M, <8 x i64> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__D_ADDR_I_I:%.*]] = alloca i64, align 8
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[__A_ADDR_I11_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__A_ADDR_I9_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__B_ADDR_I10_I:%.*]] = alloca <8 x i64>, align 64

 // CHECK-NEXT:    store <8 x i64> [[TMP41]], <8 x i64>* [[__T6_I]], align 64
 // CHECK-NEXT:    [[TMP42:%.*]] = load <8 x i64>, <8 x i64>* [[__T6_I]], align 64
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <8 x i64> [[TMP42]], i32 0
 // CHECK-NEXT:    ret i64 [[VECEXT_I]]
 long long test_mm512_mask_reduce_max_epi64(__mmask8 __M, __m512i __W){
   return _mm512_mask_reduce_max_epi64(__M, __W); 
 }
 
-// CHECK-LABEL: define i64 @test_mm512_mask_reduce_max_epu64(i8 zeroext %__M, <8 x i64> %__W) #0 {
+// CHECK-LABEL: define i64 @test_mm512_mask_reduce_max_epu64(i8 %__M, <8 x i64> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[__A_ADDR_I9_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__A_ADDR_I7_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__B_ADDR_I10_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__A_ADDR_I6_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__B_ADDR_I8_I:%.*]] = alloca <8 x i64>, align 64

 // CHECK-NEXT:    store <8 x i64> [[TMP32]], <8 x i64>* [[__T6_I]], align 64
 // CHECK-NEXT:    [[TMP33:%.*]] = load <8 x i64>, <8 x i64>* [[__T6_I]], align 64
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <8 x i64> [[TMP33]], i32 0
 // CHECK-NEXT:    ret i64 [[VECEXT_I]]
 unsigned long test_mm512_mask_reduce_max_epu64(__mmask8 __M, __m512i __W){
   return _mm512_mask_reduce_max_epu64(__M, __W); 
 }
 
-// CHECK-LABEL: define double @test_mm512_mask_reduce_max_pd(i8 zeroext %__M, <8 x double> %__W) #0 {
+// CHECK-LABEL: define double @test_mm512_mask_reduce_max_pd(i8 %__M, <8 x double> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca double, align 8
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <8 x double>, align 64
 // CHECK-NEXT:    [[__W2_ADDR_I_I:%.*]] = alloca <8 x double>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[__A_ADDR_I_I:%.*]] = alloca <8 x double>, align 64
 // CHECK-NEXT:    [[__A_ADDR_I10_I:%.*]] = alloca <2 x double>, align 16
 // CHECK-NEXT:    [[__B_ADDR_I11_I:%.*]] = alloca <2 x double>, align 16

 // CHECK-NEXT:    store <2 x double> [[TMP38]], <2 x double>* [[__T8_I]], align 16
 // CHECK-NEXT:    [[TMP39:%.*]] = load <2 x double>, <2 x double>* [[__T8_I]], align 16
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <2 x double> [[TMP39]], i32 0
 // CHECK-NEXT:    ret double [[VECEXT_I]]
 double test_mm512_mask_reduce_max_pd(__mmask8 __M, __m512d __W){
   return _mm512_mask_reduce_max_pd(__M, __W); 
 }
 
-// CHECK-LABEL: define i64 @test_mm512_mask_reduce_min_epi64(i8 zeroext %__M, <8 x i64> %__W) #0 {
+// CHECK-LABEL: define i64 @test_mm512_mask_reduce_min_epi64(i8 %__M, <8 x i64> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__D_ADDR_I_I:%.*]] = alloca i64, align 8
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[__A_ADDR_I11_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__A_ADDR_I9_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__B_ADDR_I10_I:%.*]] = alloca <8 x i64>, align 64

 // CHECK-NEXT:    store <8 x i64> [[TMP41]], <8 x i64>* [[__T6_I]], align 64
 // CHECK-NEXT:    [[TMP42:%.*]] = load <8 x i64>, <8 x i64>* [[__T6_I]], align 64
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <8 x i64> [[TMP42]], i32 0
 // CHECK-NEXT:    ret i64 [[VECEXT_I]]
 long long test_mm512_mask_reduce_min_epi64(__mmask8 __M, __m512i __W){
   return _mm512_mask_reduce_min_epi64(__M, __W); 
 }
 
-// CHECK-LABEL: define i64 @test_mm512_mask_reduce_min_epu64(i8 zeroext %__M, <8 x i64> %__W) #0 {
+// CHECK-LABEL: define i64 @test_mm512_mask_reduce_min_epu64(i8 %__M, <8 x i64> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__D_ADDR_I_I:%.*]] = alloca i64, align 8
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[__A_ADDR_I11_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__A_ADDR_I9_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__B_ADDR_I10_I:%.*]] = alloca <8 x i64>, align 64

 // CHECK-NEXT:    store <8 x i64> [[TMP41]], <8 x i64>* [[__T6_I]], align 64
 // CHECK-NEXT:    [[TMP42:%.*]] = load <8 x i64>, <8 x i64>* [[__T6_I]], align 64
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <8 x i64> [[TMP42]], i32 0
 // CHECK-NEXT:    ret i64 [[VECEXT_I]]
 long long test_mm512_mask_reduce_min_epu64(__mmask8 __M, __m512i __W){
   return _mm512_mask_reduce_min_epu64(__M, __W);
 }
 
-// CHECK-LABEL: define double @test_mm512_mask_reduce_min_pd(i8 zeroext %__M, <8 x double> %__W) #0 {
+// CHECK-LABEL: define double @test_mm512_mask_reduce_min_pd(i8 %__M, <8 x double> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca double, align 8
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <8 x double>, align 64
 // CHECK-NEXT:    [[__W2_ADDR_I_I:%.*]] = alloca <8 x double>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i8, align 1
 // CHECK-NEXT:    [[__A_ADDR_I_I:%.*]] = alloca <8 x double>, align 64
 // CHECK-NEXT:    [[__A_ADDR_I10_I:%.*]] = alloca <2 x double>, align 16
 // CHECK-NEXT:    [[__B_ADDR_I11_I:%.*]] = alloca <2 x double>, align 16

 // CHECK-NEXT:    store <4 x float> [[TMP32]], <4 x float>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[TMP33:%.*]] = load <4 x float>, <4 x float>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <4 x float> [[TMP33]], i32 0
 // CHECK-NEXT:    ret float [[VECEXT_I]]
 float test_mm512_reduce_min_ps(__m512 __W){
   return _mm512_reduce_min_ps(__W); 
 }
 
-// CHECK-LABEL: define i32 @test_mm512_mask_reduce_max_epi32(i16 zeroext %__M, <8 x i64> %__W) #0 {
+// CHECK-LABEL: define i32 @test_mm512_mask_reduce_max_epi32(i16 %__M, <8 x i64> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__S_ADDR_I_I:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <16 x i32>, align 64
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i16, align 2
 // CHECK-NEXT:    [[__A2_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__V1_ADDR_I14_I:%.*]] = alloca <2 x i64>, align 16
 // CHECK-NEXT:    [[__V2_ADDR_I15_I:%.*]] = alloca <2 x i64>, align 16

 // CHECK-NEXT:    store <4 x i32> [[TMP80]], <4 x i32>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[TMP81:%.*]] = load <4 x i32>, <4 x i32>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <4 x i32> [[TMP81]], i32 0
 // CHECK-NEXT:    ret i32 [[VECEXT_I]]
 int test_mm512_mask_reduce_max_epi32(__mmask16 __M, __m512i __W){
   return _mm512_mask_reduce_max_epi32(__M, __W); 
 }
 
-// CHECK-LABEL: define i32 @test_mm512_mask_reduce_max_epu32(i16 zeroext %__M, <8 x i64> %__W) #0 {
+// CHECK-LABEL: define i32 @test_mm512_mask_reduce_max_epu32(i16 %__M, <8 x i64> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i16, align 2
 // CHECK-NEXT:    [[__A_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__V1_ADDR_I13_I:%.*]] = alloca <2 x i64>, align 16
 // CHECK-NEXT:    [[__V2_ADDR_I14_I:%.*]] = alloca <2 x i64>, align 16
 // CHECK-NEXT:    [[__V1_ADDR_I11_I:%.*]] = alloca <2 x i64>, align 16
 // CHECK-NEXT:    [[__V2_ADDR_I12_I:%.*]] = alloca <2 x i64>, align 16

 // CHECK-NEXT:    store <4 x i32> [[TMP62]], <4 x i32>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[TMP63:%.*]] = load <4 x i32>, <4 x i32>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <4 x i32> [[TMP63]], i32 0
 // CHECK-NEXT:    ret i32 [[VECEXT_I]]
 unsigned int test_mm512_mask_reduce_max_epu32(__mmask16 __M, __m512i __W){
   return _mm512_mask_reduce_max_epu32(__M, __W); 
 }
 
-// CHECK-LABEL: define float @test_mm512_mask_reduce_max_ps(i16 zeroext %__M, <16 x float> %__W) #0 {
+// CHECK-LABEL: define float @test_mm512_mask_reduce_max_ps(i16 %__M, <16 x float> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca float, align 4
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <16 x float>, align 64
 // CHECK-NEXT:    [[__W2_ADDR_I_I:%.*]] = alloca <16 x float>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i16, align 2
 // CHECK-NEXT:    [[__A_ADDR_I_I:%.*]] = alloca <16 x float>, align 64
 // CHECK-NEXT:    [[__A_ADDR_I14_I:%.*]] = alloca <4 x float>, align 16
 // CHECK-NEXT:    [[__B_ADDR_I15_I:%.*]] = alloca <4 x float>, align 16

 // CHECK-NEXT:    store <4 x float> [[TMP57]], <4 x float>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[TMP58:%.*]] = load <4 x float>, <4 x float>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <4 x float> [[TMP58]], i32 0
 // CHECK-NEXT:    ret float [[VECEXT_I]]
 float test_mm512_mask_reduce_max_ps(__mmask16 __M, __m512 __W){
   return _mm512_mask_reduce_max_ps(__M, __W); 
 }
 
-// CHECK-LABEL: define i32 @test_mm512_mask_reduce_min_epi32(i16 zeroext %__M, <8 x i64> %__W) #0 {
+// CHECK-LABEL: define i32 @test_mm512_mask_reduce_min_epi32(i16 %__M, <8 x i64> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__S_ADDR_I_I:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <16 x i32>, align 64
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i16, align 2
 // CHECK-NEXT:    [[__A_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__V1_ADDR_I14_I:%.*]] = alloca <2 x i64>, align 16
 // CHECK-NEXT:    [[__V2_ADDR_I15_I:%.*]] = alloca <2 x i64>, align 16

 // CHECK-NEXT:    store <4 x i32> [[TMP80]], <4 x i32>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[TMP81:%.*]] = load <4 x i32>, <4 x i32>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <4 x i32> [[TMP81]], i32 0
 // CHECK-NEXT:    ret i32 [[VECEXT_I]]
 int test_mm512_mask_reduce_min_epi32(__mmask16 __M, __m512i __W){
   return _mm512_mask_reduce_min_epi32(__M, __W); 
 }
 
-// CHECK-LABEL: define i32 @test_mm512_mask_reduce_min_epu32(i16 zeroext %__M, <8 x i64> %__W) #0 {
+// CHECK-LABEL: define i32 @test_mm512_mask_reduce_min_epu32(i16 %__M, <8 x i64> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__S_ADDR_I_I:%.*]] = alloca i32, align 4
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <16 x i32>, align 64
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i16, align 2
 // CHECK-NEXT:    [[__A_ADDR_I_I:%.*]] = alloca <8 x i64>, align 64
 // CHECK-NEXT:    [[__V1_ADDR_I14_I:%.*]] = alloca <2 x i64>, align 16
 // CHECK-NEXT:    [[__V2_ADDR_I15_I:%.*]] = alloca <2 x i64>, align 16

 // CHECK-NEXT:    store <4 x i32> [[TMP80]], <4 x i32>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[TMP81:%.*]] = load <4 x i32>, <4 x i32>* [[__T10_I]], align 16
 // CHECK-NEXT:    [[VECEXT_I:%.*]] = extractelement <4 x i32> [[TMP81]], i32 0
 // CHECK-NEXT:    ret i32 [[VECEXT_I]]
 unsigned int test_mm512_mask_reduce_min_epu32(__mmask16 __M, __m512i __W){
   return _mm512_mask_reduce_min_epu32(__M, __W); 
 }
 
-// CHECK-LABEL: define float @test_mm512_mask_reduce_min_ps(i16 zeroext %__M, <16 x float> %__W) #0 {
+// CHECK-LABEL: define float @test_mm512_mask_reduce_min_ps(i16 %__M, <16 x float> %__W) #0 {
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[__W_ADDR_I_I:%.*]] = alloca float, align 4
 // CHECK-NEXT:    [[DOTCOMPOUNDLITERAL_I_I:%.*]] = alloca <16 x float>, align 64
 // CHECK-NEXT:    [[__W2_ADDR_I_I:%.*]] = alloca <16 x float>, align 64
 // CHECK-NEXT:    [[__U_ADDR_I_I:%.*]] = alloca i16, align 2
 // CHECK-NEXT:    [[__A_ADDR_I_I:%.*]] = alloca <16 x float>, align 64
 // CHECK-NEXT:    [[__A_ADDR_I14_I:%.*]] = alloca <4 x float>, align 16
 // CHECK-NEXT:    [[__B_ADDR_I15_I:%.*]] = alloca <4 x float>, align 16

clang/test/CodeGen/catch-implicit-integer-sign-changes.c

unsigned char signed_int_to_unsigned_char(signed int src) {
   // CHECK-NEXT: }
 #line 300
   return src;
 }
 
 // These 3 result (after optimizations) in simple 'icmp sge i8 %src, 0'
 
 // CHECK-LABEL: @signed_char_to_unsigned_char
-// CHECK-SAME: (i8 signext %[[SRC:.*]])
+// CHECK-SAME: (i8 %[[SRC:.*]])
 unsigned char signed_char_to_unsigned_char(signed char src) {
   // CHECK: %[[SRC_ADDR:.*]] = alloca i8
   // CHECK-NEXT: store i8 %[[SRC]], i8* %[[SRC_ADDR]]
   // CHECK-NEXT: %[[DST:.*]] = load i8, i8* %[[SRC_ADDR]]
   // CHECK-SANITIZE-NEXT: %[[SRC_NEGATIVITYCHECK:.*]] = icmp slt i8 %[[DST]], 0, !nosanitize
   // CHECK-SANITIZE-NEXT: %[[SIGNCHANGECHECK:.*]] = icmp eq i1 %[[SRC_NEGATIVITYCHECK]], false, !nosanitize
   // CHECK-SANITIZE-NEXT: br i1 %[[SIGNCHANGECHECK]], label %[[CONT:.*]], label %[[HANDLER_IMPLICIT_CONVERSION:[^,]+]],{{.*}} !nosanitize
   // CHECK-SANITIZE: [[HANDLER_IMPLICIT_CONVERSION]]:
   // CHECK-SANITIZE-ANYRECOVER-NEXT: %[[EXTSRC:.*]] = zext i8 %[[DST]] to i64, !nosanitize
   // CHECK-SANITIZE-ANYRECOVER-NEXT: %[[EXTDST:.*]] = zext i8 %[[DST]] to i64, !nosanitize
   // CHECK-SANITIZE-NORECOVER-NEXT: call void @__ubsan_handle_implicit_conversion_abort(i8* bitcast ({ {{{.*}}}, {{{.*}}}*, {{{.*}}}*, i8 }* @[[LINE_400]] to i8*), i64 %[[EXTSRC]], i64 %[[EXTDST]]){{.*}}, !nosanitize
   // CHECK-SANITIZE-RECOVER-NEXT: call void @__ubsan_handle_implicit_conversion(i8* bitcast ({ {{{.*}}}, {{{.*}}}*, {{{.*}}}*, i8 }* @[[LINE_400]] to i8*), i64 %[[EXTSRC]], i64 %[[EXTDST]]){{.*}}, !nosanitize
   // CHECK-SANITIZE-TRAP-NEXT: call void @llvm.trap(){{.*}}, !nosanitize
   // CHECK-SANITIZE-UNREACHABLE-NEXT: unreachable, !nosanitize
   // CHECK-SANITIZE: [[CONT]]:
   // CHECK-NEXT: ret i8 %[[DST]]
   // CHECK-NEXT: }
 #line 400
   return src;
 }
 
 // CHECK-LABEL: @unsigned_char_to_signed_char
-// CHECK-SAME: (i8 zeroext %[[SRC:.*]])
+// CHECK-SAME: (i8 %[[SRC:.*]])
 signed char unsigned_char_to_signed_char(unsigned char src) {
   // CHECK: %[[SRC_ADDR:.*]] = alloca i8
   // CHECK-NEXT: store i8 %[[SRC]], i8* %[[SRC_ADDR]]
   // CHECK-NEXT: %[[DST:.*]] = load i8, i8* %[[SRC_ADDR]]
   // CHECK-SANITIZE-NEXT: %[[DST_NEGATIVITYCHECK:.*]] = icmp slt i8 %[[DST]], 0, !nosanitize
   // CHECK-SANITIZE-NEXT: %[[SIGNCHANGECHECK:.*]] = icmp eq i1 false, %[[DST_NEGATIVITYCHECK]], !nosanitize
   // CHECK-SANITIZE-NEXT: br i1 %[[SIGNCHANGECHECK]], label %[[CONT:.*]], label %[[HANDLER_IMPLICIT_CONVERSION:[^,]+]],{{.*}} !nosanitize
   // CHECK-SANITIZE: [[HANDLER_IMPLICIT_CONVERSION]]:
   // CHECK-SANITIZE-ANYRECOVER-NEXT: %[[EXTSRC:.*]] = zext i8 %[[DST]] to i64, !nosanitize
   // CHECK-SANITIZE-ANYRECOVER-NEXT: %[[EXTDST:.*]] = zext i8 %[[DST]] to i64, !nosanitize
   // CHECK-SANITIZE-NORECOVER-NEXT: call void @__ubsan_handle_implicit_conversion_abort(i8* bitcast ({ {{{.*}}}, {{{.*}}}*, {{{.*}}}*, i8 }* @[[LINE_500]] to i8*), i64 %[[EXTSRC]], i64 %[[EXTDST]]){{.*}}, !nosanitize
   // CHECK-SANITIZE-RECOVER-NEXT: call void @__ubsan_handle_implicit_conversion(i8* bitcast ({ {{{.*}}}, {{{.*}}}*, {{{.*}}}*, i8 }* @[[LINE_500]] to i8*), i64 %[[EXTSRC]], i64 %[[EXTDST]]){{.*}}, !nosanitize
   // CHECK-SANITIZE-TRAP-NEXT: call void @llvm.trap(){{.*}}, !nosanitize
   // CHECK-SANITIZE-UNREACHABLE-NEXT: unreachable, !nosanitize
   // CHECK-SANITIZE: [[CONT]]:
   // CHECK-NEXT: ret i8 %[[DST]]
   // CHECK-NEXT: }
 #line 500
   return src;
 }
 
 // CHECK-LABEL: @signed_char_to_unsigned_int
-// CHECK-SAME: (i8 signext %[[SRC:.*]])
+// CHECK-SAME: (i8 %[[SRC:.*]])
 unsigned int signed_char_to_unsigned_int(signed char src) {
   // CHECK: %[[SRC_ADDR:.*]] = alloca i8
   // CHECK-NEXT: store i8 %[[SRC]], i8* %[[SRC_ADDR]]
   // CHECK-NEXT: %[[DST:.*]] = load i8, i8* %[[SRC_ADDR]]
   // CHECK-NEXT: %[[CONV:.*]] = sext i8 %[[DST]] to i32
   // CHECK-SANITIZE-NEXT: %[[SRC_NEGATIVITYCHECK:.*]] = icmp slt i8 %[[DST]], 0, !nosanitize
   // CHECK-SANITIZE-NEXT: %[[SIGNCHANGECHECK:.*]] = icmp eq i1 %[[SRC_NEGATIVITYCHECK]], false, !nosanitize
   // CHECK-SANITIZE-NEXT: br i1 %[[SIGNCHANGECHECK]], label %[[CONT:.*]], label %[[HANDLER_IMPLICIT_CONVERSION:[^,]+]],{{.*}} !nosanitize

clang/test/CodeGen/function-attributes.c

 // RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -disable-llvm-passes -Os -o - %s | FileCheck %s
 // RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -disable-llvm-passes -Os -std=c99 -o - %s | FileCheck %s
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -disable-llvm-passes -Os -std=c99 -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -disable-llvm-passes -Os -o - %s | FileCheck %s --check-prefix=CHECK-32
+// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-llvm -disable-llvm-passes -Os -std=c99 -o - %s | FileCheck %s --check-prefix=CHECK-32
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm -disable-llvm-passes -Os -std=c99 -o - %s | FileCheck %s --check-prefix=CHECK-64
+
 // CHECK: define signext i8 @f0(i32 %x) [[NUW:#[0-9]+]]
-// CHECK: define zeroext i8 @f1(i32 %x) [[NUW]]
-// CHECK: define void @f2(i8 signext %x) [[NUW]]
-// CHECK: define void @f3(i8 zeroext %x) [[NUW]]
-// CHECK: define signext i16 @f4(i32 %x) [[NUW]]
-// CHECK: define zeroext i16 @f5(i32 %x) [[NUW]]
-// CHECK: define void @f6(i16 signext %x) [[NUW]]
-// CHECK: define void @f7(i16 zeroext %x) [[NUW]]
+
+// CHECK-32: define signext i8 @f0(i32 %x) [[NUW:#[0-9]+]]
+// CHECK-32: define zeroext i8 @f1(i32 %x) [[NUW]]
+// CHECK-32: define void @f2(i8 signext %x) [[NUW]]
+// CHECK-32: define void @f3(i8 zeroext %x) [[NUW]]
+// CHECK-32: define signext i16 @f4(i32 %x) [[NUW]]
+// CHECK-32: define zeroext i16 @f5(i32 %x) [[NUW]]
+// CHECK-32: define void @f6(i16 signext %x) [[NUW]]
+// CHECK-32: define void @f7(i16 zeroext %x) [[NUW]]
+
+// CHECK-64: define signext i8 @f0(i32 %x) [[NUW:#[0-9]+]]
+// CHECK-64: define zeroext i8 @f1(i32 %x) [[NUW]]
+// CHECK-64: define void @f2(i8 %x) [[NUW]]
+// CHECK-64: define void @f3(i8 %x) [[NUW]]
+// CHECK-64: define signext i16 @f4(i32 %x) [[NUW]]
+// CHECK-64: define zeroext i16 @f5(i32 %x) [[NUW]]
+// CHECK-64: define void @f6(i16 %x) [[NUW]]
+// CHECK-64: define void @f7(i16 %x) [[NUW]]
 
 signed char f0(int x) { return x; }
 
 unsigned char f1(int x) { return x; }
 
 void f2(signed char x) { }
 
 void f3(unsigned char x) { }

clang/test/CodeGen/regcall.c

 // Win64: define dso_local x86_regcallcc void @__regcall3__v1b(i32 %a, i32 %b)
 // Lin32: define x86_regcallcc void @__regcall3__v1b(i32 inreg %a, i32 inreg %b)
 // Lin64: define x86_regcallcc void @__regcall3__v1b(i32 %a, i32 %b)
 
 void __regcall v2(char a, char b) {}
 // Win32: define dso_local x86_regcallcc void @__regcall3__v2(i8 inreg signext %a, i8 inreg signext %b)
 // Win64: define dso_local x86_regcallcc void @__regcall3__v2(i8 %a, i8 %b)
 // Lin32: define x86_regcallcc void @__regcall3__v2(i8 inreg signext %a, i8 inreg signext %b)
-// Lin64: define x86_regcallcc void @__regcall3__v2(i8 signext %a, i8 signext %b)
+// Lin64: define x86_regcallcc void @__regcall3__v2(i8 %a, i8 %b)
 
 struct Small { int x; };
 void __regcall v3(int a, struct Small b, int c) {}
 // Win32: define dso_local x86_regcallcc void @__regcall3__v3(i32 inreg %a, i32 %b.0, i32 inreg %c)
 // Win64: define dso_local x86_regcallcc void @__regcall3__v3(i32 %a, i32 %b.coerce, i32 %c)
 // Lin32: define x86_regcallcc void @__regcall3__v3(i32 inreg %a, i32 inreg %0, i32 %b.0, i32 inreg %c)
 // Lin64: define x86_regcallcc void @__regcall3__v3(i32 %a, i32 %b.coerce, i32 %c)
 

clang/test/CodeGen/x86_64-arguments-nacl.c

 void f1(struct PP_Var p1) { while(1) {} }
 
 // long doubles are 64 bits on NaCl
 // CHECK-LABEL: define double @f5()
 long double f5(void) {
   return 0;
 }
 
-// CHECK-LABEL: define void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
+// CHECK-LABEL: define void @f6(i8 %a0, i16 %a1, i32 %a2, i64 %a3, i8* %a4)
 void f6(char a0, short a1, int a2, long long a3, void *a4) {
 }
 
 // CHECK-LABEL: define i64 @f8_1()
 // CHECK-LABEL: define void @f8_2(i64 %a0.coerce)
 union u8 {
   long double a;
   int b;

clang/test/CodeGen/x86_64-arguments.c

double f4(void) {
   return 0;
 }
 
 // CHECK-LABEL: define x86_fp80 @f5()
 long double f5(void) {
   return 0;
 }
 
-// CHECK-LABEL: define void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
+// CHECK-LABEL: define void @f6(i8 %a0, i16 %a1, i32 %a2, i64 %a3, i8* %a4)
 void f6(char a0, short a1, int a2, long long a3, void *a4) {
 }
 
 // CHECK-LABEL: define void @f7(i32 %a0)
 typedef enum { A, B, C } e7;
 void f7(e7 a0) {
 }
 

clang/test/CodeGenCXX/blocks.cpp

namespace test5 {
   void test(bool cond) {
     A x;
     void (^b)() = (cond ? ^{ x.foo(); } : (void(^)()) 0);
     doWithBlock(b);
   }
 
   // CHECK-LABEL:    define void @_ZN5test54testEb(
   // CHECK:      [[COND:%.*]] = alloca i8
+  // CHECK-NEXT: [[COND]].addr = alloca i8, align 1
   // CHECK-NEXT: [[X:%.*]] = alloca [[A:%.*]], align 4
   // CHECK-NEXT: [[B:%.*]] = alloca void ()*, align 8
   // CHECK-NEXT: [[BLOCK:%.*]] = alloca [[BLOCK_T:.*]], align 8
   // CHECK-NEXT: [[CLEANUP_ACTIVE:%.*]] = alloca i1
-  // CHECK-NEXT: [[T0:%.*]] = zext i1
-  // CHECK-NEXT: store i8 [[T0]], i8* [[COND]], align 1
+  // CHECK-NEXT: store i8 [[COND]].coerce, i8* [[COND]], align 1
+  // CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[COND]], align 1
+  // CHECK-NEXT: [[COND1:%.*]] = trunc i8 [[T0]] to i1
+  // CHECK-NEXT: [[T1:%.*]] = zext i1 [[COND1]] to i8
+  // CHECK-NEXT: store i8 [[T1]], i8* [[COND]].addr, align 1
   // CHECK-NEXT: call void @_ZN5test51AC1Ev([[A]]* [[X]])
   // CHECK-NEXT: [[CLEANUP_ADDR:%.*]] = getelementptr inbounds [[BLOCK_T]], [[BLOCK_T]]* [[BLOCK]], i32 0, i32 5
-  // CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[COND]], align 1
-  // CHECK-NEXT: [[T1:%.*]] = trunc i8 [[T0]] to i1
+  // CHECK-NEXT: [[T1:%.*]] = load i8, i8* [[COND]].addr, align 1
+  // CHECK-NEXT: [[T2:%.*]] = trunc i8 [[T1]] to i1
   // CHECK-NEXT: store i1 false, i1* [[CLEANUP_ACTIVE]]
-  // CHECK-NEXT: br i1 [[T1]],
+  // CHECK-NEXT: br i1 [[T2]],
 
   // CHECK-NOT:  br
   // CHECK:      [[CAPTURE:%.*]] = getelementptr inbounds [[BLOCK_T]], [[BLOCK_T]]* [[BLOCK]], i32 0, i32 5
   // CHECK-NEXT: call void @_ZN5test51AC1ERKS0_([[A]]* [[CAPTURE]], [[A]]* dereferenceable({{[0-9]+}}) [[X]])
   // CHECK-NEXT: store i1 true, i1* [[CLEANUP_ACTIVE]]
   // CHECK-NEXT: bitcast [[BLOCK_T]]* [[BLOCK]] to void ()*
   // CHECK-NEXT: br label
   // CHECK:      br label

clang/test/CodeGenCXX/const-init-cxx11.cpp

namespace InitFromConst {
   struct S { int n = 7; S *p = 0; };
   constexpr S s = S();
   const S &r = s;
   constexpr const S *p = &r;
   constexpr int S::*mp = &S::n;
   constexpr int a[3] = { 1, 4, 9 };
 
   void test() {
-    // CHECK: call void @_ZN13InitFromConst7consumeIbEEvT_(i1 zeroext true)
+    // FIXME: This should probably be:
+    // call void @_ZN13InitFromConst7consumeIbEEvT_(i1 zeroext true)
+    // And not require an alloca
+    // CHECK: call void @_ZN13InitFromConst7consumeIbEEvT_(i8 %0)
     consume(b);
 
     // CHECK: call void @_ZN13InitFromConst7consumeIiEEvT_(i32 5)
     consume(n);
 
     // CHECK: call void @_ZN13InitFromConst7consumeIdEEvT_(double 4.300000e+00)
     consume(d);
 

clang/test/CodeGenCXX/cxx1z-initializer-aggregate.cpp

namespace Dynamic {
   struct D : A, B, C {
     int n = f();
   };
 
   D d1 = {};
   // CHECK-LABEL: define {{.*}}global_var_init
   // CHECK: call void @_ZN7Dynamic1AC2Ev({{.*}} @_ZN7Dynamic2d1E
   // CHECK: store i32 5, {{.*}}i8* getelementptr inbounds {{.*}} @_ZN7Dynamic2d1E{{.*}}, i64 8
-  // CHECK: invoke void @_ZN7Dynamic1CC2Eb({{.*}} @_ZN7Dynamic2d1E{{.*}}, i1 zeroext true)
+  // CHECK: invoke void @_ZN7Dynamic1CC2Eb({{.*}} @_ZN7Dynamic2d1E{{.*}}, i8 %0)
   // CHECK:   unwind label %[[UNWIND:.*]]
   // CHECK: invoke i32 @_ZN7Dynamic1fEv()
   // CHECK:   unwind label %[[UNWIND:.*]]
   // CHECK: store i32 {{.*}}, i32* getelementptr {{.*}} @_ZN7Dynamic2d1E, i32 0, i32 2
   // CHECK: call {{.*}} @__cxa_atexit({{.*}} @_ZN7Dynamic1DD1Ev {{.*}} @_ZN7Dynamic2d1E
   // CHECK: ret
   //
   //   UNWIND:
   // CHECK: call void @_ZN7Dynamic1BD1Ev({{.*}}i8* getelementptr inbounds {{.*}} @_ZN7Dynamic2d1E{{.*}}, i64 8
   // CHECK: call void @_ZN7Dynamic1AD1Ev({{.*}} @_ZN7Dynamic2d1E
 
   D d2 = {1, 2, false};
   // CHECK-LABEL: define {{.*}}global_var_init
   // CHECK: call void @_ZN7Dynamic1AC1Ei({{.*}} @_ZN7Dynamic2d2E{{.*}}, i32 1)
   // CHECK: store i32 2, {{.*}}i8* getelementptr inbounds {{.*}}@_ZN7Dynamic2d2E{{.*}}, i64 8
-  // CHECK: invoke void @_ZN7Dynamic1CC1Eb({{.*}} @_ZN7Dynamic2d2E{{.*}}, i1 zeroext false)
+  // CHECK: invoke void @_ZN7Dynamic1CC1Eb({{.*}} @_ZN7Dynamic2d2E{{.*}}, i8 %0)
   // CHECK: invoke i32 @_ZN7Dynamic1fEv()
   // CHECK: store i32 {{.*}}, i32* getelementptr {{.*}} @_ZN7Dynamic2d2E, i32 0, i32 2
   // CHECK: call {{.*}} @__cxa_atexit({{.*}} @_ZN7Dynamic1DD1Ev {{.*}} @_ZN7Dynamic2d2E
   // CHECK: ret void
 
   D d3 = {g(), h(), {}, i()};
   // CHECK-LABEL: define {{.*}}global_var_init
   // CHECK: %[[G_CALL:.*]] = call i32 @_ZN7Dynamic1gEv()
   // CHECK: call void @_ZN7Dynamic1AC1Ei({{.*}} @_ZN7Dynamic2d3E{{.*}}, i32 %[[G_CALL]])
   // CHECK: %[[H_CALL:.*]] = invoke i32 @_ZN7Dynamic1hEv()
   // CHECK:   unwind label %[[DESTROY_A_LPAD:.*]]
   // CHECK: store i32 %[[H_CALL]], {{.*}}i8* getelementptr inbounds {{.*}} @_ZN7Dynamic2d3E{{.*}}, i64 8
-  // CHECK: invoke void @_ZN7Dynamic1CC2Eb({{.*}} @_ZN7Dynamic2d3E{{.*}}, i1 zeroext true)
+  // CHECK: invoke void @_ZN7Dynamic1CC2Eb({{.*}} @_ZN7Dynamic2d3E{{.*}}, i8 %0)
   // CHECK:   unwind label %[[DESTROY_AB_LPAD:.*]]
   // CHECK: %[[I_CALL:.*]] = invoke i32 @_ZN7Dynamic1iEv()
   // CHECK:   unwind label %[[DESTROY_AB_LPAD:.*]]
   // CHECK: store i32 %[[I_CALL]], i32* getelementptr {{.*}} @_ZN7Dynamic2d3E, i32 0, i32 2
   // CHECK: call {{.*}} @__cxa_atexit({{.*}} @_ZN7Dynamic1DD1Ev {{.*}} @_ZN7Dynamic2d3E to i8*
   // CHECK: ret
   //
   //   DESTROY_A_LPAD:

clang/test/CodeGenCXX/exceptions.cpp

A *a() {
 
     // CHECK98:      call void @__clang_call_terminate(i8* {{%.*}}) [[NR_NUW]]
     return new(foo(),bar()) A(5);
   }
 
   // rdar://problem/8439196
   A *b(bool cond) {
 
-    // CHECK:    define [[A:%.*]]* @_ZN5test31bEb(i1 zeroext
+    // CHECK:    define [[A:%.*]]* @_ZN5test31bEb(i8 [[COND:%.*]].coerce
     // CHECK:      [[SAVED0:%.*]] = alloca i8*
     // CHECK-NEXT: [[SAVED1:%.*]] = alloca i8*
-    // CHECK-NEXT: [[CLEANUPACTIVE:%.*]] = alloca i1
+    // CHECK-NEXT: [[CLEANUP:%.*]].cond = alloca i1, align 1
 
-    // CHECK:      [[COND:%.*]] = trunc i8 {{.*}} to i1
-    // CHECK-NEXT: store i1 false, i1* [[CLEANUPACTIVE]]
-    // CHECK-NEXT: br i1 [[COND]]
+    // CHECK:      [[COND1:%.*]] = trunc i8 {{.*}} to i1
+    // CHECK-NEXT: [[CONDZEXT:%.*]] = zext i1 [[COND1]] to i8
+    // CHECK-NEXT: store i8 [[CONDZEXT]], i8* [[COND]].addr, align 1
+    // CHECK-NEXT: load i8, i8* [[COND]].addr, align 1
+    // CHECK-NEXT: [[TOBOOL:%.*]] = trunc i8 {{.*}} to i1
+    // CHECK-NEXT: store i1 false, i1* [[CLEANUP]].cond, align 1
+    // CHECK-NEXT: br i1 [[TOBOOL]]
     return (cond ?
 
     // CHECK:      [[FOO:%.*]] = call i8* @_ZN5test33fooEv()
     // CHECK-NEXT: [[NEW:%.*]] = call i8* @_ZN5test31AnwEmPvd(i64 8, i8* [[FOO]], double [[CONST:.*]])
     // CHECK-NEXT: store i8* [[NEW]], i8** [[SAVED0]]
     // CHECK-NEXT: store i8* [[FOO]], i8** [[SAVED1]]
-    // CHECK-NEXT: store i1 true, i1* [[CLEANUPACTIVE]]
+    // CHECK-NEXT: store i1 true, i1* [[CLEANUP]].cond
     // CHECK-NEXT: [[CAST:%.*]] = bitcast i8* [[NEW]] to [[A]]*
     // CHECK-NEXT: invoke void @_ZN5test35makeAEv([[A]]* sret [[CAST]])
     // CHECK: br label
     //   -> cond.end
             new(foo(),10.0) A(makeA()) :
 
     // CHECK:      [[MAKE:%.*]] = call [[A]]* @_ZN5test38makeAPtrEv()
     // CHECK:      br label
     //   -> cond.end
             makeAPtr());
 
     // cond.end:
     // CHECK:      [[RESULT:%.*]] = phi [[A]]* {{.*}}[[CAST]]{{.*}}[[MAKE]]
     // CHECK:      ret [[A]]* [[RESULT]]
 
     // in the EH path:
-    // CHECK:      [[ISACTIVE:%.*]] = load i1, i1* [[CLEANUPACTIVE]]
+    // CHECK:      [[ISACTIVE:%.*]] = load i1, i1* [[CLEANUP]].cond
     // CHECK-NEXT: br i1 [[ISACTIVE]]
     // CHECK:      [[V0:%.*]] = load i8*, i8** [[SAVED0]]
     // CHECK-NEXT: [[V1:%.*]] = load i8*, i8** [[SAVED1]]
 
     // CHECK98-NEXT: invoke void @_ZN5test31AdlEPvS1_d(i8* [[V0]], i8* [[V1]], double [[CONST]])
     // CHECK11-NEXT: call void @_ZN5test31AdlEPvS1_d(i8* [[V0]], i8* [[V1]], double [[CONST]])
   }
 }

clang/test/CodeGenCXX/forward-enum.cpp

 // RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin11.0.0 -emit-llvm -o - %s | FileCheck %s
 
 enum MyEnum : char;
 void bar(MyEnum value) { }
 
 // CHECK-LABEL: define void @_Z3foo6MyEnum
 void foo(MyEnum value)
 {
-  // CHECK: call void @_Z3bar6MyEnum(i8 signext
+  // CHECK: call void @_Z3bar6MyEnum(i8
   bar(value);
 }

clang/test/CodeGenCXX/value-init.cpp

namespace PR11124 {
   struct B2 : virtual A { int B::*b; };
   struct C2 : B2 { C2(); };      
   C2::C2() : A(3), B2() {}
   // CHECK-LABEL: define void @_ZN7PR111242C2C1Ev
   // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %{{.*}}, i8* align 8 {{.*}}, i64 16, i1 false)
   // CHECK-NEXT: call void @_ZN7PR111242B2C2Ev
 }
 
-// Ensure we produce an i1 here, and don't assert.
 // CHECK-LABEL: define void @_Z9r170806_bv(
-// CHECK: call void @_Z9r170806_ab(i1 zeroext false)
+// CHECK: call void @_Z9r170806_ab(i8 %0)
 void r170806_a(bool b = bool());
 void r170806_b() { r170806_a(); }
 
 namespace PR20256 {
   struct data { int i; };
 
   template<typename T = int>
   data g() {

clang/test/CodeGenCXX/virtual-bases.cpp

 // CHECK-LABEL: define void @_ZN1BC2Ev(%struct.B* %this, i8** %vtt) unnamed_addr
 // CHECK-LABEL: define void @_ZN1BC1Ev(%struct.B* %this) unnamed_addr
 B::B() { }
 
 struct C : virtual A {
   C(bool);
 };
 
-// CHECK-LABEL: define void @_ZN1CC2Eb(%struct.C* %this, i8** %vtt, i1 zeroext %0) unnamed_addr
-// CHECK-LABEL: define void @_ZN1CC1Eb(%struct.C* %this, i1 zeroext %0) unnamed_addr
+// CHECK-LABEL: define void @_ZN1CC2Eb(%struct.C* %this, i8** %vtt, i8 %.coerce) unnamed_addr
+// CHECK-LABEL: define void @_ZN1CC1Eb(%struct.C* %this, i8 %.coerce) unnamed_addr
 C::C(bool) { }
 
 // PR6251
 namespace PR6251 {
 
 // Test that we don't call the A<char> constructor twice.
 
 template<typename T>

clang/test/CodeGenObjC/arc-blocks.m

 
 // rdar://problem/9979150
 @interface Test12
 @property (strong) void(^ablock)(void);
 @property (nonatomic, strong) void(^nblock)(void);
 @end
 @implementation Test12
 @synthesize ablock, nblock;
-// CHECK:    define internal void ()* @"\01-[Test12 ablock]"(
-// CHECK:    call i8* @objc_getProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i1 zeroext true)
+// CHECK:      define internal void ()* @"\01-[Test12 ablock]"(
+// CHECK:      store i8 1
+// CHECK-NEXT: [[T0:%.*]] = load i8
+// CHECK-NEXT: call i8* @objc_getProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i8 [[T0]])
 
-// CHECK:    define internal void @"\01-[Test12 setAblock:]"(
-// CHECK:    call void @objc_setProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i8* {{%.*}}, i1 zeroext true, i1 zeroext true)
+// CHECK:      define internal void @"\01-[Test12 setAblock:]"(
+// CHECK:      store i8 1
+// CHECK-NEXT: [[T0:%.*]] = load i8
+// CHECK-NEXT: store i8 1
+// CHECK-NEXT: [[T1:%.*]] = load i8
+// CHECK-NEXT: call void @objc_setProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i8* {{%.*}}, i8 [[T0]], i8 [[T1]])
 
-// CHECK:    define internal void ()* @"\01-[Test12 nblock]"(
-// CHECK:    call i8* @objc_getProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i1 zeroext false)
+// CHECK:      define internal void ()* @"\01-[Test12 nblock]"(
+// CHECK:      store i8 0
+// CHECK-NEXT: [[T0:%.*]] = load i8
+// CHECK:      call i8* @objc_getProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i8 [[T0]])
 
 // CHECK:    define internal void @"\01-[Test12 setNblock:]"(
-// CHECK:    call void @objc_setProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i8* {{%.*}}, i1 zeroext false, i1 zeroext true)
+// CHECK:      store i8 0
+// CHECK-NEXT: [[T0:%.*]] = load i8
+// CHECK-NEXT: store i8 1
+// CHECK-NEXT: [[T1:%.*]] = load i8
+// CHECK-NEXT: call void @objc_setProperty(i8* {{%.*}}, i8* {{%.*}}, i64 {{%.*}}, i8* {{%.*}}, i8 [[T0]], i8 [[T1]])
 @end
 
 // rdar://problem/10131784
 void test13(id x) {
   extern void test13_helper(id);
   extern void test13_use(void(^)(void));
 
   void (^b)(void) = (x ? ^{test13_helper(x);} : 0);

clang/test/CodeGenObjC/arc-literals.m

void test_numeric() {
   // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue
   id ilit = @17;
   // CHECK: {{call.*objc_msgSend.*i32 25}}
   // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue
   id ulit = @25u;
   // CHECK: {{call.*objc_msgSend.*i64 42}}
   // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue
   id ulllit = @42ull;
-  // CHECK: {{call.*objc_msgSend.*i8 signext 97}}
+  // CHECK: {{call.*objc_msgSend.*i8 97}}
   // CHECK: call i8* @llvm.objc.retainAutoreleasedReturnValue
   id charlit = @'a';
   // CHECK: call void @llvm.objc.release
   // CHECK: call void @llvm.lifetime.end
   // CHECK: call void @llvm.objc.release
   // CHECK: call void @llvm.lifetime.end
   // CHECK: call void @llvm.objc.release
   // CHECK: call void @llvm.lifetime.end

clang/test/CodeGenObjC/arc-property.m

 // CHECK-NEXT: ret [[S1]]* [[T3]]
 
 //   The setter should be using objc_setProperty.
 // CHECK:    define internal void @"\01-[Test1 setPointer:]"(
 // CHECK:      [[T0:%.*]] = bitcast [[TEST1]]* {{%.*}} to i8*
 // CHECK-NEXT: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test1.pointer"
 // CHECK-NEXT: [[T1:%.*]] = load [[S1]]*, [[S1]]** {{%.*}}
 // CHECK-NEXT: [[T2:%.*]] = bitcast [[S1]]* [[T1]] to i8*
-// CHECK-NEXT: call void @objc_setProperty(i8* [[T0]], i8* {{%.*}}, i64 [[OFFSET]], i8* [[T2]], i1 zeroext false, i1 zeroext false)
+// CHECK-NEXT: store i8 0, i8* %coerce
+// CHECK-NEXT: [[T3:%.*]] = load i8
+// CHECK-NEXT: store i8 0, i8* %coerce
+// CHECK-NEXT: [[T4:%.*]] = load i8
+// CHECK-NEXT: call void @objc_setProperty(i8* [[T0]], i8* {{%.*}}, i64 [[OFFSET]], i8* [[T2]], i8 [[T3]], i8 [[T4]])
 // CHECK-NEXT: ret void
 
 
 // rdar://problem/12039404
 @interface Test2 {
 @private
   Class _theClass;
 }

 // CHECK-NEXT: [[T2:%.*]] = bitcast [[TEST2]]* [[T1]] to i8*
 // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i8, i8* [[T2]], i64 [[OFFSET]]
 // CHECK-NEXT: [[T4:%.*]] = bitcast i8* [[T3]] to i8**
 // CHECK-NEXT: call void @llvm.objc.storeStrong(i8** [[T4]], i8* [[T0]]) [[NUW:#[0-9]+]]
 // CHECK-NEXT: ret void
 
 // CHECK:    define internal i8* @"\01-[Test2 theClass]"(
 // CHECK:      [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test2._theClass"
-// CHECK-NEXT: [[T0:%.*]] = tail call i8* @objc_getProperty(i8* {{.*}}, i8* {{.*}}, i64 [[OFFSET]], i1 zeroext true)
-// CHECK-NEXT: ret i8* [[T0]]
+// CHECK-NEXT: store i8 1, i8* %coerce, align 1
+// CHECK-NEXT: [[T0:%.*]] = load i8
+// CHECK-NEXT: [[T1:%.*]] = tail call i8* @objc_getProperty(i8* {{.*}}, i8* {{.*}}, i64 [[OFFSET]], i8 [[T0]])
+// CHECK-NEXT: ret i8* [[T1]]
 
 // CHECK:    define internal void @"\01-[Test2 setTheClass:]"(
 // CHECK:      [[T0:%.*]] = bitcast [[TEST2]]* {{%.*}} to i8*
 // CHECK-NEXT: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test2._theClass"
 // CHECK-NEXT: [[T1:%.*]] = load i8*, i8** {{%.*}}
-// CHECK-NEXT: call void @objc_setProperty(i8* [[T0]], i8* {{%.*}}, i64 [[OFFSET]], i8* [[T1]], i1 zeroext true, i1 zeroext true)
+// CHECK-NEXT: store i8 1
+// CHECK-NEXT: [[T2:%.*]] = load i8
+// CHECK-NEXT: store i8 1
+// CHECK-NEXT: [[T3:%.*]] = load i8
+// CHECK-NEXT: call void @objc_setProperty(i8* [[T0]], i8* {{%.*}}, i64 [[OFFSET]], i8* [[T1]], i8 [[T2]], i8 [[T3]])
 // CHECK-NEXT: ret void
 
 // CHECK:    define internal void @"\01-[Test2 .cxx_destruct]"(
 // CHECK:      [[T0:%.*]] = load [[TEST2]]*, [[TEST2]]**
 // CHECK-NEXT: [[OFFSET:%.*]] = load i64, i64* @"OBJC_IVAR_$_Test2._theClass"
 // CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST2]]* [[T0]] to i8*
 // CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds i8, i8* [[T1]], i64 [[OFFSET]]
 // CHECK-NEXT: [[T3:%.*]] = bitcast i8* [[T2]] to i8**

clang/test/CodeGenObjC/arc-ternary-op.m

 // RUN: %clang_cc1 -triple x86_64-apple-darwin10 -emit-llvm -fblocks -fobjc-arc -fobjc-runtime-has-weak -O2 -disable-llvm-passes -o - %s | FileCheck %s
 
 void test0(_Bool cond) {
   id test0_helper(void) __attribute__((ns_returns_retained));
 
   // CHECK-LABEL:      define void @test0(
   // CHECK:      [[COND:%.*]] = alloca i8,
+  // CHECK-NEXT: [[COND]].addr = alloca i8,
   // CHECK-NEXT: [[X:%.*]] = alloca i8*,
   // CHECK-NEXT: [[RELVAL:%.*]] = alloca i8*
   // CHECK-NEXT: [[RELCOND:%.*]] = alloca i1
+  // CHECK-NEXT: store i8 [[COND]].coerce, i8* [[COND]]
+  // CHECK-NEXT: load
+  // CHECK-NEXT: trunc
   // CHECK-NEXT: zext
   // CHECK-NEXT: store
   // CHECK-NEXT: [[XPTR1:%.*]] = bitcast i8** [[X]] to i8*
   // CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[XPTR1]])
   // CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[COND]]
   // CHECK-NEXT: [[T1:%.*]] = trunc i8 [[T0]] to i1
   // CHECK-NEXT: store i1 false, i1* [[RELCOND]]
   // CHECK-NEXT: br i1 [[T1]],

clang/test/CodeGenObjC/atomic-aggregate-property.m

 @synthesize a;
 @end
 // CHECK-LP64: define internal double @"\01-[A x]"(
 // CHECK-LP64: load atomic i64, i64* {{%.*}} unordered, align 8
 
 // CHECK-LP64: define internal void @"\01-[A setX:]"(
 // CHECK-LP64: store atomic i64 {{%.*}}, i64* {{%.*}} unordered, align 8
 
-// CHECK-LP64: define internal void @"\01-[A y]"(
-// CHECK-LP64: call void @objc_copyStruct(i8* {{%.*}}, i8* {{%.*}}, i64 32, i1 zeroext true, i1 zeroext false)
+// CHECK-LP64:      define internal void @"\01-[A y]"(
+// CHECK-LP64: store i8 1
+// CHECK-LP64-NEXT: [[T0:%.*]] = load i8
+// CHECK-LP64-NEXT: store i8 0
+// CHECK-LP64-NEXT: [[T1:%.*]] = load i8
+// CHECK-LP64-NEXT: call void @objc_copyStruct(i8* {{%.*}}, i8* {{%.*}}, i64 32, i8 [[T0]], i8 [[T1]])
 
 // CHECK-LP64: define internal void @"\01-[A setY:]"(
-// CHECK-LP64: call void @objc_copyStruct(i8* {{%.*}}, i8* {{%.*}}, i64 32, i1 zeroext true, i1 zeroext false)
+// CHECK-LP64: store i8 1
+// CHECK-LP64-NEXT: [[T0:%.*]] = load i8
+// CHECK-LP64-NEXT: store i8 0
+// CHECK-LP64-NEXT: [[T1:%.*]] = load i8
+// CHECK-LP64-NEXT: call void @objc_copyStruct(i8* {{%.*}}, i8* {{%.*}}, i64 32, i8 [[T0]], i8 [[T1]])
 
 // CHECK-LP64: define internal void @"\01-[A z]"(
 // CHECK-LP64: call i8* @objc_memmove_collectable(
 
 // CHECK-LP64: define internal void @"\01-[A setZ:]"(
 // CHECK-LP64: call i8* @objc_memmove_collectable(
 
 // CHECK-LP64: define internal void @"\01-[A a]"(
 // (do nothing)
 
 // CHECK-LP64: define internal void @"\01-[A setA:]"(
 // (do nothing)

clang/test/CodeGenObjC/objc-literal-tests.m

 + (id)dictionaryWithObjects:(const id [])objects forKeys:(const id [])keys count:(NSUInteger)cnt;
 @end
 #endif
 
 id NSUserName();
 
 // CHECK: define i32 @main() [[NUW:#[0-9]+]]
 int main() {
-  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 97
+  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 97
   NSNumber *aNumber = @'a';
   // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 42
   NSNumber *fortyTwo = @42;
   // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 -42
   NSNumber *negativeFortyTwo = @-42;
   // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 42
   NSNumber *positiveFortyTwo = @+42;
   // CHECK: call{{.*}}@objc_msgSend{{.*}}i32 42
   NSNumber *fortyTwoUnsigned = @42u;
   // CHECK: call{{.*}}@objc_msgSend{{.*}}i64 42
   NSNumber *fortyTwoLong = @42l;
   // CHECK: call{{.*}}@objc_msgSend{{.*}}i64 42
   NSNumber *fortyTwoLongLong = @42ll;
   // CHECK: call{{.*}}@objc_msgSend{{.*}}float 0x400921FB60000000
   NSNumber *piFloat = @3.141592654f;
   // CHECK: call{{.*}}@objc_msgSend{{.*}}double 0x400921FB54411744
   NSNumber *piDouble = @3.1415926535;
-  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 1
+  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 1
   NSNumber *yesNumber = @__objc_yes;
-  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 0
+  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 0
   NSNumber *noNumber = @__objc_no;
-  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 1
+  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 1
   NSNumber *yesNumber1 = @YES;
-  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 signext 0
+  // CHECK: call{{.*}}@objc_msgSend{{.*}}i8 0
   NSNumber *noNumber1 = @NO;
 NSDictionary *dictionary = @{@"name" : NSUserName(), 
                              @"date" : [NSDate date] }; 
   return __objc_yes == __objc_no;
 }
 
 // rdar://10579122
 typedef BOOL (^foo)(void);
 extern void bar(foo a);
 
 void baz(void) {
   bar(^(void) { return YES; });
 }
 
 // CHECK: attributes [[NUW]] = { noinline {{(norecurse )?}}nounwind{{.*}} }

clang/test/CodeGenObjC/objc_copyStruct.m

-// RUN: %clang -target x86_64-unknown-windows-msvc -fobjc-runtime=ios -Wno-objc-root-class -S -o - -emit-llvm %s | FileCheck %s
-// RUN: %clang -target x86_64-apple-ios -fobjc-runtime=ios -Wno-objc-root-class -S -o - -emit-llvm %s | FileCheck %s
+// RUN: %clang -target x86_64-unknown-windows-msvc -fobjc-runtime=ios -Wno-objc-root-class -S -o - -emit-llvm %s | FileCheck %s -check-prefix CHECK-MSVC
+// RUN: %clang -target x86_64-apple-ios -fobjc-runtime=ios -Wno-objc-root-class -S -o - -emit-llvm %s | FileCheck %s -check-prefix CHECK-IOS
 
 struct S {
   float f, g;
 };
 
 @interface I
 @property struct S s;
 @end
 
 @implementation I
 @end
 
-// CHECK: declare {{.*}}void @objc_copyStruct(i8*, i8*, i64, i1, i1)
+// CHECK-MSVC: declare {{.*}}void @objc_copyStruct(i8*, i8*, i64, i1, i1)
+// CHECK-IOS: declare {{.*}}void @objc_copyStruct(i8*, i8*, i64, i8, i8)
 

clang/test/CodeGenObjC/property-atomic-bool.m

 // RUN: %clang_cc1 -triple x86_64-apple-macosx10 -emit-llvm -x objective-c %s -o - | FileCheck %s
 
 // CHECK: define internal zeroext i1 @"\01-[A0 p]"(
 // CHECK:   %[[ATOMIC_LOAD:.*]] = load atomic i8, i8* %{{.*}} seq_cst
 // CHECK:   %[[TOBOOL:.*]] = trunc i8 %[[ATOMIC_LOAD]] to i1
 // CHECK:   ret i1 %[[TOBOOL]]
 
-// CHECK: define internal void @"\01-[A0 setP:]"({{.*}} i1 zeroext {{.*}})
+// CHECK: define internal void @"\01-[A0 setP:]"({{.*}} i8* {{.*}})
 // CHECK:   store atomic i8 %{{.*}}, i8* %{{.*}} seq_cst
 // CHECK:   ret void
 
 // CHECK: define internal zeroext i1 @"\01-[A1 p]"(
 // CHECK:   %[[ATOMIC_LOAD:.*]] = load atomic i8, i8* %{{.*}} unordered
 // CHECK:   %[[TOBOOL:.*]] = trunc i8 %load to i1
 // CHECK:   ret i1 %[[TOBOOL]]
 
-// CHECK: define internal void @"\01-[A1 setP:]"({{.*}} i1 zeroext %p)
+// CHECK: define internal void @"\01-[A1 setP:]"({{.*}} i8 %p.coerce)
 // CHECK:   store atomic i8 %{{.*}}, i8* %{{.*}} unordered
 // CHECK:   ret void
 
 @interface A0
 @property(nonatomic) _Atomic(_Bool) p;
 @end
 @implementation A0
 @end

clang/test/CodeGenObjCXX/property-object-reference-1.mm

 @synthesize cppObject = _cppObject;
 
 @end
 
 // CHECK: [[cppObjectaddr:%.*]] = alloca %struct.TCPPObject*, align 8
 // CHECK: store %struct.TCPPObject* [[cppObject:%.*]], %struct.TCPPObject** [[cppObjectaddr]], align 8
 // CHECK:  [[THREE:%.*]] = load %struct.TCPPObject*, %struct.TCPPObject** [[cppObjectaddr]], align 8
 // CHECK:  [[FOUR:%.*]] = bitcast %struct.TCPPObject* [[THREE]] to i8*
-// CHECK:  call void @objc_copyStruct(i8* [[TWO:%.*]], i8* [[FOUR]], i64 256, i1 zeroext true, i1 zeroext false)
+// CHECK:  [[FIVE:%.*]] = load i8, i8* %coerce, align 1
+// CHECK:  [[SIX:%.*]] = load i8, i8* %coerce1, align 1
+// CHECK:  call void @objc_copyStruct(i8* [[TWO:%.*]], i8* [[FOUR]], i64 256, i8 [[FIVE]], i8 [[SIX]])

llvm/test/CodeGen/X86/x86-64-arg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s | FileCheck %s
-
 ; The input value is already sign extended, don't re-extend it.
 ; This testcase corresponds to:
 ;   int test(short X) { return (int)X; }
 
 target datalayout = "e-p:64:64"
 target triple = "x86_64-apple-darwin8"