[RISCV GlobalISel] Add lowerReturn for calling conv.

[wwei]

Summary

Add minimal support to lower return, and introduce an outgoing ValueHandler for returns.
Support return values with integer, pointer and aggregate types.

[lewis-revill]

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll

83

Typo: the pattern here should be [[AEXT]], right?

[lewis-revill]

See comments above. Otherwise, this looks good to me although others should evaluate too.

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

114

I don't know whether other people prefer this as well, but I'd prefer the condition here to be reversed and simply duplicate the

MIRBuilder.insertInstr(Ret);
return true;

IE:

if (Val == nullptr) {
  MIRBuilder.insertInstr(Ret);
  return true;
}

// ...

MIRBuilder.insertInstr(Ret);
return true;

[lewis-revill]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

55

What's the case where this will be used?

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll

0–1

Nitpick: no longer true with these additions.

[wwei]

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll

83

Yes, it's a typo, I'll fix it.

[wwei]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

114

To make the code look clearer and simpler, I will encapsulate a function to handle this condition.

[wwei]

Fix some typos and add a new function lowerReturnVal

[wwei]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

55

This is a reserved case. Currently, riscv backend does not implement CCAssignFnForCall and CCAssignFnForReturn , so AssignFn will be always null. If these two functions will be added later, the code is available directly.

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll

0–1

I don't understand why many test files add this assertion. So is your suggestion that we can remove this assertion?

[lewis-revill]

Thank you for the update! Please see comments.

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

55

Correct me if I'm wrong but won't the assignments already have been done when you call TLI.analyzeOutputArgs from lowerReturn?

IE: TLI.analyzeOutputArgs currently calls CC_RISCV, which essentially performs the task of a CCAssignFn.

114

That's not quite what I meant by that, though I understand the desire to reduce code duplication. Personally I prefer a little bit of duplication of code like I suggested instead of adding another helper function.

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll

0–1

Yes the comment can be removed. This is added when the test file CHECK annotations are automatically added using that tool.

[lewis-revill]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

101

Nitpick: add the /*IsRet=*/ comment.
TLI.analyzeOutputArgs(MF, CCInfo, Outs, /*IsRet=*/true, nullptr);

[wwei]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

101

done

[wwei]

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll

0–1

removed.

[wwei]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

55

That's correct.

[wwei]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

114

In my opinion, using a helper function will make the code more clear and concise, which is really a personal preference issue, regardless of whether the implementation is correct or not.

[lewis-revill]

Thanks for addressing the comments, I'd like some input from others before saying this looks good.

[dsanders]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

159

You shouldn't need to drop all the way down to align 1 for the subsequent parts. For example if we start with 8 byte alignment, an offset of 4 leaves us with 4 bytes alignment. commonAlignment(Align A, uint64_t Offset) should compute it for you

llvm/lib/Target/RISCV/RISCVCallLowering.h

 
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/ValueTypes.h"
 
 namespace llvm {
 
 class RISCVTargetLowering;
+class MachineInstrBuilder;
+class MachineIRBuilder;
 
 class RISCVCallLowering : public CallLowering {
 
 public:
   RISCVCallLowering(const RISCVTargetLowering &TLI);
 
   bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val,
                    ArrayRef<Register> VRegs) const override;
 
   bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
                             ArrayRef<ArrayRef<Register>> VRegs) const override;
 
   bool lowerCall(MachineIRBuilder &MIRBuilder,
                  CallLoweringInfo &Info) const override;
+
+private:
+  bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
+                      ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
+
+  /// A function of this type is used to perform value split action.
+  using SplitArgTy = std::function<void(ArrayRef<Register>, int)>;
+
+  template <typename T>
+  void setISDArgsForCallingConv(const Function &F, const ArgInfo &OrigArg,
+                                SmallVectorImpl<EVT> &SplitVTs,
+                                SmallVectorImpl<T> &ISDArgs, bool isRet) const;
+
+  void splitToValueTypes(const ArgInfo &OrigArg,
+                         SmallVectorImpl<ArgInfo> &SplitArgs,
+                         SmallVectorImpl<EVT> &SplitVTs, MachineFunction &MF,
+                         SplitArgTy PerformArgSplit) const;
+
+  template <typename T>
+  void updateArgLocInfo(SmallVectorImpl<CCValAssign> &ArgLocs,
+                        const SmallVectorImpl<T> &Arguments) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_RISCV_RISCVCALLLOWERING_H

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

 //===-- RISCVCallLowering.cpp - Call lowering -------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
 /// This file implements the lowering of LLVM calls to machine code calls for
 /// GlobalISel.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVCallLowering.h"
 #include "RISCVISelLowering.h"
+#include "llvm/CodeGen/Analysis.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 
 using namespace llvm;
 
+namespace {
+
+struct OutgoingValueHandler : public CallLowering::ValueHandler {
+  OutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
+                       MachineInstrBuilder MIB, CCAssignFn *AssignFn)
+      : ValueHandler(B, MRI, AssignFn), MIB(MIB) {}
+
+  MachineInstrBuilder MIB;
+
+  bool isIncomingArgumentHandler() const override { return false; }
+
+  Register getStackAddress(uint64_t Size, int64_t Offset,
+                           MachinePointerInfo &MPO) override {
+    llvm_unreachable("not implemented");
+  }
+
+  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
+                            MachinePointerInfo &MPO, CCValAssign &VA) override {
+    llvm_unreachable("not implemented");
+  }
+
+  void assignValueToReg(Register ValVReg, Register PhysReg,
+                        CCValAssign &VA) override {
+    Register ExtReg = extendRegister(ValVReg, VA);
+    MIRBuilder.buildCopy(PhysReg, ExtReg);
+    MIB.addUse(PhysReg, RegState::Implicit);
+  }
+
+  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
+                 CCValAssign::LocInfo LocInfo,
+                 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
+                 CCState &State) override {
+    if (AssignFn)
+      return AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
+    return false;
+  }
+};
+
+} // namespace
+
 RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI)
     : CallLowering(&TLI) {}
 
+bool RISCVCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
+                                       const Value *Val,
+                                       ArrayRef<Register> VRegs,
+                                       MachineInstrBuilder &Ret) const {
+  if (!Val)
+    return true;
+
+  // TODO: Only integer, pointer and aggregate types are supported now.
+  if (!Val->getType()->isIntOrPtrTy() && !Val->getType()->isAggregateType())
+    return false;
+
+  MachineFunction &MF = MIRBuilder.getMF();
+  const Function &F = MF.getFunction();
+  const DataLayout &DL = MF.getDataLayout();
+  const RISCVTargetLowering &TLI = *getTLI<RISCVTargetLowering>();
+
+  SmallVector<EVT, 4> SplitEVTs;
+  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
+  assert(VRegs.size() == SplitEVTs.size() &&
+         "For each split Type there should be exactly one VReg.");
+
+  ArgInfo OrigRetInfo(VRegs, Val->getType());
+  setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
+
+  SmallVector<ArgInfo, 4> SplitRetInfos;
+  splitToValueTypes(OrigRetInfo, SplitRetInfos, SplitEVTs, MF,
+                    [&](ArrayRef<Register> Regs, int SplitIdx) {
+                      MIRBuilder.buildUnmerge(Regs, VRegs[SplitIdx]);
+                    });
+
+  SmallVector<ISD::OutputArg, 8> Outs;
+  setISDArgsForCallingConv(F, OrigRetInfo, SplitEVTs, Outs, true);
+
+  SmallVector<CCValAssign, 16> ArgLocs;
+  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
+
+  TLI.analyzeOutputArgs(MF, CCInfo, Outs, /*IsRet=*/true, nullptr);
+  updateArgLocInfo(ArgLocs, Outs);
+
+  OutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret, nullptr);
+  return handleAssignments(CCInfo, ArgLocs, MIRBuilder, SplitRetInfos, Handler);
+}
+
 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                     const Value *Val,
                                     ArrayRef<Register> VRegs) const {
+  assert(!Val == VRegs.empty() && "Return value without a vreg");
 
   MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
-
-  if (Val != nullptr) {
+  if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
     return false;
-  }
+
   MIRBuilder.insertInstr(Ret);
   return true;
 }
 
 bool RISCVCallLowering::lowerFormalArguments(
     MachineIRBuilder &MIRBuilder, const Function &F,
     ArrayRef<ArrayRef<Register>> VRegs) const {
 
   if (F.arg_empty())
     return true;
 
   return false;
 }
 
 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
                                   CallLoweringInfo &Info) const {
   return false;
 }
+
+template <typename T>
+void RISCVCallLowering::setISDArgsForCallingConv(const Function &F,
+                                                 const ArgInfo &OrigArg,
+                                                 SmallVectorImpl<EVT> &SplitVTs,
+                                                 SmallVectorImpl<T> &ISDArgs,
+                                                 bool isRet) const {
+  const DataLayout &DL = F.getParent()->getDataLayout();
+  LLVMContext &Ctx = F.getContext();
+  CallingConv::ID CC = F.getCallingConv();
+  const RISCVTargetLowering &TLI = *getTLI<RISCVTargetLowering>();
+
+  for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
+    EVT VT = SplitVTs[i];
+    Type *SplitTy = VT.getTypeForEVT(Ctx);
+    MVT RegisterVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, VT);
+    unsigned NumParts = TLI.getNumRegistersForCallingConv(Ctx, CC, VT);
+
+    for (unsigned j = 0; j < NumParts; ++j) {
+      auto Flags = OrigArg.Flags[0];
+
+      if (j == 0)
+        Flags.setOrigAlign(TLI.getABIAlignmentForCallingConv(SplitTy, DL));
+      else
+        Flags.setOrigAlign(Align(1));
+
+      ISDArgs.emplace_back(Flags, RegisterVT, VT, true, isRet ? 0 : i, 0);
+    }
+  }
+}
+
+void RISCVCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
+                                          SmallVectorImpl<ArgInfo> &SplitArgs,
+                                          SmallVectorImpl<EVT> &SplitVTs,
+                                          MachineFunction &MF,
+                                          SplitArgTy PerformArgSplit) const {
+  const RISCVTargetLowering &TLI = *getTLI<RISCVTargetLowering>();
+  LLVMContext &Ctx = OrigArg.Ty->getContext();
+  CallingConv::ID CC = MF.getFunction().getCallingConv();
+  const DataLayout &DL = MF.getDataLayout();
+
+  // Create one ArgInfo for each virtual register in the original ArgInfo.
+  for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
+    EVT VT = SplitVTs[i];
+    Type *SplitTy = VT.getTypeForEVT(Ctx);
+    auto Flags = OrigArg.Flags[0];
+    Flags.setOrigAlign(Align(DL.getABITypeAlignment(SplitTy)));
+
+    unsigned NumParts = TLI.getNumRegistersForCallingConv(Ctx, CC, VT);
+    if (NumParts == 1) {
+      SplitArgs.emplace_back(OrigArg.Regs[i], VT.getTypeForEVT(Ctx), Flags,
+                             OrigArg.IsFixed);
+      continue;
+    }
+
+    SmallVector<Register, 8> SplitRegs;
+
+    EVT PartVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, VT);
+    Type *PartTy = PartVT.getTypeForEVT(Ctx);
+
+    for (unsigned j = 0; j < NumParts; ++j) {
+      ArgInfo Info = ArgInfo{MF.getRegInfo().createGenericVirtualRegister(
+                                 getLLTForType(*PartTy, DL)),
+                             PartTy, Flags};
+      SplitArgs.push_back(Info);
+      SplitRegs.push_back(Info.Regs[0]);
+    }
+
+    PerformArgSplit(SplitRegs, i);
+  }
+}
+
+template <typename T>
+void RISCVCallLowering::updateArgLocInfo(
+    SmallVectorImpl<CCValAssign> &ArgLocs,
+    const SmallVectorImpl<T> &Arguments) const {
+  for (unsigned i = 0; i < ArgLocs.size(); ++i) {
+    const CCValAssign &VA = ArgLocs[i];
+    CCValAssign::LocInfo LocInfo = VA.getLocInfo();
+    // TODO: LocInfo type for BCvt and Indirect need be changed?
+    if (LocInfo == CCValAssign::BCvt || LocInfo == CCValAssign::Indirect)
+      continue;
+
+    if (Arguments[i].ArgVT.getSizeInBits() >= Arguments[i].VT.getSizeInBits()) {
+      assert(LocInfo == CCValAssign::Full && "Unexpected CCValAssign::LocInfo");
+      continue;
+    }
+
+    if (Arguments[i].Flags.isSExt())
+      LocInfo = CCValAssign::LocInfo::SExt;
+    else if (Arguments[i].Flags.isZExt())
+      LocInfo = CCValAssign::LocInfo::ZExt;
+    else
+      LocInfo = CCValAssign::LocInfo::AExt;
+
+    if (VA.isMemLoc())
+      ArgLocs[i] =
+          CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
+                              VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
+    else
+      ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
+                                       VA.getLocReg(), VA.getLocVT(), LocInfo);
+  }
+}

llvm/lib/Target/RISCV/RISCVISelLowering.h

public:
 
   /// Returns the register with the specified architectural or ABI name. This
   /// method is necessary to lower the llvm.read_register.* and
   /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
   /// with the clang -ffixed-xX flag for access to be allowed.
   Register getRegisterByName(const char *RegName, LLT VT,
                              const MachineFunction &MF) const override;
 
-private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,
                         bool IsRet) const;
   void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
                          const SmallVectorImpl<ISD::OutputArg> &Outs,
                          bool IsRet, CallLoweringInfo *CLI) const;
+
+private:
   // Lower incoming arguments, copy physregs into vregs
   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
                                bool IsVarArg,
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                const SDLoc &DL, SelectionDAG &DAG,
                                SmallVectorImpl<SDValue> &InVals) const override;
   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
                       bool IsVarArg,

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator-calllowering.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 
-define void @foo() {
-  ; RV32I-LABEL: name: foo
+define void @test_ret_void() {
+  ; RV32I-LABEL: name: test_ret_void
   ; RV32I: bb.1.entry:
   ; RV32I-NEXT:   PseudoRET
 
-  ; RV64I-LABEL: name: foo
+  ; RV64I-LABEL: name: test_ret_void
   ; RV64I: bb.1.entry:
   ; RV64I-NEXT:   PseudoRET
 entry:
   ret void
 }
+
+define i8 @test_ret_i8() {
+  ; RV32I-LABEL: name: test_ret_i8
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+  ; RV32I-NEXT:   [[AEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[CST]](s8)
+  ; RV32I-NEXT:   $x10 = COPY [[AEXT]](s32)
+  ; RV32I-NEXT:   PseudoRET implicit $x10
+
+  ; RV64I-LABEL: name: test_ret_i8
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+  ; RV64I-NEXT:   [[AEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CST]](s8)
+  ; RV64I-NEXT:   $x10 = COPY [[AEXT]](s64)
+  ; RV64I-NEXT:   PseudoRET implicit $x10
+entry:
+    ret i8 1
+}
+
+define zeroext i8 @test_ret_i8_zext() {
+  ; RV32I-LABEL: name: test_ret_i8_zext
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+  ; RV32I-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[CST]](s8)
+  ; RV32I-NEXT:   $x10 = COPY [[ZEXT]](s32)
+  ; RV32I-NEXT:   PseudoRET implicit $x10
+
+  ; RV64I-LABEL: name: test_ret_i8_zext
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+  ; RV64I-NEXT:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CST]](s8)
+  ; RV64I-NEXT:   $x10 = COPY [[ZEXT]](s64)
+  ; RV64I-NEXT:   PseudoRET implicit $x10
+entry:
+    ret i8 1
+}
+
+define signext i16 @test_ret_i16_sext() {
+  ; RV32I-LABEL: name: test_ret_i16_sext
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+  ; RV32I-NEXT:   [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[CST]](s16)
+  ; RV32I-NEXT:   $x10 = COPY [[SEXT]](s32)
+  ; RV32I-NEXT:   PseudoRET implicit $x10
+
+  ; RV64I-LABEL: name: test_ret_i16_sext
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+  ; RV64I-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[CST]](s16)
+  ; RV64I-NEXT:   $x10 = COPY [[SEXT]](s64)
+  ; RV64I-NEXT:   PseudoRET implicit $x10
+entry:
+    ret i16 1
+}
+
+define i32 @test_ret_i32() {
+  ; RV32I-LABEL: name: test_ret_i32
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; RV32I-NEXT:   $x10 = COPY [[CST]](s32)
+  ; RV32I-NEXT:   PseudoRET implicit $x10
+
+  ; RV64I-LABEL: name: test_ret_i32
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; RV64I-NEXT:   [[AEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[CST]](s32)
+  ; RV64I-NEXT:   $x10 = COPY [[AEXT]](s64)
+  ; RV64I-NEXT:   PseudoRET implicit $x10
+entry:
+  ret i32 1
+}
+
+define i64 @test_ret_i64() {
+  ; RV32I-LABEL: name: test_ret_i64
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967296
+  ; RV32I-NEXT:   [[CST1:%[0-9]+]]:_(s32), [[CST2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CST]](s64)
+  ; RV32I-NEXT:   $x10 = COPY [[CST1]](s32)
+  ; RV32I-NEXT:   $x11 = COPY [[CST2]](s32)
+  ; RV32I-NEXT:   PseudoRET implicit $x10, implicit $x11
+
+  ; RV64I-LABEL: name: test_ret_i64
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967296
+  ; RV64I-NEXT:   $x10 = COPY [[CST]](s64)
+  ; RV64I-NEXT:   PseudoRET implicit $x10
+entry:
+  ret i64 4294967296
+}
+
+define i32* @test_ret_i32_ptr() {
+  ; RV32I-LABEL: name: test_ret_i32_ptr
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[UDEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+  ; RV32I-NEXT:   $x10 = COPY [[UDEF]](p0)
+  ; RV32I-NEXT:   PseudoRET implicit $x10
+
+  ; RV64I-LABEL: name: test_ret_i32_ptr
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[UDEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+  ; RV64I-NEXT:   $x10 = COPY [[UDEF]](p0)
+  ; RV64I-NEXT:   PseudoRET implicit $x10
+entry:
+  ret i32* undef
+}
+
+define [2 x i32] @test_ret_2xi32() {
+  ; RV32I-LABEL: name: test_ret_2xi32
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; RV32I-NEXT:   [[CST2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+  ; RV32I-NEXT:   $x10 = COPY [[CST1]](s32)
+  ; RV32I-NEXT:   $x11 = COPY [[CST2]](s32)
+  ; RV32I-NEXT:   PseudoRET implicit $x10, implicit $x11
+
+  ; RV64I-LABEL: name: test_ret_2xi32
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; RV64I-NEXT:   [[CST2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+  ; RV64I-NEXT:   [[AEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[CST1]](s32)
+  ; RV64I-NEXT:   $x10 = COPY [[AEXT1]](s64)
+  ; RV64I-NEXT:   [[AEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[CST2]](s32)
+  ; RV64I-NEXT:   $x11 = COPY [[AEXT2]](s64)
+  ; RV64I-NEXT:   PseudoRET implicit $x10, implicit $x11
+entry:
+  ret [2 x i32] [i32 1, i32 2]
+}