Added tests for instructions with 0 and 2 defs.

Fixed G_FCONSTANT and added test for it.

Extracted MIPatternMtach changes.

Added basic version of isCanonicalized for global-isel. Copied from sdag.

Rebased. Updated uniform test (Jay fixed reg-bank-select for uniform min and max) and added test for v2i16 which we don't combine.
Renamed G_AMDGPU_MED3 to G_AMDGPU_SMED3 since this patch also adds UMED3.

Looks good, I would like for other reviewers to also take a look.

Removed isVector checks for non-Vector opcodes. Use Register instead of unsigned.

Add a few unit tests and break for vector types on some opcodes.

There is no need for helper state class.

Dropping icmp move for from this patch. Leaving zext_trunc_fold.
Zext is selected into AND with 1. zext_trunc_fold results in getting rid of the SCC copies when zext was the only instruction between icmp and select/branch.

Ping.

Use replaceSingleDefInstWithReg.

Use zext_trunc_fold from generic combiner to separately fold all cases of zext(trunc x) -> x made by regbankselect.
icmp move before select/brcond has to be aware of current state of MF since we run combines top-down and instructions (trunc) can be left without uses (zext was deleted by zext_trunc_fold)

Adding vectors.

Adding non-splat test.
isKnownToBeAPowerOfTwo ends up checking known bits for build_vector and fails for non-splat values.

Handle some cases with many uses. Adding icmp fold without move for the case when we can't move icmp because code looks nicer in the case with more than one use.

Addressed review comments.

Removing target dependent semantics.

Sorry about the delay. Use (int)Offset to check for one in most significant bit and potential unsigned overflow. DAG equivalent in SITargetLowering::setBufferOffsets also uses int for offset.

Move combines after register bank select. Check for register bank of the result register and only combine for vgpr bank. There is mir test for sgpr bank min/max input for completeness. However sgpr bank min/max are transformed to compare + select in regbankselect and we should not expect them in post regbank combiner.

Should we move this combine after register bank select and skip min/max with sgpr bank?

Address review comments.

Use MIPatternMatch to match source pattern. Use Optional instead of return 0. Separate from fp med3 function to avoid bitcasted G_FCONSTANT and explicitly match G_CONSTANT.

Add braces.

Pre-commit the test.

Use setInstrAndDebugLoc.

Respect description of ISD::FMAXNUM and ISD::FMAXNUM_IEEE (their behavior is not affected by IEEE mode).
Legalizer will deal with use of FMAXNUM when IEEE=true (makes sure that potential SNaN input gets quieted) and we can try to fold FMAXNUM_IEEE later.
Most of the test changes come from clamp/fmed on top of fcanonicalize with IEEE=true.

Fix typos.

Patch also affects constants with vector type. Effectively, during legalization, fcanonicalize will not be inserted when input was vector constant.

define amdgpu_kernel void @maxnum_v2f16_imm_b(<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %a) {
entry:
  %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
  %add = fadd <2 x half> %a.val, <half 9.0, half 8.0>
  %r.val = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %add, <2 x half> <half 4.0, half 3.0>) ;<half 4.0, half 3.0> will not get fcanonicalized during legalization after this patch
  store <2 x half> %r.val, <2 x half> addrspace(1)* %r
  ret void
}

This won't be visible in end result since there is fcanonicalize + build_vector combine in SITargetLowering::performFCanonicalizeCombine. Test changes were for non-constant build_vectors.
Add comment to indicate vector constants are handled bellow.

Simplify logic in 'is safe to clamp' checks.