[DAGCombine][ARM] x ==/!= c -> (x - c) ==/!= 0 iff '-c' can be folded into the x node.

[lebedev.ri]

Summary

This fold, helps recover from the rest of the D62266 ARM regressions.
https://rise4fun.com/Alive/TvpC

Note that while the fold is quite flexible, i'we restricted it
to the single interesting pattern at the moment.

[lebedev.ri]

Rebased, ping @efriedma.

[efriedma]

Can you add test coverage for some other target, maybe x86?

Can you add test coverage for a few more variations? Maybe something with SUBCARRY?

[lebedev.ri]

In D62450#1525641, @efriedma wrote:

Can you add test coverage for some other target, maybe x86?

Can you add test coverage for a few more variations? Maybe something with SUBCARRY?

I don't know how to add standalone test coverage here.

[deadalnix]

It's indeed not clear if what you have is the result of the legalizer. In this case just proceed.

[lebedev.ri]

In D62450#1717999, @deadalnix wrote:

It's indeed not clear if what you have is the result of the legalizer. In this case just proceed.

Okay :(
Thanks for the review.

[mstorsjo]

This broke building of Qt, ffmpeg/libav and libgcrypt for mingw-i686, with failed asserts `BitWidth == RHS.BitWidth && "Bit widths must be the same"', see https://bugs.llvm.org/show_bug.cgi?id=43769 for reproduction sample.

[hans]

In D62450#1718457, @mstorsjo wrote:

This broke building of Qt, ffmpeg/libav and libgcrypt for mingw-i686, with failed asserts `BitWidth == RHS.BitWidth && "Bit widths must be the same"', see https://bugs.llvm.org/show_bug.cgi?id=43769 for reproduction sample.

It also broke Chromium, see https://bugs.chromium.org/p/chromium/issues/detail?id=1016949#c1 for our reproducer.

I've reverted in 684ebc6.

[lebedev.ri]

In D62450#1719057, @hans wrote:

In D62450#1718457, @mstorsjo wrote:

This broke building of Qt, ffmpeg/libav and libgcrypt for mingw-i686, with failed asserts `BitWidth == RHS.BitWidth && "Bit widths must be the same"', see https://bugs.llvm.org/show_bug.cgi?id=43769 for reproduction sample.

It also broke Chromium, see https://bugs.chromium.org/p/chromium/issues/detail?id=1016949#c1 for our reproducer.

I've reverted in 684ebc6.

Thanks, this one is different from the first report.

llvm/include/llvm/CodeGen/TargetLowering.h

private:
 
   SDValue prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
                             SDValue CompTargetNode, ISD::CondCode Cond,
                             DAGCombinerInfo &DCI, const SDLoc &DL,
                             SmallVectorImpl<SDNode *> &Created) const;
   SDValue buildSREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
                           ISD::CondCode Cond, DAGCombinerInfo &DCI,
                           const SDLoc &DL) const;
+
+  /// x ==/!= c  ->  (x - c) ==/!= 0  iff '-c' can be folded into the x node.
+  SDValue optimizeSetCCToComparisonWithZero(EVT SCCVT, SDValue N0,
+                                            ConstantSDNode *N1C,
+                                            ISD::CondCode Cond,
+                                            DAGCombinerInfo &DCI,
+                                            const SDLoc &DL) const;
 };
 
 /// Given an LLVM IR type and return type attributes, compute the return value
 /// EVTs and flags, and optionally also the offsets, if the return value is
 /// being lowered to memory.
 void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr,
                    SmallVectorImpl<ISD::OutputArg> &Outs,
                    const TargetLowering &TLI, const DataLayout &DL);
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_TARGETLOWERING_H

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(),
                                  !DCI.isBeforeLegalize());
   SDValue One = DAG.getConstant(1, DL, ShiftVT);
   SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One);
   if (!DCI.isCalledByLegalizer())
     DCI.AddToWorklist(YShl1.getNode());
   return DAG.getSetCC(DL, VT, X, YShl1, Cond);
 }
 
+/// x ==/!= c  ->  (x - c) ==/!= 0  iff '-c' can be folded into the x node.
+SDValue TargetLowering::optimizeSetCCToComparisonWithZero(
+    EVT SCCVT, SDValue N0, ConstantSDNode *N1C, ISD::CondCode Cond,
+    DAGCombinerInfo &DCI, const SDLoc &DL) const {
+  assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+         "Only for equality-comparisons.");
+
+  // LHS should not be used elsewhere, to avoid creating an extra node.
+  if (!N0.hasOneUse())
+    return SDValue();
+
+  // Will we able to fold the '-c' into 'x' node?
+  bool IsAdd;
+  switch (N0.getOpcode()) {
+  default:
+    return SDValue(); // Don't know about that node.
+  case ISD::ADD:
+  case ISD::SUB:
+    return SDValue(); // Let's not touch these.
+  case ISD::ADDCARRY:
+    IsAdd = true;
+    break;
+  case ISD::SUBCARRY:
+    IsAdd = false;
+    break;
+  }
+
+  // Second operand must be a constant.
+  ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
+  if (!N01C)
+    return SDValue();
+
+  // And let's be even more specific for now, it must be a zero constant.
+  // It is possible to relax this requirement, but a precise cost-model needed.
+  if (!N01C->isNullValue())
+    return SDValue();
+
+  SelectionDAG &DAG = DCI.DAG;
+  EVT OpVT = N0.getValueType();
+
+  // (y + N01C) - N1C = y + (N01C - N1C)
+  // (y - N01C) - N1C = y - (N01C + N1C)
+  SDValue NewC = DAG.FoldConstantArithmetic(IsAdd ? ISD::SUB : ISD::ADD, DL,
+                                            OpVT, N01C, N1C);
+  assert(NewC && "Constant-folding failed!");
+
+  SmallVector<SDValue, 3> N0Ops(N0.getNode()->ops().begin(),
+                                N0.getNode()->ops().end());
+  N0Ops[1] = NewC;
+
+  N0 = DAG.getNode(N0.getOpcode(), DL, N0->getVTList(), N0Ops);
+
+  SDValue Zero = DAG.getConstant(0, DL, OpVT);
+  return DAG.getSetCC(DL, SCCVT, N0, Zero, Cond);
+}
+
 /// Try to simplify a setcc built with the specified operands and cc. If it is
 /// unable to simplify it, return a null SDValue.
 SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
                                       ISD::CondCode Cond, bool foldBooleans,
                                       DAGCombinerInfo &DCI,
                                       const SDLoc &dl) const {
   SelectionDAG &DAG = DCI.DAG;
   EVT OpVT = N0.getValueType();
if (auto *N1C = isConstOrConstSplat(N1)) {
     if (Cond == ISD::SETEQ || Cond == ISD::SETNE) {
       // (X & (C l>>/<< Y)) ==/!= 0  -->  ((X <</l>> Y) & C) ==/!= 0
       if (C1.isNullValue())
         if (SDValue CC = optimizeSetCCByHoistingAndByConstFromLogicalShift(
                 VT, N0, N1, Cond, DCI, dl))
           return CC;
     }
 
+    if (Cond == ISD::SETEQ || Cond == ISD::SETNE)
+      if (SDValue CC =
+              optimizeSetCCToComparisonWithZero(VT, N0, N1C, Cond, DCI, dl))
+        return CC;
+
     // If we have "setcc X, C0", check to see if we can shrink the immediate
     // by changing cc.
     // TODO: Support this for vectors after legalize ops.
     if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
       // SETUGT X, SINTMAX  -> SETLT X, 0
       if (Cond == ISD::SETUGT &&
           C1 == APInt::getSignedMaxValue(OperandBitSize))
         return DAG.getSetCC(dl, VT, N0,

llvm/test/CodeGen/ARM/addsubcarry-promotion.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O2 -mtriple armv7a < %s | FileCheck --check-prefixes=ARM,ARMV7A %s
 
 ; RUN: llc -O2 -mtriple thumbv6m < %s | FileCheck --check-prefixes=THUMB1,THUMBV6M %s
 ; RUN: llc -O2 -mtriple thumbv8m.base < %s | FileCheck --check-prefixes=THUMB1,THUMBV8M-BASE %s
 
 ; RUN: llc -O2 -mtriple thumbv7a < %s | FileCheck --check-prefixes=THUMB,THUMBV7A %s
 ; RUN: llc -O2 -mtriple thumbv8m.main < %s | FileCheck --check-prefixes=THUMB,THUMBV8M-MAIN %s
 
 define void @fn1(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 {
 ; ARM-LABEL: fn1:
 ; ARM:       @ %bb.0: @ %entry
 ; ARM-NEXT:    rsb r2, r2, #0
 ; ARM-NEXT:    adds r0, r1, r0
 ; ARM-NEXT:    movw r1, #65535
 ; ARM-NEXT:    sxth r2, r2
-; ARM-NEXT:    adc r0, r2, #0
-; ARM-NEXT:    uxth r0, r0
-; ARM-NEXT:    cmp r0, r1
+; ARM-NEXT:    adc r0, r2, #1
+; ARM-NEXT:    tst r0, r1
 ; ARM-NEXT:    bxeq lr
 ; ARM-NEXT:  .LBB0_1: @ %for.cond
 ; ARM-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; ARM-NEXT:    b .LBB0_1
 ;
-; THUMBV6M-LABEL: fn1:
-; THUMBV6M:       @ %bb.0: @ %entry
-; THUMBV6M-NEXT:    rsbs r2, r2, #0
-; THUMBV6M-NEXT:    sxth r2, r2
-; THUMBV6M-NEXT:    movs r3, #0
-; THUMBV6M-NEXT:    adds r0, r1, r0
-; THUMBV6M-NEXT:    adcs r3, r2
-; THUMBV6M-NEXT:    uxth r0, r3
-; THUMBV6M-NEXT:    ldr r1, .LCPI0_0
-; THUMBV6M-NEXT:    cmp r0, r1
-; THUMBV6M-NEXT:    beq .LBB0_2
-; THUMBV6M-NEXT:  .LBB0_1: @ %for.cond
-; THUMBV6M-NEXT:    @ =>This Inner Loop Header: Depth=1
-; THUMBV6M-NEXT:    b .LBB0_1
-; THUMBV6M-NEXT:  .LBB0_2: @ %if.end
-; THUMBV6M-NEXT:    bx lr
-; THUMBV6M-NEXT:    .p2align 2
-; THUMBV6M-NEXT:  @ %bb.3:
-; THUMBV6M-NEXT:  .LCPI0_0:
-; THUMBV6M-NEXT:    .long 65535 @ 0xffff
-;
-; THUMBV8M-BASE-LABEL: fn1:
-; THUMBV8M-BASE:       @ %bb.0: @ %entry
-; THUMBV8M-BASE-NEXT:    rsbs r2, r2, #0
-; THUMBV8M-BASE-NEXT:    sxth r2, r2
-; THUMBV8M-BASE-NEXT:    movs r3, #0
-; THUMBV8M-BASE-NEXT:    adds r0, r1, r0
-; THUMBV8M-BASE-NEXT:    adcs r3, r2
-; THUMBV8M-BASE-NEXT:    uxth r0, r3
-; THUMBV8M-BASE-NEXT:    movw r1, #65535
-; THUMBV8M-BASE-NEXT:    cmp r0, r1
-; THUMBV8M-BASE-NEXT:    beq .LBB0_2
-; THUMBV8M-BASE-NEXT:  .LBB0_1: @ %for.cond
-; THUMBV8M-BASE-NEXT:    @ =>This Inner Loop Header: Depth=1
-; THUMBV8M-BASE-NEXT:    b .LBB0_1
-; THUMBV8M-BASE-NEXT:  .LBB0_2: @ %if.end
-; THUMBV8M-BASE-NEXT:    bx lr
+; THUMB1-LABEL: fn1:
+; THUMB1:       @ %bb.0: @ %entry
+; THUMB1-NEXT:    rsbs r2, r2, #0
+; THUMB1-NEXT:    sxth r2, r2
+; THUMB1-NEXT:    movs r3, #1
+; THUMB1-NEXT:    adds r0, r1, r0
+; THUMB1-NEXT:    adcs r3, r2
+; THUMB1-NEXT:    lsls r0, r3, #16
+; THUMB1-NEXT:    beq .LBB0_2
+; THUMB1-NEXT:  .LBB0_1: @ %for.cond
+; THUMB1-NEXT:    @ =>This Inner Loop Header: Depth=1
+; THUMB1-NEXT:    b .LBB0_1
+; THUMB1-NEXT:  .LBB0_2: @ %if.end
+; THUMB1-NEXT:    bx lr
 ;
 ; THUMB-LABEL: fn1:
 ; THUMB:       @ %bb.0: @ %entry
 ; THUMB-NEXT:    rsbs r2, r2, #0
 ; THUMB-NEXT:    adds r0, r0, r1
-; THUMB-NEXT:    movw r1, #65535
 ; THUMB-NEXT:    sxth r2, r2
-; THUMB-NEXT:    adc r0, r2, #0
-; THUMB-NEXT:    uxth r0, r0
-; THUMB-NEXT:    cmp r0, r1
+; THUMB-NEXT:    adc r0, r2, #1
+; THUMB-NEXT:    lsls r0, r0, #16
 ; THUMB-NEXT:    it eq
 ; THUMB-NEXT:    bxeq lr
 ; THUMB-NEXT:  .LBB0_1: @ %for.cond
 ; THUMB-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; THUMB-NEXT:    b .LBB0_1
 entry:
   %add = add i32 %b, %a
   %cmp = icmp ult i32 %add, %b