[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)

[lebedev.ri]

Summary

This *might* be the last fold for sink-addsub-of-const.ll, but i'm not sure yet.

As far as i can tell, there are no regressions here (ignoring x86-32),
all changes are either good or neutral.

This, almost surprisingly to me, fixes the motivational tests (in shift-amount-mod.ll)
@reg32_lshr_by_sub_from_negated from PR41952.

https://rise4fun.com/Alive/vMd3

[RKSimon]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

3017 ↗

(On Diff #202546)

Do we gain anything from the general case here? This seems to cause a small increase in register pressure in many cases - limit to the (0 - x) - y negation case only?

[lebedev.ri]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

3017 ↗

(On Diff #202546)

Could you please be more specific?
The only regressions i'm seeing are 32-bit @reg64_lshr_by_sub_from_negated*
The obvious positives are all these newly-formed neg
https://godbolt.org/z/JK0ldm <- which is kinda the endgoal here.

If we limit this to only hoist neg (and this will be the first such restriction
in all of these patches), then naturally, the @reg64_lshr_by_sub_from_negated*
pattern will no longer produce neg, since the sub 64, %x will not be sunk.

That can still be fixed, if we transform C-X to neg(x)+C or so in DAGCombine,
I was actually going to look into that, but it looked to not be necessary
with this patch in it's current form.

[RKSimon]

LGTM

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

3017 ↗

(On Diff #202546)

Yes I think your right - sorry I was being over cautious!

[lebedev.ri]

Thank you for the review!

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

3017 ↗

(On Diff #202546)

No problem, thank you for confirming my understanding here!

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitSUB(SDNode *N) {
   }
   // (x - C) - y  ->  (x - y) - C
   // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
   if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
       isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
     SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
     return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
   }
+  // (C - x) - y  ->  C - (x + y)
+  if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
+      isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
+    SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
+    return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
+  }
 
   // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
   // rather than 'sub 0/1' (the sext should get folded).
   // sub X, (zext i1 Y) --> add X, (sext i1 Y)
   if (N1.getOpcode() == ISD::ZERO_EXTEND &&
       N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
       TLI.getBooleanContents(VT) ==
           TargetLowering::ZeroOrNegativeOneBooleanContent) {

llvm/trunk/test/CodeGen/AArch64/shift-amount-mod.ll

 ;||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||;
 
 ;==============================================================================;
 ; subtraction from negated shift amount
 
 define i32 @reg32_lshr_by_sub_from_negated(i32 %val, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: reg32_lshr_by_sub_from_negated:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #32
-; CHECK-NEXT:    sub w8, w8, w1
-; CHECK-NEXT:    sub w8, w8, w2
+; CHECK-NEXT:    add w8, w1, w2
+; CHECK-NEXT:    neg w8, w8
 ; CHECK-NEXT:    lsr w0, w0, w8
 ; CHECK-NEXT:    ret
   %nega = sub i32 32, %a
   %negasubb = sub i32 %nega, %b
   %shifted = lshr i32 %val, %negasubb
   ret i32 %shifted
 }
 define i64 @reg64_lshr_by_sub_from_negated(i64 %val, i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: reg64_lshr_by_sub_from_negated:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #64
-; CHECK-NEXT:    sub x8, x8, x1
-; CHECK-NEXT:    sub x8, x8, x2
+; CHECK-NEXT:    add x8, x1, x2
+; CHECK-NEXT:    neg x8, x8
 ; CHECK-NEXT:    lsr x0, x0, x8
 ; CHECK-NEXT:    ret
   %nega = sub i64 64, %a
   %negasubb = sub i64 %nega, %b
   %shifted = lshr i64 %val, %negasubb
   ret i64 %shifted
 }
 
; CHECK-NEXT:    ret
   %negaaddbitwidth = add i64 %negshamt, 64
   %shifted = lshr i64 %val, %negaaddbitwidth
   ret i64 %shifted
 }
 
 define i32 @reg32_lshr_by_negated_unfolded_sub_b(i32 %val, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: reg32_lshr_by_negated_unfolded_sub_b:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    neg w8, w1
-; CHECK-NEXT:    sub w8, w8, w2
+; CHECK-NEXT:    add w8, w1, w2
+; CHECK-NEXT:    neg w8, w8
 ; CHECK-NEXT:    lsr w0, w0, w8
 ; CHECK-NEXT:    ret
   %nega = sub i32 0, %a
   %negaaddbitwidth = add i32 %nega, 32
   %negaaddbitwidthsubb = sub i32 %negaaddbitwidth, %b
   %shifted = lshr i32 %val, %negaaddbitwidthsubb
   ret i32 %shifted
 }
 define i64 @reg64_lshr_by_negated_unfolded_sub_b(i64 %val, i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: reg64_lshr_by_negated_unfolded_sub_b:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    neg x8, x1
-; CHECK-NEXT:    sub x8, x8, x2
+; CHECK-NEXT:    add x8, x1, x2
+; CHECK-NEXT:    neg x8, x8
 ; CHECK-NEXT:    lsr x0, x0, x8
 ; CHECK-NEXT:    ret
   %nega = sub i64 0, %a
   %negaaddbitwidth = add i64 %nega, 64
   %negaaddbitwidthsubb = sub i64 %negaaddbitwidth, %b
   %shifted = lshr i64 %val, %negaaddbitwidthsubb
   ret i64 %shifted
 }

llvm/trunk/test/CodeGen/AArch64/sink-addsub-of-const.ll

 }
 
 ; sub (sub C, %x), %y
 ; sub %y, (sub C, %x)
 
 define i32 @sink_sub_from_const_to_sub(i32 %a, i32 %b) {
 ; CHECK-LABEL: sink_sub_from_const_to_sub:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #32
-; CHECK-NEXT:    sub w8, w8, w0
-; CHECK-NEXT:    sub w0, w8, w1
+; CHECK-NEXT:    add w8, w0, w1
+; CHECK-NEXT:    mov w9, #32
+; CHECK-NEXT:    sub w0, w9, w8
 ; CHECK-NEXT:    ret
   %t0 = sub i32 32, %a
   %r = sub i32 %t0, %b
   ret i32 %r
 }
 define i32 @sink_sub_from_const_to_sub2(i32 %a, i32 %b) {
 ; CHECK-LABEL: sink_sub_from_const_to_sub2:
 ; CHECK:       // %bb.0:

 ; sub (sub C, %x), %y
 ; sub %y, (sub C, %x)
 
 define <4 x i32> @vec_sink_sub_from_const_to_sub(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: vec_sink_sub_from_const_to_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI22_0
 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI22_0]
+; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    sub v0.4s, v2.4s, v0.4s
-; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    ret
   %t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a
   %r = sub <4 x i32> %t0, %b
   ret <4 x i32> %r
 }
 define <4 x i32> @vec_sink_sub_from_const_to_sub2(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: vec_sink_sub_from_const_to_sub2:
 ; CHECK:       // %bb.0:

llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll

 }
 
 define i32 @fm9(i32 inreg %a) #0 {
 ; CHECK-LABEL: fm9:
 ; CHECK:       ! %bb.0:
 ; CHECK-NEXT:    st %fp, [--%sp]
 ; CHECK-NEXT:    add %sp, 0x8, %fp
 ; CHECK-NEXT:    sub %sp, 0x8, %sp
-; CHECK-NEXT:    sub %r0, %r6, %r3
-; CHECK-NEXT:    sh %r6, 0x3, %r9
-; CHECK-NEXT:    sub %r3, %r9, %rv
+; CHECK-NEXT:    sh %r6, 0x3, %r3
+; CHECK-NEXT:    add %r6, %r3, %r3
+; CHECK-NEXT:    sub %r0, %r3, %rv
 ; CHECK-NEXT:    ld -4[%fp], %pc ! return
 ; CHECK-NEXT:    add %fp, 0x0, %sp
 ; CHECK-NEXT:    ld -8[%fp], %fp
   %1 = mul nsw i32 %a, -9
   ret i32 %1
 }
 
 define i32 @fm10(i32 inreg %a) #0 {
 ; CHECK-LABEL: fm10:
 ; CHECK:       ! %bb.0:
 ; CHECK-NEXT:    st %fp, [--%sp]
 ; CHECK-NEXT:    add %sp, 0x8, %fp
 ; CHECK-NEXT:    sub %sp, 0x8, %sp
-; CHECK-NEXT:    sh %r6, 0x1, %r3
-; CHECK-NEXT:    sub %r0, %r3, %r3
-; CHECK-NEXT:    sh %r6, 0x3, %r9
-; CHECK-NEXT:    sub %r3, %r9, %rv
+; CHECK-NEXT:    sh %r6, 0x3, %r3
+; CHECK-NEXT:    sh %r6, 0x1, %r9
+; CHECK-NEXT:    add %r9, %r3, %r3
+; CHECK-NEXT:    sub %r0, %r3, %rv
 ; CHECK-NEXT:    ld -4[%fp], %pc ! return
 ; CHECK-NEXT:    add %fp, 0x0, %sp
 ; CHECK-NEXT:    ld -8[%fp], %fp
   %1 = mul nsw i32 %a, -10
   ret i32 %1
 }
 
 define i32 @h1(i32 inreg %a) #0 {

llvm/trunk/test/CodeGen/Mips/const-mult.ll

 ; MIPS32-NEXT:    addu $3, $3, $7
 ; MIPS32-NEXT:    addu $1, $3, $1
 ; MIPS32-NEXT:    addu $1, $1, $13
 ; MIPS32-NEXT:    subu $1, $4, $1
 ; MIPS32-NEXT:    sltu $3, $zero, $5
 ; MIPS32-NEXT:    subu $1, $1, $3
 ; MIPS32-NEXT:    subu $5, $1, $12
 ; MIPS32-NEXT:    subu $4, $9, $10
-; MIPS32-NEXT:    negu $1, $8
-; MIPS32-NEXT:    subu $3, $1, $11
+; MIPS32-NEXT:    addu $1, $8, $11
+; MIPS32-NEXT:    negu $3, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    negu $2, $2
 ;
 ; MIPS64-LABEL: mul170141183460469231731687303715884105723_128:
 ; MIPS64:       # %bb.0: # %entry
 ; MIPS64-NEXT:    dsrl $1, $4, 62
 ; MIPS64-NEXT:    dsll $2, $5, 2
 ; MIPS64-NEXT:    or $1, $2, $1

llvm/trunk/test/CodeGen/Mips/madd-msub.ll

 ; 32-NEXT:    mthi $1
 ; 32-NEXT:    msubu $5, $4
 ; 32-NEXT:    mfhi $2
 ; 32-NEXT:    jr $ra
 ; 32-NEXT:    mflo $3
 ;
 ; 32R6-LABEL: msub2:
 ; 32R6:       # %bb.0: # %entry
-; 32R6-NEXT:    mul $1, $5, $4
-; 32R6-NEXT:    sltu $2, $6, $1
-; 32R6-NEXT:    muhu $3, $5, $4
-; 32R6-NEXT:    negu $3, $3
-; 32R6-NEXT:    subu $2, $3, $2
+; 32R6-NEXT:    muhu $1, $5, $4
+; 32R6-NEXT:    mul $3, $5, $4
+; 32R6-NEXT:    sltu $2, $6, $3
+; 32R6-NEXT:    addu $1, $1, $2
+; 32R6-NEXT:    negu $2, $1
 ; 32R6-NEXT:    jr $ra
-; 32R6-NEXT:    subu $3, $6, $1
+; 32R6-NEXT:    subu $3, $6, $3
 ;
 ; DSP-LABEL: msub2:
 ; DSP:       # %bb.0: # %entry
 ; DSP-NEXT:    addiu $1, $zero, 0
 ; DSP-NEXT:    mtlo $6, $ac0
 ; DSP-NEXT:    mthi $1, $ac0
 ; DSP-NEXT:    msubu $ac0, $5, $4
 ; DSP-NEXT:    mfhi $2, $ac0

 ; 64R6-NEXT:    dmul $1, $5, $4
 ; 64R6-NEXT:    jr $ra
 ; 64R6-NEXT:    dsubu $2, $6, $1
 ;
 ; 16-LABEL: msub2:
 ; 16:       # %bb.0: # %entry
 ; 16-NEXT:    multu $5, $4
 ; 16-NEXT:    mflo $2
-; 16-NEXT:    mfhi $4
-; 16-NEXT:    subu $3, $6, $2
+; 16-NEXT:    mfhi $3
 ; 16-NEXT:    sltu $6, $2
-; 16-NEXT:    move $2, $24
-; 16-NEXT:    neg $4, $4
-; 16-NEXT:    subu $2, $4, $2
+; 16-NEXT:    move $4, $24
+; 16-NEXT:    addu $4, $3, $4
+; 16-NEXT:    subu $3, $6, $2
+; 16-NEXT:    neg $2, $4
 ; 16-NEXT:    jrc $ra
 entry:
   %conv = zext i32 %c to i64
   %conv2 = zext i32 %a to i64
   %conv4 = zext i32 %b to i64
   %mul = mul nsw i64 %conv4, %conv2
   %sub = sub nsw i64 %conv, %mul
   ret i64 %sub

llvm/trunk/test/CodeGen/X86/shift-amount-mod.ll

 
 ;==============================================================================;
 ; subtraction from negated shift amount
 
 define i32 @reg32_lshr_by_sub_from_negated(i32 %val, i32 %a, i32 %b) nounwind {
 ; X32-LABEL: reg32_lshr_by_sub_from_negated:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movl $32, %ecx
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    addl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    negb %cl
 ; X32-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X32-NEXT:    shrl %cl, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: reg32_lshr_by_sub_from_negated:
 ; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edx killed $edx def $rdx
+; X64-NEXT:    # kill: def $esi killed $esi def $rsi
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $32, %ecx
-; X64-NEXT:    subl %esi, %ecx
-; X64-NEXT:    subl %edx, %ecx
+; X64-NEXT:    leal (%rsi,%rdx), %ecx
+; X64-NEXT:    negb %cl
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shrl %cl, %eax
 ; X64-NEXT:    retq
   %nega = sub i32 32, %a
   %negasubb = sub i32 %nega, %b
   %shifted = lshr i32 %val, %negasubb
   ret i32 %shifted
 }
 define i64 @reg64_lshr_by_sub_from_negated(i64 %val, i64 %a, i64 %b) nounwind {
 ; X32-LABEL: reg64_lshr_by_sub_from_negated:
 ; X32:       # %bb.0:
 ; X32-NEXT:    pushl %esi
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; X32-NEXT:    movl $64, %ecx
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    addl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    movb $64, %cl
+; X32-NEXT:    subb %dl, %cl
 ; X32-NEXT:    movl %esi, %edx
 ; X32-NEXT:    shrl %cl, %edx
 ; X32-NEXT:    shrdl %cl, %esi, %eax
 ; X32-NEXT:    testb $32, %cl
 ; X32-NEXT:    je .LBB25_2
 ; X32-NEXT:  # %bb.1:
 ; X32-NEXT:    movl %edx, %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:  .LBB25_2:
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: reg64_lshr_by_sub_from_negated:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movl $64, %ecx
-; X64-NEXT:    subl %esi, %ecx
-; X64-NEXT:    subl %edx, %ecx
+; X64-NEXT:    leal (%rdx,%rsi), %ecx
+; X64-NEXT:    negb %cl
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shrq %cl, %rax
 ; X64-NEXT:    retq
   %nega = sub i64 64, %a
   %negasubb = sub i64 %nega, %b
   %shifted = lshr i64 %val, %negasubb
   ret i64 %shifted
 }
; X64-NEXT:    retq
   %shifted = lshr i64 %val, %negaaddbitwidth
   ret i64 %shifted
 }
 
 define i32 @reg32_lshr_by_negated_unfolded_sub_b(i32 %val, i32 %a, i32 %b) nounwind {
 ; X32-LABEL: reg32_lshr_by_negated_unfolded_sub_b:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    xorl %ecx, %ecx
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    addl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    negb %cl
 ; X32-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X32-NEXT:    shrl %cl, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: reg32_lshr_by_negated_unfolded_sub_b:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %esi, %ecx
+; X64-NEXT:    # kill: def $edx killed $edx def $rdx
+; X64-NEXT:    # kill: def $esi killed $esi def $rsi
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    negl %ecx
-; X64-NEXT:    subl %edx, %ecx
+; X64-NEXT:    leal (%rsi,%rdx), %ecx
+; X64-NEXT:    negb %cl
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shrl %cl, %eax
 ; X64-NEXT:    retq
   %nega = sub i32 0, %a
   %negaaddbitwidth = add i32 %nega, 32
   %negaaddbitwidthsubb = sub i32 %negaaddbitwidth, %b
   %shifted = lshr i32 %val, %negaaddbitwidthsubb
   ret i32 %shifted
 }
 define i64 @reg64_lshr_by_negated_unfolded_sub_b(i64 %val, i64 %a, i64 %b) nounwind {
 ; X32-LABEL: reg64_lshr_by_negated_unfolded_sub_b:
 ; X32:       # %bb.0:
 ; X32-NEXT:    pushl %esi
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; X32-NEXT:    xorl %ecx, %ecx
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    addb $64, %cl
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    addl {{[0-9]+}}(%esp), %edx
+; X32-NEXT:    movb $64, %cl
+; X32-NEXT:    subb %dl, %cl
 ; X32-NEXT:    movl %esi, %edx
 ; X32-NEXT:    shrl %cl, %edx
 ; X32-NEXT:    shrdl %cl, %esi, %eax
 ; X32-NEXT:    testb $32, %cl
 ; X32-NEXT:    je .LBB37_2
 ; X32-NEXT:  # %bb.1:
 ; X32-NEXT:    movl %edx, %eax
 ; X32-NEXT:    xorl %edx, %edx
 ; X32-NEXT:  .LBB37_2:
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: reg64_lshr_by_negated_unfolded_sub_b:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movl $64, %ecx
-; X64-NEXT:    subl %esi, %ecx
-; X64-NEXT:    subl %edx, %ecx
+; X64-NEXT:    leal (%rdx,%rsi), %ecx
+; X64-NEXT:    negb %cl
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shrq %cl, %rax
 ; X64-NEXT:    retq
   %nega = sub i64 0, %a
   %negaaddbitwidth = add i64 %nega, 64
   %negaaddbitwidthsubb = sub i64 %negaaddbitwidth, %b
   %shifted = lshr i64 %val, %negaaddbitwidthsubb
   ret i64 %shifted

llvm/trunk/test/CodeGen/X86/sink-addsub-of-const.ll

 }
 
 ; sub (sub C, %x), %y
 ; sub %y, (sub C, %x)
 
 define i32 @sink_sub_from_const_to_sub(i32 %a, i32 %b) {
 ; X32-LABEL: sink_sub_from_const_to_sub:
 ; X32:       # %bb.0:
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    addl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl $32, %eax
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    subl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    subl %ecx, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: sink_sub_from_const_to_sub:
 ; X64:       # %bb.0:
+; X64-NEXT:    addl %esi, %edi
 ; X64-NEXT:    movl $32, %eax
 ; X64-NEXT:    subl %edi, %eax
-; X64-NEXT:    subl %esi, %eax
 ; X64-NEXT:    retq
   %t0 = sub i32 32, %a
   %r = sub i32 %t0, %b
   ret i32 %r
 }
 define i32 @sink_sub_from_const_to_sub2(i32 %a, i32 %b) {
 ; X32-LABEL: sink_sub_from_const_to_sub2:
 ; X32:       # %bb.0:

 
 ; sub (sub C, %x), %y
 ; sub %y, (sub C, %x)
 
 define <4 x i32> @vec_sink_sub_from_const_to_sub(<4 x i32> %a, <4 x i32> %b) {
 ; ALL-LABEL: vec_sink_sub_from_const_to_sub:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    movdqa {{.*#+}} xmm2 = <42,24,u,46>
+; ALL-NEXT:    paddd %xmm1, %xmm0
 ; ALL-NEXT:    psubd %xmm0, %xmm2
-; ALL-NEXT:    psubd %xmm1, %xmm2
 ; ALL-NEXT:    movdqa %xmm2, %xmm0
 ; ALL-NEXT:    ret{{[l|q]}}
   %t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a
   %r = sub <4 x i32> %t0, %b
   ret <4 x i32> %r
 }
 define <4 x i32> @vec_sink_sub_from_const_to_sub2(<4 x i32> %a, <4 x i32> %b) {
 ; X32-LABEL: vec_sink_sub_from_const_to_sub2: