[DAGCombiner][X86][AArch64][AMDGPU] (x + C) - y -> (x - y) + C fold

[lebedev.ri]

Summary

The main motivation is shown by all these neg instructions that are now created.
In particular, the @reg32_lshr_by_negated_unfolded_sub_b test.

AArch64 test changes all look good (neg created), or neutral.

X86 changes look neutral (vectors), or good (neg / xor eax, eax created).

I'm not sure about X86/ragreedy-hoist-spill.ll, it looks like the spill
is now hoisted into preheader (which should still be good?),
2 4-byte reloads become 1 8-byte reload, and are elsewhere,
but i'm not sure how that affects that loop.

I'm unable to interpret AMDGPU change, looks neutral-ish?

This is hopefully a step towards solving PR41952.

https://rise4fun.com/Alive/pkdq (we are missing more patterns, i'll submit them later)

[lebedev.ri]

Better test coverage.

[lebedev.ri]

test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll

6 ↗

(On Diff #200738)

@arsenm I believe D62263 recovers (and improves upon?) from changes here, somewhat, PTAL.

[bjope]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2926 ↗

(On Diff #200738)

Not sure if it is super important, or common, in reality. But maybe this should be trigger for an add-like-or as well?

An ADD with no common bits set in the operands is canonicalized into OR by DAGCombiner, so there could be lots of OR:s out there that really are ADD:s.

[lebedev.ri]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2926 ↗

(On Diff #200738)

Yes, correct observation. I did think about it when writing,
but i did not see any easy way to do that here.
Any suggestions?

[bjope]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2926 ↗

(On Diff #200738)

We could introduce some helper to make it easier to match an "add-like" node. However, checking "noCommonBitsSet" to detect if an OR is add-like currently involves ValueTracking, so it is not a cheap operation. We probably want to see that we get some payback if doing that, and not just wasting time.

Since we already match on ISD::ADD in several places above, it might have been too much to ask for in this patch. So I think we can save it for later.

[lebedev.ri]

Do x86 test changes look good?

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

2926 ↗

(On Diff #200738)

Since we already match on ISD::ADD in several places above, it might have been too much to ask for in this patch. So I think we can save it for later.

I agree. Thank you for taking a look.

test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll

6 ↗

(On Diff #200738)

I've verified that with that patch, the original test (with non-auto-generated check lines) passes, so i'm going to assume this is ok.

[RKSimon]

The x86 changes look OK to me.

[lebedev.ri]

In D62223#1517555, @RKSimon wrote:

The x86 changes look OK to me.

Thank you.
That means this patch is only waiting for @arsenm to comment whether D62263 sufficiently addresses this AMDGPU regression.

[arsenm]

LGTM

[lebedev.ri]

In D62223#1519314, @arsenm wrote:

LGTM

Thank you for the review!

Time to land first few of these patches. :)

[RKSimon]

LGTM

[lebedev.ri]

Rebased, NFC.

[lebedev.ri]

One of the patches seems to have introduced a hang in test-suite, reverted.

[lebedev.ri]

And once more.
rL362109 + rL362110

[brooksmoses]

Unfortunately, we (Google) are seeing some regressions on our internal benchmarks on x86_64 -- mostly around 2%, but in some cases a good bit more -- from this revision and some of the subsequent revisions in the series, notably r362217. Just wanted to give you a heads-up at this point -- we're still working to try to understand the underlying reasons and get a reproducing test-case, but it looks like these are going to block our internal release until they're addressed.

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
     return V;
 
   if (SDValue V = foldAddSubOfSignBit(N, DAG))
     return V;
 
   if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
     return V;
 
+  // Hoist one-use addition by constant:  (x + C) - y  ->  (x - y) + C
+  if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
+      isConstantOrConstantVector(N0.getOperand(1))) {
+    SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
+    return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
+  }
+
   // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
   // rather than 'sub 0/1' (the sext should get folded).
   // sub X, (zext i1 Y) --> add X, (sext i1 Y)
   if (N1.getOpcode() == ISD::ZERO_EXTEND &&
       N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
       TLI.getBooleanContents(VT) ==
           TargetLowering::ZeroOrNegativeOneBooleanContent) {
     SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));

llvm/trunk/test/CodeGen/AArch64/shift-amount-mod.ll

; CHECK-NEXT:    ret
   %negaaddbitwidth = add i64 %negshamt, 64
   %shifted = lshr i64 %val, %negaaddbitwidth
   ret i64 %shifted
 }
 
 define i32 @reg32_lshr_by_negated_unfolded_sub_b(i32 %val, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: reg32_lshr_by_negated_unfolded_sub_b:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #32
-; CHECK-NEXT:    sub w8, w8, w1
+; CHECK-NEXT:    neg w8, w1
 ; CHECK-NEXT:    sub w8, w8, w2
 ; CHECK-NEXT:    lsr w0, w0, w8
 ; CHECK-NEXT:    ret
   %nega = sub i32 0, %a
   %negaaddbitwidth = add i32 %nega, 32
   %negaaddbitwidthsubb = sub i32 %negaaddbitwidth, %b
   %shifted = lshr i32 %val, %negaaddbitwidthsubb
   ret i32 %shifted
 }
 define i64 @reg64_lshr_by_negated_unfolded_sub_b(i64 %val, i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: reg64_lshr_by_negated_unfolded_sub_b:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #64
-; CHECK-NEXT:    sub x8, x8, x1
+; CHECK-NEXT:    neg x8, x1
 ; CHECK-NEXT:    sub x8, x8, x2
 ; CHECK-NEXT:    lsr x0, x0, x8
 ; CHECK-NEXT:    ret
   %nega = sub i64 0, %a
   %negaaddbitwidth = add i64 %nega, 64
   %negaaddbitwidthsubb = sub i64 %negaaddbitwidth, %b
   %shifted = lshr i64 %val, %negaaddbitwidthsubb
   ret i64 %shifted

llvm/trunk/test/CodeGen/AArch64/sink-addsub-of-const.ll

 
 ; sub (add %x, C), %y
 ; sub %y, (add %x, C)
 
 define i32 @sink_add_of_const_to_sub(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: sink_add_of_const_to_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub w8, w0, w1
-; CHECK-NEXT:    add w8, w8, #32 // =32
-; CHECK-NEXT:    sub w0, w8, w2
+; CHECK-NEXT:    sub w8, w8, w2
+; CHECK-NEXT:    add w0, w8, #32 // =32
 ; CHECK-NEXT:    ret
   %t0 = sub i32 %a, %b
   %t1 = add i32 %t0, 32 ; constant always on RHS
   %r = sub i32 %t1, %c
   ret i32 %r
 }
 define i32 @sink_add_of_const_to_sub2(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: sink_add_of_const_to_sub2:

 
 ; sub (sub %x, C), %y
 ; sub %y, (sub %x, C)
 
 define i32 @sink_sub_of_const_to_sub(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: sink_sub_of_const_to_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub w8, w0, w1
-; CHECK-NEXT:    sub w8, w8, #32 // =32
-; CHECK-NEXT:    sub w0, w8, w2
+; CHECK-NEXT:    sub w8, w8, w2
+; CHECK-NEXT:    sub w0, w8, #32 // =32
 ; CHECK-NEXT:    ret
   %t0 = sub i32 %a, %b
   %t1 = sub i32 %t0, 32
   %r = sub i32 %t1, %c
   ret i32 %r
 }
 define i32 @sink_sub_of_const_to_sub2(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: sink_sub_of_const_to_sub2:

 
 ; sub (sub C, %x), %y
 ; sub %y, (sub C, %x)
 
 define i32 @sink_sub_from_const_to_sub(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: sink_sub_from_const_to_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sub w8, w1, w0
-; CHECK-NEXT:    add w8, w8, #32 // =32
-; CHECK-NEXT:    sub w0, w8, w2
+; CHECK-NEXT:    sub w8, w8, w2
+; CHECK-NEXT:    add w0, w8, #32 // =32
 ; CHECK-NEXT:    ret
   %t0 = sub i32 %a, %b
   %t1 = sub i32 32, %t0
   %r = sub i32 %t1, %c
   ret i32 %r
 }
 define i32 @sink_sub_from_const_to_sub2(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: sink_sub_from_const_to_sub2:

 ; sub %y, (add %x, C)
 
 define <4 x i32> @vec_sink_add_of_const_to_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: vec_sink_add_of_const_to_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI18_0
 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI18_0]
 ; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    add v0.4s, v0.4s, v3.4s
 ; CHECK-NEXT:    sub v0.4s, v0.4s, v2.4s
+; CHECK-NEXT:    add v0.4s, v0.4s, v3.4s
 ; CHECK-NEXT:    ret
   %t0 = sub <4 x i32> %a, %b
   %t1 = add <4 x i32> %t0, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
   %r = sub <4 x i32> %t1, %c
   ret <4 x i32> %r
 }
 define <4 x i32> @vec_sink_add_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: vec_sink_add_of_const_to_sub2:

 ; sub %y, (sub C, %x)
 
 define <4 x i32> @vec_sink_sub_from_const_to_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: vec_sink_sub_from_const_to_sub:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI22_0
 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI22_0]
 ; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
-; CHECK-NEXT:    add v0.4s, v0.4s, v3.4s
 ; CHECK-NEXT:    sub v0.4s, v0.4s, v2.4s
+; CHECK-NEXT:    add v0.4s, v0.4s, v3.4s
 ; CHECK-NEXT:    ret
   %t0 = sub <4 x i32> %a, %b
   %t1 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %t0
   %r = sub <4 x i32> %t1, %c
   ret <4 x i32> %r
 }
 define <4 x i32> @vec_sink_sub_from_const_to_sub2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: vec_sink_sub_from_const_to_sub2:

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll

 ; VARIANT0-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; VARIANT0-NEXT:    s_load_dword s2, s[0:1], 0xb
 ; VARIANT0-NEXT:    s_mov_b32 s7, 0xf000
 ; VARIANT0-NEXT:    s_mov_b32 s6, 0
 ; VARIANT0-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
 ; VARIANT0-NEXT:    v_mov_b32_e32 v2, 0
 ; VARIANT0-NEXT:    s_waitcnt lgkmcnt(0)
 ; VARIANT0-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
-; VARIANT0-NEXT:    s_add_i32 s2, s2, -1
-; VARIANT0-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
+; VARIANT0-NEXT:    s_waitcnt expcnt(0)
+; VARIANT0-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
+; VARIANT0-NEXT:    s_waitcnt vmcnt(0)
 ; VARIANT0-NEXT:    s_barrier
-; VARIANT0-NEXT:    v_sub_i32_e32 v3, vcc, s2, v0
+; VARIANT0-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
 ; VARIANT0-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; VARIANT0-NEXT:    v_lshl_b64 v[3:4], v[3:4], 2
 ; VARIANT0-NEXT:    buffer_load_dword v0, v[3:4], s[4:7], 0 addr64
 ; VARIANT0-NEXT:    s_waitcnt vmcnt(0)
 ; VARIANT0-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
 ; VARIANT0-NEXT:    s_endpgm
 ;
 ; VARIANT1-LABEL: test_barrier:
 ; VARIANT1:       ; %bb.0: ; %entry
 ; VARIANT1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; VARIANT1-NEXT:    s_load_dword s2, s[0:1], 0xb
 ; VARIANT1-NEXT:    s_mov_b32 s7, 0xf000
 ; VARIANT1-NEXT:    s_mov_b32 s6, 0
 ; VARIANT1-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
 ; VARIANT1-NEXT:    v_mov_b32_e32 v2, 0
 ; VARIANT1-NEXT:    s_waitcnt lgkmcnt(0)
 ; VARIANT1-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
-; VARIANT1-NEXT:    s_add_i32 s2, s2, -1
+; VARIANT1-NEXT:    s_waitcnt expcnt(0)
+; VARIANT1-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
 ; VARIANT1-NEXT:    s_barrier
-; VARIANT1-NEXT:    v_sub_i32_e32 v3, vcc, s2, v0
+; VARIANT1-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
 ; VARIANT1-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; VARIANT1-NEXT:    v_lshl_b64 v[3:4], v[3:4], 2
-; VARIANT1-NEXT:    s_waitcnt expcnt(0)
 ; VARIANT1-NEXT:    buffer_load_dword v0, v[3:4], s[4:7], 0 addr64
 ; VARIANT1-NEXT:    s_waitcnt vmcnt(0)
 ; VARIANT1-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
 ; VARIANT1-NEXT:    s_endpgm
 ;
 ; VARIANT2-LABEL: test_barrier:
 ; VARIANT2:       ; %bb.0: ; %entry
 ; VARIANT2-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; VARIANT2-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
 ; VARIANT2-NEXT:    s_load_dword s0, s[0:1], 0x2c
 ; VARIANT2-NEXT:    s_waitcnt lgkmcnt(0)
 ; VARIANT2-NEXT:    v_mov_b32_e32 v2, s3
 ; VARIANT2-NEXT:    v_add_co_u32_e32 v1, vcc, s2, v1
 ; VARIANT2-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
 ; VARIANT2-NEXT:    global_store_dword v[1:2], v0, off
 ; VARIANT2-NEXT:    s_waitcnt vmcnt(0)
 ; VARIANT2-NEXT:    s_barrier
-; VARIANT2-NEXT:    s_add_i32 s0, s0, -1
-; VARIANT2-NEXT:    v_sub_u32_e32 v3, s0, v0
+; VARIANT2-NEXT:    v_sub_u32_e32 v0, s0, v0
+; VARIANT2-NEXT:    v_add_u32_e32 v3, -1, v0
 ; VARIANT2-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; VARIANT2-NEXT:    v_lshlrev_b64 v[3:4], 2, v[3:4]
 ; VARIANT2-NEXT:    v_mov_b32_e32 v0, s3
 ; VARIANT2-NEXT:    v_add_co_u32_e32 v3, vcc, s2, v3
 ; VARIANT2-NEXT:    v_addc_co_u32_e32 v4, vcc, v0, v4, vcc
 ; VARIANT2-NEXT:    global_load_dword v0, v[3:4], off
 ; VARIANT2-NEXT:    s_waitcnt vmcnt(0)
 ; VARIANT2-NEXT:    global_store_dword v[1:2], v0, off
 ; VARIANT2-NEXT:    s_endpgm
 ;
 ; VARIANT3-LABEL: test_barrier:
 ; VARIANT3:       ; %bb.0: ; %entry
 ; VARIANT3-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; VARIANT3-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
 ; VARIANT3-NEXT:    s_load_dword s0, s[0:1], 0x2c
 ; VARIANT3-NEXT:    s_waitcnt lgkmcnt(0)
 ; VARIANT3-NEXT:    v_mov_b32_e32 v2, s3
 ; VARIANT3-NEXT:    v_add_co_u32_e32 v1, vcc, s2, v1
 ; VARIANT3-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
 ; VARIANT3-NEXT:    global_store_dword v[1:2], v0, off
 ; VARIANT3-NEXT:    s_barrier
-; VARIANT3-NEXT:    s_add_i32 s0, s0, -1
-; VARIANT3-NEXT:    v_sub_u32_e32 v3, s0, v0
+; VARIANT3-NEXT:    v_sub_u32_e32 v0, s0, v0
+; VARIANT3-NEXT:    v_add_u32_e32 v3, -1, v0
 ; VARIANT3-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; VARIANT3-NEXT:    v_lshlrev_b64 v[3:4], 2, v[3:4]
 ; VARIANT3-NEXT:    v_mov_b32_e32 v0, s3
 ; VARIANT3-NEXT:    v_add_co_u32_e32 v3, vcc, s2, v3
 ; VARIANT3-NEXT:    v_addc_co_u32_e32 v4, vcc, v0, v4, vcc
 ; VARIANT3-NEXT:    global_load_dword v0, v[3:4], off
 ; VARIANT3-NEXT:    s_waitcnt vmcnt(0)
 ; VARIANT3-NEXT:    global_store_dword v[1:2], v0, off

llvm/trunk/test/CodeGen/X86/combine-add.ll

; AVX-NEXT:    retq
   %3 = add <4 x i32> %a, %2
   ret <4 x i32> %3
 }
 
 ; fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
 define <4 x i32> @combine_vec_add_sub_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %d) {
 ; SSE-LABEL: combine_vec_add_sub_sub:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    paddd {{.*}}(%rip), %xmm0
 ; SSE-NEXT:    paddd %xmm2, %xmm1
 ; SSE-NEXT:    psubd %xmm1, %xmm0
+; SSE-NEXT:    paddd {{.*}}(%rip), %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: combine_vec_add_sub_sub:
 ; AVX:       # %bb.0:
-; AVX-NEXT:    vpaddd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vpaddd %xmm2, %xmm1, %xmm1
 ; AVX-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpaddd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %1 = sub <4 x i32> %a, %b
   %2 = sub <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %d
   %3 = add <4 x i32> %1, %2
   ret <4 x i32> %3
 }
 
 ; fold (a+b) -> (a|b) iff a and b share no bits.

llvm/trunk/test/CodeGen/X86/ragreedy-hoist-spill.ll

 ; CHECK-NEXT:    popq %r15
 ; CHECK-NEXT:    popq %rbp
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  LBB0_5: ## %if.end25
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    je LBB0_55
 ; CHECK-NEXT:  ## %bb.6: ## %SyTime.exit2720
-; CHECK-NEXT:    movq %rdx, %r14
-; CHECK-NEXT:    movq %rdi, %r15
+; CHECK-NEXT:    movq %rdx, %rbx
+; CHECK-NEXT:    movq %rdi, %rbp
 ; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rcx
 ; CHECK-NEXT:    cmpq %rax, %rcx
 ; CHECK-NEXT:    jae LBB0_8
 ; CHECK-NEXT:  ## %bb.7: ## %for.body.lr.ph
 ; CHECK-NEXT:    movl $512, %edx ## imm = 0x200
 ; CHECK-NEXT:    movl $32, %esi
 ; CHECK-NEXT:    callq _memset
 ; CHECK-NEXT:  LBB0_8: ## %while.body.preheader
-; CHECK-NEXT:    imulq $1040, %r14, %rax ## imm = 0x410
+; CHECK-NEXT:    movq %rbp, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
+; CHECK-NEXT:    imulq $1040, %rbx, %rax ## imm = 0x410
 ; CHECK-NEXT:    movq _syBuf@{{.*}}(%rip), %rcx
 ; CHECK-NEXT:    leaq 8(%rcx,%rax), %rbx
-; CHECK-NEXT:    movl $1, %r14d
+; CHECK-NEXT:    movl $1, %r15d
 ; CHECK-NEXT:    movq _syCTRO@{{.*}}(%rip), %rax
 ; CHECK-NEXT:    movb $1, %cl
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_9: ## %do.body
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movl $0, (%rax)
 ; CHECK-NEXT:    testb %cl, %cl
 ; CHECK-NEXT:    jne LBB0_9
 ; CHECK-NEXT:  ## %bb.10: ## %do.end
-; CHECK-NEXT:    xorl %r12d, %r12d
-; CHECK-NEXT:    testb %r12b, %r12b
+; CHECK-NEXT:    xorl %r14d, %r14d
+; CHECK-NEXT:    testb %r14b, %r14b
 ; CHECK-NEXT:    jne LBB0_11
 ; CHECK-NEXT:  ## %bb.12: ## %while.body200.preheader
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    leaq {{.*}}(%rip), %rsi
 ; CHECK-NEXT:    leaq {{.*}}(%rip), %rdi
 ; CHECK-NEXT:    xorl %ebp, %ebp
-; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    xorl %r13d, %r13d
 ; CHECK-NEXT:    jmp LBB0_13
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_14: ## %while.body200
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    leal 1(%r12), %eax
+; CHECK-NEXT:    leal 1(%r14), %eax
 ; CHECK-NEXT:    cmpl $21, %eax
 ; CHECK-NEXT:    ja LBB0_20
 ; CHECK-NEXT:  ## %bb.15: ## %while.body200
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl $-1, %ecx
+; CHECK-NEXT:    movl $-1, %r13d
 ; CHECK-NEXT:    movslq (%rsi,%rax,4), %rax
 ; CHECK-NEXT:    addq %rsi, %rax
 ; CHECK-NEXT:    jmpq *%rax
 ; CHECK-NEXT:  LBB0_18: ## %while.cond201.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    movl $1, %r13d
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:  LBB0_44: ## %while.cond1037.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    testb %dl, %dl
-; CHECK-NEXT:    movl %r12d, %ecx
+; CHECK-NEXT:    movl %r14d, %r13d
 ; CHECK-NEXT:    jne LBB0_21
 ; CHECK-NEXT:    jmp LBB0_55
 ; CHECK-NEXT:  LBB0_26: ## %sw.bb474
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
 ; CHECK-NEXT:    testb %dl, %dl
-; CHECK-NEXT:    ## implicit-def: $r13
+; CHECK-NEXT:    ## implicit-def: $r12
 ; CHECK-NEXT:    jne LBB0_34
 ; CHECK-NEXT:  ## %bb.27: ## %do.body479.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    testb %dl, %dl
-; CHECK-NEXT:    ## implicit-def: $r13
+; CHECK-NEXT:    ## implicit-def: $r12
 ; CHECK-NEXT:    jne LBB0_34
 ; CHECK-NEXT:  ## %bb.28: ## %land.rhs485.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    ## implicit-def: $rax
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_29: ## %land.rhs485
 ; CHECK-NEXT:    ## Parent Loop BB0_13 Depth=1
 ; CHECK-NEXT:    ## => This Inner Loop Header: Depth=2
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    js LBB0_55
 ; CHECK-NEXT:  ## %bb.30: ## %cond.true.i.i2780
 ; CHECK-NEXT:    ## in Loop: Header=BB0_29 Depth=2
-; CHECK-NEXT:    movq %rax, %r13
+; CHECK-NEXT:    movq %rax, %r12
 ; CHECK-NEXT:    testb %dl, %dl
 ; CHECK-NEXT:    jne LBB0_32
 ; CHECK-NEXT:  ## %bb.31: ## %lor.rhs500
 ; CHECK-NEXT:    ## in Loop: Header=BB0_29 Depth=2
 ; CHECK-NEXT:    movl $256, %esi ## imm = 0x100
 ; CHECK-NEXT:    callq ___maskrune
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    testb %dl, %dl
 ; CHECK-NEXT:    je LBB0_34
 ; CHECK-NEXT:  LBB0_32: ## %do.body479.backedge
 ; CHECK-NEXT:    ## in Loop: Header=BB0_29 Depth=2
-; CHECK-NEXT:    leaq 1(%r13), %rax
+; CHECK-NEXT:    leaq 1(%r12), %rax
 ; CHECK-NEXT:    testb %dl, %dl
 ; CHECK-NEXT:    jne LBB0_29
 ; CHECK-NEXT:  ## %bb.33: ## %if.end517.loopexitsplit
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    incq %r13
+; CHECK-NEXT:    incq %r12
 ; CHECK-NEXT:  LBB0_34: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax ## 8-byte Reload
-; CHECK-NEXT:    addl $-324, %eax ## imm = 0xFEBC
+; CHECK-NEXT:    leal -324(%r13), %eax
 ; CHECK-NEXT:    cmpl $59, %eax
 ; CHECK-NEXT:    ja LBB0_35
 ; CHECK-NEXT:  ## %bb.57: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    movabsq $576460756598390785, %rcx ## imm = 0x800000100000001
 ; CHECK-NEXT:    btq %rax, %rcx
 ; CHECK-NEXT:    jb LBB0_38
 ; CHECK-NEXT:  LBB0_35: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    cmpl $11, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Reload
+; CHECK-NEXT:    cmpl $11, %r13d
 ; CHECK-NEXT:    je LBB0_38
 ; CHECK-NEXT:  ## %bb.36: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    cmpl $24, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Reload
+; CHECK-NEXT:    cmpl $24, %r13d
 ; CHECK-NEXT:    je LBB0_38
 ; CHECK-NEXT:  ## %bb.37: ## %if.then532
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    movq _SyFgets.yank@{{.*}}(%rip), %rax
 ; CHECK-NEXT:    movb $0, (%rax)
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_38: ## %for.cond534
 ; CHECK-NEXT:    ## Parent Loop BB0_13 Depth=1
 ; CHECK-NEXT:    ## => This Inner Loop Header: Depth=2
 ; CHECK-NEXT:    testb %dl, %dl
 ; CHECK-NEXT:    jne LBB0_38
 ; CHECK-NEXT:  ## %bb.39: ## %for.cond542.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    testb %dl, %dl
-; CHECK-NEXT:    movb $0, (%r13)
-; CHECK-NEXT:    movl %r12d, %ecx
+; CHECK-NEXT:    movb $0, (%r12)
+; CHECK-NEXT:    movl %r14d, %r13d
 ; CHECK-NEXT:    leaq {{.*}}(%rip), %rsi
 ; CHECK-NEXT:    leaq {{.*}}(%rip), %rdi
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:  LBB0_45: ## %sw.bb1134
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rcx
 ; CHECK-NEXT:    cmpq %rax, %rcx
 ; CHECK-NEXT:    jb LBB0_55
 ; CHECK-NEXT:  ## %bb.46: ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    xorl %ebp, %ebp
-; CHECK-NEXT:    movl $268, %ecx ## imm = 0x10C
+; CHECK-NEXT:    movl $268, %r13d ## imm = 0x10C
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:  LBB0_19: ## %sw.bb243
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl $2, %ecx
+; CHECK-NEXT:    movl $2, %r13d
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:  LBB0_40: ## %sw.bb566
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl $20, %ecx
+; CHECK-NEXT:    movl $20, %r13d
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_13: ## %while.body200
 ; CHECK-NEXT:    ## =>This Loop Header: Depth=1
 ; CHECK-NEXT:    ## Child Loop BB0_29 Depth 2
 ; CHECK-NEXT:    ## Child Loop BB0_38 Depth 2
-; CHECK-NEXT:    leal -268(%r12), %eax
+; CHECK-NEXT:    leal -268(%r14), %eax
 ; CHECK-NEXT:    cmpl $105, %eax
 ; CHECK-NEXT:    ja LBB0_14
 ; CHECK-NEXT:  ## %bb.56: ## %while.body200
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    movslq (%rdi,%rax,4), %rax
 ; CHECK-NEXT:    addq %rdi, %rax
 ; CHECK-NEXT:    jmpq *%rax
 ; CHECK-NEXT:  LBB0_20: ## %sw.bb256
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl %r12d, %ecx
+; CHECK-NEXT:    movl %r14d, %r13d
 ; CHECK-NEXT:  LBB0_21: ## %while.cond197.backedge
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    decl %r14d
-; CHECK-NEXT:    testl %r14d, %r14d
-; CHECK-NEXT:    movl %ecx, %r12d
+; CHECK-NEXT:    decl %r15d
+; CHECK-NEXT:    testl %r15d, %r15d
+; CHECK-NEXT:    movl %r13d, %r14d
 ; CHECK-NEXT:    jg LBB0_13
 ; CHECK-NEXT:    jmp LBB0_22
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_42: ## %while.cond864
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    jmp LBB0_42
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_43: ## %while.cond962
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    jmp LBB0_43
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_25: ## %for.cond357
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    jmp LBB0_25
 ; CHECK-NEXT:  LBB0_11:
 ; CHECK-NEXT:    xorl %ebp, %ebp
-; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    xorl %r13d, %r13d
 ; CHECK-NEXT:  LBB0_22: ## %while.end1465
-; CHECK-NEXT:    incl %ecx
-; CHECK-NEXT:    cmpl $16, %ecx
+; CHECK-NEXT:    incl %r13d
+; CHECK-NEXT:    cmpl $16, %r13d
 ; CHECK-NEXT:    ja LBB0_50
 ; CHECK-NEXT:  ## %bb.23: ## %while.end1465
 ; CHECK-NEXT:    movl $83969, %eax ## imm = 0x14801
-; CHECK-NEXT:    btl %ecx, %eax
+; CHECK-NEXT:    btl %r13d, %eax
 ; CHECK-NEXT:    jae LBB0_50
 ; CHECK-NEXT:  ## %bb.24:
-; CHECK-NEXT:    xorl %ebx, %ebx
+; CHECK-NEXT:    xorl %ebp, %ebp
+; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload
 ; CHECK-NEXT:  LBB0_48: ## %if.then1477
 ; CHECK-NEXT:    movl $1, %edx
 ; CHECK-NEXT:    callq _write
-; CHECK-NEXT:    addq $8189, %r15 ## imm = 0x1FFD
-; CHECK-NEXT:    subq %rbx, %r15
-; CHECK-NEXT:    addq _syHistory@{{.*}}(%rip), %r15
+; CHECK-NEXT:    subq %rbp, %rbx
+; CHECK-NEXT:    movq _syHistory@{{.*}}(%rip), %rax
+; CHECK-NEXT:    leaq 8189(%rbx,%rax), %rax
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_49: ## %for.body1723
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    decq %r15
+; CHECK-NEXT:    decq %rax
 ; CHECK-NEXT:    jmp LBB0_49
 ; CHECK-NEXT:  LBB0_50: ## %for.cond1480.preheader
 ; CHECK-NEXT:    movl $512, %eax ## imm = 0x200
 ; CHECK-NEXT:    cmpq %rax, %rax
 ; CHECK-NEXT:    jae LBB0_55
 ; CHECK-NEXT:  ## %bb.51: ## %for.body1664.lr.ph
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al

 ; CHECK-NEXT:    cmpq %rax, %rax
 ; CHECK-NEXT:    jl LBB0_53
 ; CHECK-NEXT:  LBB0_54: ## %while.cond1683.preheader
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:  LBB0_55: ## %if.then.i
 ; CHECK-NEXT:    ud2
 ; CHECK-NEXT:  LBB0_47: ## %if.then1477.loopexit
-; CHECK-NEXT:    movq %r15, %rbx
+; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload
+; CHECK-NEXT:    movq %rbx, %rbp
 ; CHECK-NEXT:    jmp LBB0_48
 ; CHECK-NEXT:  LBB0_16: ## %while.cond635.preheader
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    je LBB0_41
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_17: ## %for.body643.us
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1

llvm/trunk/test/CodeGen/X86/shift-amount-mod.ll

; X64-NEXT:    retq
   %shifted = lshr i64 %val, %negaaddbitwidth
   ret i64 %shifted
 }
 
 define i32 @reg32_lshr_by_negated_unfolded_sub_b(i32 %val, i32 %a, i32 %b) nounwind {
 ; X32-LABEL: reg32_lshr_by_negated_unfolded_sub_b:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movl $32, %ecx
+; X32-NEXT:    xorl %ecx, %ecx
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X32-NEXT:    shrl %cl, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: reg32_lshr_by_negated_unfolded_sub_b:
 ; X64:       # %bb.0:
+; X64-NEXT:    movl %esi, %ecx
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $32, %ecx
-; X64-NEXT:    subl %esi, %ecx
+; X64-NEXT:    negl %ecx
 ; X64-NEXT:    subl %edx, %ecx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; X64-NEXT:    shrl %cl, %eax
 ; X64-NEXT:    retq
   %nega = sub i32 0, %a
   %negaaddbitwidth = add i32 %nega, 32
   %negaaddbitwidthsubb = sub i32 %negaaddbitwidth, %b
   %shifted = lshr i32 %val, %negaaddbitwidthsubb
   ret i32 %shifted
 }
 define i64 @reg64_lshr_by_negated_unfolded_sub_b(i64 %val, i64 %a, i64 %b) nounwind {
 ; X32-LABEL: reg64_lshr_by_negated_unfolded_sub_b:
 ; X32:       # %bb.0:
 ; X32-NEXT:    pushl %esi
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; X32-NEXT:    movl $64, %ecx
+; X32-NEXT:    xorl %ecx, %ecx
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    addb $64, %cl
 ; X32-NEXT:    movl %esi, %edx
 ; X32-NEXT:    shrl %cl, %edx
 ; X32-NEXT:    shrdl %cl, %esi, %eax
 ; X32-NEXT:    testb $32, %cl
 ; X32-NEXT:    je .LBB37_2
 ; X32-NEXT:  # %bb.1:
 ; X32-NEXT:    movl %edx, %eax
 ; X32-NEXT:    xorl %edx, %edx

llvm/trunk/test/CodeGen/X86/sink-addsub-of-const.ll

 ; sub (add %x, C), %y
 ; sub %y, (add %x, C)
 
 define i32 @sink_add_of_const_to_sub(i32 %a, i32 %b, i32 %c) {
 ; X32-LABEL: sink_add_of_const_to_sub:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    addl $32, %eax
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    addl $32, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: sink_add_of_const_to_sub:
 ; X64:       # %bb.0:
 ; X64-NEXT:    # kill: def $edi killed $edi def $rdi
 ; X64-NEXT:    subl %esi, %edi
+; X64-NEXT:    subl %edx, %edi
 ; X64-NEXT:    leal 32(%rdi), %eax
-; X64-NEXT:    subl %edx, %eax
 ; X64-NEXT:    retq
   %t0 = sub i32 %a, %b
   %t1 = add i32 %t0, 32 ; constant always on RHS
   %r = sub i32 %t1, %c
   ret i32 %r
 }
 define i32 @sink_add_of_const_to_sub2(i32 %a, i32 %b, i32 %c) {
 ; X32-LABEL: sink_add_of_const_to_sub2:

 ; sub (sub %x, C), %y
 ; sub %y, (sub %x, C)
 
 define i32 @sink_sub_of_const_to_sub(i32 %a, i32 %b, i32 %c) {
 ; X32-LABEL: sink_sub_of_const_to_sub:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    addl $-32, %eax
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    addl $-32, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: sink_sub_of_const_to_sub:
 ; X64:       # %bb.0:
 ; X64-NEXT:    # kill: def $edi killed $edi def $rdi
 ; X64-NEXT:    subl %esi, %edi
+; X64-NEXT:    subl %edx, %edi
 ; X64-NEXT:    leal -32(%rdi), %eax
-; X64-NEXT:    subl %edx, %eax
 ; X64-NEXT:    retq
   %t0 = sub i32 %a, %b
   %t1 = sub i32 %t0, 32
   %r = sub i32 %t1, %c
   ret i32 %r
 }
 define i32 @sink_sub_of_const_to_sub2(i32 %a, i32 %b, i32 %c) {
 ; X32-LABEL: sink_sub_of_const_to_sub2:

 ; sub (sub C, %x), %y
 ; sub %y, (sub C, %x)
 
 define i32 @sink_sub_from_const_to_sub(i32 %a, i32 %b, i32 %c) {
 ; X32-LABEL: sink_sub_from_const_to_sub:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    addl $32, %eax
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    addl $32, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: sink_sub_from_const_to_sub:
 ; X64:       # %bb.0:
 ; X64-NEXT:    # kill: def $esi killed $esi def $rsi
 ; X64-NEXT:    subl %edi, %esi
+; X64-NEXT:    subl %edx, %esi
 ; X64-NEXT:    leal 32(%rsi), %eax
-; X64-NEXT:    subl %edx, %eax
 ; X64-NEXT:    retq
   %t0 = sub i32 %a, %b
   %t1 = sub i32 32, %t0
   %r = sub i32 %t1, %c
   ret i32 %r
 }
 define i32 @sink_sub_from_const_to_sub2(i32 %a, i32 %b, i32 %c) {
 ; X32-LABEL: sink_sub_from_const_to_sub2:

 
 ; sub (add %x, C), %y
 ; sub %y, (add %x, C)
 
 define <4 x i32> @vec_sink_add_of_const_to_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; X32-LABEL: vec_sink_add_of_const_to_sub:
 ; X32:       # %bb.0:
 ; X32-NEXT:    psubd %xmm1, %xmm0
-; X32-NEXT:    paddd {{\.LCPI.*}}, %xmm0
 ; X32-NEXT:    psubd %xmm2, %xmm0
+; X32-NEXT:    paddd {{\.LCPI.*}}, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: vec_sink_add_of_const_to_sub:
 ; X64:       # %bb.0:
 ; X64-NEXT:    psubd %xmm1, %xmm0
-; X64-NEXT:    paddd {{.*}}(%rip), %xmm0
 ; X64-NEXT:    psubd %xmm2, %xmm0
+; X64-NEXT:    paddd {{.*}}(%rip), %xmm0
 ; X64-NEXT:    retq
   %t0 = sub <4 x i32> %a, %b
   %t1 = add <4 x i32> %t0, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
   %r = sub <4 x i32> %t1, %c
   ret <4 x i32> %r
 }
 define <4 x i32> @vec_sink_add_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; X32-LABEL: vec_sink_add_of_const_to_sub2:

 
 ; sub (sub C, %x), %y
 ; sub %y, (sub C, %x)
 
 define <4 x i32> @vec_sink_sub_from_const_to_sub(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; X32-LABEL: vec_sink_sub_from_const_to_sub:
 ; X32:       # %bb.0:
 ; X32-NEXT:    psubd %xmm0, %xmm1
-; X32-NEXT:    paddd {{\.LCPI.*}}, %xmm1
 ; X32-NEXT:    psubd %xmm2, %xmm1
+; X32-NEXT:    paddd {{\.LCPI.*}}, %xmm1
 ; X32-NEXT:    movdqa %xmm1, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: vec_sink_sub_from_const_to_sub:
 ; X64:       # %bb.0:
 ; X64-NEXT:    psubd %xmm0, %xmm1
-; X64-NEXT:    paddd {{.*}}(%rip), %xmm1
 ; X64-NEXT:    psubd %xmm2, %xmm1
+; X64-NEXT:    paddd {{.*}}(%rip), %xmm1
 ; X64-NEXT:    movdqa %xmm1, %xmm0
 ; X64-NEXT:    retq
   %t0 = sub <4 x i32> %a, %b
   %t1 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %t0
   %r = sub <4 x i32> %t1, %c
   ret <4 x i32> %r
 }
 define <4 x i32> @vec_sink_sub_from_const_to_sub2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {

llvm/trunk/test/CodeGen/X86/zext-sext.ll

 define void @func([40 x i16]* %a, i32* %b, i16** %c, i64* %d) nounwind {
 ; CHECK-LABEL: func:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movslq (%rsi), %rax
 ; CHECK-NEXT:    movl $4, %esi
 ; CHECK-NEXT:    subq %rax, %rsi
 ; CHECK-NEXT:    movq (%rdx), %rax
 ; CHECK-NEXT:    movswl 8(%rdi), %edx
-; CHECK-NEXT:    movabsq $5089792277106559579, %rdi # imm = 0x46A2931BF1768A5B
 ; CHECK-NEXT:    movswl (%rax,%rsi,2), %eax
 ; CHECK-NEXT:    movl $1, %esi
 ; CHECK-NEXT:    imull %edx, %eax
 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    addl $2138875574, %eax # imm = 0x7F7CA6B6
 ; CHECK-NEXT:    cmpl $-8608074, %eax # imm = 0xFF7CA6B6
-; CHECK-NEXT:    movslq %eax, %r8
+; CHECK-NEXT:    movslq %eax, %rdi
 ; CHECK-NEXT:    setl %dl
 ; CHECK-NEXT:    cmpl $2138875573, %eax # imm = 0x7F7CA6B5
-; CHECK-NEXT:    movq %r8, %r9
+; CHECK-NEXT:    movq %rdi, %r8
 ; CHECK-NEXT:    leal -1(%rdx,%rdx), %edx
 ; CHECK-NEXT:    cmovlel %edx, %esi
-; CHECK-NEXT:    subq %rax, %r9
-; CHECK-NEXT:    addq %r8, %rdi
+; CHECK-NEXT:    subq %rax, %r8
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    cmpl $1, %esi
-; CHECK-NEXT:    cmovneq %rax, %r9
-; CHECK-NEXT:    testl %r8d, %r8d
-; CHECK-NEXT:    cmovnsq %rax, %r9
-; CHECK-NEXT:    movabsq $-5089792279245435153, %rax # imm = 0xB95D6CE38F0CCEEF
-; CHECK-NEXT:    subq %r9, %rdi
-; CHECK-NEXT:    addq (%rcx), %rdi
-; CHECK-NEXT:    addq %rdi, %rax
+; CHECK-NEXT:    cmovneq %rax, %r8
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    cmovnsq %rax, %r8
+; CHECK-NEXT:    movq (%rcx), %rax
+; CHECK-NEXT:    subq %r8, %rdi
+; CHECK-NEXT:    leaq -2138875574(%rax,%rdi), %rax
 ; CHECK-NEXT:    movq %rax, (%rcx)
 ; CHECK-NEXT:    retq
 entry:
   %tmp103 = getelementptr inbounds [40 x i16], [40 x i16]* %a, i64 0, i64 4
   %tmp104 = load i16, i16* %tmp103, align 2
   %tmp105 = sext i16 %tmp104 to i32
   %tmp106 = load i32, i32* %b, align 4
   %tmp107 = sub nsw i32 4, %tmp106