This is an archive of the discontinued LLVM Phabricator instance.

Differential D62664

[DAGCombine] (A+C1)-C2 -> A+(C1-C2) constant-fold
ClosedPublic

Authored by lebedev.ri on May 30 2019, 7:14 AM.

Details

Reviewers
RKSimon
craig.topper
spatel
t.p.northover
Commits
rG0a3dbbcdfb54: [DAGCombine] (A+C1)-C2 -> A+(C1-C2) constant-fold
rL362133: [DAGCombine] (A+C1)-C2 -> A+(C1-C2) constant-fold
Summary

Direct sibling of D62662, the root cause of the endless combine loop in D62257

https://rise4fun.com/Alive/d3W

Diff Detail

Repository
rL LLVM

Event Timeline

lebedev.ri created this revision.May 30 2019, 7:14 AM
Herald added a subscriber: javed.absar. · View Herald TranscriptMay 30 2019, 7:14 AM
lebedev.ri added a parent revision: D62663: [DAGCombine] Use FoldConstantArithmetic() to perform C2-(A+C1) -> (C2-C1)-A fold.May 30 2019, 7:15 AM
lebedev.ri added a child revision: D62257: [DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold.
lebedev.ri updated this revision to Diff 202223.May 30 2019, 9:12 AM

Better test coverage.

lebedev.ri added a child revision: D62689: [DAGCombine] (A-C1)-C2 -> A-(C1+C2) constant-fold.May 30 2019, 9:36 AM
lebedev.ri removed a child revision: D62257: [DAGCombiner][X86][AArch64] (x - C) + y -> (x + y) - C fold.
lebedev.ri updated this revision to Diff 202230.May 30 2019, 9:55 AM

And actually fix the test coverage (:
Sorry for the noise.

t.p.northover accepted this revision.May 30 2019, 9:56 AM
t.p.northover added a subscriber: t.p.northover.

Looks reasonable.

This revision is now accepted and ready to land.May 30 2019, 9:56 AM
Closed by commit rL362133: [DAGCombine] (A+C1)-C2 -> A+(C1-C2) constant-fold (authored by lebedevri). · Explain WhyMay 30 2019, 12:25 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
SelectionDAG/
10 lines
test/
CodeGen/
AArch64/
13 lines
X86/
16 lines

Diff 202272

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,857 Lines • ▼ Show 20 LinesSDValue DAGCombiner::visitSUB(SDNode *N) {
// fold (A+B)-A -> B // fold (A+B)-A -> B
if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
return N0.getOperand(1); return N0.getOperand(1);
// fold (A+B)-B -> A // fold (A+B)-B -> A
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
return N0.getOperand(0); return N0.getOperand(0);
// fold (A+C1)-C2 -> A+(C1-C2)
if (N0.getOpcode() == ISD::ADD &&
isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
SDValue NewC = DAG.FoldConstantArithmetic(
ISD::SUB, DL, VT, N0.getOperand(1).getNode(), N1.getNode());
assert(NewC && "Constant folding failed");
return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
}
// fold C2-(A+C1) -> (C2-C1)-A // fold C2-(A+C1) -> (C2-C1)-A
if (N1.getOpcode() == ISD::ADD) { if (N1.getOpcode() == ISD::ADD) {
SDValue N11 = N1.getOperand(1); SDValue N11 = N1.getOperand(1);
if (isConstantOrConstantVector(N0, /* NoOpaques */ true) && if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
isConstantOrConstantVector(N11, /* NoOpaques */ true)) { isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(), SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
N11.getNode()); N11.getNode());
assert(NewC && "Constant folding failed"); assert(NewC && "Constant folding failed");
▲ Show 20 Lines • Show All 17,333 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/addsub-constant-folding.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
; (x+c1)-c2 ; (x+c1)-c2
define <4 x i32> @add_const_sub_const(<4 x i32> %arg) { define <4 x i32> @add_const_sub_const(<4 x i32> %arg) {
; CHECK-LABEL: add_const_sub_const: ; CHECK-LABEL: add_const_sub_const:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #6
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #2
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) { define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) {
; CHECK-LABEL: add_const_sub_const_extrause: ; CHECK-LABEL: add_const_sub_const_extrause:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32 // =32 ; CHECK-NEXT: sub sp, sp, #32 // =32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: movi v1.4s, #8 ; CHECK-NEXT: movi v1.4s, #8
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill ; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: bl use ; CHECK-NEXT: bl use
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload ; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: movi v0.4s, #2 ; CHECK-NEXT: movi v0.4s, #6
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s ; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
; CHECK-NEXT: add sp, sp, #32 // =32 ; CHECK-NEXT: add sp, sp, #32 // =32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @use(<4 x i32> %t0) call void @use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) {
; CHECK-LABEL: add_const_sub_const_nonsplat: ; CHECK-LABEL: add_const_sub_const_nonsplat:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI5_0 ; CHECK-NEXT: adrp x8, .LCPI5_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0] ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]
; CHECK-NEXT: adrp x8, .LCPI5_1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_1]
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
; c2-(x+c1) ; c2-(x+c1)
▲ Show 20 Lines • Show All 343 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/addsub-constant-folding.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
} }
; (x+c1)-c2 ; (x+c1)-c2
define <4 x i32> @add_const_sub_const(<4 x i32> %arg) { define <4 x i32> @add_const_sub_const(<4 x i32> %arg) {
; X86-LABEL: add_const_sub_const: ; X86-LABEL: add_const_sub_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0
; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: add_const_sub_const: ; X64-LABEL: add_const_sub_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) { define <4 x i32> @add_const_sub_const_extrause(<4 x i32> %arg) {
; X86-LABEL: add_const_sub_const_extrause: ; X86-LABEL: add_const_sub_const_extrause:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: subl $28, %esp ; X86-NEXT: subl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: .cfi_def_cfa_offset 32
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: movdqa %xmm0, %xmm1
; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill
; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8]
; X86-NEXT: paddd %xmm1, %xmm0
; X86-NEXT: calll use ; X86-NEXT: calll use
; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload ; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload
; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: add_const_sub_const_extrause: ; X64-LABEL: add_const_sub_const_extrause:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: subq $24, %rsp ; X64-NEXT: subq $24, %rsp
; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: .cfi_def_cfa_offset 32
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: movdqa %xmm0, %xmm1
; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill ; X64-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
; X64-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8]
; X64-NEXT: paddd %xmm1, %xmm0
; X64-NEXT: callq use ; X64-NEXT: callq use
; X64-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload ; X64-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: addq $24, %rsp ; X64-NEXT: addq $24, %rsp
; X64-NEXT: .cfi_def_cfa_offset 8 ; X64-NEXT: .cfi_def_cfa_offset 8
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
call void @use(<4 x i32> %t0) call void @use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) {
; X86-LABEL: add_const_sub_const_nonsplat: ; X86-LABEL: add_const_sub_const_nonsplat:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0
; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: add_const_sub_const_nonsplat: ; X64-LABEL: add_const_sub_const_nonsplat:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
; c2-(x+c1) ; c2-(x+c1)
▲ Show 20 Lines • Show All 505 Lines • Show Last 20 Lines