[DAGCombiner][X86][AArch64][SPARC][SystemZ] y - (x + C) -> (y - x) - C fold

[lebedev.ri]

Summary

Direct sibling of D62223 patch.
While i don't have a direct motivational pattern for this,
it would seem to make sense to handle both patterns (or none),
for symmetry?

The aarch64 changes look neutral;
sparc and systemz look like improvement (one less instruction each);
x86 changes - 32bit case improves, 64bit case shows that LEA no longer
gets constructed, which may be because that whole test is -mattr=+slow-lea,+slow-3ops-lea

https://rise4fun.com/Alive/ffh

[t.p.northover]

Looks reasonable to me.

[lebedev.ri]

Better test coverage.

@t.p.northover thanks! awaiting @RKSimon / etc, and a parent patch

[lebedev.ri]

Rebased, NFC.

[lebedev.ri]

One of the patches seems to have introduced a hang in test-suite, reverted.

[lebedev.ri]

And once more.
rL362109 + rL362110

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
     return V;
 
   // Hoist one-use addition by constant:  (x + C) - y  ->  (x - y) + C
   if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
       isConstantOrConstantVector(N0.getOperand(1))) {
     SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
     return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
   }
+  // y - (x + C)  ->  (y - x) - C
+  if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD &&
+      isConstantOrConstantVector(N1.getOperand(1))) {
+    SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
+    return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
+  }
 
   // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
   // rather than 'sub 0/1' (the sext should get folded).
   // sub X, (zext i1 Y) --> add X, (sext i1 Y)
   if (N1.getOpcode() == ISD::ZERO_EXTEND &&
       N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
       TLI.getBooleanContents(VT) ==
           TargetLowering::ZeroOrNegativeOneBooleanContent) {

llvm/trunk/test/CodeGen/AArch64/shift-amount-mod.ll

; CHECK-NEXT:    ret
   %negaaddbitwidthsubb = sub i64 %negaaddbitwidth, %b
   %shifted = lshr i64 %val, %negaaddbitwidthsubb
   ret i64 %shifted
 }
 
 define i32 @reg32_lshr_by_b_sub_negated_unfolded(i32 %val, i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: reg32_lshr_by_b_sub_negated_unfolded:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    add w8, w1, w2
+; CHECK-NEXT:    add w8, w2, w1
 ; CHECK-NEXT:    lsr w0, w0, w8
 ; CHECK-NEXT:    ret
   %nega = sub i32 0, %a
   %negaaddbitwidth = add i32 %nega, 32
   %negaaddbitwidthsubb = sub i32 %b, %negaaddbitwidth
   %shifted = lshr i32 %val, %negaaddbitwidthsubb
   ret i32 %shifted
 }
 define i64 @reg64_lshr_by_b_sub_negated_unfolded(i64 %val, i64 %a, i64 %b) nounwind {
 ; CHECK-LABEL: reg64_lshr_by_b_sub_negated_unfolded:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    add x8, x1, x2
+; CHECK-NEXT:    add x8, x2, x1
 ; CHECK-NEXT:    lsr x0, x0, x8
 ; CHECK-NEXT:    ret
   %nega = sub i64 0, %a
   %negaaddbitwidth = add i64 %nega, 64
   %negaaddbitwidthsubb = sub i64 %b, %negaaddbitwidth
   %shifted = lshr i64 %val, %negaaddbitwidthsubb
   ret i64 %shifted
 }

llvm/trunk/test/CodeGen/AArch64/sink-addsub-of-const.ll

; CHECK-NEXT:    ret
   %t0 = sub i32 %a, %b
   %t1 = add i32 %t0, 32 ; constant always on RHS
   %r = sub i32 %t1, %c
   ret i32 %r
 }
 define i32 @sink_add_of_const_to_sub2(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: sink_add_of_const_to_sub2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub w8, w0, w1
-; CHECK-NEXT:    add w8, w8, #32 // =32
-; CHECK-NEXT:    sub w0, w2, w8
+; CHECK-NEXT:    sub w8, w1, w0
+; CHECK-NEXT:    add w8, w2, w8
+; CHECK-NEXT:    sub w0, w8, #32 // =32
 ; CHECK-NEXT:    ret
   %t0 = sub i32 %a, %b
   %t1 = add i32 %t0, 32 ; constant always on RHS
   %r = sub i32 %c, %t1
   ret i32 %r
 }
 
 ; sub (sub %x, C), %y
; CHECK-NEXT:    ret
   %r = sub <4 x i32> %t1, %c
   ret <4 x i32> %r
 }
 define <4 x i32> @vec_sink_add_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: vec_sink_add_of_const_to_sub2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI19_0
 ; CHECK-NEXT:    ldr q3, [x8, :lo12:.LCPI19_0]
-; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    add v0.4s, v0.4s, v3.4s
-; CHECK-NEXT:    sub v0.4s, v2.4s, v0.4s
+; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    add v0.4s, v2.4s, v0.4s
+; CHECK-NEXT:    sub v0.4s, v0.4s, v3.4s
 ; CHECK-NEXT:    ret
   %t0 = sub <4 x i32> %a, %b
   %t1 = add <4 x i32> %t0, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
   %r = sub <4 x i32> %c, %t1
   ret <4 x i32> %r
 }
 
 ; sub (sub %x, C), %y

llvm/trunk/test/CodeGen/SPARC/2013-05-17-CallFrame.ll

 ; V8:         .cfi_startproc
 ; V8-NEXT:  ! %bb.0: ! %entry
 ; V8-NEXT:    save %sp, -96, %sp
 ; V8-NEXT:    .cfi_def_cfa_register %fp
 ; V8-NEXT:    .cfi_window_save
 ; V8-NEXT:    .cfi_register 15, 31
 ; V8-NEXT:    add %i0, 7, %i0
 ; V8-NEXT:    and %i0, -8, %i0
-; V8-NEXT:    add %i0, 8, %i0
 ; V8-NEXT:    sub %sp, %i0, %i0
-; V8-NEXT:    add %i0, 96, %o0
-; V8-NEXT:    mov %i0, %sp
+; V8-NEXT:    add %i0, -8, %sp
+; V8-NEXT:    add %i0, 88, %o0
 ; V8-NEXT:    add %sp, -16, %sp
 ; V8-NEXT:    st %o0, [%sp+104]
 ; V8-NEXT:    st %o0, [%sp+100]
 ; V8-NEXT:    st %o0, [%sp+96]
 ; V8-NEXT:    st %o0, [%sp+92]
 ; V8-NEXT:    mov %o0, %o1
 ; V8-NEXT:    mov %o0, %o2
 ; V8-NEXT:    mov %o0, %o3

llvm/trunk/test/CodeGen/SystemZ/alloca-03.ll

 ; CHECK-NEXT:    stmg %r11, %r15, 88(%r15)
 ; CHECK-NEXT:    .cfi_offset %r11, -72
 ; CHECK-NEXT:    .cfi_offset %r15, -40
 ; CHECK-NEXT:    aghi %r15, -160
 ; CHECK-NEXT:    .cfi_def_cfa_offset 320
 ; CHECK-NEXT:    lgr %r11, %r15
 ; CHECK-NEXT:    .cfi_def_cfa_register %r11
 ; CHECK-NEXT:    lgr %r1, %r15
-; CHECK-NEXT:    sllg %r2, %r2, 3
-; CHECK-NEXT:    la %r0, 120(%r2)
+; CHECK-NEXT:    sllg %r0, %r2, 3
 ; CHECK-NEXT:    sgr %r1, %r0
-; CHECK-NEXT:    la %r2, 280(%r1)
-; CHECK-NEXT:    nill %r2, 65408
-; CHECK-NEXT:    lgr %r15, %r1
-; CHECK-NEXT:    mvghi 0(%r2), 10
+; CHECK-NEXT:    lay %r15, -120(%r1)
+; CHECK-NEXT:    la %r1, 160(%r1)
+; CHECK-NEXT:    nill %r1, 65408
+; CHECK-NEXT:    mvghi 0(%r1), 10
 ; CHECK-NEXT:    lmg %r11, %r15, 248(%r11)
 ; CHECK-NEXT:    br %r14
   %x = alloca i64, i64 %len, align 128
   store volatile i64 10, i64* %x, align 128
   ret void
 }
 
 ; Static alloca w/out alignment - part of frame.

llvm/trunk/test/CodeGen/X86/sink-addsub-of-const.ll

; X64-NEXT:    retq
   ret i32 %r
 }
 define i32 @sink_add_of_const_to_sub2(i32 %a, i32 %b, i32 %c) {
 ; X32-LABEL: sink_add_of_const_to_sub2:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    subl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    addl $32, %ecx
-; X32-NEXT:    subl %ecx, %eax
+; X32-NEXT:    addl %ecx, %eax
+; X32-NEXT:    addl $-32, %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: sink_add_of_const_to_sub2:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edx, %eax
-; X64-NEXT:    subl %esi, %edi
-; X64-NEXT:    addl $32, %edi
-; X64-NEXT:    subl %edi, %eax
+; X64-NEXT:    # kill: def $edx killed $edx def $rdx
+; X64-NEXT:    # kill: def $esi killed $esi def $rsi
+; X64-NEXT:    subl %edi, %esi
+; X64-NEXT:    leal -32(%rdx,%rsi), %eax
 ; X64-NEXT:    retq
   %t0 = sub i32 %a, %b
   %t1 = add i32 %t0, 32 ; constant always on RHS
   %r = sub i32 %c, %t1
   ret i32 %r
 }
 
 ; sub (sub %x, C), %y
; X64-NEXT:    retq
   %t0 = sub <4 x i32> %a, %b
   %t1 = add <4 x i32> %t0, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
   %r = sub <4 x i32> %t1, %c
   ret <4 x i32> %r
 }
 define <4 x i32> @vec_sink_add_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
 ; X32-LABEL: vec_sink_add_of_const_to_sub2:
 ; X32:       # %bb.0:
-; X32-NEXT:    psubd %xmm1, %xmm0
-; X32-NEXT:    paddd {{\.LCPI.*}}, %xmm0
-; X32-NEXT:    psubd %xmm0, %xmm2
-; X32-NEXT:    movdqa %xmm2, %xmm0
+; X32-NEXT:    psubd %xmm0, %xmm1
+; X32-NEXT:    paddd %xmm2, %xmm1
+; X32-NEXT:    psubd {{\.LCPI.*}}, %xmm1
+; X32-NEXT:    movdqa %xmm1, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: vec_sink_add_of_const_to_sub2:
 ; X64:       # %bb.0:
-; X64-NEXT:    psubd %xmm1, %xmm0
-; X64-NEXT:    paddd {{.*}}(%rip), %xmm0
-; X64-NEXT:    psubd %xmm0, %xmm2
-; X64-NEXT:    movdqa %xmm2, %xmm0
+; X64-NEXT:    psubd %xmm0, %xmm1
+; X64-NEXT:    paddd %xmm2, %xmm1
+; X64-NEXT:    psubd {{.*}}(%rip), %xmm1
+; X64-NEXT:    movdqa %xmm1, %xmm0
 ; X64-NEXT:    retq
   %t0 = sub <4 x i32> %a, %b
   %t1 = add <4 x i32> %t0, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
   %r = sub <4 x i32> %c, %t1
   ret <4 x i32> %r
 }
 
 ; sub (sub %x, C), %y