[CGP] Make ICMP_EQ use CR result of ICMP_S(L|G)T dominators

[Yi-Hong.Lyu]

Summary

For example:

long long test(long long a, long long b) {
  if (a << b > 0)
    return b;
  if (a << b < 0)
    return a;
  return a*b;
}

Produces:

# %bb.0:                                # %entry
        sld. 5, 3, 4
        ble 0, .LBB0_2
# %bb.1:                                # %return
        mr 3, 4
        blr
.LBB0_2:                                # %if.end
        cmpldi  5, 0
        li 5, 1
        isel 4, 4, 5, 2
        mulld 3, 4, 3
        blr

But the compare (cmpldi 5, 0) is redundant and can be removed (CR0 already contains the result of that comparison).

The root cause of this is that LLVM converts signed comparisons into equality comparison based on dominance. Equality comparisons are unsigned by default, so we get either a record-form or cmp (without the l for logical) feeding a cmpl. That is the situation we want to avoid here.

[nemanjai]

Please reduce the test case only to cases that are changing behaviour. Also, it is probably useful to commit the test case initially as an NFC patch so we can see the actual difference in codegen.

llvm/lib/CodeGen/CodeGenPrepare.cpp

1415

I think it would be very helpful to comment the code in this function. Specifically, it's good to state the pattern(s) you're looking for. Something like:

Block A:
icmp slt i32 %1, 100
...
Block B (with A being the single predecessor):
icmp eq i32 %1, 100 ; Equality is exactly opposite to SGT.
...

1420

Why do we restrict this to EQ rather than also supporting NE? Is this just the canonical form and NE never shows up?

1423

More descriptive names would probably aid readability - perhaps CmpOp1/CmpOp2.

1425

Why does this need to be restricted to constant comparisons? Could we not equivalently handle comparisons between two virtual registers?

1433

We could probably handle logical operations just as easily, couldn't we?

1452

Nit: naming convention - if you have other violations of CamelCase variable naming, please fix those as well.

llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll

36

This is already in the form you want it to be in, so it doesn't really test anything this pass does.

[Yi-Hong.Lyu]

llvm/lib/CodeGen/CodeGenPrepare.cpp

1420

The pattern we observed that could be optimized is something like:

Block A:
icmp slt i32 %1, 100
...
Block B (with A being the single predecessor):
icmp eq i32 %1, 100 ; Equality is exactly opposite to SGT.
...

icmp ne i32 %1, 100 is not supposed to be there, otherwise it would be a redundant LLVM IR.

1425

Well. I think we might be able to handle comparisons between two virtual registers equivalently. However I cannot generate test cases for it. I have tried:

long long test1(long long a, long long b, long long c) {
  if (a << b > c)
    return b;
  if (a << b < c)
    return a;
  return a * b;
}

Here is the generated LLVM IR:

; Function Attrs: norecurse nounwind readnone
define dso_local i64 @_Z5test1xxx(i64 %a, i64 %b, i64 %c) local_unnamed_addr #0 {
entry:
  %shl = shl i64 %a, %b
  %cmp = icmp sgt i64 %shl, %c
  br i1 %cmp, label %return, label %if.end

if.end:                                           ; preds = %entry
  %cmp2 = icmp slt i64 %shl, %c
  %mul = select i1 %cmp2, i64 1, i64 %b
  %spec.select = mul nsw i64 %mul, %a
  ret i64 %spec.select

return:                                           ; preds = %entry
  ret i64 %b
}

Apparently, it is not the test case we want. Do you have any test cases in mind?

1433

For other logical operations, we need to introduce a not instruction. It would add more LLVM IR and that might produce more instructions, which is we would like to avoid.

[Yi-Hong.Lyu]

Change according to comments

[Yi-Hong.Lyu]

Rebase the master (NFC testcases merged). Since it is a rebased one, please see the latest commit for review

[nemanjai]

llvm/lib/CodeGen/CodeGenPrepare.cpp

1420

I don't follow why this would be redundant IR.

BlockA:
%cmp1 = icmp slt i32 %1, 100
br i1 %cmp1, BlockC, BlockB

BlockB: ; %1 is signed-greater-than-or-equal-to 100
%cmp2 = icmp ne i32 %1, 100
br i1 %cmp2, BlockD, BlockE
...
BlockC: ; %1 is signed-less-than 100
...
BlockD: ; %1 is signed-greater-than 100
...
BlockE: ; %1 is equal to 100

Of course, if the EQ case is the canonical form, that's a different statement, but I don't think NE is automatically redundant.

[Yi-Hong.Lyu]

llvm/lib/CodeGen/CodeGenPrepare.cpp

1420

After some experiments, I think EQ is canonical form and NE never shows up. I change your pseudo LLVM IR a little bit to make it work:

; ModuleID = '<stdin>'
source_filename = "<stdin>"
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

define i64 @icmp_ne(i64 %a, i64 %b) {
BlockA:
  %shl = shl i64 %a, %b
  %cmp1 = icmp slt i64 %shl, 1
  br i1 %cmp1, label %BlockC, label %BlockB

BlockB: ; %1 is signed-greater-than-or-equal-to 1
  %cmp2 = icmp ne i64 %shl, 1
  br i1 %cmp2, label %BlockD, label %BlockE

BlockC: ; %1 is signed-less-than 1
  ret i64 %a

BlockD: ; %1 is signed-greater-than 1
  ret i64 %b

BlockE: ; %1 is equal to 1
  %mul = mul nsw i64 %a, %b
  ret i64 %mul
}

However, the NE would be transformed into EQ as:

$ opt -instcombine -S < icmp_ne.ll -o -
; ModuleID = '<stdin>'
source_filename = "<stdin>"
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

define i64 @icmp_ne(i64 %a, i64 %b) {
BlockA:
  %shl = shl i64 %a, %b
  %cmp1 = icmp slt i64 %shl, 1
  br i1 %cmp1, label %BlockC, label %BlockB

BlockB:                                           ; preds = %BlockA
  %cmp2 = icmp eq i64 %shl, 1
  br i1 %cmp2, label %BlockE, label %BlockD

BlockC:                                           ; preds = %BlockA
  ret i64 %a

BlockD:                                           ; preds = %BlockB
  ret i64 %b

BlockE:                                           ; preds = %BlockB
  %mul = mul nsw i64 %a, %b
  ret i64 %mul
}

[Yi-Hong.Lyu]

Relax the restriction so we can handle comparisons between two virtual registers equivalently. I rebase the patch to TOT so history would not work. Please review this commit directly.

[lei]

llvm/include/llvm/CodeGen/TargetLowering.h

476

nit: missing . at the end of the sentence.

llvm/lib/CodeGen/CodeGenPrepare.cpp

1415

Please add a brief description for this function and some inline documentation so we can easily follow the logic.

llvm/lib/Target/PowerPC/PPCISelLowering.h

653

follow previous conventions and put return false; in the next line.

[lebedev.ri]

llvm/include/llvm/CodeGen/TargetLowering.h

477

Please add more tests for other arches - x86, aarch64 at least

[Yi-Hong.Lyu]

1. Address Lei's comments
2. Add tests for other arches - X86, AArch64 by following Roman 's comments

[Yi-Hong.Lyu]

Add the option -cgp-icmp-eq2icmp-st to enable transformation on AArch64/X86 tests (complete addressing Roman's comments)

[Yi-Hong.Lyu]

To see how my transformation affect AArch64 and X86 tests. Please use History to compare Diff 5 (221979) and Diff 6 (221983)

[Yi-Hong.Lyu]

ping ...

[lebedev.ri]

Please precommit all the tests and rebase the patch.

[nemanjai]

And yes, please pre-commit all the tests as NFC so we can see just the code-gen differences.

llvm/include/llvm/CodeGen/TargetLowering.h

477

I think a more descriptive name would be:
isEqualityCmpFoldedWithSignedCmp()

[Yi-Hong.Lyu]

Test cases are posted here https://reviews.llvm.org/D68534. I would need approval to commit the NFC patch.

[Yi-Hong.Lyu]

Pushed https://reviews.llvm.org/D68534. Rebase the patch to TOT and address Roman and Nemanja' comments

[lebedev.ri]

Some thoughts

llvm/lib/CodeGen/CodeGenPrepare.cpp

226

What's the plan with defaulting to false?

1440

What about ICmpInst::ICMP_NE?

1443

s/not only used by/has users other than/ s/or/and/

1443–1452

You want to use canFreelyInvertAllUsersOf() i think.

1464–1465

Is this guaranteed, or are some commutative cases being missed?

1474–1475

ICmpInst::Predicate NewPred = CmpInst::getSwappedPredicate(DomPred);

1485–1489

SI->swapValues();

[Yi-Hong.Lyu]

Address Roman's comments

[Yi-Hong.Lyu]

llvm/lib/CodeGen/CodeGenPrepare.cpp

226

We indeed know it remove comparison on PowerPC but we don't know whether it has negative impacts for other targets. We disable it by default and let other target to decide whether to turn it on.

1440

Please see discussion in https://reviews.llvm.org/D60506?id=194492#inline-551643. In short, EQ is canonical form and NE never shows up.

1443–1452

canFreelyInvertAllUsersOf is internal to llvm/lib/Transforms/InstCombine/InstCombineInternal.h that I cannot include and use. Should I submit a NFC patch to move it to some header so I can invoke it?

1464–1465

It is guaranteed and I am not aware of any commutative cases being missed. Without this check, some pattern like

///   DomCond = icmp sgt/slt CmpOp0, CmpOp1 (might not be in DomBB)
///   ...
/// DomBB:
///   ...
///   br DomCond, CmpBB, FalseBB
/// CmpBB: (with DomBB being the single predecessor)
///   ...
///   Cmp = icmp eq CmpOp0, CmpOp1

would continue execution. Apparently the Cmp = icmp eq CmpOp0, CmpOp1 would be always false (i.e., redundant) and it is not the pattern we are looking for.

[Yi-Hong.Lyu]

ping ...

[nemanjai]

LGTM with some minor nits related to comments/usage addressed. I personally don't have an issue with you addressing this on the commit, but give it until early next week in case someone else speaks up regarding wanting another review.

llvm/lib/CodeGen/CodeGenPrepare.cpp

1446

Nit: the sequence isa<>; cast<> is discouraged. The preferred way is to dyn_cast and the subsequent checks are done if the return value is non-null.
Also, is the check for isConditional() actually needed? Can an unconditional branch use the result of a compare?

1460

I think a comment before this section along the following lines would help readability:

// We want to ensure that the only way control gets to the comparison
// of interest is that a less/greater than comparison on the same operands
// is false.

1474

Also a comment here would be nice. Something like:

// Convert the equality comparison to the opposite of the dominating
// comparison and swap the direction for all branch/select users.
// We have conceptually converted:
// Res = (a < b) ? <LT_RES> : (a == b) ? <EQ_RES> : <GT_RES>;
// to
// Res = (a < b) ? <LT_RES> : (a > b)  ? <GT_RES> : <EQ_RES>;
// And similarly for branches.

llvm/include/llvm/CodeGen/TargetLowering.h

virtual bool isCheapToSpeculateCtlz() const {
     return false;
   }
 
   /// Return true if ctlz instruction is fast.
   virtual bool isCtlzFast() const {
     return false;
   }
 
+  /// Return true if instruction generated for equality comparison is folded
+  /// with instruction generated for signed comparison.
+  virtual bool isEqualityCmpFoldedWithSignedCmp() const { return true; }
+
   /// Return true if it is safe to transform an integer-domain bitwise operation
   /// into the equivalent floating-point operation. This should be set to true
   /// if the target has IEEE-754-compliant fabs/fneg operations for the input
   /// type.
   virtual bool hasBitPreservingFPLogic(EVT VT) const {
     return false;
   }
 

llvm/lib/CodeGen/CodeGenPrepare.cpp

static cl::opt<bool> AddrSinkCombineScaledReg(
     "addr-sink-combine-scaled-reg", cl::Hidden, cl::init(true),
     cl::desc("Allow combining of ScaledReg field in Address sinking."));
 
 static cl::opt<bool>
     EnableGEPOffsetSplit("cgp-split-large-offset-gep", cl::Hidden,
                          cl::init(true),
                          cl::desc("Enable splitting large offset of GEP."));
 
+static cl::opt<bool> EnableICMP_EQToICMP_ST(
+    "cgp-icmp-eq2icmp-st", cl::Hidden, cl::init(false),
+    cl::desc("Enable ICMP_EQ to ICMP_S(L|G)T conversion."));
+
 namespace {
 
 enum ExtType {
   ZeroExtension,   // Zero extension has been seen.
   SignExtension,   // Sign extension has been seen.
   BothExtension    // This extension type is used if we saw sext after
                    // ZeroExtension had been set, or if we saw zext after
                    // SignExtension had been set. It makes the type
static bool sinkCmpExpression(CmpInst *Cmp, const TargetLowering &TLI) {
   if (Cmp->use_empty()) {
     Cmp->eraseFromParent();
     MadeChange = true;
   }
 
   return MadeChange;
 }
 
+/// For pattern like:
+///
+///   DomCond = icmp sgt/slt CmpOp0, CmpOp1 (might not be in DomBB)
+///   ...
+/// DomBB:
+///   ...
+///   br DomCond, TrueBB, CmpBB
+/// CmpBB: (with DomBB being the single predecessor)
+///   ...
+///   Cmp = icmp eq CmpOp0, CmpOp1
+///   ...
+///
+/// It would use two comparison on targets that lowering of icmp sgt/slt is
+/// different from lowering of icmp eq (PowerPC). This function try to convert
+/// 'Cmp = icmp eq CmpOp0, CmpOp1' to ' Cmp = icmp slt/sgt CmpOp0, CmpOp1'.
+/// After that, DomCond and Cmp can use the same comparison so reduce one
+/// comparison.
+///
+/// Return true if any changes are made.
+static bool foldICmpWithDominatingICmp(CmpInst *Cmp,
+                                       const TargetLowering &TLI) {
+  if (!EnableICMP_EQToICMP_ST && TLI.isEqualityCmpFoldedWithSignedCmp())
+    return false;
+
+  ICmpInst::Predicate Pred = Cmp->getPredicate();
+  if (Pred != ICmpInst::ICMP_EQ)
+    return false;
+
+  // If icmp eq has users other than BranchInst and SelectInst, converting it to
+  // icmp slt/sgt would introduce more redundant LLVM IR.
+  for (User *U : Cmp->users()) {
+    if (isa<BranchInst>(U))
+      continue;
+    if (isa<SelectInst>(U) && cast<SelectInst>(U)->getCondition() == Cmp)
+      continue;
+    return false;
+  }
+
+  // This is a cheap/incomplete check for dominance - just match a single
+  // predecessor with a conditional branch.
+  BasicBlock *CmpBB = Cmp->getParent();
+  BasicBlock *DomBB = CmpBB->getSinglePredecessor();
+  if (!DomBB)
+    return false;
+
+  // We want to ensure that the only way control gets to the comparison of
+  // interest is that a less/greater than comparison on the same operands is
+  // false.
+  Value *DomCond;
+  BasicBlock *TrueBB, *FalseBB;
+  if (!match(DomBB->getTerminator(), m_Br(m_Value(DomCond), TrueBB, FalseBB)))
+    return false;
+  if (CmpBB != FalseBB)
+    return false;
+
+  Value *CmpOp0 = Cmp->getOperand(0), *CmpOp1 = Cmp->getOperand(1);
+  ICmpInst::Predicate DomPred;
+  if (!match(DomCond, m_ICmp(DomPred, m_Specific(CmpOp0), m_Specific(CmpOp1))))
+    return false;
+  if (DomPred != ICmpInst::ICMP_SGT && DomPred != ICmpInst::ICMP_SLT)
+    return false;
+
+  // Convert the equality comparison to the opposite of the dominating
+  // comparison and swap the direction for all branch/select users.
+  // We have conceptually converted:
+  // Res = (a < b) ? <LT_RES> : (a == b) ? <EQ_RES> : <GT_RES>;
+  // to
+  // Res = (a < b) ? <LT_RES> : (a > b)  ? <GT_RES> : <EQ_RES>;
+  // And similarly for branches.
+  for (User *U : Cmp->users()) {
+    if (auto *BI = dyn_cast<BranchInst>(U)) {
+      assert(BI->isConditional() && "Must be conditional");
+      BI->swapSuccessors();
+      continue;
+    }
+    if (auto *SI = dyn_cast<SelectInst>(U)) {
+      // Swap operands
+      SI->swapValues();
+      SI->swapProfMetadata();
+      continue;
+    }
+    llvm_unreachable("Must be a branch or a select");
+  }
+  Cmp->setPredicate(CmpInst::getSwappedPredicate(DomPred));
+  return true;
+}
+
 bool CodeGenPrepare::optimizeCmp(CmpInst *Cmp, bool &ModifiedDT) {
   if (sinkCmpExpression(Cmp, *TLI))
     return true;
 
   if (combineToUAddWithOverflow(Cmp, ModifiedDT))
     return true;
 
   if (combineToUSubWithOverflow(Cmp, ModifiedDT))
     return true;
 
+  if (foldICmpWithDominatingICmp(Cmp, *TLI))
+    return true;
+
   return false;
 }
 
 /// Duplicate and sink the given 'and' instruction into user blocks where it is
 /// used in a compare to allow isel to generate better code for targets where
 /// this operation can be combined.
 ///
 /// Return true if any changes are made.

llvm/lib/Target/PowerPC/PPCISelLowering.h

public:
     bool isCheapToSpeculateCtlz() const override {
       return true;
     }
 
     bool isCtlzFast() const override {
       return true;
     }
 
+    bool isEqualityCmpFoldedWithSignedCmp() const override {
+      return false;
+    }
+
     bool hasAndNotCompare(SDValue) const override {
       return true;
     }
 
     bool preferIncOfAddToSubOfNot(EVT VT) const override;
 
     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
       return VT.isScalarInteger();

llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-unknown-unknown -O3 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-unknown-unknown -O3 -cgp-icmp-eq2icmp-st -verify-machineinstrs < %s | FileCheck %s
 
 ; Test cases are generated from:
 ; long long NAME(PARAM a, PARAM b) {
 ;   if (LHS > RHS)
 ;     return b;
 ;   if (LHS < RHS)
 ;     return a;\
 ;   return a * b;
 ; }
 ; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
 ; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
 
 target datalayout = "e-m:e-i64:64-n32:64"
 
 define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b__2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
 ; CHECK-NEXT:    cmn x8, #2 // =2
 ; CHECK-NEXT:    b.le .LBB0_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB0_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
 ; CHECK-NEXT:    tbnz x8, #63, .LBB1_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB1_2: // %if.end
 ; CHECK-NEXT:    cmn x8, #1 // =1
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
 ; CHECK-NEXT:    cmp x8, #0 // =0
 ; CHECK-NEXT:    b.le .LBB2_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB2_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
 ; CHECK-NEXT:    cmp x8, #1 // =1
 ; CHECK-NEXT:    b.le .LBB3_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB3_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
 ; CHECK-NEXT:    cmp x8, #2 // =2
 ; CHECK-NEXT:    b.le .LBB4_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB4_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK-LABEL: ll_a__2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmn x0, #2 // =2
 ; CHECK-NEXT:    b.le .LBB5_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB5_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -2

 ; CHECK-LABEL: ll_a__1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    tbnz x0, #63, .LBB6_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB6_2: // %if.end
 ; CHECK-NEXT:    cmn x0, #1 // =1
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -1

 ; CHECK-LABEL: ll_a_0:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, #0 // =0
 ; CHECK-NEXT:    b.le .LBB7_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB7_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 0

 ; CHECK-LABEL: ll_a_1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, #1 // =1
 ; CHECK-NEXT:    b.le .LBB8_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB8_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 1

 ; CHECK-LABEL: ll_a_2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, #2 // =2
 ; CHECK-NEXT:    b.le .LBB9_2
 ; CHECK-NEXT:  // %bb.1: // %return
 ; CHECK-NEXT:    mov x0, x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB9_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    csinc x8, x1, xzr, ge
 ; CHECK-NEXT:    mul x0, x8, x0
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 2

llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll

 ; CHECK-NEXT:    sld r5, r3, r4
 ; CHECK-NEXT:    cmpdi r5, -2
 ; CHECK-NEXT:    ble cr0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, -2
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b__1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sld r5, r3, r4
 ; CHECK-NEXT:    cmpdi r5, -1
 ; CHECK-NEXT:    ble cr0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB1_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK-LABEL: ll_a_op_b_0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sld. r5, r3, r4
 ; CHECK-NEXT:    ble cr0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB2_2: # %if.end
-; CHECK-NEXT:    cmpldi r5, 0
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sld r5, r3, r4
 ; CHECK-NEXT:    cmpdi r5, 1
 ; CHECK-NEXT:    ble cr0, .LBB3_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB3_2: # %if.end
-; CHECK-NEXT:    cmpldi r5, 1
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sld r5, r3, r4
 ; CHECK-NEXT:    cmpdi r5, 2
 ; CHECK-NEXT:    ble cr0, .LBB4_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB4_2: # %if.end
-; CHECK-NEXT:    cmpldi r5, 2
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, -2
 ; CHECK-NEXT:    ble cr0, .LBB5_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB5_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -2

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, -1
 ; CHECK-NEXT:    ble cr0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB6_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -1

 ; CHECK-LABEL: ll_a_0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 0
 ; CHECK-NEXT:    ble cr0, .LBB7_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB7_2: # %if.end
-; CHECK-NEXT:    cmpldi r3, 0
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 0

 ; CHECK-LABEL: ll_a_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
 ; CHECK-NEXT:    ble cr0, .LBB8_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB8_2: # %if.end
-; CHECK-NEXT:    cmpldi r3, 1
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 1

 ; CHECK-LABEL: ll_a_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 2
 ; CHECK-NEXT:    ble cr0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB9_2: # %if.end
-; CHECK-NEXT:    cmpldi r3, 2
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 2
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_op_b__2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, -2
 ; CHECK-NEXT:    bgt cr0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB10_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -2
   br i1 %cmp, label %return, label %if.end

 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, -1
 ; CHECK-NEXT:    ble cr0, .LBB11_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB11_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -1
   br i1 %cmp, label %return, label %if.end
 

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, 0
 ; CHECK-NEXT:    ble cr0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB12_2: # %if.end
-; CHECK-NEXT:    cmplwi r5, 0
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 0
   br i1 %cmp, label %return, label %if.end
 

 
 define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_op_b_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, 1
 ; CHECK-NEXT:    bgt cr0, .LBB13_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
-; CHECK-NEXT:    cmplwi r5, 1
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB13_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 1
   br i1 %cmp, label %return, label %if.end

 
 define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_op_b_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, 2
 ; CHECK-NEXT:    bgt cr0, .LBB14_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
-; CHECK-NEXT:    cmplwi r5, 2
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB14_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 2
   br i1 %cmp, label %return, label %if.end

 
 define i64 @i_a__2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a__2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, -2
 ; CHECK-NEXT:    bgt cr0, .LBB15_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB15_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, -2
   br i1 %cmp, label %return, label %if.end
 

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, -1
 ; CHECK-NEXT:    ble cr0, .LBB16_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB16_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK-LABEL: i_a_0:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 0
 ; CHECK-NEXT:    ble cr0, .LBB17_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB17_2: # %if.end
-; CHECK-NEXT:    cmplwi r3, 0
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 }
 
 define i64 @i_a_1(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
 ; CHECK-NEXT:    bgt cr0, .LBB18_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
-; CHECK-NEXT:    cmplwi r3, 1
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB18_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 1
   br i1 %cmp, label %return, label %if.end
 

 }
 
 define i64 @i_a_2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 2
 ; CHECK-NEXT:    bgt cr0, .LBB19_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
-; CHECK-NEXT:    cmplwi r3, 2
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r4, r5, eq
+; CHECK-NEXT:    isel r4, r5, r4, lt
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB19_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 2
   br i1 %cmp, label %return, label %if.end
 

llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-unknown-unknown -O3 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -O3 -cgp-icmp-eq2icmp-st -verify-machineinstrs < %s | FileCheck %s
 
 ; Test cases are generated from:
 ; long long NAME(PARAM a, PARAM b) {
 ;   if (LHS > RHS)
 ;     return b;
 ;   if (LHS < RHS)
 ;     return a;\
 ;   return a * b;
 ; }
 ; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
 ; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
 
 target datalayout = "e-m:e-i64:64-n32:64"
 
 define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b__2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movq %rsi, %rcx
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    shlq %cl, %rax
-; CHECK-NEXT:    cmpq $-2, %rax
-; CHECK-NEXT:    jle .LBB0_1
-; CHECK-NEXT:  # %bb.2: # %return
-; CHECK-NEXT:    movq %rcx, %rax
-; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB0_1: # %if.end
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    cmpq $-2, %rdx
+; CHECK-NEXT:    jg .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB0_2: # %return
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, -2
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b__1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movq %rsi, %rcx
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    shlq %cl, %rax
-; CHECK-NEXT:    testq %rax, %rax
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    testq %rdx, %rdx
 ; CHECK-NEXT:    js .LBB1_1
 ; CHECK-NEXT:  # %bb.2: # %return
-; CHECK-NEXT:    movq %rcx, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB1_1: # %if.end
-; CHECK-NEXT:    cmpq $-1, %rax
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    cmpq $-1, %rdx
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, -1
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b_0:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movq %rsi, %rcx
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    shlq %cl, %rax
-; CHECK-NEXT:    testq %rax, %rax
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    testq %rdx, %rdx
 ; CHECK-NEXT:    jle .LBB2_1
 ; CHECK-NEXT:  # %bb.2: # %return
-; CHECK-NEXT:    movq %rcx, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB2_1: # %if.end
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovsq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, 0
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movq %rsi, %rcx
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    shlq %cl, %rax
-; CHECK-NEXT:    cmpq $1, %rax
-; CHECK-NEXT:    jle .LBB3_1
-; CHECK-NEXT:  # %bb.2: # %return
-; CHECK-NEXT:    movq %rcx, %rax
-; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB3_1: # %if.end
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    cmpq $1, %rdx
+; CHECK-NEXT:    jg .LBB3_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    testq %rdx, %rdx
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovleq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB3_2: # %return
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, 1
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b_2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movq %rsi, %rcx
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    shlq %cl, %rax
-; CHECK-NEXT:    cmpq $2, %rax
-; CHECK-NEXT:    jle .LBB4_1
-; CHECK-NEXT:  # %bb.2: # %return
-; CHECK-NEXT:    movq %rcx, %rax
-; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB4_1: # %if.end
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rcx, %rax
+; CHECK-NEXT:    movq %rsi, %rax
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    shlq %cl, %rdx
+; CHECK-NEXT:    cmpq $2, %rdx
+; CHECK-NEXT:    jg .LBB4_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB4_2: # %return
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, 2
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a__2(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a__2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpq $-2, %rdi
-; CHECK-NEXT:    jle .LBB5_1
-; CHECK-NEXT:  # %bb.2: # %return
 ; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB5_1: # %if.end
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    cmpq $-2, %rdi
+; CHECK-NEXT:    jg .LBB5_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB5_2: # %return
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i64 %a, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -2
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a__1(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a__1:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
 ; CHECK-NEXT:    testq %rdi, %rdi
 ; CHECK-NEXT:    js .LBB6_1
 ; CHECK-NEXT:  # %bb.2: # %return
-; CHECK-NEXT:    movq %rsi, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB6_1: # %if.end
 ; CHECK-NEXT:    cmpq $-1, %rdi
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i64 %a, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -1
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_0(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_0:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq %rsi, %rax
 ; CHECK-NEXT:    testq %rdi, %rdi
 ; CHECK-NEXT:    jle .LBB7_1
 ; CHECK-NEXT:  # %bb.2: # %return
-; CHECK-NEXT:    movq %rsi, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB7_1: # %if.end
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovsq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i64 %a, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 0
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_1(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpq $1, %rdi
-; CHECK-NEXT:    jle .LBB8_1
-; CHECK-NEXT:  # %bb.2: # %return
 ; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB8_1: # %if.end
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    cmpq $1, %rdi
+; CHECK-NEXT:    jg .LBB8_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    testq %rdi, %rdi
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovleq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB8_2: # %return
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i64 %a, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 1
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_2(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpq $2, %rdi
-; CHECK-NEXT:    jle .LBB9_1
-; CHECK-NEXT:  # %bb.2: # %return
 ; CHECK-NEXT:    movq %rsi, %rax
-; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB9_1: # %if.end
-; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmoveq %rsi, %rax
+; CHECK-NEXT:    cmpq $2, %rdi
+; CHECK-NEXT:    jg .LBB9_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    cmovlq %rcx, %rax
 ; CHECK-NEXT:    imulq %rdi, %rax
+; CHECK-NEXT:  .LBB9_2: # %return
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i64 %a, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 2
   %mul = select i1 %cmp1, i64 %b, i64 1

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl %esi, %ecx
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    shll %cl, %eax
 ; CHECK-NEXT:    cmpl $-2, %eax
 ; CHECK-NEXT:    jg .LBB10_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %ecx, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    cmovll %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
 ; CHECK-NEXT:  .LBB10_2: # %return
 ; CHECK-NEXT:    movslq %ecx, %rax
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -2
   br i1 %cmp, label %return, label %if.end
 

 ; CHECK-NEXT:    testl %eax, %eax
 ; CHECK-NEXT:    js .LBB11_1
 ; CHECK-NEXT:  # %bb.2: # %return
 ; CHECK-NEXT:    movslq %ecx, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB11_1: # %if.end
 ; CHECK-NEXT:    cmpl $-1, %eax
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %ecx, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    cmovll %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
 ; CHECK-NEXT:    movslq %ecx, %rax
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK-NEXT:    shll %cl, %eax
 ; CHECK-NEXT:    testl %eax, %eax
 ; CHECK-NEXT:    jle .LBB12_1
 ; CHECK-NEXT:  # %bb.2: # %return
 ; CHECK-NEXT:    movslq %ecx, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB12_1: # %if.end
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %ecx, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    cmovsl %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
 ; CHECK-NEXT:    movslq %ecx, %rax
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK-LABEL: i_a_op_b_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl %esi, %ecx
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    shll %cl, %eax
 ; CHECK-NEXT:    cmpl $1, %eax
 ; CHECK-NEXT:    jg .LBB13_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    testl %eax, %eax
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %ecx, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    cmovlel %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
 ; CHECK-NEXT:  .LBB13_2: # %return
 ; CHECK-NEXT:    movslq %ecx, %rax
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 1
   br i1 %cmp, label %return, label %if.end
 

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl %esi, %ecx
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    shll %cl, %eax
 ; CHECK-NEXT:    cmpl $2, %eax
 ; CHECK-NEXT:    jg .LBB14_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %ecx, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    cmovll %eax, %ecx
+; CHECK-NEXT:    imull %edi, %ecx
 ; CHECK-NEXT:  .LBB14_2: # %return
 ; CHECK-NEXT:    movslq %ecx, %rax
 ; CHECK-NEXT:    retq
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 2
   br i1 %cmp, label %return, label %if.end
 

 
 define i64 @i_a__2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a__2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $-2, %edi
 ; CHECK-NEXT:    jg .LBB15_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %esi, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    cmovll %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
 ; CHECK-NEXT:  .LBB15_2: # %return
 ; CHECK-NEXT:    movslq %esi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i32 %a, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK-NEXT:    testl %edi, %edi
 ; CHECK-NEXT:    js .LBB16_1
 ; CHECK-NEXT:  # %bb.2: # %return
 ; CHECK-NEXT:    movslq %esi, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB16_1: # %if.end
 ; CHECK-NEXT:    cmpl $-1, %edi
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %esi, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    cmovll %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
 ; CHECK-NEXT:    movslq %esi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i32 %a, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i32 %a, -1

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    testl %edi, %edi
 ; CHECK-NEXT:    jle .LBB17_1
 ; CHECK-NEXT:  # %bb.2: # %return
 ; CHECK-NEXT:    movslq %esi, %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB17_1: # %if.end
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %esi, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    cmovsl %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
 ; CHECK-NEXT:    movslq %esi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i32 %a, 0
   %mul = select i1 %cmp1, i32 %b, i32 1
   %spec.select = mul nsw i32 %mul, %a
   br label %return
 
 return:                                           ; preds = %if.end, %entry
   %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
   %retval.0 = sext i32 %retval.0.in to i64
   ret i64 %retval.0
 }
 
 define i64 @i_a_1(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $1, %edi
 ; CHECK-NEXT:    jg .LBB18_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    testl %edi, %edi
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %esi, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    cmovlel %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
 ; CHECK-NEXT:  .LBB18_2: # %return
 ; CHECK-NEXT:    movslq %esi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i32 %a, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 
 define i64 @i_a_2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $2, %edi
 ; CHECK-NEXT:    jg .LBB19_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    movl $1, %eax
-; CHECK-NEXT:    cmovel %esi, %eax
-; CHECK-NEXT:    imull %edi, %eax
-; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    cmovll %eax, %esi
+; CHECK-NEXT:    imull %edi, %esi
 ; CHECK-NEXT:  .LBB19_2: # %return
 ; CHECK-NEXT:    movslq %esi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %cmp = icmp sgt i32 %a, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry