[X86] Canonicalize SGT/UGT compares with constants for JCC to use SGE/UGE to reduce the number of EFLAGs reads.

[RKSimon]

Summary

This extends D101074 so the SGT/UGT -> SGE/UGE canonicalization is used for conditional jumps as well as conditional moves and comparison results.

As discussed on PR48760, some EFLAG bits are treated independently which can require additional uops to merge together for certain Jcc cases.

I'm uncertain on how/whether to deal with the use-cr-result-of-dom-icmp-st.ll regressions, its not clear to me that this the "-cgp-icmp-eq2icmp-st flag" is actually enabled anywhere, and I get the impression that D60506 was principally a PPC combine that was made generic.

[craig.topper]

What CPUs require extra uops for Jcc? Last I knew Intel Core CPUs didn’t. Not sure about Atom or AMD.

[RKSimon]

AMD targets tend to split the flags register into subregisters, so reading fewer flags often means we avoid multiple reads.

[RKSimon]

Remove some test code that I forgot about

[pengfei]

llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll

19

Regression?

[RKSimon]

llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll

19

kind of - its actually closer to the codegen we get without the -cgp-icmp-eq2icmp-st flag - as I mentioned in the summary, this flag isn't enabled anywhere afaict

I'll add an extra test run without the flag to show the diff

[pengfei]

llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll

19

Sorry, didn't notice it mentioned.

[RKSimon]

rebase - with -cgp-icmp-eq2icmp-st disabled we still appear to have a regression

[lebedev.ri]

This review may be stuck/dead, consider abandoning if no longer relevant.
Removing myself as reviewer in attempt to clean dashboard.

llvm/lib/Target/X86/X86ISelLowering.cpp

 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
 /// condition code, returning the condition code and the LHS/RHS of the
 /// comparison to make.
 static X86::CondCode TranslateX86CC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
                                     bool isFP, SDValue &LHS, SDValue &RHS,
                                     SelectionDAG &DAG) {
   if (!isFP) {
     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
-      if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnes()) {
+      const APInt &RHSV = RHSC->getAPIntValue();
+
+      if (SetCCOpcode == ISD::SETGT && RHSV.isAllOnes()) {
         // X > -1   -> X == 0, jump !sign.
         RHS = DAG.getConstant(0, DL, RHS.getValueType());
         return X86::COND_NS;
       }
-      if (SetCCOpcode == ISD::SETLT && RHSC->isZero()) {
+      if (SetCCOpcode == ISD::SETLT && RHSV.isZero()) {
         // X < 0   -> X == 0, jump on sign.
         return X86::COND_S;
       }
-      if (SetCCOpcode == ISD::SETGE && RHSC->isZero()) {
+      if (SetCCOpcode == ISD::SETGE && RHSV.isZero()) {
         // X >= 0   -> X == 0, jump on !sign.
         return X86::COND_NS;
       }
-      if (SetCCOpcode == ISD::SETLT && RHSC->isOne()) {
+      if (SetCCOpcode == ISD::SETLT && RHSV.isOne()) {
         // X < 1   -> X <= 0
         RHS = DAG.getConstant(0, DL, RHS.getValueType());
         return X86::COND_LE;
       }
+
+      // Attempt to canonicalize SGT/UGT -> SGE/UGE compares with constant which
+      // reduces the number of EFLAGs bit reads (the GE conditions don't read
+      // ZF), this may translate to less uops depending on uarch implementation.
+      // The equivalent for SLE/ULE -> SLT/ULT isn't likely to happen as we
+      // already canonicalize to that CondCode.
+      //
+      // NOTE: Only do this if incrementing the constant doesn't increase the
+      // bit encoding size - so it must either already be a i8 or i32 immediate,
+      // or it shrinks down to that. We don't do this for any i64's to avoid
+      // additional constant materializations.
+      if (!RHSV.isZero()) {
+        // Ensure the constant+1 doesn't overflow.
+        if ((SetCCOpcode == ISD::CondCode::SETGT && !RHSV.isMaxSignedValue()) ||
+            (SetCCOpcode == ISD::CondCode::SETUGT && !RHSV.isMaxValue())) {
+          APInt RHSValPlusOne = RHSV + 1;
+          if (RHSValPlusOne.isSignedIntN(32) &&
+              (!RHSV.isSignedIntN(8) || RHSValPlusOne.isSignedIntN(8))) {
+            RHS = DAG.getConstant(RHSValPlusOne, DL, RHS.getValueType());
+            return TranslateIntegerX86CC(SetCCOpcode == ISD::CondCode::SETGT
+                                             ? ISD::CondCode::SETGE
+                                             : ISD::CondCode::SETUGE);
+          }
+        }
+      }
     }
 
     return TranslateIntegerX86CC(SetCCOpcode);
   }
 
   // First determine if it is required or is profitable to flip the operands.
 
   // If LHS is a foldable load, but RHS is not, flip the condition.
if (!Op1.getNode()) {
              "Unexpected setcc expansion!");
       if (IsStrict)
         return DAG.getMergeValues({Op0, Chain}, dl);
       return Op0;
     }
   }
 
   if (Op0.getSimpleValueType().isInteger()) {
-    // Attempt to canonicalize SGT/UGT -> SGE/UGE compares with constant which
-    // reduces the number of EFLAGs bit reads (the GE conditions don't read ZF),
-    // this may translate to less uops depending on uarch implementation. The
-    // equivalent for SLE/ULE -> SLT/ULT isn't likely to happen as we already
-    // canonicalize to that CondCode.
-    // NOTE: Only do this if incrementing the constant doesn't increase the bit
-    // encoding size - so it must either already be a i8 or i32 immediate, or it
-    // shrinks down to that. We don't do this for any i64's to avoid additional
-    // constant materializations.
-    // TODO: Can we move this to TranslateX86CC to handle jumps/branches too?
-    if (auto *Op1C = dyn_cast<ConstantSDNode>(Op1)) {
-      const APInt &Op1Val = Op1C->getAPIntValue();
-      if (!Op1Val.isZero()) {
-        // Ensure the constant+1 doesn't overflow.
-        if ((CC == ISD::CondCode::SETGT && !Op1Val.isMaxSignedValue()) ||
-            (CC == ISD::CondCode::SETUGT && !Op1Val.isMaxValue())) {
-          APInt Op1ValPlusOne = Op1Val + 1;
-          if (Op1ValPlusOne.isSignedIntN(32) &&
-              (!Op1Val.isSignedIntN(8) || Op1ValPlusOne.isSignedIntN(8))) {
-            Op1 = DAG.getConstant(Op1ValPlusOne, dl, Op0.getValueType());
-            CC = CC == ISD::CondCode::SETGT ? ISD::CondCode::SETGE
-                                            : ISD::CondCode::SETUGE;
-          }
-        }
-      }
-    }
-
     SDValue X86CC;
     SDValue EFLAGS = emitFlagsForSetcc(Op0, Op1, CC, dl, DAG, X86CC);
     SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS);
     return IsStrict ? DAG.getMergeValues({Res, Chain}, dl) : Res;
   }
 
   // Handle floating point.
   X86::CondCode CondCode = TranslateX86CC(CC, dl, /*IsFP*/ true, Op0, Op1, DAG);

llvm/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 ; Bug in FindModifiedNodeSlot cause tmp14 load to become a zextload and shr 31
 ; is then optimized away.
 @tree_code_type = external dso_local global [0 x i32]    ; <[0 x i32]*> [#uses=1]
 
 define void @copy_if_shared_r() {
 ; CHECK-LABEL: copy_if_shared_r:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl 0, %eax
 ; CHECK-NEXT:    movzbl %al, %ecx
 ; CHECK-NEXT:    movl tree_code_type(,%ecx,4), %ecx
 ; CHECK-NEXT:    decl %ecx
-; CHECK-NEXT:    cmpl $2, %ecx
-; CHECK-NEXT:    ja .LBB0_2
+; CHECK-NEXT:    cmpl $3, %ecx
+; CHECK-NEXT:    jae .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %cond_true
 ; CHECK-NEXT:    shrl $31, %eax
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:  .LBB0_2: # %cond_true17
 ; CHECK-NEXT:    retl
   %tmp = load i32, i32* null    ; <i32> [#uses=1]
   %tmp56 = and i32 %tmp, 255    ; <i32> [#uses=1]
   %gep.upgrd.1 = zext i32 %tmp56 to i64   ; <i64> [#uses=1]

llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 define void @handle_vector_size_attribute() nounwind {
 ; CHECK-LABEL: handle_vector_size_attribute:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl 0, %eax
 ; CHECK-NEXT:    decl %eax
-; CHECK-NEXT:    cmpl $1, %eax
-; CHECK-NEXT:    ja .LBB0_2
+; CHECK-NEXT:    cmpl $2, %eax
+; CHECK-NEXT:    jae .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %bb77
 ; CHECK-NEXT:    movb 0, %al
 ; CHECK-NEXT:    movb 0, %al
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:  .LBB0_2: # %bb84
 ; CHECK-NEXT:    retq
 entry:

llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll

 ; CHECK-NEXT:  Ltmp0:
 ; CHECK-NEXT:    movl %edi, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, (%esp)
 ; CHECK-NEXT:    calll __ZN12wxStringBaseaSEPKw
 ; CHECK-NEXT:  Ltmp1:
 ; CHECK-NEXT:  ## %bb.7: ## %bb3314
 ; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
 ; CHECK-NEXT:    movl 0, %eax
-; CHECK-NEXT:    cmpl $121, %eax
-; CHECK-NEXT:    ja LBB0_25
+; CHECK-NEXT:    cmpl $122, %eax
+; CHECK-NEXT:    jae LBB0_25
 ; CHECK-NEXT:  ## %bb.8: ## %bb3314
 ; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
 ; CHECK-NEXT:    jmpl *LJTI0_0(,%eax,4)
 ; CHECK-NEXT:  LBB0_10: ## %bb5809
 ; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    jne LBB0_25

llvm/test/CodeGen/X86/2009-08-12-badswitch.ll

 declare void @f25() nounwind readnone
 declare void @f26() nounwind readnone
 
 define internal fastcc i32 @foo(i64 %bar) nounwind ssp {
 ; CHECK-LABEL: foo:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    pushq %rax
 ; CHECK-NEXT:    addq $-2, %rdi
-; CHECK-NEXT:    cmpq $25, %rdi
-; CHECK-NEXT:    ja LBB0_2
+; CHECK-NEXT:    cmpq $26, %rdi
+; CHECK-NEXT:    jae LBB0_2
 ; CHECK-NEXT:  ## %bb.1: ## %bb49
 ; CHECK-NEXT:    leaq LJTI0_0(%rip), %rax
 ; CHECK-NEXT:    movslq (%rax,%rdi,4), %rcx
 ; CHECK-NEXT:    addq %rax, %rcx
 ; CHECK-NEXT:    jmpq *%rcx
 ; CHECK-NEXT:  LBB0_3: ## %RRETURN_6
 ; CHECK-NEXT:    callq _f2
 ; CHECK-NEXT:    jmp LBB0_28

llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB108_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu (%rdi,%rax,4), %xmm1
 ; CHECK-NEXT:    vpcmpltd %xmm0, %xmm1, %k1
 ; CHECK-NEXT:    vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
 ; CHECK-NEXT:    vmovdqu %xmm1, (%rdi,%rax,4)
 ; CHECK-NEXT:    addq $4, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    jg .LBB108_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jge .LBB108_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
   %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB109_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu (%rdi,%rax,4), %ymm1
 ; CHECK-NEXT:    vpcmpltd %ymm0, %ymm1, %k1
 ; CHECK-NEXT:    vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1}
 ; CHECK-NEXT:    vmovdqu %ymm1, (%rdi,%rax,4)
 ; CHECK-NEXT:    addq $8, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    jg .LBB109_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jge .LBB109_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB110_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu64 (%rdi,%rax,4), %zmm1
 ; CHECK-NEXT:    vpcmpltd %zmm0, %zmm1, %k1
 ; CHECK-NEXT:    vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1}
 ; CHECK-NEXT:    vmovdqu64 %zmm1, (%rdi,%rax,4)
 ; CHECK-NEXT:    addq $16, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    jg .LBB110_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jge .LBB110_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB111_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu (%rdi,%rax,8), %xmm1
 ; CHECK-NEXT:    vpcmpltq %xmm0, %xmm1, %k1
 ; CHECK-NEXT:    vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
 ; CHECK-NEXT:    vmovdqu %xmm1, (%rdi,%rax,8)
 ; CHECK-NEXT:    addq $2, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    jg .LBB111_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jge .LBB111_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
   %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB112_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu (%rdi,%rax,8), %ymm1
 ; CHECK-NEXT:    vpcmpltq %ymm0, %ymm1, %k1
 ; CHECK-NEXT:    vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1}
 ; CHECK-NEXT:    vmovdqu %ymm1, (%rdi,%rax,8)
 ; CHECK-NEXT:    addq $4, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    jg .LBB112_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jge .LBB112_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB113_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu64 (%rdi,%rax,8), %zmm1
 ; CHECK-NEXT:    vpcmpltq %zmm0, %zmm1, %k1
 ; CHECK-NEXT:    vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1}
 ; CHECK-NEXT:    vmovdqu64 %zmm1, (%rdi,%rax,8)
 ; CHECK-NEXT:    addq $8, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    jg .LBB113_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jge .LBB113_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB114_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu (%rdi,%rax,4), %xmm1
 ; CHECK-NEXT:    vpcmpltud %xmm0, %xmm1, %k1
 ; CHECK-NEXT:    vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
 ; CHECK-NEXT:    vmovdqu %xmm1, (%rdi,%rax,4)
 ; CHECK-NEXT:    addq $4, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    ja .LBB114_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jae .LBB114_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
   %tmp2 = getelementptr inbounds i32, i32* %arg, i64 %tmp

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB115_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu (%rdi,%rax,4), %ymm1
 ; CHECK-NEXT:    vpcmpltud %ymm0, %ymm1, %k1
 ; CHECK-NEXT:    vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1}
 ; CHECK-NEXT:    vmovdqu %ymm1, (%rdi,%rax,4)
 ; CHECK-NEXT:    addq $8, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    ja .LBB115_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jae .LBB115_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB116_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu64 (%rdi,%rax,4), %zmm1
 ; CHECK-NEXT:    vpcmpltud %zmm0, %zmm1, %k1
 ; CHECK-NEXT:    vpbroadcastd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1}
 ; CHECK-NEXT:    vmovdqu64 %zmm1, (%rdi,%rax,4)
 ; CHECK-NEXT:    addq $16, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    ja .LBB116_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jae .LBB116_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB117_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu (%rdi,%rax,8), %xmm1
 ; CHECK-NEXT:    vpcmpltuq %xmm0, %xmm1, %k1
 ; CHECK-NEXT:    vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
 ; CHECK-NEXT:    vmovdqu %xmm1, (%rdi,%rax,8)
 ; CHECK-NEXT:    addq $2, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    ja .LBB117_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jae .LBB117_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]
   %tmp2 = getelementptr inbounds i64, i64* %arg, i64 %tmp

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB118_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu (%rdi,%rax,8), %ymm1
 ; CHECK-NEXT:    vpcmpltuq %ymm0, %ymm1, %k1
 ; CHECK-NEXT:    vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1 {%k1}
 ; CHECK-NEXT:    vmovdqu %ymm1, (%rdi,%rax,8)
 ; CHECK-NEXT:    addq $4, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    ja .LBB118_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jae .LBB118_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB119_1: # %bb1
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    vmovdqu64 (%rdi,%rax,8), %zmm1
 ; CHECK-NEXT:    vpcmpltuq %zmm0, %zmm1, %k1
 ; CHECK-NEXT:    vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1 {%k1}
 ; CHECK-NEXT:    vmovdqu64 %zmm1, (%rdi,%rax,8)
 ; CHECK-NEXT:    addq $8, %rax
-; CHECK-NEXT:    cmpq $1023, %rax # imm = 0x3FF
-; CHECK-NEXT:    ja .LBB119_1
+; CHECK-NEXT:    cmpq $1024, %rax # imm = 0x400
+; CHECK-NEXT:    jae .LBB119_1
 ; CHECK-NEXT:  # %bb.2: # %bb10
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
 bb:
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb
   %tmp = phi i64 [ 0, %bb ], [ %tmp8, %bb1 ]

llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll

 ; RUN: llc < %s -O0 -stop-after=livedebugvalues -o - | FileCheck %s
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.13.0"
 
 define void @foo(i32* %p) !dbg !4 {
 bb:
   %tmp = load i32, i32* %p, align 4, !dbg !7
   ; CHECK: $eax = MOV32rm killed {{.*}} $rdi, {{.*}} debug-location !7 :: (load (s32) from %ir.p)
   ; CHECK-NEXT: $rax = KILL killed renamable $eax, debug-location !7
   ; CHECK-NEXT: MOV64mr $rsp, 1, $noreg, -8, $noreg, $rax :: (store (s64) into %stack.0)
-  ; CHECK-NEXT: SUB64ri8 renamable $rax, 3, implicit-def $eflags, debug-location !7
+  ; CHECK-NEXT: SUB64ri8 renamable $rax, 4, implicit-def $eflags, debug-location !7
 
   switch i32 %tmp, label %bb7 [
     i32 0, label %bb1
     i32 1, label %bb2
     i32 2, label %bb3
     i32 3, label %bb4
   ], !dbg !8
 

llvm/test/CodeGen/X86/loop-blocks.ll

 
 ;      CHECK: .LBB2_1:
 ; CHECK-NEXT:   callq body
 ; CHECK-NEXT:   callq get
 ; CHECK-NEXT:   cmpl $2, %eax
 ; CHECK-NEXT:   jge .LBB2_2
 ; CHECK-NEXT:   callq bar99
 ; CHECK-NEXT:   callq get
-; CHECK-NEXT:   cmpl $2999, %eax
-; CHECK-NEXT:   jg .LBB2_6
+; CHECK-NEXT:   cmpl $3000, %eax
+; CHECK-NEXT:   jge .LBB2_6
 ; CHECK-NEXT:   callq block_a_true_func
 ; CHECK-NEXT:   callq block_a_merge_func
 ; CHECK-NEXT:   jmp .LBB2_1
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB2_6:
 ; CHECK-NEXT:   callq block_a_false_func
 ; CHECK-NEXT:   callq block_a_merge_func
 ; CHECK-NEXT:   jmp .LBB2_1

llvm/test/CodeGen/X86/loop-strength-reduce7.ll

 ; CHECK-NEXT:    xorl %edx, %edx
 ; CHECK-NEXT:    movl %eax, %esi
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_3: ## %bb29.i38
 ; CHECK-NEXT:    ## Parent Loop BB0_2 Depth=1
 ; CHECK-NEXT:    ## => This Inner Loop Header: Depth=2
 ; CHECK-NEXT:    incl %edx
 ; CHECK-NEXT:    addl $12, %esi
-; CHECK-NEXT:    cmpl $11, %edx
-; CHECK-NEXT:    jbe LBB0_3
+; CHECK-NEXT:    cmpl $12, %edx
+; CHECK-NEXT:    jb LBB0_3
 ; CHECK-NEXT:  ## %bb.1: ## %bb28.i37.loopexit
 ; CHECK-NEXT:    ## in Loop: Header=BB0_2 Depth=1
 ; CHECK-NEXT:    addl $4, %eax
 ; CHECK-NEXT:    addl $168, %ecx
 ; CHECK-NEXT:    jmp LBB0_2
 entry:
   br label %bb4
 

llvm/test/CodeGen/X86/machine-cse.ll

 declare void @printf(...) nounwind
 
 define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
 ; CHECK-LABEL: commute:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
 ; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
 ; CHECK-NEXT:    leal -1(%rdi), %eax
-; CHECK-NEXT:    cmpl $2, %eax
-; CHECK-NEXT:    ja .LBB1_4
+; CHECK-NEXT:    cmpl $3, %eax
+; CHECK-NEXT:    jae .LBB1_4
 ; CHECK-NEXT:  # %bb.1: # %sw.bb
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    jne .LBB1_4
 ; CHECK-NEXT:  # %bb.2: # %if.end34
 ; CHECK-NEXT:    pushq %rax
 ; CHECK-NEXT:    imull %edi, %esi
 ; CHECK-NEXT:    leal (%rsi,%rsi,2), %esi

llvm/test/CodeGen/X86/mul-constant-result.ll

 ; X86-NEXT:  .LBB0_2:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    testl %edx, %edx
 ; X86-NEXT:    je .LBB0_4
 ; X86-NEXT:  # %bb.3:
 ; X86-NEXT:    movl %esi, %eax
 ; X86-NEXT:  .LBB0_4:
 ; X86-NEXT:    decl %ecx
-; X86-NEXT:    cmpl $31, %ecx
-; X86-NEXT:    ja .LBB0_7
+; X86-NEXT:    cmpl $32, %ecx
+; X86-NEXT:    jae .LBB0_7
 ; X86-NEXT:  # %bb.5:
 ; X86-NEXT:    jmpl *.LJTI0_0(,%ecx,4)
 ; X86-NEXT:  .LBB0_6:
 ; X86-NEXT:    addl %eax, %eax
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ; X86-NEXT:  .LBB0_7:

 ; X64-HSW-NEXT:    # kill: def $edi killed $edi def $rdi
 ; X64-HSW-NEXT:    cmpl $2, %esi
 ; X64-HSW-NEXT:    movl $1, %ecx
 ; X64-HSW-NEXT:    movl %esi, %eax
 ; X64-HSW-NEXT:    cmovgel %ecx, %eax
 ; X64-HSW-NEXT:    testl %esi, %esi
 ; X64-HSW-NEXT:    cmovel %ecx, %eax
 ; X64-HSW-NEXT:    decl %edi
-; X64-HSW-NEXT:    cmpl $31, %edi
-; X64-HSW-NEXT:    ja .LBB0_3
+; X64-HSW-NEXT:    cmpl $32, %edi
+; X64-HSW-NEXT:    jae .LBB0_3
 ; X64-HSW-NEXT:  # %bb.1:
 ; X64-HSW-NEXT:    jmpq *.LJTI0_0(,%rdi,8)
 ; X64-HSW-NEXT:  .LBB0_2:
 ; X64-HSW-NEXT:    addl %eax, %eax
 ; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
 ; X64-HSW-NEXT:    retq
 ; X64-HSW-NEXT:  .LBB0_3:
 ; X64-HSW-NEXT:    xorl %eax, %eax

llvm/test/CodeGen/X86/optimize-max-0.ll

 ; CHECK-NEXT:    ## in Loop: Header=BB0_4 Depth=1
 ; CHECK-NEXT:    xorl %esi, %esi
 ; CHECK-NEXT:    jmp LBB0_4
 ; CHECK-NEXT:  LBB0_12: ## %bb18.loopexit
 ; CHECK-NEXT:    movl (%esp), %eax ## 4-byte Reload
 ; CHECK-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
 ; CHECK-NEXT:    addl %ecx, %eax
 ; CHECK-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
-; CHECK-NEXT:    cmpl $1, %edi
-; CHECK-NEXT:    jle LBB0_13
+; CHECK-NEXT:    cmpl $2, %edi
+; CHECK-NEXT:    jl LBB0_13
 ; CHECK-NEXT:  ## %bb.7: ## %bb.nph5
 ; CHECK-NEXT:    cmpl $2, %ebp
 ; CHECK-NEXT:    jl LBB0_13
 ; CHECK-NEXT:  ## %bb.8: ## %bb.nph5.split
 ; CHECK-NEXT:    movl %ebp, %edx
 ; CHECK-NEXT:    shrl $31, %edx
 ; CHECK-NEXT:    addl %ebp, %edx
 ; CHECK-NEXT:    sarl %edx

 ; CHECK-NEXT:    ## in Loop: Header=BB1_4 Depth=1
 ; CHECK-NEXT:    xorl %esi, %esi
 ; CHECK-NEXT:    jmp LBB1_4
 ; CHECK-NEXT:  LBB1_12: ## %bb18.loopexit
 ; CHECK-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
 ; CHECK-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
 ; CHECK-NEXT:    addl %ecx, %eax
 ; CHECK-NEXT:    movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
-; CHECK-NEXT:    cmpl $1, %ebp
-; CHECK-NEXT:    jbe LBB1_13
+; CHECK-NEXT:    cmpl $2, %ebp
+; CHECK-NEXT:    jb LBB1_13
 ; CHECK-NEXT:  ## %bb.7: ## %bb.nph5
 ; CHECK-NEXT:    cmpl $2, %edi
 ; CHECK-NEXT:    jb LBB1_13
 ; CHECK-NEXT:  ## %bb.8: ## %bb.nph5.split
 ; CHECK-NEXT:    movl %edi, %ebp
 ; CHECK-NEXT:    shrl %ebp
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    shrl %eax

llvm/test/CodeGen/X86/pr38217.ll

 ; CHECK-NEXT:    movl %r10d, %r11d
 ; CHECK-NEXT:    movq %rsi, %rcx
 ; CHECK-NEXT:    subq %r11, %rcx
 ; CHECK-NEXT:    movzwl _ZL11DIGIT_TABLE(%rdi,%rdi), %edi
 ; CHECK-NEXT:    movw %di, -1(%rcx)
 ; CHECK-NEXT:    movzwl _ZL11DIGIT_TABLE(%rax,%rax), %eax
 ; CHECK-NEXT:    movw %ax, -3(%rcx)
 ; CHECK-NEXT:    addl $4, %r10d
-; CHECK-NEXT:    cmpq $99999999, %r9 # imm = 0x5F5E0FF
+; CHECK-NEXT:    cmpq $100000000, %r9 # imm = 0x5F5E100
 ; CHECK-NEXT:    movq %rdx, %r9
-; CHECK-NEXT:    ja .LBB0_2
+; CHECK-NEXT:    jae .LBB0_2
 ; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    retq
   %3 = icmp ugt i64 %0, 9999
   br i1 %3, label %4, label %31
 
 ; <label>:4:                                      ; preds = %2, %4
   %5 = phi i64 [ %9, %4 ], [ %0, %2 ]
   %6 = phi i32 [ %29, %4 ], [ 0, %2 ]

llvm/test/CodeGen/X86/pr38795.ll

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_16: # %for.inc
 ; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
 ; CHECK-NEXT:    movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
 ; CHECK-NEXT:    movb %dh, %dl
 ; CHECK-NEXT:  .LBB0_1: # %for.cond
 ; CHECK-NEXT:    # =>This Loop Header: Depth=1
 ; CHECK-NEXT:    # Child Loop BB0_20 Depth 2
-; CHECK-NEXT:    cmpb $8, %dl
+; CHECK-NEXT:    cmpb $9, %dl
 ; CHECK-NEXT:    movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
-; CHECK-NEXT:    ja .LBB0_3
+; CHECK-NEXT:    jae .LBB0_3
 ; CHECK-NEXT:  # %bb.2: # %for.cond
 ; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
 ; CHECK-NEXT:    testb %bl, %bl
 ; CHECK-NEXT:    je .LBB0_3
 ; CHECK-NEXT:  # %bb.4: # %if.end
 ; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
 ; CHECK-NEXT:    movl %ecx, %eax
 ; CHECK-NEXT:    cltd
 ; CHECK-NEXT:    idivl a
 ; CHECK-NEXT:    movb {{[-0-9]+}}(%e{{[sb]}}p), %dl # 1-byte Reload
 ; CHECK-NEXT:    movb %cl, %dh
 ; CHECK-NEXT:    movl $0, h
-; CHECK-NEXT:    cmpb $8, %dl
-; CHECK-NEXT:    jg .LBB0_8
+; CHECK-NEXT:    cmpb $9, %dl
+; CHECK-NEXT:    jge .LBB0_8
 ; CHECK-NEXT:  # %bb.5: # %if.then13
 ; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
 ; CHECK-NEXT:    movl %eax, %esi
 ; CHECK-NEXT:    movl $.str, (%esp)
 ; CHECK-NEXT:    movb %dh, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
 ; CHECK-NEXT:    calll printf
 ; CHECK-NEXT:    movb {{[-0-9]+}}(%e{{[sb]}}p), %dh # 1-byte Reload
 ; CHECK-NEXT:    testb %bl, %bl

llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll

 ; CHECK-NEXT:    testl %r15d, %r15d
 ; CHECK-NEXT:    movl %r14d, %r13d
 ; CHECK-NEXT:    jle LBB0_22
 ; CHECK-NEXT:  LBB0_13: ## %while.body200
 ; CHECK-NEXT:    ## =>This Loop Header: Depth=1
 ; CHECK-NEXT:    ## Child Loop BB0_29 Depth 2
 ; CHECK-NEXT:    ## Child Loop BB0_38 Depth 2
 ; CHECK-NEXT:    leal -268(%r13), %eax
-; CHECK-NEXT:    cmpl $105, %eax
-; CHECK-NEXT:    ja LBB0_14
+; CHECK-NEXT:    cmpl $106, %eax
+; CHECK-NEXT:    jae LBB0_14
 ; CHECK-NEXT:  ## %bb.56: ## %while.body200
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    movslq (%rbx,%rax,4), %rax
 ; CHECK-NEXT:    addq %rbx, %rax
 ; CHECK-NEXT:    jmpq *%rax
 ; CHECK-NEXT:  LBB0_44: ## %while.cond1037.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    testb %r12b, %r12b
 ; CHECK-NEXT:    movl %r13d, %r14d
 ; CHECK-NEXT:    jne LBB0_21
 ; CHECK-NEXT:    jmp LBB0_55
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_14: ## %while.body200
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    leal 1(%r13), %eax
-; CHECK-NEXT:    cmpl $21, %eax
-; CHECK-NEXT:    ja LBB0_20
+; CHECK-NEXT:    cmpl $22, %eax
+; CHECK-NEXT:    jae LBB0_20
 ; CHECK-NEXT:  ## %bb.15: ## %while.body200
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    movl $-1, %r14d
 ; CHECK-NEXT:    movslq (%rdx,%rax,4), %rax
 ; CHECK-NEXT:    addq %rdx, %rax
 ; CHECK-NEXT:    jmpq *%rax
 ; CHECK-NEXT:  LBB0_18: ## %while.cond201.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1

 ; CHECK-NEXT:    movl $2, %r14d
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:  LBB0_33: ## %if.end517.loopexitsplit
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    incq %rbp
 ; CHECK-NEXT:  LBB0_34: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    leal -324(%r14), %eax
-; CHECK-NEXT:    cmpl $59, %eax
-; CHECK-NEXT:    ja LBB0_35
+; CHECK-NEXT:    cmpl $60, %eax
+; CHECK-NEXT:    jae LBB0_35
 ; CHECK-NEXT:  ## %bb.57: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    movabsq $576460756598390785, %rcx ## imm = 0x800000100000001
 ; CHECK-NEXT:    btq %rax, %rcx
 ; CHECK-NEXT:    jb LBB0_38
 ; CHECK-NEXT:  LBB0_35: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    cmpl $11, %r14d

 ; CHECK-NEXT:  LBB0_25: ## %for.cond357
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    jmp LBB0_25
 ; CHECK-NEXT:  LBB0_11:
 ; CHECK-NEXT:    movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
 ; CHECK-NEXT:    xorl %r14d, %r14d
 ; CHECK-NEXT:  LBB0_22: ## %while.end1465
 ; CHECK-NEXT:    incl %r14d
-; CHECK-NEXT:    cmpl $16, %r14d
-; CHECK-NEXT:    ja LBB0_50
+; CHECK-NEXT:    cmpl $17, %r14d
+; CHECK-NEXT:    jae LBB0_50
 ; CHECK-NEXT:  ## %bb.23: ## %while.end1465
 ; CHECK-NEXT:    movl $83969, %eax ## imm = 0x14801
 ; CHECK-NEXT:    btl %r14d, %eax
 ; CHECK-NEXT:    jae LBB0_50
 ; CHECK-NEXT:  ## %bb.24:
 ; CHECK-NEXT:    xorl %ebp, %ebp
 ; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload
 ; CHECK-NEXT:  LBB0_48: ## %if.then1477

llvm/test/CodeGen/X86/reverse_branches.ll

 ; CHECK-NEXT:    jmp LBB0_1
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_6: ## %for.inc9
 ; CHECK-NEXT:    ## in Loop: Header=BB0_1 Depth=1
 ; CHECK-NEXT:    incl %r12d
 ; CHECK-NEXT:  LBB0_1: ## %for.cond
 ; CHECK-NEXT:    ## =>This Loop Header: Depth=1
 ; CHECK-NEXT:    ## Child Loop BB0_3 Depth 2
-; CHECK-NEXT:    cmpl $999, %r12d ## imm = 0x3E7
-; CHECK-NEXT:    jg LBB0_7
+; CHECK-NEXT:    cmpl $1000, %r12d ## imm = 0x3E8
+; CHECK-NEXT:    jge LBB0_7
 ; CHECK-NEXT:  ## %bb.2: ## %for.cond1.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_1 Depth=1
 ; CHECK-NEXT:    movl $-1, %ebp
 ; CHECK-NEXT:    movq %r15, %rdi
 ; CHECK-NEXT:    movq %r14, %rbx
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_3: ## %for.cond1
 ; CHECK-NEXT:    ## Parent Loop BB0_1 Depth=1
 ; CHECK-NEXT:    ## => This Inner Loop Header: Depth=2
 ; CHECK-NEXT:    incl %ebp
-; CHECK-NEXT:    cmpl $999, %ebp ## imm = 0x3E7
-; CHECK-NEXT:    jg LBB0_6
+; CHECK-NEXT:    cmpl $1000, %ebp ## imm = 0x3E8
+; CHECK-NEXT:    jge LBB0_6
 ; CHECK-NEXT:  ## %bb.4: ## %for.body3
 ; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=2
 ; CHECK-NEXT:    addq $1002, %rbx ## imm = 0x3EA
 ; CHECK-NEXT:    leaq 1001(%rdi), %r13
 ; CHECK-NEXT:    movl $1000, %edx ## imm = 0x3E8
 ; CHECK-NEXT:    movl $120, %esi
 ; CHECK-NEXT:    callq _memchr
 ; CHECK-NEXT:    cmpq %rax, %rbx

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_15: ## %for.inc38
 ; CHECK-NEXT:    ## in Loop: Header=BB0_8 Depth=1
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:  LBB0_8: ## %for.cond14
 ; CHECK-NEXT:    ## =>This Loop Header: Depth=1
 ; CHECK-NEXT:    ## Child Loop BB0_10 Depth 2
 ; CHECK-NEXT:    ## Child Loop BB0_12 Depth 3
-; CHECK-NEXT:    cmpl $999, %eax ## imm = 0x3E7
-; CHECK-NEXT:    jg LBB0_16
+; CHECK-NEXT:    cmpl $1000, %eax ## imm = 0x3E8
+; CHECK-NEXT:    jge LBB0_16
 ; CHECK-NEXT:  ## %bb.9: ## %for.cond18.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_8 Depth=1
 ; CHECK-NEXT:    movq %rcx, %rdx
 ; CHECK-NEXT:    xorl %esi, %esi
 ; CHECK-NEXT:    xorl %edi, %edi
 ; CHECK-NEXT:    jmp LBB0_10
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_14: ## %exit
 ; CHECK-NEXT:    ## in Loop: Header=BB0_10 Depth=2
 ; CHECK-NEXT:    addq %rsi, %rbp
 ; CHECK-NEXT:    incq %rdi
 ; CHECK-NEXT:    decq %rsi
 ; CHECK-NEXT:    addq $1001, %rdx ## imm = 0x3E9
 ; CHECK-NEXT:    cmpq $-1000, %rbp ## imm = 0xFC18
 ; CHECK-NEXT:    jne LBB0_5
 ; CHECK-NEXT:  LBB0_10: ## %for.cond18
 ; CHECK-NEXT:    ## Parent Loop BB0_8 Depth=1
 ; CHECK-NEXT:    ## => This Loop Header: Depth=2
 ; CHECK-NEXT:    ## Child Loop BB0_12 Depth 3
-; CHECK-NEXT:    cmpl $999, %edi ## imm = 0x3E7
-; CHECK-NEXT:    jg LBB0_15
+; CHECK-NEXT:    cmpl $1000, %edi ## imm = 0x3E8
+; CHECK-NEXT:    jge LBB0_15
 ; CHECK-NEXT:  ## %bb.11: ## %for.body20
 ; CHECK-NEXT:    ## in Loop: Header=BB0_10 Depth=2
 ; CHECK-NEXT:    movq $-1000, %rbp ## imm = 0xFC18
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_12: ## %do.body.i
 ; CHECK-NEXT:    ## Parent Loop BB0_8 Depth=1
 ; CHECK-NEXT:    ## Parent Loop BB0_10 Depth=2
 ; CHECK-NEXT:    ## => This Inner Loop Header: Depth=3

llvm/test/CodeGen/X86/sibcall.ll

 }
 
 
 define dso_local i32 @t6(i32 %x) nounwind ssp {
 ; X86-LABEL: t6:
 ; X86:       # %bb.0:
 ; X86-NEXT:    subl $12, %esp
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    cmpl $9, %eax
-; X86-NEXT:    jg .LBB6_2
+; X86-NEXT:    cmpl $10, %eax
+; X86-NEXT:    jge .LBB6_2
 ; X86-NEXT:  # %bb.1: # %bb
 ; X86-NEXT:    decl %eax
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    calll t6
 ; X86-NEXT:    addl $12, %esp
 ; X86-NEXT:    retl
 ; X86-NEXT:  .LBB6_2: # %bb1
 ; X86-NEXT:    addl $12, %esp
 ; X86-NEXT:    jmp bar # TAILCALL
 ;
 ; X64-LABEL: t6:
 ; X64:       # %bb.0:
-; X64-NEXT:    cmpl $9, %edi
-; X64-NEXT:    jg .LBB6_2
+; X64-NEXT:    cmpl $10, %edi
+; X64-NEXT:    jge .LBB6_2
 ; X64-NEXT:  # %bb.1: # %bb
 ; X64-NEXT:    decl %edi
 ; X64-NEXT:    jmp t6 # TAILCALL
 ; X64-NEXT:  .LBB6_2: # %bb1
 ; X64-NEXT:    jmp bar # TAILCALL
 ;
 ; X32-LABEL: t6:
 ; X32:       # %bb.0:
-; X32-NEXT:    cmpl $9, %edi
-; X32-NEXT:    jg .LBB6_2
+; X32-NEXT:    cmpl $10, %edi
+; X32-NEXT:    jge .LBB6_2
 ; X32-NEXT:  # %bb.1: # %bb
 ; X32-NEXT:    decl %edi
 ; X32-NEXT:    jmp t6 # TAILCALL
 ; X32-NEXT:  .LBB6_2: # %bb1
 ; X32-NEXT:    jmp bar # TAILCALL
   %t0 = icmp slt i32 %x, 10
   br i1 %t0, label %bb, label %bb1
 

 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl %eax, (%esp)
 ; X86-NEXT:    calll t22_f_sret@PLT
 ; X86-NEXT:    addl $8, %esp
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: t22_non_sret_to_sret:
 ; X64:       # %bb.0:
-; X64-NEXT:    jmp  t22_f_sret@PLT                  # TAILCALL
+; X64-NEXT:    jmp t22_f_sret@PLT # TAILCALL
 ;
 ; X32-LABEL: t22_non_sret_to_sret:
 ; X32:       # %bb.0:
-; X32-NEXT:    jmp  t22_f_sret@PLT                  # TAILCALL
+; X32-NEXT:    jmp t22_f_sret@PLT # TAILCALL
   tail call ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind
   ret void
 }
 
 declare dso_local fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo)) nounwind
 declare dso_local fastcc void @t21_f_sret2(%struct.foo* noalias sret(%struct.foo), %struct.foo* noalias) nounwind
 declare dso_local fastcc void @t21_f_non_sret(%struct.foo*) nounwind
 
 declare ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo)) nounwind
 
 declare ccc void @f_sret(%struct.foo* noalias sret(%struct.foo), i32, i32) nounwind

llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll

 define dso_local i32 @_Z3barPi(i32* %p) {
 ; CHECK-LABEL: _Z3barPi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfence
 ; CHECK-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    lfence
 ; CHECK-NEXT:    movl $4, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    lfence
-; CHECK-NEXT:    cmpl $3, (%rdi)
+; CHECK-NEXT:    cmpl $4, (%rdi)
 ; CHECK-NEXT:    lfence
-; CHECK-NEXT:    jg .LBB1_2
+; CHECK-NEXT:    jge .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    lfence
 ; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    lfence
 ; CHECK-NEXT:    movslq (%rax), %rax
 ; CHECK-NEXT:    lfence
 ; CHECK-NEXT:    movl -24(%rsp,%rax,4), %eax
 ; CHECK-NEXT:    lfence
 ; CHECK-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    lfence
 ; CHECK-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB1_2: # %if.else
 ; CHECK-NEXT:    lfence
 ; CHECK-NEXT:    movl $-1, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    lfence
 ; CHECK-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
 ; CHECK-NEXT:    retq
 ;
 ; X86-ONE-LFENCE-LABEL: _Z3barPi:
 ; X86-ONE-LFENCE:       # %bb.0: # %entry
 ; X86-ONE-LFENCE-NEXT:    lfence
 ; X86-ONE-LFENCE-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
 ; X86-ONE-LFENCE-NEXT:    movl $4, -{{[0-9]+}}(%rsp)
-; X86-ONE-LFENCE-NEXT:    cmpl $3, (%rdi)
-; X86-ONE-LFENCE-NEXT:    jg .LBB1_2
+; X86-ONE-LFENCE-NEXT:    cmpl $4, (%rdi)
+; X86-ONE-LFENCE-NEXT:    jge .LBB1_2
 ; X86-ONE-LFENCE-NEXT:  # %bb.1: # %if.then
 ; X86-ONE-LFENCE-NEXT:    lfence
 ; X86-ONE-LFENCE-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; X86-ONE-LFENCE-NEXT:    movslq (%rax), %rax
 ; X86-ONE-LFENCE-NEXT:    movl -24(%rsp,%rax,4), %eax
 ; X86-ONE-LFENCE-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
 ; X86-ONE-LFENCE-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
 ; X86-ONE-LFENCE-NEXT:    retq
 ; X86-ONE-LFENCE-NEXT:  .LBB1_2: # %if.else
 ; X86-ONE-LFENCE-NEXT:    lfence
 ; X86-ONE-LFENCE-NEXT:    movl $-1, -{{[0-9]+}}(%rsp)
 ; X86-ONE-LFENCE-NEXT:    movl -{{[0-9]+}}(%rsp), %eax
 ; X86-ONE-LFENCE-NEXT:    retq
 ;
 ; X86-OMIT-BR-LABEL: _Z3barPi:
 ; X86-OMIT-BR:       # %bb.0: # %entry
 ; X86-OMIT-BR-NEXT:    lfence
 ; X86-OMIT-BR-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
 ; X86-OMIT-BR-NEXT:    lfence
 ; X86-OMIT-BR-NEXT:    movl $4, -{{[0-9]+}}(%rsp)
 ; X86-OMIT-BR-NEXT:    lfence
-; X86-OMIT-BR-NEXT:    cmpl $3, (%rdi)
-; X86-OMIT-BR-NEXT:    jg .LBB1_2
+; X86-OMIT-BR-NEXT:    cmpl $4, (%rdi)
+; X86-OMIT-BR-NEXT:    jge .LBB1_2
 ; X86-OMIT-BR-NEXT:  # %bb.1: # %if.then
 ; X86-OMIT-BR-NEXT:    lfence
 ; X86-OMIT-BR-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; X86-OMIT-BR-NEXT:    lfence
 ; X86-OMIT-BR-NEXT:    movslq (%rax), %rax
 ; X86-OMIT-BR-NEXT:    lfence
 ; X86-OMIT-BR-NEXT:    movl -24(%rsp,%rax,4), %eax
 ; X86-OMIT-BR-NEXT:    lfence

 ;
 ; X86-NON-CONST-LABEL: _Z3barPi:
 ; X86-NON-CONST:       # %bb.0: # %entry
 ; X86-NON-CONST-NEXT:    lfence
 ; X86-NON-CONST-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
 ; X86-NON-CONST-NEXT:    lfence
 ; X86-NON-CONST-NEXT:    movl $4, -{{[0-9]+}}(%rsp)
 ; X86-NON-CONST-NEXT:    lfence
-; X86-NON-CONST-NEXT:    cmpl $3, (%rdi)
+; X86-NON-CONST-NEXT:    cmpl $4, (%rdi)
 ; X86-NON-CONST-NEXT:    lfence
-; X86-NON-CONST-NEXT:    jg .LBB1_2
+; X86-NON-CONST-NEXT:    jge .LBB1_2
 ; X86-NON-CONST-NEXT:  # %bb.1: # %if.then
 ; X86-NON-CONST-NEXT:    lfence
 ; X86-NON-CONST-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; X86-NON-CONST-NEXT:    lfence
 ; X86-NON-CONST-NEXT:    movslq (%rax), %rax
 ; X86-NON-CONST-NEXT:    lfence
 ; X86-NON-CONST-NEXT:    movl -24(%rsp,%rax,4), %eax
 ; X86-NON-CONST-NEXT:    lfence

llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll

 ; This function's switch is crafted to trigger jump-table lowering in the x86
 ; backend so that we can test how the exact jump table lowering behaves.
 define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
 ; X64-LABEL: test_switch_jumptable:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    movq %rsp, %rcx
 ; X64-NEXT:    movq $-1, %rax
 ; X64-NEXT:    sarq $63, %rcx
-; X64-NEXT:    cmpl $3, %edi
-; X64-NEXT:    ja .LBB6_2
+; X64-NEXT:    cmpl $4, %edi
+; X64-NEXT:    jae .LBB6_2
 ; X64-NEXT:  # %bb.1: # %entry
-; X64-NEXT:    cmovaq %rax, %rcx
+; X64-NEXT:    cmovaeq %rax, %rcx
 ; X64-NEXT:    movl %edi, %edx
 ; X64-NEXT:    movq .LJTI6_0(,%rdx,8), %rdx
 ; X64-NEXT:    orq %rcx, %rdx
 ; X64-NEXT:    jmpq *%rdx
 ; X64-NEXT:  .LBB6_3: # Block address taken
 ; X64-NEXT:    # %bb1
 ; X64-NEXT:    cmpq $.LBB6_3, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx
 ; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $7, %eax
 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    retq
 ; X64-NEXT:  .LBB6_2: # %bb0
-; X64-NEXT:    cmovbeq %rax, %rcx
+; X64-NEXT:    cmovbq %rax, %rcx
 ; X64-NEXT:    shlq $47, %rcx
 ; X64-NEXT:    movl $2, %eax
 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    retq
 ; X64-NEXT:  .LBB6_4: # Block address taken
 ; X64-NEXT:    # %bb2
 ; X64-NEXT:    cmpq $.LBB6_4, %rdx
 ; X64-NEXT:    cmovneq %rax, %rcx

 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    retq
 ;
 ; X64-PIC-LABEL: test_switch_jumptable:
 ; X64-PIC:       # %bb.0: # %entry
 ; X64-PIC-NEXT:    movq %rsp, %rcx
 ; X64-PIC-NEXT:    movq $-1, %rax
 ; X64-PIC-NEXT:    sarq $63, %rcx
-; X64-PIC-NEXT:    cmpl $3, %edi
-; X64-PIC-NEXT:    ja .LBB6_2
+; X64-PIC-NEXT:    cmpl $4, %edi
+; X64-PIC-NEXT:    jae .LBB6_2
 ; X64-PIC-NEXT:  # %bb.1: # %entry
-; X64-PIC-NEXT:    cmovaq %rax, %rcx
+; X64-PIC-NEXT:    cmovaeq %rax, %rcx
 ; X64-PIC-NEXT:    movl %edi, %edx
 ; X64-PIC-NEXT:    leaq .LJTI6_0(%rip), %rsi
 ; X64-PIC-NEXT:    movslq (%rsi,%rdx,4), %rdx
 ; X64-PIC-NEXT:    addq %rsi, %rdx
 ; X64-PIC-NEXT:    orq %rcx, %rdx
 ; X64-PIC-NEXT:    jmpq *%rdx
 ; X64-PIC-NEXT:  .LBB6_3: # Block address taken
 ; X64-PIC-NEXT:    # %bb1
 ; X64-PIC-NEXT:    leaq .LBB6_3(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx
 ; X64-PIC-NEXT:    cmovneq %rax, %rcx
 ; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $7, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    retq
 ; X64-PIC-NEXT:  .LBB6_2: # %bb0
-; X64-PIC-NEXT:    cmovbeq %rax, %rcx
+; X64-PIC-NEXT:    cmovbq %rax, %rcx
 ; X64-PIC-NEXT:    shlq $47, %rcx
 ; X64-PIC-NEXT:    movl $2, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    retq
 ; X64-PIC-NEXT:  .LBB6_4: # Block address taken
 ; X64-PIC-NEXT:    # %bb2
 ; X64-PIC-NEXT:    leaq .LBB6_4(%rip), %rsi
 ; X64-PIC-NEXT:    cmpq %rsi, %rdx

 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    retq
 ;
 ; X64-RETPOLINE-LABEL: test_switch_jumptable:
 ; X64-RETPOLINE:       # %bb.0: # %entry
 ; X64-RETPOLINE-NEXT:    movq %rsp, %rcx
 ; X64-RETPOLINE-NEXT:    movq $-1, %rax
 ; X64-RETPOLINE-NEXT:    sarq $63, %rcx
-; X64-RETPOLINE-NEXT:    cmpl $1, %edi
-; X64-RETPOLINE-NEXT:    jg .LBB7_4
+; X64-RETPOLINE-NEXT:    cmpl $2, %edi
+; X64-RETPOLINE-NEXT:    jge .LBB7_4
 ; X64-RETPOLINE-NEXT:  # %bb.1: # %entry
-; X64-RETPOLINE-NEXT:    cmovgq %rax, %rcx
+; X64-RETPOLINE-NEXT:    cmovgeq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    testl %edi, %edi
 ; X64-RETPOLINE-NEXT:    je .LBB7_7
 ; X64-RETPOLINE-NEXT:  # %bb.2: # %entry
 ; X64-RETPOLINE-NEXT:    cmoveq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    cmpl $1, %edi
 ; X64-RETPOLINE-NEXT:    jne .LBB7_6
 ; X64-RETPOLINE-NEXT:  # %bb.3: # %bb2
 ; X64-RETPOLINE-NEXT:    cmovneq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    shlq $47, %rcx
 ; X64-RETPOLINE-NEXT:    movl $13, %eax
 ; X64-RETPOLINE-NEXT:    orq %rcx, %rsp
 ; X64-RETPOLINE-NEXT:    retq
 ; X64-RETPOLINE-NEXT:  .LBB7_4: # %entry
-; X64-RETPOLINE-NEXT:    cmovleq %rax, %rcx
-; X64-RETPOLINE-NEXT:    cmpl $2, %edi
+; X64-RETPOLINE-NEXT:    cmovlq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    je .LBB7_8
 ; X64-RETPOLINE-NEXT:  # %bb.5: # %entry
 ; X64-RETPOLINE-NEXT:    cmoveq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    cmpl $3, %edi
 ; X64-RETPOLINE-NEXT:    jne .LBB7_6
 ; X64-RETPOLINE-NEXT:  # %bb.9: # %bb5
 ; X64-RETPOLINE-NEXT:    cmovneq %rax, %rcx
 ; X64-RETPOLINE-NEXT:    shlq $47, %rcx

 ; also arranges for fallthroughs from case to case to ensure that this pattern
 ; too can be handled.
 define dso_local i32 @test_switch_jumptable_fallthrough(i32 %idx, i32* %a.ptr, i32* %b.ptr, i32* %c.ptr, i32* %d.ptr) nounwind {
 ; X64-LABEL: test_switch_jumptable_fallthrough:
 ; X64:       # %bb.0: # %entry
 ; X64-NEXT:    movq %rsp, %r9
 ; X64-NEXT:    movq $-1, %r10
 ; X64-NEXT:    sarq $63, %r9
-; X64-NEXT:    cmpl $3, %edi
-; X64-NEXT:    ja .LBB7_2
+; X64-NEXT:    cmpl $4, %edi
+; X64-NEXT:    jae .LBB7_2
 ; X64-NEXT:  # %bb.1: # %entry
-; X64-NEXT:    cmovaq %r10, %r9
+; X64-NEXT:    cmovaeq %r10, %r9
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    movl %edi, %esi
 ; X64-NEXT:    movq .LJTI7_0(,%rsi,8), %rsi
 ; X64-NEXT:    orq %r9, %rsi
 ; X64-NEXT:    jmpq *%rsi
 ; X64-NEXT:  .LBB7_2: # %bb0
-; X64-NEXT:    cmovbeq %r10, %r9
+; X64-NEXT:    cmovbq %r10, %r9
 ; X64-NEXT:    movl (%rsi), %eax
 ; X64-NEXT:    orl %r9d, %eax
 ; X64-NEXT:    movq $.LBB7_3, %rsi
 ; X64-NEXT:  .LBB7_3: # Block address taken
 ; X64-NEXT:    # %bb1
 ; X64-NEXT:    cmpq $.LBB7_3, %rsi
 ; X64-NEXT:    cmovneq %r10, %r9
 ; X64-NEXT:    addl (%rdx), %eax

 ; X64-NEXT:    orq %r9, %rsp
 ; X64-NEXT:    retq
 ;
 ; X64-PIC-LABEL: test_switch_jumptable_fallthrough:
 ; X64-PIC:       # %bb.0: # %entry
 ; X64-PIC-NEXT:    movq %rsp, %r9
 ; X64-PIC-NEXT:    movq $-1, %r10
 ; X64-PIC-NEXT:    sarq $63, %r9
-; X64-PIC-NEXT:    cmpl $3, %edi
-; X64-PIC-NEXT:    ja .LBB7_2
+; X64-PIC-NEXT:    cmpl $4, %edi
+; X64-PIC-NEXT:    jae .LBB7_2
 ; X64-PIC-NEXT:  # %bb.1: # %entry
-; X64-PIC-NEXT:    cmovaq %r10, %r9
+; X64-PIC-NEXT:    cmovaeq %r10, %r9
 ; X64-PIC-NEXT:    xorl %eax, %eax
 ; X64-PIC-NEXT:    movl %edi, %esi
 ; X64-PIC-NEXT:    leaq .LJTI7_0(%rip), %rdi
 ; X64-PIC-NEXT:    movslq (%rdi,%rsi,4), %rsi
 ; X64-PIC-NEXT:    addq %rdi, %rsi
 ; X64-PIC-NEXT:    orq %r9, %rsi
 ; X64-PIC-NEXT:    jmpq *%rsi
 ; X64-PIC-NEXT:  .LBB7_2: # %bb0
-; X64-PIC-NEXT:    cmovbeq %r10, %r9
+; X64-PIC-NEXT:    cmovbq %r10, %r9
 ; X64-PIC-NEXT:    movl (%rsi), %eax
 ; X64-PIC-NEXT:    orl %r9d, %eax
 ; X64-PIC-NEXT:    leaq .LBB7_3(%rip), %rsi
 ; X64-PIC-NEXT:  .LBB7_3: # Block address taken
 ; X64-PIC-NEXT:    # %bb1
 ; X64-PIC-NEXT:    leaq .LBB7_3(%rip), %rdi
 ; X64-PIC-NEXT:    cmpq %rdi, %rsi
 ; X64-PIC-NEXT:    cmovneq %r10, %r9

 ; X64-PIC-NEXT:    retq
 ;
 ; X64-RETPOLINE-LABEL: test_switch_jumptable_fallthrough:
 ; X64-RETPOLINE:       # %bb.0: # %entry
 ; X64-RETPOLINE-NEXT:    movq %rsp, %r9
 ; X64-RETPOLINE-NEXT:    movq $-1, %r10
 ; X64-RETPOLINE-NEXT:    sarq $63, %r9
 ; X64-RETPOLINE-NEXT:    xorl %eax, %eax
-; X64-RETPOLINE-NEXT:    cmpl $1, %edi
-; X64-RETPOLINE-NEXT:    jg .LBB8_5
+; X64-RETPOLINE-NEXT:    cmpl $2, %edi
+; X64-RETPOLINE-NEXT:    jge .LBB8_5
 ; X64-RETPOLINE-NEXT:  # %bb.1: # %entry
-; X64-RETPOLINE-NEXT:    cmovgq %r10, %r9
+; X64-RETPOLINE-NEXT:    cmovgeq %r10, %r9
 ; X64-RETPOLINE-NEXT:    testl %edi, %edi
 ; X64-RETPOLINE-NEXT:    je .LBB8_2
 ; X64-RETPOLINE-NEXT:  # %bb.3: # %entry
 ; X64-RETPOLINE-NEXT:    cmoveq %r10, %r9
 ; X64-RETPOLINE-NEXT:    cmpl $1, %edi
 ; X64-RETPOLINE-NEXT:    jne .LBB8_8
 ; X64-RETPOLINE-NEXT:  # %bb.4:
 ; X64-RETPOLINE-NEXT:    cmovneq %r10, %r9
 ; X64-RETPOLINE-NEXT:    jmp .LBB8_10
 ; X64-RETPOLINE-NEXT:  .LBB8_5: # %entry
-; X64-RETPOLINE-NEXT:    cmovleq %r10, %r9
-; X64-RETPOLINE-NEXT:    cmpl $2, %edi
+; X64-RETPOLINE-NEXT:    cmovlq %r10, %r9
 ; X64-RETPOLINE-NEXT:    je .LBB8_6
 ; X64-RETPOLINE-NEXT:  # %bb.7: # %entry
 ; X64-RETPOLINE-NEXT:    cmoveq %r10, %r9
 ; X64-RETPOLINE-NEXT:    cmpl $3, %edi
 ; X64-RETPOLINE-NEXT:    jne .LBB8_8
 ; X64-RETPOLINE-NEXT:  # %bb.13:
 ; X64-RETPOLINE-NEXT:    cmovneq %r10, %r9
 ; X64-RETPOLINE-NEXT:    jmp .LBB8_12

llvm/test/CodeGen/X86/switch-bt.ll

 }
 
 declare void @foo(i32)
 
 ; Don't zero extend the test operands to pointer type if it can be avoided.
 ; rdar://8781238
 define void @test2(i32 %x) nounwind ssp {
 ; CHECK-LABEL: test2:
-; CHECK: cmpl $6
-; CHECK: ja
+; CHECK: cmpl $7
+; CHECK: jae
 
 ; CHECK-NEXT: movl $91
 ; CHECK-NOT: movl
 ; CHECK-NEXT: btl
 ; CHECK-NEXT: jae
 entry:
   switch i32 %x, label %if.end [
     i32 6, label %if.then

 if.end:                                           ; preds = %entry
   ret void
 }
 
 declare void @bar()
 
 define void @test3(i32 %x) nounwind {
 ; CHECK-LABEL: test3:
-; CHECK: cmpl $5
-; CHECK: ja
+; CHECK: cmpl $6
+; CHECK: jae
 ; CHECK: cmpl $4
 ; CHECK: je
   switch i32 %x, label %if.end [
     i32 0, label %if.then
     i32 1, label %if.then
     i32 2, label %if.then
     i32 3, label %if.then
     i32 5, label %if.then

 sw.default:
   store i32 7, i32* %y
   br label %sw.epilog
 sw.epilog:
   ret void
 
 ; The balanced binary switch here would start with a comparison against 39, but
 ; it is currently starting with 29 because of the density-sum heuristic.
-; CHECK: cmpl $39
-; CHECK: jg
+; CHECK: cmpl $40
+; CHECK: jge
 ; CHECK: cmpl $10
 ; CHECK: je
 ; CHECK: cmpl $20
 ; CHECK: je
 ; CHECK: cmpl $30
 ; CHECK: jne
-; CHECK: cmpl $40
-; CHECK: je
 ; CHECK: cmpl $50
 ; CHECK: je
 ; CHECK: cmpl $60
 ; CHECK: jne
 }
 
 
 ; Omit the range check when the default case is unreachable, see PR43129.

llvm/test/CodeGen/X86/switch-density.ll

 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 bb2: tail call void @g(i32 1) br label %return
 return: ret void
 
 ; Should pivot around 400 for two subtrees with two jump tables each.
 ; CHECK-LABEL: sparse
 ; CHECK-NOT: cmpl
-; CHECK: cmpl $399
+; CHECK: cmpl $400
 ; CHECK: cmpl $100
 ; CHECK: cmpl $300
-; CHECK: cmpl $400
 ; CHECK: cmpl $500
 }
 
 define void @med(i32 %x) {
 entry:
   switch i32 %x, label %return [
     i32 30, label %bb0
     i32 10, label %bb1
     i32 40, label %bb1
     i32 50, label %bb2
     i32 20, label %bb3
   ]
 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 bb2: tail call void @g(i32 1) br label %return
 bb3: tail call void @g(i32 2) br label %return
 return: ret void
 
 ; Lowered as a jump table when sparse, and branches when dense.
 ; CHECK-LABEL: med
 ; SPARSE: addl $-10
-; SPARSE: cmpl $40
-; SPARSE: ja
+; SPARSE: cmpl $41
+; SPARSE: jae
 ; SPARSE: jmpq *.LJTI
 ; DENSE-NOT: cmpl
-; DENSE: cmpl $29
+; DENSE: cmpl $30
 ; DENSE-DAG: cmpl $10
 ; DENSE-DAG: cmpl $20
 ; DENSE-DAG: cmpl $30
 ; DENSE-DAG: cmpl $40
 ; DENSE-DAG: cmpl $50
 ; DENSE: retq
 }
   
 define void @dense(i32 %x) {
 entry:
   switch i32 %x, label %return [
     i32 12, label %bb0
     i32 4,  label %bb1
     i32 16, label %bb1
     i32 20, label %bb2
     i32 8,  label %bb3
   ]
 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 bb2: tail call void @g(i32 1) br label %return
 bb3: tail call void @g(i32 2) br label %return
 return: ret void
 
 ; Lowered as a jump table when sparse, and branches when dense.
 ; CHECK-LABEL: dense
 ; CHECK: addl $-4
-; CHECK: cmpl $16
-; CHECK: ja
+; CHECK: cmpl $17
+; CHECK: jae
 ; CHECK: jmpq *.LJTI
 }
 
 define void @dense_optsize(i32 %x) optsize {
 entry:
   switch i32 %x, label %return [
     i32 12, label %bb0
     i32 4,  label %bb1
     i32 16, label %bb1
     i32 20, label %bb2
     i32 8,  label %bb3
   ]
 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 bb2: tail call void @g(i32 1) br label %return
 bb3: tail call void @g(i32 2) br label %return
 return: ret void
 
 ; Lowered as branches.
 ; CHECK-LABEL: dense_optsize
-; CHECK: cmpl $11
+; CHECK: cmpl $12
 ; CHECK: cmpl $20
 ; CHECK: cmpl $16
 ; CHECK: cmpl $12
 ; CHECK: cmpl $4
 ; CHECK: cmpl $8
 ; CHECK: retq
 }
 

 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 bb2: tail call void @g(i32 1) br label %return
 bb3: tail call void @g(i32 2) br label %return
 return: ret void
 
 ; Lowered as branches.
 ; CHECK-LABEL: dense_pgso
-; CHECK: cmpl $11
+; CHECK: cmpl $12
 ; CHECK: cmpl $20
 ; CHECK: cmpl $16
 ; CHECK: cmpl $12
 ; CHECK: cmpl $4
 ; CHECK: cmpl $8
 ; CHECK: retq
 }
 

llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll

 
 ; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x5999999a), %[[PEELED_SWITCH_LABEL:.*]](0x26666666)
 ; CHECK:    %[[VAL:[0-9]+]]:gr32 = COPY $edi
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18568, implicit-def $eflags
 ; CHECK:    JCC_1 %[[PEELED_CASE_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[PEELED_SWITCH_LABEL]]
 ; CHECK:  [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[BB1_LABEL:.*]](0x0206d3a0), %[[BB2_LABEL:.*]](0x7df92c60)
-; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18311, implicit-def $eflags
-; CHECK:    JCC_1 %[[BB2_LABEL]], 15, implicit $eflags
+; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18312, implicit-def $eflags
+; CHECK:    JCC_1 %[[BB2_LABEL]], 13, implicit $eflags
 ; CHECK:    JMP_1 %[[BB1_LABEL]]
 ; CHECK:  [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE2_LABEL:.*]](0x35e50d5b), %[[BB3_LABEL:.*]](0x4a1af2a5)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], -8826, implicit-def $eflags
 ; CHECK:    JCC_1 %[[CASE2_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[BB3_LABEL]]
 ; CHECK:  [[BB3_LABEL]]
 ; CHECK:    successors: %[[CASE5_LABEL:.*]](0x45d173c8), %[[BB4_LABEL:.*]](0x3a2e8c38)

 ; CHECK:   successors: %[[PEELED_CASE_LABEL:.*]](0x59999999), %[[PEELED_SWITCH_LABEL:.*]](0x26666667)
 ; CHECK:   %[[VAL:[0-9]+]]:gr32 = COPY $edi
 ; CHECK:   %{{[0-9]+}}:gr32 = ADD32ri8 %{{[0-9]+}}, -85, implicit-def dead $eflags
 ; CHECK:   %{{[0-9]+}}:gr32 = SUB32ri8 %{{[0-9]+}}, 2, implicit-def $eflags
 ; CHECK:   JCC_1 %[[PEELED_CASE_LABEL]], 2, implicit $eflags
 ; CHECK:   JMP_1 %[[PEELED_SWITCH_LABEL]]
 ; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[BB1_LABEL:.*]](0x0088888a), %[[BB2_LABEL:.*]](0x7f777776)
-; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 4, implicit-def $eflags
-; CHECK:    JCC_1 %[[BB2_LABEL]], 15, implicit $eflags
+; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 5, implicit-def $eflags
+; CHECK:    JCC_1 %[[BB2_LABEL]], 13, implicit $eflags
 ; CHECK:    JMP_1 %[[BB1_LABEL]]
 ; CHECK:  [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE4_LABEL:.*]](0x7f775a4f), %[[BB3_LABEL:.*]](0x0088a5b1)
 ; CHECK:    %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 1, implicit-def $eflags
 ; CHECK:    JCC_1 %[[CASE4_LABEL]], 4, implicit $eflags
 ; CHECK:    JMP_1 %[[BB3_LABEL]]
 ; CHECK:  [[BB3_LABEL]].{{[a-zA-Z0-9.]+}}:
 ; CHECK:    successors: %[[CASE1_LABEL:.*]](0x66666666), %[[DEFAULT_BB_LABEL:.*]](0x1999999a)

llvm/test/CodeGen/X86/switch-zextload.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s | FileCheck %s
 
 ; Do zextload, instead of a load and a separate zext.
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin9.6"
   %struct.move_s = type { i32, i32, i32, i32, i32, i32 }
   %struct.node_t = type { i8, i8, i8, i8, i32, i32, %struct.node_t**, %struct.node_t*, %struct.move_s }
 
 define fastcc void @set_proof_and_disproof_numbers(%struct.node_t* nocapture %node) nounwind {
 ; CHECK-LABEL: set_proof_and_disproof_numbers:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    movzbl 0, %eax
-; CHECK-NEXT:    cmpl $3, %eax
-; CHECK-NEXT:    ja LBB0_3
+; CHECK-NEXT:    cmpl $4, %eax
+; CHECK-NEXT:    jae LBB0_3
 ; CHECK-NEXT:  ## %bb.1: ## %entry
 ; CHECK-NEXT:    jmpl *LJTI0_0(,%eax,4)
 ; CHECK-NEXT:  LBB0_3: ## %return
 ; CHECK-NEXT:    retl
 ; CHECK-NEXT:  LBB0_2: ## %bb31
 ; CHECK-NEXT:    ud2
 entry:
   %0 = load i8, i8* null, align 1    ; <i8> [#uses=1]

llvm/test/CodeGen/X86/switch.ll

 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 bb2: tail call void @g(i32 1) br label %return
 return: ret void
 
 ; Lowered as a jump table, both with and without optimization.
 ; CHECK-LABEL: basic
 ; CHECK: decl
-; CHECK: cmpl $4
-; CHECK: ja
+; CHECK: cmpl $5
+; CHECK: jae
 ; CHECK: jmpq *.LJTI
 ; NOOPT-LABEL: basic
 ; NOOPT: decl
-; NOOPT: subl $4
-; NOOPT: ja
+; NOOPT: subl $5
+; NOOPT: jae
 ; NOOPT: movq .LJTI
 ; NOOPT: jmpq
 }
 
 ; Should never be lowered as a jump table because of the attribute
 define void @basic_nojumptable(i32 %x) "no-jump-tables"="true" {
 entry:
   switch i32 %x, label %return [

 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 bb2: tail call void @g(i32 1) br label %return
 return: ret void
 
 ; Lowered as a jump table, both with and without optimization.
 ; CHECK-LABEL: basic_nojumptable_false
 ; CHECK: decl
-; CHECK: cmpl $4
-; CHECK: ja
+; CHECK: cmpl $5
+; CHECK: jae
 ; CHECK: jmpq *.LJTI
 }
 
 
 define void @simple_ranges(i32 %x) {
 entry:
   switch i32 %x, label %return [
     i32 0, label %bb0

 
 
 
 ; Should be lowered to two range checks.
 ; CHECK-LABEL: simple_ranges
 ; CHECK: leal -100
 ; CHECK: cmpl $4
 ; CHECK: jb
-; CHECK: cmpl $3
-; CHECK: ja
+; CHECK: cmpl $4
+; CHECK: jae
 
 ; We do this even at -O0, because it's cheap and makes codegen faster.
 ; NOOPT-LABEL: simple_ranges
 ; NOOPT: subl $4
 ; NOOPT: jb
 ; NOOPT: addl $-100
 ; NOOPT: subl $4
 ; NOOPT: jb

 bb2: tail call void @g(i32 2) br label %return
 bb3: tail call void @g(i32 3) br label %return
 bb4: tail call void @g(i32 4) br label %return
 return: ret void
 
 ; Cases 0-5 could be lowered with two bit tests,
 ; but with 6-8, the whole switch is suitable for a jump table.
 ; CHECK-LABEL: jt_is_better
-; CHECK: cmpl $8
-; CHECK: ja
+; CHECK: cmpl $9
+; CHECK: jae
 ; CHECK: jmpq *.LJTI
 }
 
 
 define void @bt_is_better(i32 %x) {
 entry:
   switch i32 %x, label %return [
     i32 0, label %bb0
entry:
   ]
 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 return: ret void
 
 ; Should pivot around 400 for two subtrees of equal size.
 ; CHECK-LABEL: optimal_pivot1
 ; CHECK-NOT: cmpl
-; CHECK: cmpl $399
+; CHECK: cmpl $400
 }
 
 
 define void @optimal_pivot2(i32 %x) {
 entry:
   switch i32 %x, label %return [
     i32 100, label %bb0   i32 101, label %bb1   i32 102, label %bb2   i32 103, label %bb3
     i32 200, label %bb0   i32 201, label %bb1   i32 202, label %bb2   i32 203, label %bb3
     i32 300, label %bb0   i32 301, label %bb1   i32 302, label %bb2   i32 303, label %bb3
     i32 400, label %bb0   i32 401, label %bb1   i32 402, label %bb2   i32 403, label %bb3
 
   ]
 bb0: tail call void @g(i32 0) br label %return
 bb1: tail call void @g(i32 1) br label %return
 bb2: tail call void @g(i32 2) br label %return
 bb3: tail call void @g(i32 3) br label %return
 return: ret void
 
 ; Should pivot around 300 for two subtrees with two jump tables each.
 ; CHECK-LABEL: optimal_pivot2
 ; CHECK-NOT: cmpl
-; CHECK: cmpl $299
+; CHECK: cmpl $300
 ; CHECK: jmpq *.LJTI
 ; CHECK: jmpq *.LJTI
 ; CHECK: jmpq *.LJTI
 ; CHECK: jmpq *.LJTI
 }
 
 
 define void @optimal_jump_table1(i32 %x) {

 bb4: tail call void @g(i32 4) br label %return
 bb5: tail call void @g(i32 5) br label %return
 return: ret void
 
 ; Splitting in the largest gap (between 6 and 12) would yield suboptimal result.
 ; Expecting a jump table from 5 to 15.
 ; CHECK-LABEL: optimal_jump_table1
 ; CHECK: leal -5
-; CHECK: cmpl $10
+; CHECK: cmpl $11
 ; CHECK: jmpq *.LJTI
 
 ; At -O0, we don't build jump tables for only parts of a switch.
 ; NOOPT-LABEL: optimal_jump_table1
 ; NOOPT: testl %edi, %edi
 ; NOOPT: je
 ; NOOPT: subl $5, [[REG:%e[abcd][xi]]]
 ; NOOPT: je

 bb4: tail call void @g(i32 4) br label %return
 bb5: tail call void @g(i32 5) br label %return
 return: ret void
 
 ; Partitioning the cases to the minimum number of dense sets is not good enough.
 ; This can be partitioned as {0,1,2,9},{14,15} or {0,1,2},{9,14,15}. The former
 ; should be preferred. Expecting a table from 0-9.
 ; CHECK-LABEL: optimal_jump_table2
-; CHECK: cmpl $9
+; CHECK: cmpl $10
 ; CHECK: jmpq *.LJTI
 }
 
 
 define void @optimal_jump_table3(i32 %x) {
 entry:
   switch i32 %x, label %return [
     i32 1,  label %bb0

 bb4: tail call void @g(i32 4) br label %return
 return: ret void
 
 ; Splitting to maximize left-right density sum and gap size would split this
 ; between 3 and 10, and then between 20 and 25. It's better to build a table
 ; from 1-20.
 ; CHECK-LABEL: optimal_jump_table3
 ; CHECK: leal -1
-; CHECK: cmpl $19
+; CHECK: cmpl $20
 ; CHECK: jmpq *.LJTI
 }
 
 %struct.S = type { %struct.S*, i32 }
 define void @phi_node_trouble(%struct.S* %s) {
 entry:
   br label %header
 header:

 bb3: tail call void @g(i32 3) br label %return
 bb4: tail call void @g(i32 4) br label %return
 bb5: tail call void @g(i32 5) br label %return
 return: ret void
 
 ; Make sure to pick a pivot in the middle also with zero-weight cases.
 ; CHECK-LABEL: zero_weight_tree
 ; CHECK-NOT: cmpl
-; CHECK: cmpl $29
+; CHECK: cmpl $30
 }
 
 !3 = !{!"branch_weights", i32 1, i32 10, i32 0, i32 0, i32 0, i32 0, i32 10}
 
 
 define void @left_leaning_weight_balanced_tree(i32 %x) {
 entry:
   switch i32 %x, label %return [

 
 ; Without branch probabilities, the pivot would be 40, since that would yield
 ; equal-sized sub-trees. When taking weights into account, case 70 becomes the
 ; pivot. Since there is room for 3 cases in a leaf, cases 50 and 60 are also
 ; included in the right-hand side because that doesn't reduce their rank.
 
 ; CHECK-LABEL: left_leaning_weight_balanced_tree
 ; CHECK-NOT: cmpl
-; CHECK: cmpl $49
+; CHECK: cmpl $50
 }
 
 !4 = !{!"branch_weights", i32 1, i32 10, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1000}
 
 
 define void @left_leaning_weight_balanced_tree2(i32 %x) {
 entry:
   switch i32 %x, label %return [

 return: ret void
 
 ; Same as the previous test, except case 50 has higher rank to the left than it
 ; would have on the right. Case 60 would have the same rank on both sides, so is
 ; moved into the leaf.
 
 ; CHECK-LABEL: left_leaning_weight_balanced_tree2
 ; CHECK-NOT: cmpl
-; CHECK: cmpl $59
+; CHECK: cmpl $60
 }
 
 !5 = !{!"branch_weights", i32 1, i32 10, i32 1, i32 1, i32 1, i32 1, i32 90, i32 70, i32 1000}
 
 
 define void @right_leaning_weight_balanced_tree(i32 %x) {
 entry:
   switch i32 %x, label %return [

 bb6: tail call void @g(i32 6) br label %return
 bb7: tail call void @g(i32 7) br label %return
 return: ret void
 
 ; Analogous to left_leaning_weight_balanced_tree.
 
 ; CHECK-LABEL: right_leaning_weight_balanced_tree
 ; CHECK-NOT: cmpl
-; CHECK: cmpl $19
+; CHECK: cmpl $20
 }
 
 !6 = !{!"branch_weights", i32 1, i32 1000, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 10}
 
 
 define void @jump_table_affects_balance(i32 %x) {
 entry:
   switch i32 %x, label %return [

 bb3: tail call void @g(i32 3) br label %return
 return: ret void
 
 ; CHECK-LABEL: jump_table_affects_balance
 ; If the tree were balanced based on number of clusters, {0-3,100} would go on
 ; the left and {200,300} on the right. However, the jump table weights as much
 ; as its components, so 100 is selected as the pivot.
 ; CHECK-NOT: cmpl
-; CHECK: cmpl $99
+; CHECK: cmpl $100
 }
 
 
 define void @pr23738(i4 %x) {
 entry:
   switch i4 %x, label %bb0 [
     i4 0, label %bb1
     i4 1, label %bb1

llvm/test/CodeGen/X86/tail-dup-multiple-latch-loop.ll

 ; CHECK-NEXT:    jmp .LBB1_1
 ; CHECK-NEXT:  .LBB1_7: # in Loop: Header=BB1_1 Depth=1
 ; CHECK-NEXT:    addl $7, %eax
 ; CHECK-NEXT:    incq %rdi
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movzbl (%rdi), %ecx
 ; CHECK-NEXT:    decb %cl
-; CHECK-NEXT:    cmpb $5, %cl
-; CHECK-NEXT:    ja .LBB1_9
+; CHECK-NEXT:    cmpb $6, %cl
+; CHECK-NEXT:    jae .LBB1_9
 ; CHECK-NEXT:  # %bb.2: # in Loop: Header=BB1_1 Depth=1
 ; CHECK-NEXT:    movzbl %cl, %ecx
 ; CHECK-NEXT:    jmpq *.LJTI1_0(,%rcx,8)
 ; CHECK-NEXT:  .LBB1_3: # in Loop: Header=BB1_1 Depth=1
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:    incq %rdi
 ; CHECK-NEXT:    jmp .LBB1_1
 ; CHECK-NEXT:  .LBB1_4: # in Loop: Header=BB1_1 Depth=1

llvm/test/CodeGen/X86/tail-merge-unreachable.ll

sw.bb2:
   unreachable
 end:
   %p = phi i32 [ 1, %sw ], [ 0, %entry ]
   ret i32 %p
 
 ; CHECK-LABEL: tail_merge_unreachable:
 ; Range Check
 ; CHECK: addl $-96
-; CHECK: cmpl $5
-; CHECK: jbe [[JUMP_TABLE_BLOCK:[.][A-Za-z0-9_]+]]
+; CHECK: cmpl $6
+; CHECK: jb [[JUMP_TABLE_BLOCK:[.][A-Za-z0-9_]+]]
 ; CHECK: retq
 ; CHECK: [[JUMP_TABLE_BLOCK]]:
 ; CHECK: btl
 ; CHECK: jae [[UNREACHABLE_BLOCK:[.][A-Za-z0-9_]+]]
 ; CHECK: [[UNREACHABLE_BLOCK]]:
 ; CHECK: .Lfunc_end0
 }

llvm/test/CodeGen/X86/tail-threshold.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-pc-linux-gnu -tail-merge-threshold 2 < %s | FileCheck %s
 
 ; Test that we still do some merging if a block has more than
 ; tail-merge-threshold predecessors.
 
 declare void @bar()
 
 define void @foo(i32 %xxx) nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    pushq %rax
-; CHECK-NEXT:    cmpl $3, %edi
-; CHECK-NEXT:    ja .LBB0_4
+; CHECK-NEXT:    cmpl $4, %edi
+; CHECK-NEXT:    jae .LBB0_4
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    jmpq *.LJTI0_0(,%rax,8)
 ; CHECK-NEXT:  .LBB0_3: # %bb3
 ; CHECK-NEXT:    callq bar@PLT
 ; CHECK-NEXT:    popq %rax
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB0_4: # %bb4

llvm/test/CodeGen/X86/twoaddr-lea.ll

 ; assert/crash from http://llvm.org/PR28301
 define void @ham() {
 ; CHECK-LABEL: ham:
 ; CHECK:       ## %bb.0: ## %bb
 ; CHECK-NEXT:    xorl %r8d, %r8d
 ; CHECK-NEXT:    movq _global@GOTPCREL(%rip), %rdx
 ; CHECK-NEXT:    movq _global2@GOTPCREL(%rip), %rsi
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    cmpl $10, %eax
-; CHECK-NEXT:    jle LBB3_2
+; CHECK-NEXT:    cmpl $11, %eax
+; CHECK-NEXT:    jl LBB3_2
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB3_6: ## %bb2
 ; CHECK-NEXT:    ## =>This Loop Header: Depth=1
 ; CHECK-NEXT:    ## Child Loop BB3_7 Depth 2
 ; CHECK-NEXT:    movl (%rdx), %edi
 ; CHECK-NEXT:    leal (%rdi,%rax), %ecx
 ; CHECK-NEXT:    movslq %ecx, %rcx
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB3_7: ## %bb6
 ; CHECK-NEXT:    ## Parent Loop BB3_6 Depth=1
 ; CHECK-NEXT:    ## => This Inner Loop Header: Depth=2
 ; CHECK-NEXT:    movq %rax, (%rsi)
 ; CHECK-NEXT:    movq %rcx, (%rsi)
 ; CHECK-NEXT:    movl %edi, (%rdx)
 ; CHECK-NEXT:    testb %r8b, %r8b
 ; CHECK-NEXT:    jne LBB3_7
 ; CHECK-NEXT:  ## %bb.8: ## %bb9
 ; CHECK-NEXT:    ## in Loop: Header=BB3_6 Depth=1
 ; CHECK-NEXT:    addq $4, %rax
-; CHECK-NEXT:    cmpl $10, %eax
-; CHECK-NEXT:    jg LBB3_6
+; CHECK-NEXT:    cmpl $11, %eax
+; CHECK-NEXT:    jge LBB3_6
 ; CHECK-NEXT:  LBB3_2: ## %bb3.preheader
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB3_3: ## %bb3
 ; CHECK-NEXT:    ## =>This Loop Header: Depth=1
 ; CHECK-NEXT:    ## Child Loop BB3_4 Depth 2
 ; CHECK-NEXT:    movq %rcx, %rdx
 ; CHECK-NEXT:    addq $4, %rcx

llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll

 ;   return a * b;
 ; }
 ; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1
 ; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS.
 
 target datalayout = "e-m:e-i64:64-n32:64"
 
 define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
 ; DEFAULT-LABEL: ll_a_op_b__2:
 ; DEFAULT:       # %bb.0: # %entry
 ; DEFAULT-NEXT:    movq %rsi, %rcx
 ; DEFAULT-NEXT:    movq %rdi, %rax
 ; DEFAULT-NEXT:    shlq %cl, %rax
-; DEFAULT-NEXT:    cmpq $-2, %rax
-; DEFAULT-NEXT:    jle .LBB0_1
+; DEFAULT-NEXT:    cmpq $-1, %rax
+; DEFAULT-NEXT:    jl .LBB0_1
 ; DEFAULT-NEXT:  # %bb.2: # %return
 ; DEFAULT-NEXT:    movq %rcx, %rax
 ; DEFAULT-NEXT:    retq
 ; DEFAULT-NEXT:  .LBB0_1: # %if.end
+; DEFAULT-NEXT:    cmpq $-2, %rax
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmoveq %rcx, %rax
 ; DEFAULT-NEXT:    imulq %rdi, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: ll_a_op_b__2:
 ; EQ2ICMP:       # %bb.0: # %entry
 ; EQ2ICMP-NEXT:    movq %rsi, %rax
 ; EQ2ICMP-NEXT:    movq %rdi, %rdx
 ; EQ2ICMP-NEXT:    movl %eax, %ecx
 ; EQ2ICMP-NEXT:    shlq %cl, %rdx
-; EQ2ICMP-NEXT:    cmpq $-2, %rdx
-; EQ2ICMP-NEXT:    jg .LBB0_2
+; EQ2ICMP-NEXT:    cmpq $-1, %rdx
+; EQ2ICMP-NEXT:    jge .LBB0_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    cmpq $-2, %rdx
 ; EQ2ICMP-NEXT:    movl $1, %ecx
 ; EQ2ICMP-NEXT:    cmovlq %rcx, %rax
 ; EQ2ICMP-NEXT:    imulq %rdi, %rax
 ; EQ2ICMP-NEXT:  .LBB0_2: # %return
 ; EQ2ICMP-NEXT:    retq
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -2

 }
 
 define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
 ; DEFAULT-LABEL: ll_a_op_b_1:
 ; DEFAULT:       # %bb.0: # %entry
 ; DEFAULT-NEXT:    movq %rsi, %rcx
 ; DEFAULT-NEXT:    movq %rdi, %rax
 ; DEFAULT-NEXT:    shlq %cl, %rax
-; DEFAULT-NEXT:    cmpq $1, %rax
-; DEFAULT-NEXT:    jle .LBB3_1
+; DEFAULT-NEXT:    cmpq $2, %rax
+; DEFAULT-NEXT:    jl .LBB3_1
 ; DEFAULT-NEXT:  # %bb.2: # %return
 ; DEFAULT-NEXT:    movq %rcx, %rax
 ; DEFAULT-NEXT:    retq
 ; DEFAULT-NEXT:  .LBB3_1: # %if.end
+; DEFAULT-NEXT:    cmpq $1, %rax
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmoveq %rcx, %rax
 ; DEFAULT-NEXT:    imulq %rdi, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: ll_a_op_b_1:
 ; EQ2ICMP:       # %bb.0: # %entry
 ; EQ2ICMP-NEXT:    movq %rsi, %rax
 ; EQ2ICMP-NEXT:    movq %rdi, %rdx
 ; EQ2ICMP-NEXT:    movl %eax, %ecx
 ; EQ2ICMP-NEXT:    shlq %cl, %rdx
-; EQ2ICMP-NEXT:    cmpq $1, %rdx
-; EQ2ICMP-NEXT:    jg .LBB3_2
+; EQ2ICMP-NEXT:    cmpq $2, %rdx
+; EQ2ICMP-NEXT:    jge .LBB3_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    testq %rdx, %rdx
 ; EQ2ICMP-NEXT:    movl $1, %ecx
-; EQ2ICMP-NEXT:    cmovlq %rcx, %rax
+; EQ2ICMP-NEXT:    cmovleq %rcx, %rax
 ; EQ2ICMP-NEXT:    imulq %rdi, %rax
 ; EQ2ICMP-NEXT:  .LBB3_2: # %return
 ; EQ2ICMP-NEXT:    retq
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, 1
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
 ; DEFAULT-LABEL: ll_a_op_b_2:
 ; DEFAULT:       # %bb.0: # %entry
 ; DEFAULT-NEXT:    movq %rsi, %rcx
 ; DEFAULT-NEXT:    movq %rdi, %rax
 ; DEFAULT-NEXT:    shlq %cl, %rax
-; DEFAULT-NEXT:    cmpq $2, %rax
-; DEFAULT-NEXT:    jle .LBB4_1
+; DEFAULT-NEXT:    cmpq $3, %rax
+; DEFAULT-NEXT:    jl .LBB4_1
 ; DEFAULT-NEXT:  # %bb.2: # %return
 ; DEFAULT-NEXT:    movq %rcx, %rax
 ; DEFAULT-NEXT:    retq
 ; DEFAULT-NEXT:  .LBB4_1: # %if.end
+; DEFAULT-NEXT:    cmpq $2, %rax
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmoveq %rcx, %rax
 ; DEFAULT-NEXT:    imulq %rdi, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: ll_a_op_b_2:
 ; EQ2ICMP:       # %bb.0: # %entry
 ; EQ2ICMP-NEXT:    movq %rsi, %rax
 ; EQ2ICMP-NEXT:    movq %rdi, %rdx
 ; EQ2ICMP-NEXT:    movl %eax, %ecx
 ; EQ2ICMP-NEXT:    shlq %cl, %rdx
-; EQ2ICMP-NEXT:    cmpq $2, %rdx
-; EQ2ICMP-NEXT:    jg .LBB4_2
+; EQ2ICMP-NEXT:    cmpq $3, %rdx
+; EQ2ICMP-NEXT:    jge .LBB4_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    cmpq $2, %rdx
 ; EQ2ICMP-NEXT:    movl $1, %ecx
 ; EQ2ICMP-NEXT:    cmovlq %rcx, %rax
 ; EQ2ICMP-NEXT:    imulq %rdi, %rax
 ; EQ2ICMP-NEXT:  .LBB4_2: # %return
 ; EQ2ICMP-NEXT:    retq
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, 2
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a__2(i64 %a, i64 %b) {
 ; DEFAULT-LABEL: ll_a__2:
 ; DEFAULT:       # %bb.0: # %entry
-; DEFAULT-NEXT:    cmpq $-2, %rdi
-; DEFAULT-NEXT:    jle .LBB5_1
+; DEFAULT-NEXT:    cmpq $-1, %rdi
+; DEFAULT-NEXT:    jl .LBB5_1
 ; DEFAULT-NEXT:  # %bb.2: # %return
 ; DEFAULT-NEXT:    movq %rsi, %rax
 ; DEFAULT-NEXT:    retq
 ; DEFAULT-NEXT:  .LBB5_1: # %if.end
+; DEFAULT-NEXT:    cmpq $-2, %rdi
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmoveq %rsi, %rax
 ; DEFAULT-NEXT:    imulq %rdi, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: ll_a__2:
 ; EQ2ICMP:       # %bb.0: # %entry
 ; EQ2ICMP-NEXT:    movq %rsi, %rax
-; EQ2ICMP-NEXT:    cmpq $-2, %rdi
-; EQ2ICMP-NEXT:    jg .LBB5_2
+; EQ2ICMP-NEXT:    cmpq $-1, %rdi
+; EQ2ICMP-NEXT:    jge .LBB5_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    cmpq $-2, %rdi
 ; EQ2ICMP-NEXT:    movl $1, %ecx
 ; EQ2ICMP-NEXT:    cmovlq %rcx, %rax
 ; EQ2ICMP-NEXT:    imulq %rdi, %rax
 ; EQ2ICMP-NEXT:  .LBB5_2: # %return
 ; EQ2ICMP-NEXT:    retq
 entry:
   %cmp = icmp sgt i64 %a, -2
   br i1 %cmp, label %return, label %if.end

 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_1(i64 %a, i64 %b) {
 ; DEFAULT-LABEL: ll_a_1:
 ; DEFAULT:       # %bb.0: # %entry
-; DEFAULT-NEXT:    cmpq $1, %rdi
-; DEFAULT-NEXT:    jle .LBB8_1
+; DEFAULT-NEXT:    cmpq $2, %rdi
+; DEFAULT-NEXT:    jl .LBB8_1
 ; DEFAULT-NEXT:  # %bb.2: # %return
 ; DEFAULT-NEXT:    movq %rsi, %rax
 ; DEFAULT-NEXT:    retq
 ; DEFAULT-NEXT:  .LBB8_1: # %if.end
+; DEFAULT-NEXT:    cmpq $1, %rdi
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmoveq %rsi, %rax
 ; DEFAULT-NEXT:    imulq %rdi, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: ll_a_1:
 ; EQ2ICMP:       # %bb.0: # %entry
 ; EQ2ICMP-NEXT:    movq %rsi, %rax
-; EQ2ICMP-NEXT:    cmpq $1, %rdi
-; EQ2ICMP-NEXT:    jg .LBB8_2
+; EQ2ICMP-NEXT:    cmpq $2, %rdi
+; EQ2ICMP-NEXT:    jge .LBB8_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    testq %rdi, %rdi
 ; EQ2ICMP-NEXT:    movl $1, %ecx
-; EQ2ICMP-NEXT:    cmovlq %rcx, %rax
+; EQ2ICMP-NEXT:    cmovleq %rcx, %rax
 ; EQ2ICMP-NEXT:    imulq %rdi, %rax
 ; EQ2ICMP-NEXT:  .LBB8_2: # %return
 ; EQ2ICMP-NEXT:    retq
 entry:
   %cmp = icmp sgt i64 %a, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 1
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_2(i64 %a, i64 %b) {
 ; DEFAULT-LABEL: ll_a_2:
 ; DEFAULT:       # %bb.0: # %entry
-; DEFAULT-NEXT:    cmpq $2, %rdi
-; DEFAULT-NEXT:    jle .LBB9_1
+; DEFAULT-NEXT:    cmpq $3, %rdi
+; DEFAULT-NEXT:    jl .LBB9_1
 ; DEFAULT-NEXT:  # %bb.2: # %return
 ; DEFAULT-NEXT:    movq %rsi, %rax
 ; DEFAULT-NEXT:    retq
 ; DEFAULT-NEXT:  .LBB9_1: # %if.end
+; DEFAULT-NEXT:    cmpq $2, %rdi
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmoveq %rsi, %rax
 ; DEFAULT-NEXT:    imulq %rdi, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: ll_a_2:
 ; EQ2ICMP:       # %bb.0: # %entry
 ; EQ2ICMP-NEXT:    movq %rsi, %rax
-; EQ2ICMP-NEXT:    cmpq $2, %rdi
-; EQ2ICMP-NEXT:    jg .LBB9_2
+; EQ2ICMP-NEXT:    cmpq $3, %rdi
+; EQ2ICMP-NEXT:    jge .LBB9_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    cmpq $2, %rdi
 ; EQ2ICMP-NEXT:    movl $1, %ecx
 ; EQ2ICMP-NEXT:    cmovlq %rcx, %rax
 ; EQ2ICMP-NEXT:    imulq %rdi, %rax
 ; EQ2ICMP-NEXT:  .LBB9_2: # %return
 ; EQ2ICMP-NEXT:    retq
 entry:
   %cmp = icmp sgt i64 %a, 2
   br i1 %cmp, label %return, label %if.end

 }
 
 define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
 ; DEFAULT-LABEL: i_a_op_b__2:
 ; DEFAULT:       # %bb.0: # %entry
 ; DEFAULT-NEXT:    movl %esi, %ecx
 ; DEFAULT-NEXT:    movl %edi, %eax
 ; DEFAULT-NEXT:    shll %cl, %eax
-; DEFAULT-NEXT:    cmpl $-2, %eax
-; DEFAULT-NEXT:    jg .LBB10_2
+; DEFAULT-NEXT:    cmpl $-1, %eax
+; DEFAULT-NEXT:    jge .LBB10_2
 ; DEFAULT-NEXT:  # %bb.1: # %if.end
+; DEFAULT-NEXT:    cmpl $-2, %eax
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmovel %ecx, %eax
 ; DEFAULT-NEXT:    imull %edi, %eax
 ; DEFAULT-NEXT:    movl %eax, %ecx
 ; DEFAULT-NEXT:  .LBB10_2: # %return
 ; DEFAULT-NEXT:    movslq %ecx, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: i_a_op_b__2:
 ; EQ2ICMP:       # %bb.0: # %entry
 ; EQ2ICMP-NEXT:    movl %esi, %ecx
 ; EQ2ICMP-NEXT:    movl %edi, %eax
 ; EQ2ICMP-NEXT:    shll %cl, %eax
-; EQ2ICMP-NEXT:    cmpl $-2, %eax
-; EQ2ICMP-NEXT:    jg .LBB10_2
+; EQ2ICMP-NEXT:    cmpl $-1, %eax
+; EQ2ICMP-NEXT:    jge .LBB10_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    cmpl $-2, %eax
 ; EQ2ICMP-NEXT:    movl $1, %eax
 ; EQ2ICMP-NEXT:    cmovll %eax, %ecx
 ; EQ2ICMP-NEXT:    imull %edi, %ecx
 ; EQ2ICMP-NEXT:  .LBB10_2: # %return
 ; EQ2ICMP-NEXT:    movslq %ecx, %rax
 ; EQ2ICMP-NEXT:    retq
 entry:
   %shl = shl i32 %a, %b

 }
 
 define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
 ; DEFAULT-LABEL: i_a_op_b_1:
 ; DEFAULT:       # %bb.0: # %entry
 ; DEFAULT-NEXT:    movl %esi, %ecx
 ; DEFAULT-NEXT:    movl %edi, %eax
 ; DEFAULT-NEXT:    shll %cl, %eax
-; DEFAULT-NEXT:    cmpl $1, %eax
-; DEFAULT-NEXT:    jg .LBB13_2
+; DEFAULT-NEXT:    cmpl $2, %eax
+; DEFAULT-NEXT:    jge .LBB13_2
 ; DEFAULT-NEXT:  # %bb.1: # %if.end
+; DEFAULT-NEXT:    cmpl $1, %eax
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmovel %ecx, %eax
 ; DEFAULT-NEXT:    imull %edi, %eax
 ; DEFAULT-NEXT:    movl %eax, %ecx
 ; DEFAULT-NEXT:  .LBB13_2: # %return
 ; DEFAULT-NEXT:    movslq %ecx, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: i_a_op_b_1:
 ; EQ2ICMP:       # %bb.0: # %entry
 ; EQ2ICMP-NEXT:    movl %esi, %ecx
 ; EQ2ICMP-NEXT:    movl %edi, %eax
 ; EQ2ICMP-NEXT:    shll %cl, %eax
-; EQ2ICMP-NEXT:    cmpl $1, %eax
-; EQ2ICMP-NEXT:    jg .LBB13_2
+; EQ2ICMP-NEXT:    cmpl $2, %eax
+; EQ2ICMP-NEXT:    jge .LBB13_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    testl %eax, %eax
 ; EQ2ICMP-NEXT:    movl $1, %eax
-; EQ2ICMP-NEXT:    cmovll %eax, %ecx
+; EQ2ICMP-NEXT:    cmovlel %eax, %ecx
 ; EQ2ICMP-NEXT:    imull %edi, %ecx
 ; EQ2ICMP-NEXT:  .LBB13_2: # %return
 ; EQ2ICMP-NEXT:    movslq %ecx, %rax
 ; EQ2ICMP-NEXT:    retq
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 1
   br i1 %cmp, label %return, label %if.end

 }
 
 define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
 ; DEFAULT-LABEL: i_a_op_b_2:
 ; DEFAULT:       # %bb.0: # %entry
 ; DEFAULT-NEXT:    movl %esi, %ecx
 ; DEFAULT-NEXT:    movl %edi, %eax
 ; DEFAULT-NEXT:    shll %cl, %eax
-; DEFAULT-NEXT:    cmpl $2, %eax
-; DEFAULT-NEXT:    jg .LBB14_2
+; DEFAULT-NEXT:    cmpl $3, %eax
+; DEFAULT-NEXT:    jge .LBB14_2
 ; DEFAULT-NEXT:  # %bb.1: # %if.end
+; DEFAULT-NEXT:    cmpl $2, %eax
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmovel %ecx, %eax
 ; DEFAULT-NEXT:    imull %edi, %eax
 ; DEFAULT-NEXT:    movl %eax, %ecx
 ; DEFAULT-NEXT:  .LBB14_2: # %return
 ; DEFAULT-NEXT:    movslq %ecx, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: i_a_op_b_2:
 ; EQ2ICMP:       # %bb.0: # %entry
 ; EQ2ICMP-NEXT:    movl %esi, %ecx
 ; EQ2ICMP-NEXT:    movl %edi, %eax
 ; EQ2ICMP-NEXT:    shll %cl, %eax
-; EQ2ICMP-NEXT:    cmpl $2, %eax
-; EQ2ICMP-NEXT:    jg .LBB14_2
+; EQ2ICMP-NEXT:    cmpl $3, %eax
+; EQ2ICMP-NEXT:    jge .LBB14_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    cmpl $2, %eax
 ; EQ2ICMP-NEXT:    movl $1, %eax
 ; EQ2ICMP-NEXT:    cmovll %eax, %ecx
 ; EQ2ICMP-NEXT:    imull %edi, %ecx
 ; EQ2ICMP-NEXT:  .LBB14_2: # %return
 ; EQ2ICMP-NEXT:    movslq %ecx, %rax
 ; EQ2ICMP-NEXT:    retq
 entry:
   %shl = shl i32 %a, %b
return:                                           ; preds = %if.end, %entry
   %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
   %retval.0 = sext i32 %retval.0.in to i64
   ret i64 %retval.0
 }
 
 define i64 @i_a__2(i32 signext %a, i32 signext %b) {
 ; DEFAULT-LABEL: i_a__2:
 ; DEFAULT:       # %bb.0: # %entry
-; DEFAULT-NEXT:    cmpl $-2, %edi
-; DEFAULT-NEXT:    jg .LBB15_2
+; DEFAULT-NEXT:    cmpl $-1, %edi
+; DEFAULT-NEXT:    jge .LBB15_2
 ; DEFAULT-NEXT:  # %bb.1: # %if.end
+; DEFAULT-NEXT:    cmpl $-2, %edi
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmovel %esi, %eax
 ; DEFAULT-NEXT:    imull %edi, %eax
 ; DEFAULT-NEXT:    movl %eax, %esi
 ; DEFAULT-NEXT:  .LBB15_2: # %return
 ; DEFAULT-NEXT:    movslq %esi, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: i_a__2:
 ; EQ2ICMP:       # %bb.0: # %entry
-; EQ2ICMP-NEXT:    cmpl $-2, %edi
-; EQ2ICMP-NEXT:    jg .LBB15_2
+; EQ2ICMP-NEXT:    cmpl $-1, %edi
+; EQ2ICMP-NEXT:    jge .LBB15_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    cmpl $-2, %edi
 ; EQ2ICMP-NEXT:    movl $1, %eax
 ; EQ2ICMP-NEXT:    cmovll %eax, %esi
 ; EQ2ICMP-NEXT:    imull %edi, %esi
 ; EQ2ICMP-NEXT:  .LBB15_2: # %return
 ; EQ2ICMP-NEXT:    movslq %esi, %rax
 ; EQ2ICMP-NEXT:    retq
 entry:
   %cmp = icmp sgt i32 %a, -2
return:                                           ; preds = %if.end, %entry
   %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
   %retval.0 = sext i32 %retval.0.in to i64
   ret i64 %retval.0
 }
 
 define i64 @i_a_1(i32 signext %a, i32 signext %b) {
 ; DEFAULT-LABEL: i_a_1:
 ; DEFAULT:       # %bb.0: # %entry
-; DEFAULT-NEXT:    cmpl $1, %edi
-; DEFAULT-NEXT:    jg .LBB18_2
+; DEFAULT-NEXT:    cmpl $2, %edi
+; DEFAULT-NEXT:    jge .LBB18_2
 ; DEFAULT-NEXT:  # %bb.1: # %if.end
+; DEFAULT-NEXT:    cmpl $1, %edi
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmovel %esi, %eax
 ; DEFAULT-NEXT:    imull %edi, %eax
 ; DEFAULT-NEXT:    movl %eax, %esi
 ; DEFAULT-NEXT:  .LBB18_2: # %return
 ; DEFAULT-NEXT:    movslq %esi, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: i_a_1:
 ; EQ2ICMP:       # %bb.0: # %entry
-; EQ2ICMP-NEXT:    cmpl $1, %edi
-; EQ2ICMP-NEXT:    jg .LBB18_2
+; EQ2ICMP-NEXT:    cmpl $2, %edi
+; EQ2ICMP-NEXT:    jge .LBB18_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    testl %edi, %edi
 ; EQ2ICMP-NEXT:    movl $1, %eax
-; EQ2ICMP-NEXT:    cmovll %eax, %esi
+; EQ2ICMP-NEXT:    cmovlel %eax, %esi
 ; EQ2ICMP-NEXT:    imull %edi, %esi
 ; EQ2ICMP-NEXT:  .LBB18_2: # %return
 ; EQ2ICMP-NEXT:    movslq %esi, %rax
 ; EQ2ICMP-NEXT:    retq
 entry:
   %cmp = icmp sgt i32 %a, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i32 %a, 1
   %mul = select i1 %cmp1, i32 %b, i32 1
   %spec.select = mul nsw i32 %mul, %a
   br label %return
 
 return:                                           ; preds = %if.end, %entry
   %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ]
   %retval.0 = sext i32 %retval.0.in to i64
   ret i64 %retval.0
 }
 
 define i64 @i_a_2(i32 signext %a, i32 signext %b) {
 ; DEFAULT-LABEL: i_a_2:
 ; DEFAULT:       # %bb.0: # %entry
-; DEFAULT-NEXT:    cmpl $2, %edi
-; DEFAULT-NEXT:    jg .LBB19_2
+; DEFAULT-NEXT:    cmpl $3, %edi
+; DEFAULT-NEXT:    jge .LBB19_2
 ; DEFAULT-NEXT:  # %bb.1: # %if.end
+; DEFAULT-NEXT:    cmpl $2, %edi
 ; DEFAULT-NEXT:    movl $1, %eax
 ; DEFAULT-NEXT:    cmovel %esi, %eax
 ; DEFAULT-NEXT:    imull %edi, %eax
 ; DEFAULT-NEXT:    movl %eax, %esi
 ; DEFAULT-NEXT:  .LBB19_2: # %return
 ; DEFAULT-NEXT:    movslq %esi, %rax
 ; DEFAULT-NEXT:    retq
 ;
 ; EQ2ICMP-LABEL: i_a_2:
 ; EQ2ICMP:       # %bb.0: # %entry
-; EQ2ICMP-NEXT:    cmpl $2, %edi
-; EQ2ICMP-NEXT:    jg .LBB19_2
+; EQ2ICMP-NEXT:    cmpl $3, %edi
+; EQ2ICMP-NEXT:    jge .LBB19_2
 ; EQ2ICMP-NEXT:  # %bb.1: # %if.end
+; EQ2ICMP-NEXT:    cmpl $2, %edi
 ; EQ2ICMP-NEXT:    movl $1, %eax
 ; EQ2ICMP-NEXT:    cmovll %eax, %esi
 ; EQ2ICMP-NEXT:    imull %edi, %esi
 ; EQ2ICMP-NEXT:  .LBB19_2: # %return
 ; EQ2ICMP-NEXT:    movslq %esi, %rax
 ; EQ2ICMP-NEXT:    retq
 entry:
   %cmp = icmp sgt i32 %a, 2

llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll

 define void @vector_variable_shift_left_loop(i32* nocapture %arr, i8* nocapture readonly %control, i32 %count, i32 %amt0, i32 %amt1) nounwind {
 ; SSE-LABEL: vector_variable_shift_left_loop:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    testl %edx, %edx
 ; SSE-NEXT:    jle .LBB0_9
 ; SSE-NEXT:  # %bb.1: # %for.body.preheader
 ; SSE-NEXT:    movl %ecx, %r9d
 ; SSE-NEXT:    movl %edx, %eax
-; SSE-NEXT:    cmpl $31, %edx
-; SSE-NEXT:    ja .LBB0_3
+; SSE-NEXT:    cmpl $32, %edx
+; SSE-NEXT:    jae .LBB0_3
 ; SSE-NEXT:  # %bb.2:
 ; SSE-NEXT:    xorl %edx, %edx
 ; SSE-NEXT:    jmp .LBB0_6
 ; SSE-NEXT:  .LBB0_3: # %vector.ph
 ; SSE-NEXT:    movl %eax, %edx
 ; SSE-NEXT:    andl $-32, %edx
 ; SSE-NEXT:    movd %r9d, %xmm0
 ; SSE-NEXT:    movd %r8d, %xmm2

 ;
 ; AVX1-LABEL: vector_variable_shift_left_loop:
 ; AVX1:       # %bb.0: # %entry
 ; AVX1-NEXT:    testl %edx, %edx
 ; AVX1-NEXT:    jle .LBB0_9
 ; AVX1-NEXT:  # %bb.1: # %for.body.preheader
 ; AVX1-NEXT:    movl %ecx, %r9d
 ; AVX1-NEXT:    movl %edx, %eax
-; AVX1-NEXT:    cmpl $31, %edx
-; AVX1-NEXT:    ja .LBB0_3
+; AVX1-NEXT:    cmpl $32, %edx
+; AVX1-NEXT:    jae .LBB0_3
 ; AVX1-NEXT:  # %bb.2:
 ; AVX1-NEXT:    xorl %edx, %edx
 ; AVX1-NEXT:    jmp .LBB0_6
 ; AVX1-NEXT:  .LBB0_3: # %vector.ph
 ; AVX1-NEXT:    movl %eax, %edx
 ; AVX1-NEXT:    andl $-32, %edx
 ; AVX1-NEXT:    vmovd %r9d, %xmm0
 ; AVX1-NEXT:    vmovd %r8d, %xmm1

 ;
 ; AVX2-LABEL: vector_variable_shift_left_loop:
 ; AVX2:       # %bb.0: # %entry
 ; AVX2-NEXT:    testl %edx, %edx
 ; AVX2-NEXT:    jle .LBB0_9
 ; AVX2-NEXT:  # %bb.1: # %for.body.preheader
 ; AVX2-NEXT:    movl %ecx, %r9d
 ; AVX2-NEXT:    movl %edx, %eax
-; AVX2-NEXT:    cmpl $31, %edx
-; AVX2-NEXT:    ja .LBB0_3
+; AVX2-NEXT:    cmpl $32, %edx
+; AVX2-NEXT:    jae .LBB0_3
 ; AVX2-NEXT:  # %bb.2:
 ; AVX2-NEXT:    xorl %edx, %edx
 ; AVX2-NEXT:    jmp .LBB0_6
 ; AVX2-NEXT:  .LBB0_3: # %vector.ph
 ; AVX2-NEXT:    movl %eax, %edx
 ; AVX2-NEXT:    andl $-32, %edx
 ; AVX2-NEXT:    vmovd %r9d, %xmm0
 ; AVX2-NEXT:    vpbroadcastd %xmm0, %ymm0

 ;
 ; XOP-LABEL: vector_variable_shift_left_loop:
 ; XOP:       # %bb.0: # %entry
 ; XOP-NEXT:    testl %edx, %edx
 ; XOP-NEXT:    jle .LBB0_9
 ; XOP-NEXT:  # %bb.1: # %for.body.preheader
 ; XOP-NEXT:    movl %ecx, %r9d
 ; XOP-NEXT:    movl %edx, %eax
-; XOP-NEXT:    cmpl $31, %edx
-; XOP-NEXT:    ja .LBB0_3
+; XOP-NEXT:    cmpl $32, %edx
+; XOP-NEXT:    jae .LBB0_3
 ; XOP-NEXT:  # %bb.2:
 ; XOP-NEXT:    xorl %edx, %edx
 ; XOP-NEXT:    jmp .LBB0_6
 ; XOP-NEXT:  .LBB0_3: # %vector.ph
 ; XOP-NEXT:    movl %eax, %edx
 ; XOP-NEXT:    andl $-32, %edx
 ; XOP-NEXT:    vmovd %r9d, %xmm0
 ; XOP-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]

llvm/test/CodeGen/X86/widen_cast-1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=i686-unknown-unknown -mattr=+sse4.2 < %s | FileCheck %s
 ; RUN: llc -mtriple=i686-unknown-unknown -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
 
 ; Scheduler causes produce a different instruction order
 
 ; bitcast a v4i16 to v2i32
 
 define void @convert(<2 x i32>* %dst, <4 x i16>* %src) nounwind {
 ; CHECK-LABEL: convert:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %eax
 ; CHECK-NEXT:    movl $0, (%esp)
 ; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
-; CHECK-NEXT:    cmpl $3, (%esp)
-; CHECK-NEXT:    jg .LBB0_3
+; CHECK-NEXT:    cmpl $4, (%esp)
+; CHECK-NEXT:    jge .LBB0_3
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_2: # %forbody
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movl (%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; CHECK-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    psubw %xmm0, %xmm1
 ; CHECK-NEXT:    movq %xmm1, (%ecx,%eax,8)
 ; CHECK-NEXT:    incl (%esp)
-; CHECK-NEXT:    cmpl $3, (%esp)
-; CHECK-NEXT:    jle .LBB0_2
+; CHECK-NEXT:    cmpl $4, (%esp)
+; CHECK-NEXT:    jl .LBB0_2
 ; CHECK-NEXT:  .LBB0_3: # %afterfor
 ; CHECK-NEXT:    popl %eax
 ; CHECK-NEXT:    retl
 ;
 ; ATOM-LABEL: convert:
 ; ATOM:       # %bb.0: # %entry
 ; ATOM-NEXT:    pushl %eax
 ; ATOM-NEXT:    pcmpeqd %xmm0, %xmm0
 ; ATOM-NEXT:    movl $0, (%esp)
-; ATOM-NEXT:    cmpl $3, (%esp)
-; ATOM-NEXT:    jg .LBB0_3
+; ATOM-NEXT:    cmpl $4, (%esp)
+; ATOM-NEXT:    jge .LBB0_3
 ; ATOM-NEXT:    .p2align 4, 0x90
 ; ATOM-NEXT:  .LBB0_2: # %forbody
 ; ATOM-NEXT:    # =>This Inner Loop Header: Depth=1
 ; ATOM-NEXT:    movl (%esp), %eax
 ; ATOM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; ATOM-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
 ; ATOM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; ATOM-NEXT:    psubw %xmm0, %xmm1
 ; ATOM-NEXT:    movq %xmm1, (%ecx,%eax,8)
 ; ATOM-NEXT:    incl (%esp)
-; ATOM-NEXT:    cmpl $3, (%esp)
-; ATOM-NEXT:    jle .LBB0_2
+; ATOM-NEXT:    cmpl $4, (%esp)
+; ATOM-NEXT:    jl .LBB0_2
 ; ATOM-NEXT:  .LBB0_3: # %afterfor
 ; ATOM-NEXT:    popl %eax
 ; ATOM-NEXT:    retl
 entry:
   %dst.addr = alloca <2 x i32>*
   %src.addr = alloca <4 x i16>*
   %i = alloca i32, align 4
   store <2 x i32>* %dst, <2 x i32>** %dst.addr

llvm/test/CodeGen/X86/widen_cast-2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 | FileCheck %s
 ; bitcast v14i16 to v7i32
 
 define void @convert(<7 x i32>* %dst, <14 x i16>* %src) nounwind {
 ; CHECK-LABEL: convert:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %eax
 ; CHECK-NEXT:    movl $0, (%esp)
 ; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
-; CHECK-NEXT:    cmpl $3, (%esp)
-; CHECK-NEXT:    jg .LBB0_3
+; CHECK-NEXT:    cmpl $4, (%esp)
+; CHECK-NEXT:    jge .LBB0_3
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_2: # %forbody
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movl (%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    shll $5, %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; CHECK-NEXT:    movdqa (%edx,%eax), %xmm1
 ; CHECK-NEXT:    movdqa 16(%edx,%eax), %xmm2
 ; CHECK-NEXT:    psubw %xmm0, %xmm2
 ; CHECK-NEXT:    psubw %xmm0, %xmm1
 ; CHECK-NEXT:    movdqa %xmm1, (%ecx,%eax)
 ; CHECK-NEXT:    movd %xmm2, 16(%ecx,%eax)
 ; CHECK-NEXT:    pextrd $1, %xmm2, 20(%ecx,%eax)
 ; CHECK-NEXT:    pextrd $2, %xmm2, 24(%ecx,%eax)
 ; CHECK-NEXT:    incl (%esp)
-; CHECK-NEXT:    cmpl $3, (%esp)
-; CHECK-NEXT:    jle .LBB0_2
+; CHECK-NEXT:    cmpl $4, (%esp)
+; CHECK-NEXT:    jl .LBB0_2
 ; CHECK-NEXT:  .LBB0_3: # %afterfor
 ; CHECK-NEXT:    popl %eax
 ; CHECK-NEXT:    retl
 entry:
   %dst.addr = alloca <7 x i32>*
   %src.addr = alloca <14 x i16>*
   %i = alloca i32, align 4
   store <7 x i32>* %dst, <7 x i32>** %dst.addr

llvm/test/CodeGen/X86/x32-va_start.ll

 ; SSE-NEXT:  .LBB0_5: # %entry
 ; SSE-NEXT:    leal -{{[0-9]+}}(%rsp), %eax
 ; SSE-NEXT:    movl %eax, -{{[0-9]+}}(%esp)
 ; SSE-NEXT:    leal {{[0-9]+}}(%rsp), %eax
 ; SSE-NEXT:    movl %eax, -{{[0-9]+}}(%esp)
 ; SSE-NEXT:    movabsq $274877906952, %rax # imm = 0x4000000008
 ; SSE-NEXT:    movq %rax, -{{[0-9]+}}(%esp)
 ; SSE-NEXT:    movl $8, %ecx
-; SSE-NEXT:    cmpl $40, %ecx
-; SSE-NEXT:    ja .LBB0_2
+; SSE-NEXT:    cmpl $41, %ecx
+; SSE-NEXT:    jae .LBB0_2
 ; SSE-NEXT:  # %bb.1: # %vaarg.in_reg
 ; SSE-NEXT:    movl -{{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    addl %ecx, %eax
 ; SSE-NEXT:    addl $8, %ecx
 ; SSE-NEXT:    movl %ecx, -{{[0-9]+}}(%esp)
 ; SSE-NEXT:    jmp .LBB0_3
 ; SSE-NEXT:  .LBB0_2: # %vaarg.in_mem
 ; SSE-NEXT:    movl -{{[0-9]+}}(%esp), %eax

 ; NOSSE-NEXT:    movq %r9, -{{[0-9]+}}(%esp)
 ; NOSSE-NEXT:    leal -{{[0-9]+}}(%rsp), %eax
 ; NOSSE-NEXT:    movl %eax, -{{[0-9]+}}(%esp)
 ; NOSSE-NEXT:    leal {{[0-9]+}}(%rsp), %eax
 ; NOSSE-NEXT:    movl %eax, -{{[0-9]+}}(%esp)
 ; NOSSE-NEXT:    movabsq $206158430216, %rax # imm = 0x3000000008
 ; NOSSE-NEXT:    movq %rax, -{{[0-9]+}}(%esp)
 ; NOSSE-NEXT:    movl $8, %ecx
-; NOSSE-NEXT:    cmpl $40, %ecx
-; NOSSE-NEXT:    ja .LBB0_2
+; NOSSE-NEXT:    cmpl $41, %ecx
+; NOSSE-NEXT:    jae .LBB0_2
 ; NOSSE-NEXT:  # %bb.1: # %vaarg.in_reg
 ; NOSSE-NEXT:    movl -{{[0-9]+}}(%esp), %eax
 ; NOSSE-NEXT:    addl %ecx, %eax
 ; NOSSE-NEXT:    addl $8, %ecx
 ; NOSSE-NEXT:    movl %ecx, -{{[0-9]+}}(%esp)
 ; NOSSE-NEXT:    movl (%eax), %eax
 ; NOSSE-NEXT:    retq
 ; NOSSE-NEXT:  .LBB0_2: # %vaarg.in_mem
 ; NOSSE-NEXT:    movl -{{[0-9]+}}(%esp), %eax
 ; NOSSE-NEXT:    leal 8(%rax), %ecx
 ; NOSSE-NEXT:    movl %ecx, -{{[0-9]+}}(%esp)
 ; NOSSE-NEXT:    movl (%eax), %eax
 ; NOSSE-NEXT:    retq
 ;
 ; 32BITABI-LABEL: foo:
 ; 32BITABI:       # %bb.0: # %entry
 ; 32BITABI-NEXT:    subl $28, %esp
 ; 32BITABI-NEXT:    leal {{[0-9]+}}(%esp), %ecx
 ; 32BITABI-NEXT:    movl %ecx, (%esp)
-; 32BITABI-NEXT:    cmpl $40, %ecx
-; 32BITABI-NEXT:    ja .LBB0_2
+; 32BITABI-NEXT:    cmpl $41, %ecx
+; 32BITABI-NEXT:    jae .LBB0_2
 ; 32BITABI-NEXT:  # %bb.1: # %vaarg.in_reg
 ; 32BITABI-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; 32BITABI-NEXT:    addl %ecx, %eax
 ; 32BITABI-NEXT:    addl $8, %ecx
 ; 32BITABI-NEXT:    movl %ecx, (%esp)
 ; 32BITABI-NEXT:    jmp .LBB0_3
 ; 32BITABI-NEXT:  .LBB0_2: # %vaarg.in_mem
 ; 32BITABI-NEXT:    movl {{[0-9]+}}(%esp), %eax

llvm/test/CodeGen/X86/x86-shrink-wrapping.ll

 ; ENABLE-NEXT:    je LBB8_7
 ; ENABLE-NEXT:  ## %bb.1: ## %if.end
 ; ENABLE-NEXT:    cmpw $66, (%rdi)
 ; ENABLE-NEXT:    jne LBB8_7
 ; ENABLE-NEXT:  ## %bb.2: ## %lor.lhs.false
 ; ENABLE-NEXT:    movq 8(%rdi), %rdi
 ; ENABLE-NEXT:    movzwl (%rdi), %eax
 ; ENABLE-NEXT:    leal -54(%rax), %ecx
-; ENABLE-NEXT:    cmpl $14, %ecx
-; ENABLE-NEXT:    ja LBB8_3
+; ENABLE-NEXT:    cmpl $15, %ecx
+; ENABLE-NEXT:    jae LBB8_3
 ; ENABLE-NEXT:  ## %bb.8: ## %lor.lhs.false
 ; ENABLE-NEXT:    movl $24599, %edx ## imm = 0x6017
 ; ENABLE-NEXT:    btl %ecx, %edx
 ; ENABLE-NEXT:    jae LBB8_3
 ; ENABLE-NEXT:  LBB8_7: ## %cleanup
 ; ENABLE-NEXT:    popq %rax
 ; ENABLE-NEXT:    retq
 ; ENABLE-NEXT:  LBB8_3: ## %lor.lhs.false

 ; DISABLE-NEXT:    je LBB8_7
 ; DISABLE-NEXT:  ## %bb.1: ## %if.end
 ; DISABLE-NEXT:    cmpw $66, (%rdi)
 ; DISABLE-NEXT:    jne LBB8_7
 ; DISABLE-NEXT:  ## %bb.2: ## %lor.lhs.false
 ; DISABLE-NEXT:    movq 8(%rdi), %rdi
 ; DISABLE-NEXT:    movzwl (%rdi), %eax
 ; DISABLE-NEXT:    leal -54(%rax), %ecx
-; DISABLE-NEXT:    cmpl $14, %ecx
-; DISABLE-NEXT:    ja LBB8_3
+; DISABLE-NEXT:    cmpl $15, %ecx
+; DISABLE-NEXT:    jae LBB8_3
 ; DISABLE-NEXT:  ## %bb.8: ## %lor.lhs.false
 ; DISABLE-NEXT:    movl $24599, %edx ## imm = 0x6017
 ; DISABLE-NEXT:    btl %ecx, %edx
 ; DISABLE-NEXT:    jae LBB8_3
 ; DISABLE-NEXT:  LBB8_7: ## %cleanup
 ; DISABLE-NEXT:    popq %rax
 ; DISABLE-NEXT:    retq
 ; DISABLE-NEXT:  LBB8_3: ## %lor.lhs.false