- User Since
- Feb 5 2019, 2:01 PM (36 w, 6 d)
Fri, Oct 18
Thu, Oct 10
Sun, Oct 6
Address Roman and Nemanja' comments
Commited by https://reviews.llvm.org/rL373876
Fri, Oct 4
Test cases are posted here https://reviews.llvm.org/D68534. I would need approval to commit the NFC patch.
Thu, Oct 3
Wed, Oct 2
Address Jonsong and Nemanja's comments
Tue, Oct 1
Our buildbot http://lab.llvm.org:8011/builders/clang-ppc64le-linux-lnt seem broken by this patch either.
Mon, Sep 30
Fri, Sep 27
Thu, Sep 26
Address Amy's comment
To see how my transformation affect AArch64 and X86 tests. Please use History to compare Diff 5 (221979) and Diff 6 (221983)
Add the option -cgp-icmp-eq2icmp-st to enable transformation on AArch64/X86 tests (complete addressing Roman's comments)
- Address Lei's comments
- Add tests for other arches - x86, aarch6 by following Roman 's comments
Mon, Sep 23
Reduce the MIR test cases (Address Jinsong's comments)
Sun, Sep 22
Address Jinsong's comments
Sep 18 2019
Sep 17 2019
Address Jinsong's comment
Sep 8 2019
Aug 31 2019
Address Stefan's comments
Aug 29 2019
Jul 23 2019
Address Stefan's review comments
Jul 17 2019
Added LLVM IR testcases as requested.
Jul 4 2019
May 22 2019
Relax the restriction so we can handle comparisons between two virtual registers equivalently. I rebase the patch to TOT so history would not work. Please review this commit directly.
May 21 2019
It was commited to the wrong place and correct here https://reviews.llvm.org/rG00e85f753583
Done here https://reviews.llvm.org/rG00e85f753583. Sorry for the inconvenience
My fault. Should I reverse the commit and commit the right patch again or just create another patch to move it?
Forgot adding Differential Revision: in the end of commit https://github.com/llvm/llvm-project/commit/6e19543a2a2013bd357eb15e383b435cd0cbb810. Close it manually.
May 17 2019
May 15 2019
May 9 2019
Rebase the master (NFC testcases merged). Since it is a rebased one, please see the latest commit for review
Change according to comments
May 8 2019
Apr 11 2019
Apr 10 2019
Mar 27 2019
The implementation change seems reasonable. I encode the instruction manually and it is correct. LGTM.
Mar 21 2019
I think I addressed all the comments above. This is a gentle ping ...
Mar 18 2019
Mar 12 2019
Mar 5 2019
Add default in the switch to address Jinsong's comment
Mar 4 2019
I export LLVM_VERIFY_MACHINEINSTRS=1 and run the LIT/LNT tests with my patch and it pass either.
Mar 3 2019
By the way, this patch passes Bootstrap, SPEC 2006, SPEC 2017, llvm-on-power/Benchmarks/ tests on power8/power9
I think using f0 here is OK. Take another instruction lxsdx for example:
$ echo '0x7c 0xe5 0xfc 0x98' | ./build/release/bin/llvm-mc --disassemble -triple powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-asm-full-reg-names .text lxsdx f7, r5, r31
According to the spec, lxsdx will output to VSX[XT]. It uses vsfrc since it only uses first dword (VSX[XT].dword is undefined). That's our intention to print f7 instead of vs7 here. Go back the this case, lxsibzx has the same situation as lxsdx. Besides, XXSPLTWs only uses in the pattern xxspltw XT,XB, 1 so it is well-defined to use f0 here (f0.word = vs0.word).
Mar 1 2019
This commit seems cause failure of clang-ppc64be-linux (http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/30804), clang-ppc64be-linux-multistage (http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/16234), clang-ppc64be-linux-lnt (http://lab.llvm.org:8011/builders/clang-ppc64be-linux-lnt/builds/25016)
Feb 26 2019
Feb 13 2019
This patch seems cause failure of buildbot http://lab.llvm.org:8011/builders/clang-ppc64le-linux-multistage/builds/9150
Feb 8 2019
This commit seems cause failure in http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/29842
Feb 5 2019
This commit cause failure on clang-ppc64be-linux-lnt