- User Since
- Feb 5 2019, 2:01 PM (11 w, 19 h)
Thu, Apr 11
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Wed, Mar 27
The implementation change seems reasonable. I encode the instruction manually and it is correct. LGTM.
Mar 21 2019
I think I addressed all the comments above. This is a gentle ping ...
Mar 18 2019
Mar 12 2019
Mar 5 2019
Add default in the switch to address Jinsong's comment
Mar 4 2019
I export LLVM_VERIFY_MACHINEINSTRS=1 and run the LIT/LNT tests with my patch and it pass either.
Mar 3 2019
By the way, this patch passes Bootstrap, SPEC 2006, SPEC 2017, llvm-on-power/Benchmarks/ tests on power8/power9
I think using f0 here is OK. Take another instruction lxsdx for example:
$ echo '0x7c 0xe5 0xfc 0x98' | ./build/release/bin/llvm-mc --disassemble -triple powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-asm-full-reg-names .text lxsdx f7, r5, r31
According to the spec, lxsdx will output to VSX[XT]. It uses vsfrc since it only uses first dword (VSX[XT].dword is undefined). That's our intention to print f7 instead of vs7 here. Go back the this case, lxsibzx has the same situation as lxsdx. Besides, XXSPLTWs only uses in the pattern xxspltw XT,XB, 1 so it is well-defined to use f0 here (f0.word = vs0.word).
Mar 1 2019
This commit seems cause failure of clang-ppc64be-linux (http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/30804), clang-ppc64be-linux-multistage (http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/16234), clang-ppc64be-linux-lnt (http://lab.llvm.org:8011/builders/clang-ppc64be-linux-lnt/builds/25016)
Feb 26 2019
Feb 13 2019
This patch seems cause failure of buildbot http://lab.llvm.org:8011/builders/clang-ppc64le-linux-multistage/builds/9150
Feb 8 2019
This commit seems cause failure in http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/29842
Feb 5 2019
This commit cause failure on clang-ppc64be-linux-lnt