[System Model] Introduce a target system model

[greened]

Summary

Add the concept of a per-subtarget system model, incorporating information
about caches, execution resources, write-combining buffers and software
prefetching configuration.

This is TableGen-driven so that targets may conveniently define new system
models and associate system models with subtargets.

By default, processor classes use a system model that captures the legacy
values exposed by TargetTransformInfo and/or MCSubtarget and friends.
Targets may opt-in to custom system models by defining them and associating
them in instantiations of the Processor template, similarly to how schedulers
are associated.

This patch is for overall higher-level design discussion, to provide a view of where this is going. Smaller patches to review for actual merging will follow.

[greened]

A larger design question I have about this is the proper place to put software prefetching configuration. Right now it lives at the memory model level, in that a memory model specifies a cache heirachy along with a software prefetch configuration. I wonder if we should allow for software prefetching configuration for each cache level, as targets might want different policies depending on which cache level they are prefetching into. I don't think we have any examples of that in the codebase today but I can imagine cases where targets might want it.

[greened]

Ping?

[greened]

Ping?

[Meinersbur]

Thank you for pushing this forward and sorry for the delay.

Could you add some central high-level documentation about what the memory system model is? E.g. describe that an MCSystemModel has a list of execution resources, memory hierarchies, prefetch configs and write-combining buffers. A Cache hierarchy as a total size, line size, associativity, etc. To get the interpretation eight, please add more details about ever parameter, particularly the prefetch configs. Some other examples than ARM big.LITTLE would be nice as well.

What exactly is a "prefetch config"? Is there a prefetch config for each cache level? Different hardware mechanisms for prefetch (e.g. stride detection or software-estabslished). Different strategies for inserting prefetch instruction selectable at compile-time?

AFAICS, this patch does uses the default model for all targets?

llvm/include/llvm/Analysis/TargetTransformInfo.h

777–784

[bikeshedding] The name should indicate that these methods just return some information. How about isPrefetchingReads/etc.?

1185–1210

It is interesting that getCacheSize/getCacheAssociativity return llvm::Optionals and are cache-level specific, but not getCacheLineSize

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

379–383

Could you add some documentation about what these special values mean?

llvm/include/llvm/MC/MCSubtargetInfo.h

98–105

I don't understand the idea of the resolve... API. What is a target overriding it supposed to do? There are not overrides in this patch. Why not providing a default implementation of getCacheSize that targets can override?

llvm/include/llvm/MC/MCSystemModel.h

407–408

[style] These trailing empty comment lines don't seem to be useful. The current LLVM code base does not have them.

444

Could we avoid the static initializer?

465

The type has 'Set' in its name, but is an alias for a vector?

469

Why does it need to be mutable?

llvm/include/llvm/Target/TargetSoftwarePrefetchConfig.td

45–48

ISA instructions or µOps? Why not cycles?

49–53

Isn't this algorithm-dependent, i.e. the size of the loop?

llvm/lib/MC/MCSubtargetInfo.cpp

307

I find this handling of --help strange, but the current MCSubtargetInfo::getSchedModelForCPU does the same thing.

llvm/lib/MC/MCSystemModel.cpp

28–49

where are these used?

67

[typo] lttle

[simoll]

This takes a while to digest. Some quick remarks for now (also inline):

• Is there a way to query the number of (automatic) HW prefetchers?
• Does the interface provide the latency of each cache level (hit)/memory (miss)?

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

383

What is this method supposed to return?
The right value seems to be a property of a specific pair of a loop and a target architecture rather than just the target alone.

[Meinersbur]

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

383

It is used by LoopDataPrefetch. TargetTransformInfo.h contains a description:

/// \return The maximum number of iterations to prefetch ahead.  If the
/// required number of iterations is more than this number, no prefetching is
/// performed.
unsigned getMaxPrefetchIterationsAhead() const;

I assume it was added just because the current code base already defines it.

[greened]

In D58736#1434008, @Meinersbur wrote:

Thank you for pushing this forward and sorry for the delay.

Could you add some central high-level documentation about what the memory system model is? E.g. describe that an MCSystemModel has a list of execution resources, memory hierarchies, prefetch configs and write-combining buffers. A Cache hierarchy as a total size, line size, associativity, etc. To get the interpretation eight, please add more details about ever parameter, particularly the prefetch configs. Some other examples than ARM big.LITTLE would be nice as well.

Will do.

What exactly is a "prefetch config"? Is there a prefetch config for each cache level? Different hardware mechanisms for prefetch (e.g. stride detection or software-estabslished). Different strategies for inserting prefetch instruction selectable at compile-time?

This is certainly an area for exploration. Currently the model doesn't have a prefetch config for each cache level but we could make it so. I'm not sure if the flexibility will be needed or not. We haven't needed in the past but processors are getting a lot more complicated in this area.

The intent is to describe parameters for software prefetching. It doesn't attempt to describe hardware prefetchers but that may be useful depending on the problem at hand. I think that's something we could consider for later.

AFAICS, this patch does uses the default model for all targets?

Yes, currently. My intent was not to disrupt how anything currently works as far as what TTI returns for its interfaces. Individual subtargets can then opt-in by defining a non-default model.

[greened]

In D58736#1434370, @simoll wrote:

This takes a while to digest. Some quick remarks for now (also inline):

Yes, I know it's a big patch. I wanted to provide the whole context but can certainly break it up into smaller pieces for review if that's easier. Would it be useful to post smaller pieces for review/commit but maintain this patch for reference? I don't intend to actually commit all this as one big change.

• Is there a way to query the number of (automatic) HW prefetchers?

Not currently. It's something we could add later.

• Does the interface provide the latency of each cache level (hit)/memory (miss)?

The latency of each level is the latency for a hit. I hadn't considered a separate miss latency as I thought the last "level" would be DRAM and the latency for that would approximate the latency of a full miss. Of course the various cache levels will have a longer miss latency than a direct DRAM access but I hadn't considered that overhead to be arge enough to model. If we think it is then we can do that.

[greened]

llvm/include/llvm/Analysis/TargetTransformInfo.h

777–784

Good point. I think shouldPrefetchReads would better convey what this is supposed to be telling us.

1185–1210

Yeah. I assume that's because on almost every processor, the cache line size is the same thoughout the cache heirarchy so the interface was designed assuming that no cache level parameter was necessary. If there's no cache level parameter, there's no possiblity of the user providing a non-existent cache level and thus no need for an llvm::Optional.

However, there have been processors in the past where cache line size varied by level and certainly when you have a heterogeneous system the cache line size will not be uniform across the system.

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

383

Yes, that's exactly right. When I originally posted the RFC I suggested a single prefetch distance in bytes. Others chimed in and said they preferred to think in terms of loop iterations and that is indeed what LoopDataPrefetch does. LoopDataPrefetch also drove the inclsion of getMinPrefetchStride.

Since I didn't want to affect how current passes work, I added the necessary inrfrastructure to have the system model specify it. I expect that as we gain experience we may eliminate some of these interfaces.

llvm/include/llvm/MC/MCSubtargetInfo.h

98–105

This is something I don't have in our local implementation, but after posting the RFC several people said they'd like to model GPUs and big.LITTLE-style systems. In such hybrid systems, there is no single "L2 cache," for example. If a client asks the system model, "Give me the size of the L2 cache," what should it do? Return the L2 of the CPU, the L2 of the GPU or something else? That's the idea of the resolve... stuff. Somebody has to decide what to do which is what these virtual APIs are suggesting.

SubtargetInfo might not be the right place for this, but lacking a better place for it, I just put it here. I could remove all this for the initial changeset and just return some default with an override as you suggest. I'm definitely open to ideas/opinions here.

llvm/include/llvm/MC/MCSystemModel.h

444

Maybe? I took cues for how the scheduler stuff is implemented and it uses similar static initializers. I'll look into this and see if there is a better way.

469

It doesn't. This is leftover from a time when I thought initCacheInfoCache and friends could be called lazily. I'll rework this.

llvm/include/llvm/Target/TargetSoftwarePrefetchConfig.td

45–48

LoopDataPrefetch thinks in terms of IR Instructions. I'll clarify the comment and name. Maybe we should reconsider how LoopDataPrefetch thinks about things but I'd prefer to leave that for later work. I want to be confident we can model the way things work today before we go changing a bunch of things.

49–53

Yep. Again, this is driven by LoopDataPrefetch.

llvm/lib/MC/MCSubtargetInfo.cpp

307

Right. That's what I used as guidance.

llvm/lib/MC/MCSystemModel.cpp

28–49

They aren't anymore. Will remove.

[greened]

Updated to address comments.

Next week I plan to start submitting smaller changes to build up to what's here. So comments on the overall design of this patch would be great, but it's huge and not the best vehicle for discussing details.

I want to start getting the foundational pieces in, likely starting with abstracting the prefetching stuff via TTI which will hopefully be non-controversial.

[arsenm]

llvm/include/llvm/CodeGen/BasicTTIImpl.h

523

All of these should probably have address space arguments

[greened]

llvm/include/llvm/CodeGen/BasicTTIImpl.h

523

What would the address space argument specify? What are the use-cases for modeling caches with address spaces? Perhaps this could replace the resolve... APIs. That would be nice.

These are existing interfaces so what would be the best way to transition them?

[greened]

I just posted D63614, the subset of this patch covering only the changes to TTI and related classes.

llvm/include/llvm/CodeGen/BasicTTIImpl.h

523

It's probably more productive to continue this discussion on D63614, which is the TTI part of this patch.

llvm/include/llvm/Analysis/TargetTransformInfo.h

public:
   };
 
   /// \return The size of the cache level in bytes, if available.
   llvm::Optional<unsigned> getCacheSize(CacheLevel Level) const;
 
   /// \return The associativity of the cache level, if available.
   llvm::Optional<unsigned> getCacheAssociativity(CacheLevel Level) const;
 
-  /// \return How much before a load we should place the prefetch instruction.
-  /// This is currently measured in number of instructions.
+  /// \return Whether to prefetch loads.
+  bool shouldPrefetchReads() const;
+
+  /// \return Whether to prefetch stores.
+  bool shouldPrefetchWrites() const;
+
+  /// \return How much before a load we should place the prefetch
+  /// instruction.  This is currently measured in number of
+  /// instructions.
   unsigned getPrefetchDistance() const;
 
-  /// \return Some HW prefetchers can handle accesses up to a certain constant
-  /// stride.  This is the minimum stride in bytes where it makes sense to start
-  /// adding SW prefetches.  The default is 1, i.e. prefetch with any stride.
+  /// \return Some HW prefetchers can handle accesses up to a certain
+  /// constant stride.  This is the minimum stride in bytes where it
+  /// makes sense to start adding SW prefetches.  The default is 1,
+  /// i.e. prefetch with any stride.
   unsigned getMinPrefetchStride() const;
 
-  /// \return The maximum number of iterations to prefetch ahead.  If the
-  /// required number of iterations is more than this number, no prefetching is
-  /// performed.
+  /// \return The maximum number of iterations to prefetch ahead.  If
+  /// the required number of iterations is more than this number, no
+  /// prefetching is performed.
   unsigned getMaxPrefetchIterationsAhead() const;
 
   /// \return The maximum interleave factor that any transform should try to
   /// perform for this target. This number depends on the level of parallelism
   /// and the number of execution units in the CPU.
   unsigned getMaxInterleaveFactor(unsigned VF) const;
 
   /// Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
virtual int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
                             Type *Ty) = 0;
   virtual unsigned getNumberOfRegisters(bool Vector) = 0;
   virtual unsigned getRegisterBitWidth(bool Vector) const = 0;
   virtual unsigned getMinVectorRegisterBitWidth() = 0;
   virtual bool shouldMaximizeVectorBandwidth(bool OptSize) const = 0;
   virtual unsigned getMinimumVF(unsigned ElemWidth) const = 0;
   virtual bool shouldConsiderAddressTypePromotion(
       const Instruction &I, bool &AllowPromotionWithoutCommonHeader) = 0;
-  virtual unsigned getCacheLineSize() = 0;
-  virtual llvm::Optional<unsigned> getCacheSize(CacheLevel Level) = 0;
-  virtual llvm::Optional<unsigned> getCacheAssociativity(CacheLevel Level) = 0;
-  virtual unsigned getPrefetchDistance() = 0;
-  virtual unsigned getMinPrefetchStride() = 0;
-  virtual unsigned getMaxPrefetchIterationsAhead() = 0;
+  virtual unsigned getCacheLineSize() const = 0;
+  virtual llvm::Optional<unsigned> getCacheSize(CacheLevel Level) const = 0;
+  virtual llvm::Optional<unsigned> getCacheAssociativity(CacheLevel Level) const = 0;
+
+  /// \return Whether to prefetch loads.
+  virtual bool shouldPrefetchReads() const = 0;
+
+  /// \return Whether to prefetch stores.
+  virtual bool shouldPrefetchWrites() const = 0;
+
+  /// \return How much before a load we should place the prefetch
+  /// instruction.  This is currently measured in number of
+  /// instructions.
+  virtual unsigned getPrefetchDistance() const = 0;
+
+  /// \return Some HW prefetchers can handle accesses up to a certain
+  /// constant stride.  This is the minimum stride in bytes where it
+  /// makes sense to start adding SW prefetches.  The default is 1,
+  /// i.e. prefetch with any stride.
+  virtual unsigned getMinPrefetchStride() const = 0;
+
+  /// \return The maximum number of iterations to prefetch ahead.  If
+  /// the required number of iterations is more than this number, no
+  /// prefetching is performed.
+  virtual unsigned getMaxPrefetchIterationsAhead() const = 0;
+
   virtual unsigned getMaxInterleaveFactor(unsigned VF) = 0;
   virtual unsigned
   getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
                          OperandValueKind Opd2Info,
                          OperandValueProperties Opd1PropInfo,
                          OperandValueProperties Opd2PropInfo,
                          ArrayRef<const Value *> Args) = 0;
   virtual int getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
public:
   unsigned getMinimumVF(unsigned ElemWidth) const override {
     return Impl.getMinimumVF(ElemWidth);
   }
   bool shouldConsiderAddressTypePromotion(
       const Instruction &I, bool &AllowPromotionWithoutCommonHeader) override {
     return Impl.shouldConsiderAddressTypePromotion(
         I, AllowPromotionWithoutCommonHeader);
   }
-  unsigned getCacheLineSize() override {
+  unsigned getCacheLineSize() const override {
     return Impl.getCacheLineSize();
   }
-  llvm::Optional<unsigned> getCacheSize(CacheLevel Level) override {
+  llvm::Optional<unsigned> getCacheSize(CacheLevel Level) const override {
     return Impl.getCacheSize(Level);
   }
-  llvm::Optional<unsigned> getCacheAssociativity(CacheLevel Level) override {
+  llvm::Optional<unsigned> getCacheAssociativity(CacheLevel Level) const override {
     return Impl.getCacheAssociativity(Level);
   }
-  unsigned getPrefetchDistance() override { return Impl.getPrefetchDistance(); }
-  unsigned getMinPrefetchStride() override {
+
+  /// Return whether we should do software prefetching for loads on
+  /// this target.
+  ///
+  bool shouldPrefetchReads() const override {
+    return Impl.shouldPrefetchReads();
+  }
+
+  /// Return whether we should do software prefetching for stores on
+  /// this target.
+  ///
+  bool shouldPrefetchWrites() const override {
+    return Impl.shouldPrefetchWrites();
+  }
+
+  /// Return the preferred prefetch distance in terms of instructions.
+  ///
+  unsigned getPrefetchDistance() const override {
+    return Impl.getPrefetchDistance();
+  }
+
+  /// Return the minimum stride necessary to trigger software
+  /// prefetching.
+  ///
+  unsigned getMinPrefetchStride() const override {
     return Impl.getMinPrefetchStride();
   }
-  unsigned getMaxPrefetchIterationsAhead() override {
+
+  /// Return the maximum prefetch distance in terms of loop
+  /// iterations.
+  ///
+  unsigned getMaxPrefetchIterationsAhead() const override {
     return Impl.getMaxPrefetchIterationsAhead();
   }
+
   unsigned getMaxInterleaveFactor(unsigned VF) override {
     return Impl.getMaxInterleaveFactor(VF);
   }
   unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
                                             unsigned &JTSize) override {
     return Impl.getEstimatedNumberOfCaseClusters(SI, JTSize);
   }
   unsigned

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

public:
 
   bool
   shouldConsiderAddressTypePromotion(const Instruction &I,
                                      bool &AllowPromotionWithoutCommonHeader) {
     AllowPromotionWithoutCommonHeader = false;
     return false;
   }
 
-  unsigned getCacheLineSize() { return 0; }
+  unsigned getCacheLineSize() const { return 0; }
 
-  llvm::Optional<unsigned> getCacheSize(TargetTransformInfo::CacheLevel Level) {
+  llvm::Optional<unsigned> getCacheSize(TargetTransformInfo::CacheLevel Level) const {
     switch (Level) {
     case TargetTransformInfo::CacheLevel::L1D:
       LLVM_FALLTHROUGH;
     case TargetTransformInfo::CacheLevel::L2D:
       return llvm::Optional<unsigned>();
     }
 
     llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
   }
 
   llvm::Optional<unsigned> getCacheAssociativity(
-    TargetTransformInfo::CacheLevel Level) {
+    TargetTransformInfo::CacheLevel Level) const {
     switch (Level) {
     case TargetTransformInfo::CacheLevel::L1D:
       LLVM_FALLTHROUGH;
     case TargetTransformInfo::CacheLevel::L2D:
       return llvm::Optional<unsigned>();
     }
 
     llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
   }
 
-  unsigned getPrefetchDistance() { return 0; }
+  /// \return Whether to prefetch loads.
+  bool shouldPrefetchReads() const { return false; };
 
-  unsigned getMinPrefetchStride() { return 1; }
+  /// \return Whether to prefetch stores.
+  bool shouldPrefetchWrites() const { return false; }
 
-  unsigned getMaxPrefetchIterationsAhead() { return UINT_MAX; }
+  /// \return How much before a load we should place the prefetch
+  /// instruction.  This is currently measured in number of
+  /// instructions.
+  unsigned getPrefetchDistance() const { return 0; }
+
+  /// \return The minimum stride in bytes where it makes sense to
+  /// start adding SW prefetches.  Some HW prefetchers can handle
+  /// accesses up to a certain constant stride, above which we should
+  /// start issuing SW prefetches.  The default is 1, i.e. prefetch
+  /// with any stride.
+  unsigned getMinPrefetchStride() const { return 1; }
+
+  /// \return The maximum number of iterations to prefetch ahead.  If
+  /// the required number of iterations is more than this number, no
+  /// prefetching is performed.
+  unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
 
   unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
 
   unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
                                   TTI::OperandValueKind Opd1Info,
                                   TTI::OperandValueKind Opd2Info,
                                   TTI::OperandValueProperties Opd1PropInfo,
                                   TTI::OperandValueProperties Opd2PropInfo,

llvm/include/llvm/CodeGen/BasicTTIImpl.h

public:
 
   int getInstructionLatency(const Instruction *I) {
     if (isa<LoadInst>(I))
       return getST()->getSchedModel().DefaultLoadLatency;
 
     return BaseT::getInstructionLatency(I);
   }
 
+  // \return The total cache size at level Level in bytes.
+  virtual Optional<unsigned>
+  getCacheSize(TargetTransformInfo::CacheLevel Level) const {
+    return Optional<unsigned>(
+      getST()->getCacheSize(static_cast<unsigned>(Level)));
+  }
+
+  // \return The number of cache ways at level Level.
+  virtual Optional<unsigned>
+  getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const {
+    return Optional<unsigned>(
+      getST()->getCacheAssociativity(static_cast<unsigned>(Level)));
+  }
+
+  // \return The cache line size in bytes.
+  virtual unsigned getCacheLineSize() const {
+    return getST()->getCacheLineSize();
+  }
+
+  /// \return Whether to prefetch loads.
+  virtual bool shouldPrefetchReads() const {
+    return getST()->shouldPrefetchReads();
+  }
+
+  /// \return Whether to prefetch stores.
+  virtual bool shouldPrefetchWrites() const {
+    return getST()->shouldPrefetchWrites();
+  }
+
+  /// \return How much before a load we should place the prefetch
+  /// instruction.  This is currently measured in number of
+  /// instructions.
+  virtual unsigned getPrefetchDistance() const {
+    return getST()->getPrefetchDistance();
+  }
+
+  /// \return The minimum stride in bytes where it makes sense to
+  /// start adding SW prefetches.  Some HW prefetchers can handle
+  /// accesses up to a certain constant stride, above which we should
+  /// start issuing SW prefetches.
+  virtual unsigned getMinPrefetchStride() const {
+    return getST()->getMinPrefetchStride();
+  }
+
+  /// \return The maximum number of iterations to prefetch ahead.  If
+  /// the required number of iterations is more than this number, no
+  /// prefetching is performed.
+  virtual unsigned getMaxPrefetchIterationsAhead() const {
+    return getST()->getMaxPrefetchIterationsAhead();
+  }
+
   /// @}
 
   /// \name Vector TTI Implementations
   /// @{
 
   unsigned getNumberOfRegisters(bool Vector) { return Vector ? 0 : 1; }
 
   unsigned getRegisterBitWidth(bool Vector) const { return 32; }

llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

 struct MCWriteProcResEntry;
 class RegisterBankInfo;
 class SDep;
 class SelectionDAGTargetInfo;
 struct SubtargetFeatureKV;
 struct SubtargetSubTypeKV;
 struct SubtargetInfoKV;
 class SUnit;
+class TargetSystemModel;
 class TargetFrameLowering;
 class TargetInstrInfo;
 class TargetLowering;
 class TargetRegisterClass;
 class TargetRegisterInfo;
 class TargetSchedModel;
 class Triple;
 

llvm/include/llvm/MC/MCSubtargetInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCSUBTARGETINFO_H
 #define LLVM_MC_MCSUBTARGETINFO_H
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCSystemModel.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 #include <string>
 

 
 //===----------------------------------------------------------------------===//
 
 /// Used to provide key value pairs for feature and CPU bit flags.
 struct SubtargetSubTypeKV {
   const char *Key;                      ///< K-V key string
   FeatureBitArray Implies;              ///< K-V bit mask
   const MCSchedModel *SchedModel;
+  const MCSystemModel *SystemModel;
 
   /// Compare routine for std::lower_bound
   bool operator<(StringRef S) const {
     return StringRef(Key) < S;
   }
 
   /// Compare routine for std::is_sorted.
   bool operator<(const SubtargetSubTypeKV &Other) const {
class MCSubtargetInfo {
   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
   ArrayRef<SubtargetSubTypeKV> ProcDesc;  // Processor descriptions
 
   // Scheduler machine model
   const MCWriteProcResEntry *WriteProcResTable;
   const MCWriteLatencyEntry *WriteLatencyTable;
   const MCReadAdvanceEntry *ReadAdvanceTable;
   const MCSchedModel *CPUSchedModel;
+  const MCSystemModel *CPUSystemModel;
 
   const InstrStage *Stages;            // Instruction itinerary stages
   const unsigned *OperandCycles;       // Itinerary operand cycles
   const unsigned *ForwardingPaths;
   FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
 
+  // Resolve API
+  //
+  // For some systems, how to answer questions like, "How big is the
+  // L1 cache?" is not straightforward.  For example, a system might
+  // be composed of two different core types, each with a
+  // differently-sized L1 cache.  At the global view level, what
+  // should be used as the "size of L1," the bigger or smaller cache?
+  //
+  // The resolve APIs allow targets to override how these decisions
+  // are made.  If multiple answers for a query are possible, the
+  // target is given a list of matching resources and it may sort how
+  // how to answer the question.
+
+  /// If caches at a particular level are of different sizes, ask the
+  /// target what to do.  By default, return zero.
+  ///
+  virtual Optional<unsigned>
+  resolveCacheSize(unsigned Level,
+                   const MCSystemModel::CacheLevelList &Levels) const {
+    return Optional<unsigned>(0);
+  }
+
+  /// If caches at a particular level are of different
+  /// associativities, ask the target what to do.  By default, return
+  /// one.
+  ///
+  virtual Optional<unsigned>
+  resolveCacheAssociativity(unsigned Level,
+                            const MCSystemModel::CacheLevelList &Levels) const {
+    return Optional<unsigned>(1);
+  }
+
+  /// If cache lines at a particular level are of different sizes, ask
+  /// the target what to do.  By default, return zero.
+  ///
+  virtual Optional<unsigned>
+  resolveCacheLineSize(unsigned Level,
+                       const MCSystemModel::CacheLevelList &Levels) const {
+    return Optional<unsigned>(0);
+  }
+
+  /// If prefetcher configs report differences on whether they are
+  /// enabled for reads, ask the target what to do.  By default,
+  /// return the first enable/disable setting we find.
+  ///
+  virtual bool resolvePrefetchReads(
+    const MCSystemModel::PrefetchConfigList &Prefetchers) const {
+    return (*Prefetchers.begin())->isEnabledForReads();
+  }
+
+  /// If prefetcher configs report differences on whether they are
+  /// enabled for writes, ask the target what to do.  By default,
+  /// return the first enable/disable setting we find.
+  ///
+  virtual bool resolvePrefetchWrites(
+    const MCSystemModel::PrefetchConfigList &Prefetchers) const {
+    return (*Prefetchers.begin())->isEnabledForWrites();
+  }
+
+  /// If prefetcher configs report different distances, ask the target
+  /// what to do.  By default, return the first distance we find.
+  ///
+  virtual unsigned resolvePrefetchDistanceInInstructions(
+    const MCSystemModel::PrefetchConfigList &Prefetchers) const {
+    return (*Prefetchers.begin())->getDistanceInInstructions();
+  }
+
+  /// If prefetcher configs report different max distances, ask the
+  /// target what to do.  By default, return the first distance we
+  /// find.
+  ///
+  virtual unsigned resolveMaxPrefetchIterationsAhead(
+    const MCSystemModel::PrefetchConfigList &Prefetchers) const {
+    return (*Prefetchers.begin())->getMaxDistanceInIterations();
+  }
+
+  /// If prefetcher configs report different min strides, ask the
+  /// target what to do.  By default, return the first stride we find.
+  ///
+  virtual unsigned resolveMinPrefetchStride(
+    const MCSystemModel::PrefetchConfigList &Prefetchers) const {
+    return (*Prefetchers.begin())->getMinByteStride();
+  }
+
 public:
   MCSubtargetInfo(const MCSubtargetInfo &) = default;
   MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
                   ArrayRef<SubtargetFeatureKV> PF,
                   ArrayRef<SubtargetSubTypeKV> PD,
                   const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
                   const MCReadAdvanceEntry *RA, const InstrStage *IS,
                   const unsigned *OC, const unsigned *FP);
resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
     return 0;
   }
 
   /// Check whether the CPU string is valid.
   bool isCPUStringValid(StringRef CPU) const {
     auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
     return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
   }
+
+  /// Get the system model of a CPU.
+  const MCSystemModel &getSystemModelForCPU(StringRef CPU) const;
+
+  /// Get the system model for this subtarget's CPU.
+  const MCSystemModel &getSystemModel() const { return *CPUSystemModel; }
+
+  /// Return the cache size in bytes for the given level of cache.
+  /// Level is zero-based, so a value of zero means the first level of
+  /// cache.  If the size at the level is ambiguous (for example,
+  /// there are two different types of cores with different L1 sizes),
+  /// ask the target what to do via resolveCacheSize.
+  ///
+  virtual Optional<unsigned> getCacheSize(unsigned Level) const;
+
+  /// Return the cache associatvity for the given level of cache.
+  /// Level is zero-based, so a value of zero means the first level of
+  /// cache.  If the associativity at the level is ambiguous (for
+  /// example, there are two different types of cores with different
+  /// L1 associativities), ask the target what to do via
+  /// resolveCacheAssociativity.
+  ///
+  virtual Optional<unsigned> getCacheAssociativity(unsigned Level) const;
+
+  /// Return the target cache line size in bytes at a given level.  If
+  /// there are multiple such caches with different sizes, ask the
+  /// target what to do via resolveCacheLineSize.
+  ///
+  virtual Optional<unsigned> getCacheLineSize(unsigned Level) const;
+
+  /// Return the target cache line size in bytes.  By default, return
+  /// the line size for the bottom-most level of cache.  This provides
+  /// a more convenient interface for the common case where all cache
+  /// levels have the same line size.  Return zero if there is no
+  /// cache model.
+  ///
+  virtual unsigned getCacheLineSize() const {
+    Optional<unsigned> Size = getCacheLineSize(0);
+    if (Size)
+      return *Size;
+
+    return 0;
+  }
+
+  /// Return whether we should do software prefetching for loads on
+  /// this target.
+  ///
+  virtual bool shouldPrefetchReads() const;
+
+  /// Return whether we should do software prefetching for stores on
+  /// this target.
+  ///
+  virtual bool shouldPrefetchWrites() const;
+
+  /// Return the preferred prefetch distance in terms of instructions.
+  /// Return the prefetch config for the topmost memory model that has
+  /// a prefetcher.  If there are multiple such models with different
+  /// prefetching configs, return 0.  The target will have to override
+  /// this to do the right thing.
+  ///
+  virtual unsigned getPrefetchDistance() const;
+
+  /// Return the maximum prefetch distance in terms of loop
+  /// iterations.  Return the prefetch config for the topmost memory
+  /// model that has a prefetcher.  If there are multiple such models
+  /// with different prefetching configs, return 0.  The target will
+  /// have to override this to do the right thing.
+  ///
+  virtual unsigned getMaxPrefetchIterationsAhead() const;
+
+  /// Return the minimum stride necessary to trigger software
+  /// prefetching.  Return the prefetch config for the topmost memory
+  /// model that has a prefetcher.  If there are multiple such models
+  /// with different prefetching configs, return 0.  The target will
+  /// have to override this to do the right thing.
+  ///
+  virtual unsigned getMinPrefetchStride() const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_MC_MCSUBTARGETINFO_H

llvm/include/llvm/MC/MCSystemModel.h

+//=== MC/MCSystemModel.h - Target System Model --------------*- C++ -*-=======//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes an abstract interface used to get information
+// about a target machine's execution engine, including core
+// specifications, memory models and other things related to execution
+// resources.
+//
+// A system model is a collection of execution resources along with a
+// memory model.  Execution resources may describe things like
+// sockets, cores and hardware threads.  A memory model describes the
+// cache heirarchy private to each execution resource as well as
+// available write-combining buffers and a software prefetching
+// configuration.
+//
+// For example, imagine we're describing a system like this:
+//
+// 1 Socket
+// 48 cores per socket
+// 4 threads per core
+// 32K per-core L1 cache
+// 1M per-core L2 cache
+// 32M socket-level L3 cache
+// A software prefetcher
+// 8 write-combining buffers
+//
+// Then the system model may look something like this:
+//
+//                        System ---------------------.
+//                          |                         |
+//                     1 x "Socket" - "L3" 32M      <-|
+//                          |         8 x "WCBuf"     |
+//                          |                         |
+//                     48 x "Core"  - "L2" 1M       <-|
+//                          |         "L1" 32L      <-|
+//                          |         "Prefetcher"  <-'
+//                          |            Distance: 800 bytes
+//                     4 x "Thread"
+//
+// The pieces to the right of the execution resource make up the
+// memory model.
+//
+// Note how at the system level we can see the global view of the
+// cache hierarchy as well as any software prefetcher configs.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MC_MCSYSTEMMODEL_H
+#define LLVM_MC_MCSYSTEMMODEL_H
+
+#include "llvm/ADT/iterator.h"
+#include "llvm/ADT/SmallVector.h"
+
+#include <cassert>
+
+namespace llvm {
+
+/// Provide information about write-combining buffers.  These are
+/// typically used by hardware to buffer non-temporal stores for
+/// efficient data streaming.  Each buffer expects a more-or-less
+/// linear stream of writes.  A write outside the current cache line
+/// being filled causes the buffer to flush, so software should not
+/// oversubscribe the available hardware resources.  If it does, in
+/// the worst case bufffers will thrash and flush after each write, as
+/// each address sent will map to a cache line outside those currently
+/// being filled.  For example, assuming hardware has two buffers,
+/// streaming arrays A and B in the following loop is fine, as writes
+/// to A will map to, say, buffer 0 and writes to B will map to buffer
+/// 1.  If C were also streamed, in the worst case its writes would
+/// ping-pong between buffers 0 and 1, flushing one or the other after
+/// each write to C, degrading the streaming of A and B.
+///
+/// do {
+///   A[i] = ...
+///   B[i] = ...
+///   C[i] = ...
+/// } while(i < Something);
+class MCWriteCombiningBufferInfo {
+private:
+  unsigned ID;
+  const char *Name;
+  const int NumBuffers;  // The number of write-commbining buffers
+
+public:
+  MCWriteCombiningBufferInfo(unsigned I, const char *TheName, int NumBufs)
+      : ID(I), Name(TheName), NumBuffers(NumBufs) {}
+
+  virtual ~MCWriteCombiningBufferInfo();
+
+  /// Return the buffer ID number.
+  ///
+  unsigned getID() const { return ID; }
+
+  /// Return the buffer name for debugging.
+  ///
+  const char *getName() const { return Name; }
+
+  /// Return the number of available write-combining buffers.
+  ///
+  int getNumBuffers() const { return NumBuffers; }
+};
+
+/// MCSoftwarePrefetcherConfig - Provide information about how to
+/// configure the software prefetcher.
+class MCSoftwarePrefetcherConfig {
+private:
+  unsigned ID;
+  const char *Name;
+  const bool EnabledForReads;
+  const bool EnabledForWrites;
+  const unsigned BytesAhead;
+  const unsigned MinBytesAhead;
+  const unsigned MaxBytesAhead;
+  const unsigned InstructionsAhead;
+  const unsigned MaxIterationsAhead;
+  const unsigned MinByteStride;
+
+public:
+  MCSoftwarePrefetcherConfig(unsigned I,
+                             const char *TheName,
+                             bool EnableForReads,
+                             bool EnableForWrites,
+                             unsigned NumBytesAhead,
+                             unsigned MinNumBytesAhead,
+                             unsigned MaxNumBytesAhead,
+                             unsigned NumInstructionsAhead,
+                             unsigned MaxNumIterationsAhead,
+                             unsigned MinStride)
+      : ID(I),
+        Name(TheName),
+        EnabledForReads(EnableForReads),
+        EnabledForWrites(EnableForWrites),
+        BytesAhead(NumBytesAhead),
+        MinBytesAhead(MinNumBytesAhead),
+        MaxBytesAhead(MaxNumBytesAhead),
+        InstructionsAhead(NumInstructionsAhead),
+        MaxIterationsAhead(MaxNumIterationsAhead),
+        MinByteStride(MinStride) {}
+
+  virtual ~MCSoftwarePrefetcherConfig();
+
+  /// Return the prefetch config ID number.
+  ///
+  unsigned getID() const { return ID; }
+
+  /// Return the prefetch config name for debugging.
+  ///
+  const char *getName() const { return Name; }
+
+  /// Return whether we should do software prefetching for loads.
+  ///
+  bool isEnabledForReads() const { return EnabledForReads; }
+
+  /// Return whether we should do software prefetching for stores.
+  ///
+  bool isEnabledForWrites() const { return EnabledForWrites; }
+
+  /// Return the preferred prefetch distance in bytes.  A value of 0
+  /// tells the software prefetcher to determine distance using
+  /// heuristics.
+  unsigned getDistanceInBytes() const { return BytesAhead; }
+
+  /// Never prefetch less that this number of bytes ahead.
+  unsigned getMinDistanceInBytes() const { return MinBytesAhead; }
+
+  /// Never prefetch more that this number of bytes ahead.
+  unsigned getMaxDistanceInBytes() const { return MaxBytesAhead; }
+
+  /// Return the preferred prefetch distance in terms of number of
+  /// instructions.
+  unsigned getDistanceInInstructions() const { return InstructionsAhead; }
+
+  /// Never prefetch more than this number of loop iterations ahead.
+  unsigned getMaxDistanceInIterations() const { return MaxIterationsAhead; }
+
+  /// Prefetch only if the byte stride is at least this large.
+  unsigned getMinByteStride() const { return MinByteStride; }
+};
+
+/// Provide information about a specific level in the cache (size,
+/// associativity, etc.).
+class MCCacheLevelInfo {
+private:
+  unsigned ID;
+  const char *Name;
+  const unsigned Size;     // Size of cache in bytes
+  const unsigned LineSize; // Size of cache line in bytes
+  const unsigned Ways;     // Number of ways
+  const unsigned Latency;  // Number of cycles to load
+
+public:
+  MCCacheLevelInfo(unsigned I,
+                   const char *TheName,
+                   uint64_t TotalSize,
+                   unsigned TheLineSize,
+                   unsigned NumWays,
+                   unsigned TheLatency)
+      : ID(I),
+        Name(TheName),
+        Size(TotalSize),
+        LineSize(TheLineSize),
+        Ways(NumWays),
+        Latency(TheLatency) {}
+
+  virtual ~MCCacheLevelInfo();
+
+  /// Return the register class ID number.
+  ///
+  unsigned getID() const { return ID; }
+
+  /// Return the register class name for debugging.
+  const char *getName() const { return Name; }
+
+  /// Return the total size of the cache level in bytes.
+  uint64_t getSizeInBytes() const { return Size; }
+
+  /// Return the size of the cache line in bytes.
+  unsigned getLineSizeInBytes() const { return LineSize; }
+
+  /// Return the number of ways.
+  unsigned getAssociativity() const { return Ways; }
+
+  /// Return the latency of a load in clocks.
+  unsigned getLatency() const { return Latency; }
+};
+
+
+/// Aggregate some number of cache levels together along with a
+/// software prefetching configuration and write-combining buffer
+/// information into a model of the memory system as viewed from a
+/// particular execution resource.  For example, a core my have L1 and
+/// L2 caches private to it, while a socket may have an L3 shared by
+/// all cores contained by the socket.  The core memory model will
+/// list L1 and L2 and the socket memory model will list L3.
+class MCMemoryModel {
+public:
+  typedef const MCCacheLevelInfo *cachelevel_iterator;
+
+private:
+  unsigned IDNum;
+  const char *Name;
+
+  const MCCacheLevelInfo *Levels;  // Array of cache levels
+  unsigned NumLevels;              // Number of cache levels
+  // Write-combining buffer information
+  const MCWriteCombiningBufferInfo &WCBuffers;
+  // Software prefetching config
+  const MCSoftwarePrefetcherConfig &SoftwarePrefetcher;
+
+public:
+  MCMemoryModel(unsigned I,
+                const char *TheName,
+                const MCCacheLevelInfo *CacheLevels,
+                unsigned NumCacheLevels,
+                const MCWriteCombiningBufferInfo &WCBufs,
+                const MCSoftwarePrefetcherConfig &PrefetcherConfig)
+      : IDNum(I),
+        Name(TheName),
+        Levels(CacheLevels),
+        NumLevels(NumCacheLevels),
+        WCBuffers(WCBufs),
+        SoftwarePrefetcher(PrefetcherConfig) {}
+
+  virtual ~MCMemoryModel();
+
+  /// Return the memory model ID number.
+  unsigned getID() const { return IDNum; }
+
+  /// Return the memory model name for debugging.
+  const char *getName() const { return Name; }
+
+  //===--------------------------------------------------------------------===//
+  // Cache Level Information
+
+  /// Index the hierarchy for a cache level.  Note that this is a
+  /// piece of the global cache hierarchy private to the execution
+  /// resource using the memory model, and shared by any contained
+  /// execution resources.  As such "level 0" (or level 1, etc.) has
+  /// no correspondence to a global-view cache level.  Thus names like
+  /// "L1" aren't very useful.
+  const MCCacheLevelInfo &getCacheLevel(unsigned Level) const {
+    assert(Level < NumLevels &&
+           "Attempting to access record for invalid cache level!");
+    return Levels[Level];
+  }
+
+  /// Return the number of cache levels.
+  unsigned getNumCacheLevels() const {
+    return NumLevels;
+  }
+
+  /// Cache level iterators
+  cachelevel_iterator begin() const { return Levels; }
+  cachelevel_iterator end() const {
+    return Levels + getNumCacheLevels();
+  }
+
+  //===--------------------------------------------------------------------===//
+  // Write Combining  Buffer Information
+
+  /// Return the write combining buffer info.
+  const MCWriteCombiningBufferInfo &getWCBufferInfo() const {
+    return WCBuffers;
+  }
+
+  //===--------------------------------------------------------------------===//
+  // Software Prefetcher Configuration
+
+  /// Return the software prefetcher configuration.
+  const MCSoftwarePrefetcherConfig &getSoftwarePrefetcherConfig() const {
+    return SoftwarePrefetcher;
+  }
+};
+
+class MCExecutionResource;
+
+/// Provide information about the number of execution resources of a
+/// given type are contained within an execution resource.  For example
+/// at the socket level there may be a core resource descriptor specifying
+/// that the socket has 48 cores.
+///
+/// MCExecutionResourceDesc exists so that we don't need to
+/// instantiate multiple independent, equivalent MCExecutionResources.
+/// If we're modeling a socket with 48 cores each having four threads,
+/// we would not want to instantiate 192 entirely equivalent objects
+/// to describe the threads.  Instead we instantiate one
+/// MCExecutionResourceDesc desribing 48 cores containing one
+/// MCExecutionResourceDesc describing four threads.
+class MCExecutionResourceDesc {
+  unsigned ID;
+  const char *Name;
+  const MCExecutionResource *Resource;  // The described resource
+  unsigned NumResources;                // The resource count
+
+public:
+  MCExecutionResourceDesc(unsigned I,
+                          const char *TheName,
+                          const MCExecutionResource *R,
+                          unsigned N)
+      : ID(I), Name(TheName), Resource(R), NumResources(N) {}
+
+  /// Return the resource descriptor ID number.
+  unsigned getID() const { return ID; }
+
+  /// Return the resource descriptor name for debugging.
+  const char *getName() const { return Name; }
+
+  /// Get the resource.
+  const MCExecutionResource &getResource() const {
+    return *Resource;
+  }
+
+  /// Get the number of resources represented by this descriptor.
+  unsigned getNumResources() const {
+    return NumResources;
+  }
+};
+
+/// Provide information about a specific kind of execution resource
+/// (core, thread, etc.).  A resource contains a memory model
+/// describing the pieces of the memory heirarchy private to it.  For
+/// example a core may contain two levels of private cache and the
+/// socket containing the cores may contain one level of cache private
+/// to it.
+///
+/// An MCExecutionResource may contain MCExecutionResourceDescs
+/// describing child resources.  For example, a core may contain four
+/// hardware threads.
+class MCExecutionResource {
+  unsigned ID;
+  const char *Name;
+
+  /// An array of execution resource desciptors, allowing an execution
+  /// resource to contain a variety of resources; for example a socket
+  /// containing some number of big cores and some number of little
+  /// cores
+  const MCExecutionResourceDesc *const *Contained;
+
+  /// The number of unique contained execution resource types
+  unsigned NumContained;
+
+  /// The memory model for this execution resource
+  const MCMemoryModel &MemoryModel;
+
+public:
+
+  using resource_iterator =
+    pointee_iterator<const MCExecutionResourceDesc *const *>;
+
+  MCExecutionResource(unsigned I,
+                      const char *TheName,
+                      const MCExecutionResourceDesc *const *C,
+                      unsigned NC,
+                      const MCMemoryModel &M)
+      : ID(I), Name(TheName), Contained(C), NumContained(NC), MemoryModel(M) {}
+
+  virtual ~MCExecutionResource();     // Allow subclasses
+
+  /// Return the resource ID number.
+  unsigned getID() const { return ID; }
+
+  /// Return the resource name for debugging.
+  const char *getName() const { return Name; }
+
+  /// Return the memory model for this resource.
+  const MCMemoryModel &getMemoryModel() const {
+    return MemoryModel;
+  }
+
+  /// Return the number of unique execution resource types contained
+  /// within this one.
+  unsigned getNumContainedExecutionResourceTypes() const {
+    return NumContained;
+  }
+
+  /// Iterate over unique contained resources.
+  resource_iterator begin() const {
+    return resource_iterator(Contained);
+  }
+  resource_iterator end() const {
+    return resource_iterator(Contained + NumContained);
+  }
+
+  /// Get the resrouce descriptor indexed by the given value.
+  const MCExecutionResourceDesc &getResourceDescriptor(unsigned Index) const {
+    assert(Index < getNumContainedExecutionResourceTypes() &&
+           "Overindexing resource descriptors!");
+    return *Contained[Index];
+  }
+};
+
+/// Model a collection of execution resources coupled with other
+/// information.  This also aggregates information about the resource
+/// memory models, presenting a global system view of memory
+/// characteristics.
+///
+/// An MCSystemModel is simply a collection of
+/// MCExecutionResourceDescs along with a cache model and software
+/// prefetcher configuration.  The MCExecutionResourceDescs describe
+/// hardware execution resources, such as sockets, cores and threads.
+/// What exactly an "execution resource" means is entirely up to the
+/// target.
+class MCSystemModel {
+  unsigned ID;
+  const char *Name;
+
+  /// An array of execution resource descriptor pointers
+  const MCExecutionResourceDesc *const *Resources;
+  unsigned NumResources;  /// Number of entries in the array
+
+  static const MCSystemModel Default;
+
+public:
+  // Caches of information about execution resources and their memory
+  // models.
+
+  // Make the cache topology indexable by level.  The bottom-most
+  // cache level of each resource makes up level zero.  For example:
+  //
+  //  Thread
+  //     |
+  //  Big Core  Little Core
+  //          \/
+  //        Socket
+  //
+  // If the big core has an L1 and L2 cache, the little core has an L1
+  // cache and the socket has an L3 cache, the big and little L1s go
+  // into the L1 set, the big core L2 goes into the L2 set and the
+  // socket L3 goes into the L3 set.
+
+  using CacheLevelList = SmallVector<const MCCacheLevelInfo *, 4>;
+
+private:
+  using CacheLevelInfo = SmallVector<CacheLevelList, 4>;
+  CacheLevelInfo CacheLevels;
+
+  /// Cache information about caches on an as-needed basis.
+  void initCacheInfoCache();
+
+public:
+  using PrefetchConfigList = SmallVector<const MCSoftwarePrefetcherConfig *, 4>;
+
+private:
+  PrefetchConfigList Prefetchers;
+
+  /// Cache information about prefetchers on an as-needed basis.
+  void initPrefetchConfigCache();
+
+public:
+  /// Convenience values for indexing the global-view cache hierarchy.
+  enum CacheLevel {
+    L1 = 0,
+    L2,
+    L3,
+    L4
+  };
+
+  using resource_iterator =
+    pointee_iterator<const MCExecutionResourceDesc *const *>;
+
+  MCSystemModel(unsigned I,
+                const char *TheName,
+                const MCExecutionResourceDesc *const *R,
+                unsigned NR)
+      : ID(I), Name(TheName), Resources(R), NumResources(NR) {
+    initCacheInfoCache();
+    initPrefetchConfigCache();
+  }
+
+  virtual ~MCSystemModel();
+
+  /// Return the default initialized model.
+  static const MCSystemModel &getDefaultSystemModel() {
+    return Default;
+  }
+
+  /// Return the execution engine ID number.
+  unsigned getID() const { return ID; }
+
+  /// Return the execution engine name for debugging.
+  const char *getName() const { return Name; }
+
+  /// Return the number of unique execution resource types.
+  unsigned getNumExecutionResourceTypes() const {
+    return NumResources;
+  }
+
+  /// Iterate over top-level execution resources.
+  resource_iterator begin() const {
+    return resource_iterator(Resources);
+  }
+  resource_iterator end() const {
+    return resource_iterator(Resources + NumResources);
+  }
+
+  /// Get the resource descriptor indexed by the given value.
+  const MCExecutionResourceDesc &getResourceDescriptor(unsigned Index) const {
+    assert(Index < getNumExecutionResourceTypes() &&
+           "Overindexing resource descriptors!");
+    return *Resources[Index];
+  }
+
+  /// Retrieve cached information about cache levels.
+  const CacheLevelList *getCacheLevelInfo(unsigned Level) const {
+    if (Level >= CacheLevels.size()) {
+      return nullptr;
+    }
+
+    return &CacheLevels[Level];
+  }
+
+  /// Retrieve cached information about prefetchers.
+  const PrefetchConfigList &getSoftwarePrefetcherInfo() const {
+    return Prefetchers;
+  }
+};
+
+} // End llvm namespace
+
+#endif

llvm/include/llvm/Target/Target.td

 
 /// A custom predicate used to determine if an instruction is
 /// deprecated or not.
 class ComplexDeprecationPredicate<string dep> {
   string ComplexDeprecationPredicate = dep;
 }
 
 //===----------------------------------------------------------------------===//
+// Pull in the common support for execution engine generation.
+//
+include "llvm/Target/TargetSystemModel.td"
+
+//===----------------------------------------------------------------------===//
 // Processor chip sets - These values represent each of the chip sets supported
 // by the scheduler.  Each Processor definition requires corresponding
 // instruction itineraries.
 //
 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
   // Name - Chip set name.  Used by command line (-mcpu=) to determine the
   // appropriate target chip.
   //
   string Name = n;
 
   // SchedModel - The machine model for scheduling and instruction cost.
   //
   SchedMachineModel SchedModel = NoSchedModel;
 
+  // System - A system model describing execution resources and
+  // the machine memory model.
+  SystemModel System = MinimalSystemModel;
+
   // ProcItin - The scheduling information for the target processor.
   //
   ProcessorItineraries ProcItin = pi;
 
   // Features - list of
   list<SubtargetFeature> Features = f;
 }
 

llvm/include/llvm/Target/TargetCacheModel.td

+//===- TargetCacheModel.td - Target cache information----------*- tablegen -*-//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// This represents a specific level within the cache hierarchy.
+//===----------------------------------------------------------------------===//
+class Size<int s>     : Int<s>;
+class Ways<int w>     : Int<w>;
+class LineSize<int l> : Int<l>;
+class Latency<int t>  : Int<t>;
+
+class CacheLevel<Size size, LineSize linesize, Ways ways, Latency latency> {
+  int Size = size.Value;
+  int LineSize = linesize.Value;
+  int Ways = ways.Value;
+  int Latency = latency.Value;
+}
+
+def NoCacheLevel : CacheLevel<Size<0>, LineSize<0>, Ways<0>, Latency<0>>;
+
+//===----------------------------------------------------------------------===//
+// This models a specific cache hierarchy.  Levels should be given in order
+// from lowest to highest (e.g. L1, then L2...).
+//===----------------------------------------------------------------------===//
+class CacheHierarchy<list<CacheLevel> levels> {
+  list<CacheLevel> Levels = levels;
+}
+
+def NoCaches : CacheHierarchy<[]>;
+
+//===----------------------------------------------------------------------===//
+// Provide some common cache sizes.
+//===----------------------------------------------------------------------===//
+def _1KiB   : Int<1024>;
+def _16KiB  : Int<!shl(_1KiB.Value, 4)>;
+def _32KiB  : Int<!shl(_16KiB.Value, 1)>;
+def _64KiB  : Int<!shl(_32KiB.Value, 1)>;
+def _128KiB : Int<!shl(_64KiB.Value, 1)>;
+def _256KiB : Int<!shl(_128KiB.Value, 1)>;
+def _512KiB : Int<!shl(_256KiB.Value, 1)>;
+def _1MiB   : Int<!shl(_512KiB.Value, 1)>;
+def _2MiB   : Int<!shl(_1MiB.Value, 1)>;
+def _4MiB   : Int<!shl(_2MiB.Value, 1)>;
+def _6MiB   : Int<!add(_2MiB.Value, _4MiB.Value)>;
+def _8MiB   : Int<!shl(_4MiB.Value, 1)>;
+def _12MiB  : Int<!add(_8MiB.Value, _4MiB.Value)>;
+def _16MiB  : Int<!shl(_8MiB.Value, 1)>;
+def _20MiB  : Int<!add(_16MiB.Value, _4MiB.Value)>;
+def _25MiB  : Int<!add(_20MiB.Value, !add(_4MiB.Value, _1MiB.Value))>;
+def _32MiB  : Int<!shl(_16MiB.Value, 1)>;
+def _40MiB  : Int<!add(_32MiB.Value, _8MiB.Value)>;

llvm/include/llvm/Target/TargetMemoryModel.td

+//===- TargetMemoryModel.td - Target memory system information-*- tablegen -*-//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the target-independent memory hiearchy interfaces which
+// should be implemented by each target that makes use of such information.
+//
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/TargetCacheModel.td"
+include "llvm/Target/TargetWCBufferModel.td"
+include "llvm/Target/TargetSoftwarePrefetchConfig.td"
+
+//===----------------------------------------------------------------------===//
+// MemorySystem - This models a memory subsystem.
+//===----------------------------------------------------------------------===//
+class MemoryModel<CacheHierarchy c,
+                  WriteCombiningBuffer w,
+                  SoftwarePrefetcher p> {
+  CacheHierarchy Caches = c;
+  WriteCombiningBuffer WCBuffers = w;
+  SoftwarePrefetcher Prefetcher = p;
+}
+
+// For execution resources that really don't have a memory model.
+//
+def NoMemoryModel : MemoryModel<NoCaches,
+                                NoWCBuffers,
+                                NoSoftwarePrefetcher>;
+
+//===----------------------------------------------------------------------===//
+// Define the minimal memory model needed to implement legacy TTI interfaces.
+//===----------------------------------------------------------------------===//
+def MinimalMemoryModel : MemoryModel<NoCaches,
+                                     NoWCBuffers,
+                                     TransitionSoftwarePrefetcher>;

llvm/include/llvm/Target/TargetSoftwarePrefetchConfig.td

+//===- TargetSoftwarePrefetchConfig.td - Target prefetch info--*- tablegen -*-//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// SoftwarePrefetcher - This provides parameters to software prefetching.
+//===----------------------------------------------------------------------===//
+class IsReadEnabled<int v>         : Int<v>;
+class IsWriteEnabled<int v>        : Int<v>;
+class ByteDistance<int d>          : Int<d>;
+class MinByteDistance<int d>       : Int<d>;
+class MaxByteDistance<int d>       : Int<d>;
+class InstructionDistance<int d>   : Int<d>;
+class MaxIterationDistance<int d>  : Int<d>;
+class MinByteStride<int s>         : Int<s>;
+
+// Describe a software prefetching configuration.  The current
+// LoopDataPrefetcher thinks of distance in terms of prefetching some
+// number of instructions ahead.  Other prefetchers may want to think
+// about distance in terms of bytes ahead or number of loop iterations
+// ahead.  Still other prefetchers may want to use a heuristic to
+// determine distance, in which case the distance values below can be set
+// to zero.
+class SoftwarePrefetcher<IsReadEnabled re,
+                         IsWriteEnabled we,
+                         ByteDistance bd,
+                         MinByteDistance bnd,
+                         MaxByteDistance bxd,
+                         InstructionDistance id,
+                         MaxIterationDistance ixd,
+                         MinByteStride ns> {
+  int EnabledForReads = re.Value;      // Do prefetching for loads.
+  int EnabledForWrites = we.Value;     // Do prefetching for stores.
+  int BytesAhead = bd.Value;           // Average "good" prefetch distance.  Set
+                                       // to zero to tell the prefetcher to use
+                                       // heuristics to determine an appropriate
+                                       // distance.
+  int MinBytesAhead = bnd.Value;       // Don't prefetch anything less than this
+                                       // far ahead.
+  int MaxBytesAhead = bxd.Value;       // Don't prefetch anything more than this
+                                       // far ahead.
+  int InstructionsAhead = id.Value;    // Prefetch this many instructions ahead,
+                                       // used by prefetchers that operate in
+                                       // terms of instruction distance rather
+                                       // than bytes.
+  int MaxIterationsAhead = ixd.Value;  // Don't prefetch more than this number
+                                       // of iterations ahead.  Used by
+                                       // prefetchers that operate in terms of
+                                       // iteration distance rather than
+                                       // bytes.
+  int MinStride = ns.Value;            // Don't prefetch unless stride is at
+                                       // least this large.
+}
+
+
+def ReadEnabled  : IsReadEnabled<1>;
+def ReadDisabled : IsReadEnabled<0>;
+
+def WriteEnabled  : IsWriteEnabled<1>;
+def WriteDisabled : IsWriteEnabled<0>;
+
+def HeuristicByteDistance        : ByteDistance<0>;
+def HeuristicInstructionDistance : InstructionDistance<0>;
+
+def NoSoftwarePrefetcher : SoftwarePrefetcher<ReadDisabled,
+                                              WriteDisabled,
+                                              HeuristicByteDistance,
+                                              MinByteDistance<0>,
+                                              MaxByteDistance<0>,
+                                              HeuristicInstructionDistance,
+                                              MaxIterationDistance<0>,
+                                              MinByteStride<0>>;
+
+// This is for targets that define some aspects of prefetching in
+// target-specific TTI.  Until such targets are ported to the system
+// model, they should continue to work as they do now.  Once the porting
+// is complete, TransitionSoftwarePrefetcher use should migrate to
+// NoSoftwarePrefetcher or to the appropriate target-defined software
+// prefetch configuration.
+//
+def TransitionSoftwarePrefetcher :
+     SoftwarePrefetcher<ReadEnabled,
+                        WriteEnabled,
+                        HeuristicByteDistance,
+                        MinByteDistance<0>,
+                        MaxByteDistance<0>,
+                        HeuristicInstructionDistance,
+                        // Legacy TTI used UINT_MAX, which isn't available in
+                        // TableGen.  Approximate it with some thing that will
+                        // work on 32-bit hosts.
+                        MaxIterationDistance<4294967295>,
+                        MinByteStride<1>>;

llvm/include/llvm/Target/TargetSystemModel.td

+//===- TargetSystemModel.td - Target Hardware Info --------*- tablegen -*-====//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the target-independent execution hardware available.  It
+// should be implemented by each target that makes use of such information.
+//
+//===----------------------------------------------------------------------===//
+
+
+//===----------------------------------------------------------------------===//
+// A convenience wrapper to hold an integer value for later consumption.
+// This is used to give names to common integer-y concepts like sizes
+// and flags.
+//===----------------------------------------------------------------------===//
+class Int<int value> {
+  int Value = value;
+}
+
+include "llvm/Target/TargetMemoryModel.td"
+
+class ExecutionResource;
+
+class ExecutionResourceDesc<ExecutionResource resource, int numresources> {
+  ExecutionResource Resource = resource;
+  int NumResources = numresources;
+}
+
+//===----------------------------------------------------------------------===//
+// This models a particular group of execution resources (threads, cores,
+// etc.), describing the relationship among them and their cache sharing
+// characteristics.
+//===----------------------------------------------------------------------===//
+class ExecutionResource<list<ExecutionResourceDesc> contained,
+                        MemoryModel memmodel> {
+  list<ExecutionResourceDesc> Contained = contained;
+  MemoryModel MemModel = memmodel;
+}
+
+//===----------------------------------------------------------------------===//
+// Define some common execution resources, mainly for readability.
+//===----------------------------------------------------------------------===//
+class Thread : ExecutionResource<[], NoMemoryModel>;
+class Core<list<ExecutionResourceDesc> contained,
+           MemoryModel memmodel> :
+      ExecutionResource<contained, memmodel>;
+class Socket<list<ExecutionResourceDesc> contained,
+       MemoryModel memmodel> :
+      ExecutionResource<contained, memmodel>;
+
+//===----------------------------------------------------------------------===//
+// This models a collection of execution resources as well as the machine
+// memory model.
+//===----------------------------------------------------------------------===//
+class SystemModel<list<ExecutionResourceDesc> resources> {
+  list<ExecutionResourceDesc> Resources = resources;
+}
+
+//===----------------------------------------------------------------------===//
+// Define the minimal execution engine needed to implement legacy TTI
+// interfaces.
+//===----------------------------------------------------------------------===//
+def MinimalCore : Core<[], MinimalMemoryModel>;
+
+def MinimalCoreResourceDesc : ExecutionResourceDesc<MinimalCore, 1>;
+
+def MinimalSystemModel : SystemModel<[MinimalCoreResourceDesc]>;

llvm/include/llvm/Target/TargetWCBufferModel.td

+//===- TargetWCBufferModel.td - Target buffer information------*- tablegen -*-//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// WriteCombiningBuffer - This models hardware buffers that combine
+//                        writes into a single transaction.  Typically
+//                        these are used for non-temporal store operations.
+//
+// NumBuffers        - The number of effective buffers available.
+//===----------------------------------------------------------------------===//
+class WriteCombiningBuffer<int n> {
+  int NumBuffers = n;
+}
+
+def NoWCBuffers : WriteCombiningBuffer<0>;

llvm/lib/Analysis/TargetTransformInfo.cpp

llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
   return TTIImpl->getCacheSize(Level);
 }
 
 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
   CacheLevel Level) const {
   return TTIImpl->getCacheAssociativity(Level);
 }
 
+bool TargetTransformInfo::shouldPrefetchReads() const {
+  return TTIImpl->shouldPrefetchReads();
+}
+
+bool TargetTransformInfo::shouldPrefetchWrites() const {
+  return TTIImpl->shouldPrefetchWrites();
+}
+
 unsigned TargetTransformInfo::getPrefetchDistance() const {
   return TTIImpl->getPrefetchDistance();
 }
 
 unsigned TargetTransformInfo::getMinPrefetchStride() const {
   return TTIImpl->getMinPrefetchStride();
 }
 

llvm/lib/MC/CMakeLists.txt

add_llvm_library(LLVMMC
   MCSectionCOFF.cpp
   MCSectionELF.cpp
   MCSectionMachO.cpp
   MCSectionWasm.cpp
   MCStreamer.cpp
   MCSubtargetInfo.cpp
   MCSymbol.cpp
   MCSymbolELF.cpp
+  MCSystemModel.cpp
   MCTargetOptions.cpp
   MCValue.cpp
   MCWasmObjectTargetWriter.cpp
   MCWasmStreamer.cpp
   MCWin64EH.cpp
   MCWinCOFFStreamer.cpp
   MCWinEH.cpp
   MachObjectWriter.cpp

llvm/lib/MC/MCSubtargetInfo.cpp

 //===- MCSubtargetInfo.cpp - Subtarget Information ------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/MC/MCSystemModel.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 #include <cassert>
 #include <cstring>
else
       ApplyFeatureFlag(Bits, Feature, ProcFeatures);
   }
 
   return Bits;
 }
 
 void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
-  if (!CPU.empty())
+  if (!CPU.empty()) {
     CPUSchedModel = &getSchedModelForCPU(CPU);
-  else
+    CPUSystemModel = &getSystemModelForCPU(CPU);
+  }
+  else {
     CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
+    CPUSystemModel = &MCSystemModel::getDefaultSystemModel();
+  }
 }
 
 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
 }
 
 MCSubtargetInfo::MCSubtargetInfo(
     const Triple &TT, StringRef C, StringRef FS,
MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
   const MCSchedModel &SchedModel = getSchedModelForCPU(CPU);
   return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
 }
 
 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
   InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
                                   ForwardingPaths);
 }
+
+const MCSystemModel &
+MCSubtargetInfo::getSystemModelForCPU(StringRef CPU) const {
+  assert(std::is_sorted(ProcDesc.begin(), ProcDesc.end()) &&
+         "Processor machine model table is not sorted");
+
+  // Find entry
+  const SubtargetSubTypeKV *CPUEntry = Find(CPU, ProcDesc);
+
+  if (!CPUEntry) {
+    if (CPU != "help") // Don't error if the user asked for help.
+      errs() << "'" << CPU
+             << "' is not a recognized processor for this target"
+             << " (ignoring processor)\n";
+    return MCSystemModel::getDefaultSystemModel();
+  }
+
+  assert(CPUEntry->SystemModel && "Missing processor SystemModel value");
+  return *CPUEntry->SystemModel;
+}
+
+Optional<unsigned> MCSubtargetInfo::getCacheSize(unsigned Level) const {
+  const MCSystemModel::CacheLevelList *Levels =
+    getSystemModel().getCacheLevelInfo(Level);
+
+  if (Levels == nullptr) {
+    return Optional<unsigned>();
+  }
+
+  Optional<unsigned> Size;
+  for (const auto *LevelInfo : *Levels) {
+    if (!Size) {
+      Size = Optional<unsigned>(LevelInfo->getSizeInBytes());
+      continue;
+    }
+    if (LevelInfo->getSizeInBytes() != *Size)
+      // Cache at this level are of different sizes.
+      return resolveCacheSize(Level, *Levels);
+  }
+
+  return Size;
+}
+
+Optional<unsigned>
+MCSubtargetInfo::getCacheAssociativity(unsigned Level) const {
+  const MCSystemModel::CacheLevelList *Levels =
+    getSystemModel().getCacheLevelInfo(Level);
+
+  if (Levels == nullptr) {
+    return Optional<unsigned>();
+  }
+
+  Optional<unsigned> Associativity;
+  for (const auto *LevelInfo : *Levels) {
+    if (!Associativity) {
+      Associativity = Optional<unsigned>(LevelInfo->getAssociativity());
+      continue;
+    }
+    if (LevelInfo->getAssociativity() != *Associativity)
+      // Cache at this level are of different sizes.
+      return resolveCacheAssociativity(Level, *Levels);
+  }
+
+  return Associativity;
+}
+
+Optional<unsigned> MCSubtargetInfo::getCacheLineSize(unsigned Level) const {
+  const MCSystemModel::CacheLevelList *Levels =
+    getSystemModel().getCacheLevelInfo(Level);
+
+  if (Levels == nullptr) {
+    return Optional<unsigned>();
+  }
+
+  Optional<unsigned> Size;
+  for (const auto *LevelInfo : *Levels) {
+    if (!Size) {
+      Size = Optional<unsigned>(LevelInfo->getLineSizeInBytes());
+      continue;
+    }
+    if (LevelInfo->getLineSizeInBytes() != *Size)
+      return resolveCacheLineSize(Level, *Levels);
+  }
+
+  return Size;
+}
+
+bool MCSubtargetInfo::shouldPrefetchReads() const {
+  Optional<bool> Enabled;
+
+  const MCSystemModel::PrefetchConfigList &PrefetcherConfigs =
+    getSystemModel().getSoftwarePrefetcherInfo();
+
+  for (const auto *PrefetcherConfig : PrefetcherConfigs) {
+    if (!Enabled) {
+      Enabled = Optional<bool>(PrefetcherConfig->isEnabledForReads());
+      continue;
+    }
+    if (PrefetcherConfig->isEnabledForReads() != *Enabled)
+      return resolvePrefetchReads(PrefetcherConfigs);
+  }
+
+  return Enabled ? *Enabled : false;
+}
+
+bool MCSubtargetInfo::shouldPrefetchWrites() const {
+  Optional<bool> Enabled;
+
+  const MCSystemModel::PrefetchConfigList &PrefetcherConfigs =
+    getSystemModel().getSoftwarePrefetcherInfo();
+
+  for (const auto *PrefetcherConfig : PrefetcherConfigs) {
+    if (!Enabled) {
+      Enabled = Optional<bool>(PrefetcherConfig->isEnabledForWrites());
+      continue;
+    }
+    if (PrefetcherConfig->isEnabledForWrites() != *Enabled)
+      return resolvePrefetchWrites(PrefetcherConfigs);
+  }
+
+  return Enabled ? *Enabled : false;
+}
+
+unsigned MCSubtargetInfo::getPrefetchDistance() const {
+  Optional<unsigned> Distance;
+
+  const MCSystemModel::PrefetchConfigList &PrefetcherConfigs =
+    getSystemModel().getSoftwarePrefetcherInfo();
+
+  for (const auto *PrefetcherConfig : PrefetcherConfigs) {
+    if (!Distance) {
+      Distance =
+        Optional<unsigned>(PrefetcherConfig->getDistanceInInstructions());
+      continue;
+    }
+    if (PrefetcherConfig->getDistanceInInstructions() != *Distance)
+      return resolvePrefetchDistanceInInstructions(PrefetcherConfigs);
+  }
+
+  return Distance ? *Distance : 0;
+}
+
+unsigned MCSubtargetInfo::getMaxPrefetchIterationsAhead() const {
+  Optional<unsigned> Distance;
+
+  const MCSystemModel::PrefetchConfigList &PrefetcherConfigs =
+    getSystemModel().getSoftwarePrefetcherInfo();
+
+  for (const auto *PrefetcherConfig : PrefetcherConfigs) {
+    if (!Distance) {
+      Distance =
+        Optional<unsigned>(PrefetcherConfig->getMaxDistanceInIterations());
+      continue;
+    }
+    if (PrefetcherConfig->getMaxDistanceInIterations() != *Distance)
+      return resolveMaxPrefetchIterationsAhead(PrefetcherConfigs);
+  }
+
+  return Distance ? *Distance : 0;
+}
+
+unsigned MCSubtargetInfo::getMinPrefetchStride() const {
+  Optional<unsigned> Distance;
+
+  const MCSystemModel::PrefetchConfigList &PrefetcherConfigs =
+    getSystemModel().getSoftwarePrefetcherInfo();
+
+  for (const auto *PrefetcherConfig : PrefetcherConfigs) {
+    if (!Distance) {
+      Distance = Optional<unsigned>(PrefetcherConfig->getMinByteStride());
+      continue;
+    }
+    if (PrefetcherConfig->getMinByteStride() != *Distance)
+      return resolveMinPrefetchStride(PrefetcherConfigs);
+  }
+
+  return Distance ? *Distance : 0;
+}

llvm/lib/MC/MCSystemModel.cpp

+//=== MC/MCSystemModel.cpp - Target System Model ------------*- C++ -*-=======//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defioned MCSystemModel methods.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCSystemModel.h"
+#include <functional>
+
+namespace llvm {
+
+MCWriteCombiningBufferInfo::~MCWriteCombiningBufferInfo() {}
+MCSoftwarePrefetcherConfig::~MCSoftwarePrefetcherConfig() {}
+MCCacheLevelInfo::~MCCacheLevelInfo() {}
+MCMemoryModel::~MCMemoryModel() {}
+
+MCExecutionResource::~MCExecutionResource() {}
+MCSystemModel::~MCSystemModel() {}
+
+const MCSystemModel MCSystemModel::Default(0,
+                                           "Default System Model",
+                                           nullptr,
+                                           0);
+
+
+void MCSystemModel::initCacheInfoCache() {
+  // Create a global cache topology.  The tricky part is collapsing
+  // the execution resource levels properly.  For example, let's say
+  // we have a system with a CPU socket and a GPU socket.  The CPU
+  // socket contains two core types: big and little.  The CPUsocket
+  // contains an L3 cache, the big core contains and L2 and L1 cache
+  // and the little core contains an L1 cache.  The GPU socket
+  // contains shared L2 and L3 caches and GPU cores have a private L1
+  // cache:
+  //
+  //              System
+  //              /    \
+  //    (L2, L3) GPU   CPU (L3)
+  //              |   /     \
+  //         (L1) C  L (L1)  B (L1, L2)
+  //
+  // We want the final topology to look like this:
+  //
+  //          L3 (GPU) L3 (CPU)
+  //          L2 (GPU) L2 (B)
+  //          L1 (C) L1 (L) L1(B)
+  //
+  // The algorithm below recursively determines the topology for the
+  // resources below the current one, then merges the lists from all
+  // child resources so that it is no longer than the maximum size of
+  // any child list.  Child lists are ordered by cache level, so the
+  // lowest level of cache appears first.
+  //
+  auto mergeCacheInfo = [](const CacheLevelInfo &I1,
+                           const CacheLevelInfo &I2) -> CacheLevelInfo {
+    CacheLevelInfo Result;
+    unsigned Length = std::max(I1.size(), I2.size());
+    for (unsigned i = 0; i < Length; ++i) {
+      Result.push_back(CacheLevelList());
+      if (i < I1.size())
+        Result.back().append(I1[i].begin(), I1[i].end());
+      if (i < I2.size())
+        Result.back().append(I2[i].begin(), I2[i].end());
+    }
+
+    return Result;
+  };
+
+  std::function<CacheLevelInfo(const MCExecutionResourceDesc &)> getCacheInfo =
+    [&](const MCExecutionResourceDesc &Desc) -> CacheLevelInfo {
+      const MCExecutionResource &Resource = Desc.getResource();
+
+      CacheLevelInfo Result;
+      for (const auto &ContainedDesc : Resource) {
+        Result = mergeCacheInfo(Result, getCacheInfo(ContainedDesc));
+      }
+
+      // Add cache information for this resource.
+      for (const auto &Level : Resource.getMemoryModel()) {
+        Result.push_back(CacheLevelList());
+        Result.back().push_back(&Level);
+      }
+
+      return Result;
+    };
+
+  CacheLevels.clear();
+
+  for (const auto &Desc : *this)
+    CacheLevels = mergeCacheInfo(CacheLevels, getCacheInfo(Desc));
+}
+
+void MCSystemModel::initPrefetchConfigCache() {
+  Prefetchers.clear();
+
+  using WorkListType = SmallVector<const MCExecutionResourceDesc *, 4>;
+  WorkListType WorkList;
+  for (const auto &ResourceDesc : *this) {
+    WorkList.push_back(&ResourceDesc);
+  }
+
+  while (!WorkList.empty()) {
+    const MCExecutionResourceDesc *Item = WorkList.back();
+    WorkList.pop_back();
+    const MCExecutionResource &Resource = Item->getResource();
+    const MCSoftwarePrefetcherConfig &Prefetcher =
+      Resource.getMemoryModel().getSoftwarePrefetcherConfig();
+    if (Prefetcher.isEnabledForReads() || Prefetcher.isEnabledForWrites()) {
+      Prefetchers.push_back(&Prefetcher);
+    }
+    for (const auto &ResourceDesc : Resource) {
+      WorkList.push_back(&ResourceDesc);
+    }
+  }
+}
+
+}  // end llvm namespace

llvm/lib/Target/AArch64/AArch64Subtarget.h

public:
   bool useEL3ForTP() const { return UseEL3ForTP; }
 
   bool useRSqrt() const { return UseRSqrt; }
   bool force32BitJumpTables() const { return Force32BitJumpTables; }
   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
   unsigned getVectorInsertExtractBaseCost() const {
     return VectorInsertExtractBaseCost;
   }
-  unsigned getCacheLineSize() const { return CacheLineSize; }
-  unsigned getPrefetchDistance() const { return PrefetchDistance; }
-  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
-  unsigned getMaxPrefetchIterationsAhead() const {
+  unsigned getCacheLineSize() const override { return CacheLineSize; }
+  unsigned getPrefetchDistance() const override { return PrefetchDistance; }
+  unsigned getMinPrefetchStride() const override { return MinPrefetchStride; }
+  unsigned getMaxPrefetchIterationsAhead() const override {
     return MaxPrefetchIterationsAhead;
   }
   unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
   unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
 
   unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
 
   unsigned getWideningBaseCost() const { return WideningBaseCost; }

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
                                  unsigned AddressSpace,
                                  bool UseMaskForCond = false,
                                  bool UseMaskForGaps = false);
 
   bool
   shouldConsiderAddressTypePromotion(const Instruction &I,
                                      bool &AllowPromotionWithoutCommonHeader);
 
-  unsigned getCacheLineSize();
-
-  unsigned getPrefetchDistance();
-
-  unsigned getMinPrefetchStride();
-
-  unsigned getMaxPrefetchIterationsAhead();
-
   bool shouldExpandReduction(const IntrinsicInst *II) const {
     return false;
   }
 
   bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
                              TTI::ReductionFlags Flags) const;
 
   int getArithmeticReductionCost(unsigned Opcode, Type *Ty,

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

if (const GetElementPtrInst *GEPInst = dyn_cast<GetElementPtrInst>(U)) {
         AllowPromotionWithoutCommonHeader = true;
         break;
       }
     }
   }
   return Considerable;
 }
 
-unsigned AArch64TTIImpl::getCacheLineSize() {
-  return ST->getCacheLineSize();
-}
-
-unsigned AArch64TTIImpl::getPrefetchDistance() {
-  return ST->getPrefetchDistance();
-}
-
-unsigned AArch64TTIImpl::getMinPrefetchStride() {
-  return ST->getMinPrefetchStride();
-}
-
-unsigned AArch64TTIImpl::getMaxPrefetchIterationsAhead() {
-  return ST->getMaxPrefetchIterationsAhead();
-}
-
 bool AArch64TTIImpl::useReductionIntrinsic(unsigned Opcode, Type *Ty,
                                            TTI::ReductionFlags Flags) const {
   assert(isa<VectorType>(Ty) && "Expected Ty to be a vector type");
   unsigned ScalarBits = Ty->getScalarSizeInBits();
   switch (Opcode) {
   case Instruction::FAdd:
   case Instruction::FMul:
   case Instruction::And:

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

 
 #define GET_INSTRINFO_MC_DESC
 #include "AMDGPUGenInstrInfo.inc"
 
 #define GET_SUBTARGETINFO_MC_DESC
 #include "AMDGPUGenSubtargetInfo.inc"
 
 #define NoSchedModel NoSchedModelR600
+#define NoCaches NoCachesR600
+#define NoWCBuffers NoWCBuffersR600
+#define NoSoftwarePrefetcher NoSoftwarePrefetcherR600
+#define TransitionSoftwarePrefetcher TransitionSoftwarePrefetcherR600
+#define NoMemoryModel NoMemoryModelR600
+#define MinimalMemoryModel MinimalMemoryModelR600
+#define MinimalCore MinimalCoreR600
+#define MinimalCoreContained MinimalCoreContainedR600
+#define MinimalCoreResourceDesc MinimalCoreResourceDescR600
+#define MinimalSystemModelResources MinimalSystemModelResourcesR600
+#define MinimalSystemModel MinimalSystemModelR600
 #define GET_SUBTARGETINFO_MC_DESC
 #include "R600GenSubtargetInfo.inc"
 #undef NoSchedModelR600
+#undef NoCachesR600
+#undef NoWCBuffersR600
+#undef NoSoftwarePrefetcherR600
+#undef TransitionSoftwarePrefetcherR600
+#undef NoMemoryModelR600
+#undef MinimalMemoryModelR600
+#undef MinimalCoreR600
+#undef MinimalCoreContainedR600
+#undef MinimalCoreResourceDescR600
+#undef MinimalSystemModelResourcesR600
+#undef MinimalSystemModelR600
 
 #define GET_REGINFO_MC_DESC
 #include "AMDGPUGenRegisterInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "R600GenRegisterInfo.inc"
 
 static MCInstrInfo *createAMDGPUMCInstrInfo() {

llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h

public:
   // The Hexagon target can unroll loops with run-time trip counts.
   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                TTI::UnrollingPreferences &UP);
 
   /// Bias LSR towards creating post-increment opportunities.
   bool shouldFavorPostInc() const;
 
   // L1 cache prefetch.
-  unsigned getPrefetchDistance() const;
-  unsigned getCacheLineSize() const;
+  unsigned getPrefetchDistance() const override;
+  unsigned getCacheLineSize() const override;
 
   /// @}
 
   /// \name Vector TTI Implementations
   /// @{
 
   unsigned getNumberOfRegisters(bool vector) const;
   unsigned getMaxInterleaveFactor(unsigned VF);

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h

public:
   /// @{
   bool useColdCCForColdCall(Function &F);
   bool enableAggressiveInterleaving(bool LoopHasReductions);
   const TTI::MemCmpExpansionOptions *enableMemCmpExpansion(
       bool IsZeroCmp) const;
   bool enableInterleavedAccessVectorization();
   unsigned getNumberOfRegisters(bool Vector);
   unsigned getRegisterBitWidth(bool Vector) const;
-  unsigned getCacheLineSize();
-  unsigned getPrefetchDistance();
+  unsigned getCacheLineSize() const override;
+  unsigned getPrefetchDistance() const override;
   unsigned getMaxInterleaveFactor(unsigned VF);
   int vectorCostAdjustment(int Cost, unsigned Opcode, Type *Ty1, Type *Ty2);
   int getArithmeticInstrCost(
       unsigned Opcode, Type *Ty,
       TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
       TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
       TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
       TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) const {
   }
 
   if (ST->isPPC64())
     return 64;
   return 32;
 
 }
 
-unsigned PPCTTIImpl::getCacheLineSize() {
+unsigned PPCTTIImpl::getCacheLineSize() const {
   // Check first if the user specified a custom line size.
   if (CacheLineSize.getNumOccurrences() > 0)
     return CacheLineSize;
 
   // On P7, P8 or P9 we have a cache line size of 128.
   unsigned Directive = ST->getDarwinDirective();
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
       Directive == PPC::DIR_PWR9)
     return 128;
 
   // On other processors return a default of 64 bytes.
   return 64;
 }
 
-unsigned PPCTTIImpl::getPrefetchDistance() {
+unsigned PPCTTIImpl::getPrefetchDistance() const {
   // This seems like a reasonable default for the BG/Q (this pass is enabled, by
   // default, only on the BG/Q).
   return 300;
 }
 
 unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
   unsigned Directive = ST->getDarwinDirective();
   // The 440 has no SIMD support, but floating-point instructions

llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h

public:
   /// @}
 
   /// \name Vector TTI Implementations
   /// @{
 
   unsigned getNumberOfRegisters(bool Vector);
   unsigned getRegisterBitWidth(bool Vector) const;
 
-  unsigned getCacheLineSize() { return 256; }
-  unsigned getPrefetchDistance() { return 2000; }
-  unsigned getMinPrefetchStride() { return 2048; }
+  unsigned getCacheLineSize() const override { return 256; }
+  unsigned getPrefetchDistance() const override { return 2000; }
+  unsigned getMinPrefetchStride() const override { return 2048; }
 
   bool hasDivRemOp(Type *DataType, bool IsSigned);
   bool prefersVectorizedAddressing() { return false; }
   bool LSRWithInstrQueries() { return true; }
   bool supportsEfficientVectorElementLoadStore() { return true; }
   bool enableInterleavedAccessVectorization() { return true; }
 
   int getArithmeticInstrCost(

llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp

private:
   }
 
   unsigned getMaxPrefetchIterationsAhead() {
     if (MaxPrefetchIterationsAhead.getNumOccurrences() > 0)
       return MaxPrefetchIterationsAhead;
     return TTI->getMaxPrefetchIterationsAhead();
   }
 
+  bool prefetchReads() {
+    return TTI->shouldPrefetchReads();
+  }
+
+  bool prefetchWrites() {
+    if (PrefetchWrites.getNumOccurrences() > 0)
+      return PrefetchWrites;
+    return TTI->shouldPrefetchWrites();
+  }
+
   AssumptionCache *AC;
   LoopInfo *LI;
   ScalarEvolution *SE;
   const TargetTransformInfo *TTI;
   OptimizationRemarkEmitter *ORE;
 };
 
 /// Legacy class for inserting loop data prefetches.
bool LoopDataPrefetch::runOnLoop(Loop *L) {
 
   SmallVector<std::pair<Instruction *, const SCEVAddRecExpr *>, 16> PrefLoads;
   for (const auto BB : L->blocks()) {
     for (auto &I : *BB) {
       Value *PtrValue;
       Instruction *MemI;
 
       if (LoadInst *LMemI = dyn_cast<LoadInst>(&I)) {
+        if (!prefetchReads()) continue;
         MemI = LMemI;
         PtrValue = LMemI->getPointerOperand();
       } else if (StoreInst *SMemI = dyn_cast<StoreInst>(&I)) {
-        if (!PrefetchWrites) continue;
+        if (!prefetchWrites()) continue;
         MemI = SMemI;
         PtrValue = SMemI->getPointerOperand();
       } else continue;
 
       unsigned PtrAddrSpace = PtrValue->getType()->getPointerAddressSpace();
       if (PtrAddrSpace)
         continue;
 

llvm/test/TableGen/SystemModelEmitter.td

+// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+// Define a thread.
+def CoreThread : Thread;
+
+// Define a big core.
+def BigCoreL1 : CacheLevel<Size<_64KiB.Value>,
+                            LineSize<64>,
+                            Ways<2>,
+                            Latency<3>>;
+
+def BigCoreL2 : CacheLevel<Size<_512KiB.Value>,
+                            LineSize<64>,
+                            Ways<16>,
+                            Latency<12>>;
+
+def BigCoreCacheHierarchy : CacheHierarchy<[BigCoreL1, BigCoreL2]>;
+
+def BigCoreWCBuffers : WriteCombiningBuffer<4>;
+
+def BigCoreSoftwarePrefetcher : SoftwarePrefetcher<ReadEnabled,
+                                                   WriteEnabled,
+                                                   HeuristicByteDistance,
+                                                   MinByteDistance<64>,
+                                                   MaxByteDistance<640>,
+                                                   InstructionDistance<200>,
+                     MaxIterationDistance<4>,
+                     MinByteStride<2048>>;
+
+def BigCoreMemoryModel : MemoryModel<BigCoreCacheHierarchy,
+                                     BigCoreWCBuffers,
+                                     BigCoreSoftwarePrefetcher>;
+
+def BigCoreThreadDesc : ExecutionResourceDesc<CoreThread, 4>;
+
+def BigCore : Core<[BigCoreThreadDesc], BigCoreMemoryModel>;
+
+// Define a little core.
+def LittleCoreL1 : CacheLevel<Size<_32KiB.Value>,
+                              LineSize<32>,
+                              Ways<2>,
+                              Latency<3>>;
+
+def LittleCoreCacheHierarchy : CacheHierarchy<[LittleCoreL1]>;
+
+def LittleCoreWCBuffers : WriteCombiningBuffer<2>;
+
+def LittleCoreSoftwarePrefetcher : SoftwarePrefetcher<ReadEnabled,
+                                                      WriteEnabled,
+                                                      HeuristicByteDistance,
+                                                      MinByteDistance<12>,
+                                                      MaxByteDistance<120>,
+                                                      InstructionDistance<100>,
+                                                      MaxIterationDistance<2>,
+                                                      MinByteStride<512>>;
+
+
+def LittleCoreMemoryModel : MemoryModel<LittleCoreCacheHierarchy,
+                                        LittleCoreWCBuffers,
+                                        LittleCoreSoftwarePrefetcher>;
+
+def LittleCoreThreadDesc : ExecutionResourceDesc<CoreThread, 2>;
+
+def LittleCore : Core<[LittleCoreThreadDesc], LittleCoreMemoryModel>;
+
+// Define the socket-level memory model.
+def SocketL3 : CacheLevel<Size<_2MiB.Value>,
+                          LineSize<64>,
+                          Ways<16>,
+                          Latency<33>>;
+
+def SocketCacheHierarchy : CacheHierarchy<[SocketL3]>;
+
+// Prefetching and write-combining are handled at the core level.
+def SocketMemoryModel : MemoryModel<SocketCacheHierarchy,
+                                    NoWCBuffers,
+                                    NoSoftwarePrefetcher>;
+
+// Define an execution engine containing big cores.
+def HomogeneousCoreDesc   : ExecutionResourceDesc<BigCore, 32>;
+
+def HomogeneousSocket     : Socket<[HomogeneousCoreDesc], SocketMemoryModel>;
+
+def HomogeneousSocketDesc : ExecutionResourceDesc<HomogeneousSocket, 1>;
+
+def HomogeneousModel : SystemModel<[HomogeneousSocketDesc]>;
+
+// Define a socket containing big cores and little cores.
+def HeterogeneousBigCoreDesc    : ExecutionResourceDesc<BigCore, 2>;
+def HeterogeneousLittleCoreDesc : ExecutionResourceDesc<LittleCore, 16>;
+
+def HeterogeneousSocket : Socket<[HeterogeneousBigCoreDesc,
+                                  HeterogeneousLittleCoreDesc],
+                                 SocketMemoryModel>;
+
+def HeterogeneousSocketDesc : ExecutionResourceDesc<HeterogeneousSocket, 1>;
+
+def HeterogeneousModel : SystemModel<[HeterogeneousSocketDesc]>;
+
+
+def HomogeneousProc : Processor<"BigProc", NoItineraries, []> {
+  let System = HomogeneousModel;
+}
+
+def HeterogeneousProc : Processor<"BigLittleProc", NoItineraries, []> {
+  let System = HeterogeneousModel;
+}
+
+def MyProcDefault : Processor<"DefaultProc", NoItineraries, []>;
+
+def MyTarget : Target;
+
+// CHECK: // System model components
+// CHECK-NEXT: // ===============================================================
+// CHECK-NEXT: //
+
+// CHECK: // Cache models
+// CHECK-NEXT: //
+// CHECK-NEXT: static const llvm::MCCacheLevelInfo BigCoreCacheHierarchy[] = {
+// CHECK-NEXT:   llvm::MCCacheLevelInfo(1, "BigCoreL1", 65536, 64, 2, 3),
+// CHECK-NEXT:   llvm::MCCacheLevelInfo(2, "BigCoreL2", 524288, 64, 16, 12)
+// CHECK-NEXT: };  // BigCoreCacheHierarchy
+
+// CHECK: static const llvm::MCCacheLevelInfo LittleCoreCacheHierarchy[] = {
+// CHECK-NEXT:   llvm::MCCacheLevelInfo(3, "LittleCoreL1", 32768, 32, 2, 3)
+// CHECK-NEXT: };  // LittleCoreCacheHierarchy
+
+// CHECK: static const llvm::MCCacheLevelInfo NoCaches[] = {
+// CHECK-NEXT:   llvm::MCCacheLevelInfo(0, "Empty", 0, 0, 0, 0)
+// CHECK-NEXT: };  // NoCaches
+
+// CHECK: static const llvm::MCCacheLevelInfo SocketCacheHierarchy[] = {
+// CHECK-NEXT:   llvm::MCCacheLevelInfo(4, "SocketL3", 2097152, 64, 16, 33)
+// CHECK-NEXT: };  // SocketCacheHierarchy
+
+// CHECK: // Write-combining buffers
+// CHECK-NEXT: //
+// CHECK-NEXT: static const llvm::MCWriteCombiningBufferInfo BigCoreWCBuffers(5, "BigCoreWCBuffers", 4);
+
+// CHECK: static const llvm::MCWriteCombiningBufferInfo LittleCoreWCBuffers(6, "LittleCoreWCBuffers", 2);
+
+// CHECK: static const llvm::MCWriteCombiningBufferInfo NoWCBuffers(7, "NoWCBuffers", 0);
+
+// CHECK: // Software prefetch configs
+// CHECK-NEXT: //
+// CHECK-NEXT: static const llvm::MCSoftwarePrefetcherConfig BigCoreSoftwarePrefetcher(8, "BigCoreSoftwarePrefetcher", 1, 1, 0, 64, 640, 200, 4, 2048);
+
+// CHECK: static const llvm::MCSoftwarePrefetcherConfig LittleCoreSoftwarePrefetcher(9, "LittleCoreSoftwarePrefetcher", 1, 1, 0, 12, 120, 100, 2, 512);
+
+// CHECK: static const llvm::MCSoftwarePrefetcherConfig NoSoftwarePrefetcher(10, "NoSoftwarePrefetcher", 0, 0, 0, 0, 0, 0, 0, 0);
+
+// CHECK: static const llvm::MCSoftwarePrefetcherConfig TransitionSoftwarePrefetcher(11, "TransitionSoftwarePrefetcher", 1, 1, 0, 0, 0, 0, 4294967295, 1);
+
+// CHECK: // Memory models
+// CHECK-NEXT: //
+// CHECK-NEXT: static const llvm::MCMemoryModel BigCoreMemoryModel(12, "BigCoreMemoryModel", BigCoreCacheHierarchy, 2, BigCoreWCBuffers, BigCoreSoftwarePrefetcher);
+
+// CHECK: static const llvm::MCMemoryModel LittleCoreMemoryModel(13, "LittleCoreMemoryModel", LittleCoreCacheHierarchy, 1, LittleCoreWCBuffers, LittleCoreSoftwarePrefetcher);
+
+// CHECK: static const llvm::MCMemoryModel MinimalMemoryModel(14, "MinimalMemoryModel", NoCaches, 0, NoWCBuffers, TransitionSoftwarePrefetcher);
+
+// CHECK: static const llvm::MCMemoryModel NoMemoryModel(15, "NoMemoryModel", NoCaches, 0, NoWCBuffers, NoSoftwarePrefetcher);
+
+// CHECK: static const llvm::MCMemoryModel SocketMemoryModel(16, "SocketMemoryModel", SocketCacheHierarchy, 1, NoWCBuffers, NoSoftwarePrefetcher);
+
+// CHECK: // System models
+// CHECK-NEXT: //
+// CHECK-NEXT: static const llvm::MCExecutionResourceDesc *CoreThreadContained[] = {
+// CHECK-NEXT:   nullptr
+// CHECK-NEXT: };
+
+// CHECK: static const llvm::MCExecutionResource CoreThread(17, "CoreThread", CoreThreadContained, 0, NoMemoryModel);
+
+// CHECK: static const llvm::MCExecutionResourceDesc BigCoreThreadDesc(18, "BigCoreThreadDesc", &CoreThread, 4);
+
+// CHECK: static const llvm::MCExecutionResourceDesc *BigCoreContained[] = {
+// CHECK-NEXT:   &BigCoreThreadDesc
+// CHECK-NEXT: };
+
+// CHECK: static const llvm::MCExecutionResource BigCore(19, "BigCore", BigCoreContained, 1, BigCoreMemoryModel);
+
+// CHECK: static const llvm::MCExecutionResourceDesc HeterogeneousBigCoreDesc(20, "HeterogeneousBigCoreDesc", &BigCore, 2);
+
+// CHECK: static const llvm::MCExecutionResourceDesc LittleCoreThreadDesc(21, "LittleCoreThreadDesc", &CoreThread, 2);
+
+// CHECK: static const llvm::MCExecutionResourceDesc *LittleCoreContained[] = {
+// CHECK-NEXT:   &LittleCoreThreadDesc
+// CHECK-NEXT: };
+
+// CHECK: static const llvm::MCExecutionResource LittleCore(22, "LittleCore", LittleCoreContained, 1, LittleCoreMemoryModel);
+
+// CHECK: static const llvm::MCExecutionResourceDesc HeterogeneousLittleCoreDesc(23, "HeterogeneousLittleCoreDesc", &LittleCore, 16);
+
+// CHECK: static const llvm::MCExecutionResourceDesc *HeterogeneousSocketContained[] = {
+// CHECK-NEXT:   &HeterogeneousBigCoreDesc,
+// CHECK-NEXT:   &HeterogeneousLittleCoreDesc
+// CHECK-NEXT: };
+
+// CHECK: static const llvm::MCExecutionResource HeterogeneousSocket(24, "HeterogeneousSocket", HeterogeneousSocketContained, 2, SocketMemoryModel);
+
+// CHECK: static const llvm::MCExecutionResourceDesc HeterogeneousSocketDesc(25, "HeterogeneousSocketDesc", &HeterogeneousSocket, 1);
+
+// CHECK: static const llvm::MCExecutionResourceDesc *HeterogeneousModelResources[] = {
+// CHECK-NEXT:   &HeterogeneousSocketDesc
+// CHECK-NEXT: };
+
+// CHECK: static const llvm::MCSystemModel HeterogeneousModel(26, "HeterogeneousModel", HeterogeneousModelResources, 1);
+
+// CHECK: static const llvm::MCExecutionResourceDesc HomogeneousCoreDesc(26, "HomogeneousCoreDesc", &BigCore, 32);
+
+// CHECK: static const llvm::MCExecutionResourceDesc *HomogeneousSocketContained[] = {
+// CHECK-NEXT:   &HomogeneousCoreDesc
+// CHECK-NEXT: };
+
+// CHECK: static const llvm::MCExecutionResource HomogeneousSocket(27, "HomogeneousSocket", HomogeneousSocketContained, 1, SocketMemoryModel);
+
+// CHECK: static const llvm::MCExecutionResourceDesc HomogeneousSocketDesc(28, "HomogeneousSocketDesc", &HomogeneousSocket, 1);
+
+// CHECK: static const llvm::MCExecutionResourceDesc *HomogeneousModelResources[] = {
+// CHECK-NEXT:   &HomogeneousSocketDesc
+// CHECK-NEXT: };
+
+// CHECK: static const llvm::MCSystemModel HomogeneousModel(29, "HomogeneousModel", HomogeneousModelResources, 1);
+
+// CHECK: static const llvm::MCExecutionResourceDesc *MinimalCoreContained[] = {
+// CHECK-NEXT:   nullptr
+// CHECK-NEXT: };
+
+// CHECK: static const llvm::MCExecutionResource MinimalCore(29, "MinimalCore", MinimalCoreContained, 0, MinimalMemoryModel);
+
+// CHECK: static const llvm::MCExecutionResourceDesc MinimalCoreResourceDesc(30, "MinimalCoreResourceDesc", &MinimalCore, 1);
+
+// CHECK: static const llvm::MCExecutionResourceDesc *MinimalSystemModelResources[] = {
+// CHECK-NEXT:   &MinimalCoreResourceDesc
+// CHECK-NEXT: };
+
+// CHECK: static const llvm::MCSystemModel MinimalSystemModel(31, "MinimalSystemModel", MinimalSystemModelResources, 1);
+
+// CHECK: // Sorted (by key) array of values for CPU subtype.
+// CHECK-NEXT: extern const llvm::SubtargetSubTypeKV MyTargetSubTypeKV[] = {
+// CHECK-NEXT:   { "BigLittleProc", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel, &HeterogeneousModel },
+// CHECK-NEXT:   { "BigProc", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel, &HomogeneousModel },
+// CHECK-NEXT:   { "DefaultProc", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel, &MinimalSystemModel },
+// CHECK-NEXT: };

llvm/unittests/MC/CMakeLists.txt

 set(LLVM_LINK_COMPONENTS
   ${LLVM_TARGETS_TO_BUILD}
   MC
   MCDisassembler
   Support
   )
 
 add_llvm_unittest(MCTests
   Disassembler.cpp
   DwarfLineTables.cpp
   StringTableBuilderTest.cpp
+  SystemModel.cpp
   TargetRegistry.cpp
   )

llvm/unittests/MC/SystemModel.cpp

+//===- unittests/MC/SystemModel.cpp ---------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCSystemModel.h"
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+namespace {
+
+TEST(SystemModel, Topology1Tests) {
+  // Test this topology:
+  //
+  //              System
+  //              /    \
+  //    (L2, L3) GPU   CPU (L3)
+  //              |   /     \
+  //         (L1) C  L (L1)  B (L1, L2)
+
+  const unsigned BigL1 = 0;
+  const unsigned BigL2 = 1;
+
+  const unsigned LittleL1 = 0;
+
+  const unsigned GPUCoreL1 = 0;
+
+  const unsigned CPUL3 = 0;
+
+  const unsigned GPUL2 = 0;
+  const unsigned GPUL3 = 1;
+
+  const unsigned Big = 0;
+  const unsigned Little = 1;
+
+  const unsigned GPU = 0;
+
+  const unsigned CPUSocket = 0;
+  const unsigned GPUSocket = 1;
+
+  // Define cache parameters.
+  const char *BigCacheLevelNames[]        = { "BigL1", "BigL2" };
+  unsigned BigCacheLevelSizes[]           = { 1024*16, 1024 * 1024*4 };
+  unsigned BigCacheLevelLineSizes[]       = { 32,      32 };
+  unsigned BigCacheLevelAssociativities[] = { 8,       24 };
+  unsigned BigCacheLevelLatencies[]       = { 2,       12 };
+
+  const char *LittleCacheLevelNames[]        = { "LittleL1" };
+  unsigned LittleCacheLevelSizes[]           = { 1024*8 };
+  unsigned LittleCacheLevelLineSizes[]       = { 32 };
+  unsigned LittleCacheLevelAssociativities[] = { 8 };
+  unsigned LittleCacheLevelLatencies[]       = { 2 };
+
+  const char *CPUCacheLevelNames[]        = { "CPUL3" };
+  unsigned CPUCacheLevelSizes[]           = { 1024*1024*8 };
+  unsigned CPUCacheLevelLineSizes[]       = { 32 };
+  unsigned CPUCacheLevelAssociativities[] = { 32 };
+  unsigned CPUCacheLevelLatencies[]       = { 50 };
+
+  const char *GPUCoreCacheLevelNames[]        = { "GPUCoreL1" };
+  unsigned GPUCoreCacheLevelSizes[]           = { 1024*32 };
+  unsigned GPUCoreCacheLevelLineSizes[]       = { 64 };
+  unsigned GPUCoreCacheLevelAssociativities[] = { 8 };
+  unsigned GPUCoreCacheLevelLatencies[]       = { 2 };
+
+  const char *GPUCacheLevelNames[]        = { "GPUL2", "GPUL3" };
+  unsigned GPUCacheLevelSizes[]           = { 1024*64, 1024*1024*2 };
+  unsigned GPUCacheLevelLineSizes[]       = { 64,      64 };
+  unsigned GPUCacheLevelAssociativities[] = { 24,      32 };
+  unsigned GPUCacheLevelLatencies[]       = { 12,      50 };
+
+  // Define thread parameters.
+  const char *ThreadName = "Thread";
+
+  // Define core parameters.
+  // The GPU has four cores with two thread team schedulers of vector
+  // length 64, for a total of 512 "threads."
+  const char *CPUCoreNames[] = { "BigCore", "LittleCore" };
+  unsigned CPUCoreCounts[]   = { 2,         8 };
+  unsigned CPUThreadCounts[] = { 4,         2 };
+
+  const char *GPUCoreNames[] = { "GPUCore" };
+  unsigned GPUCoreCounts[]   = { 4 };
+  // Threads in a core.  The GPU has two thread team schedulers, each
+  // team may be a vector length of, say, 64 which we don't model.
+  unsigned GPUThreadCounts[] = { 2 };
+
+  // Define socket parameters.
+  const char *SocketNames[] = { "CPU", "GPU" };
+  unsigned CoreTypeCounts[] = { 2,     1 };
+
+  unsigned ID = 0;
+
+  // Define write-combining buffers.
+  MCWriteCombiningBufferInfo WCBufs(ID++, "WCBufs", 4);
+  MCWriteCombiningBufferInfo NoWCBufs(ID++, "NoWCBufs", 0);
+
+  // Define software prefetchers.
+  MCSoftwarePrefetcherConfig Prefetcher(ID++, "Prefetcher", true, true, 1024,
+                                        512, 4096, 100, 4, 32);
+
+  MCSoftwarePrefetcherConfig NoPrefetcher(ID++, "NoPrefetcher", false, false, 0,
+                                          0, 0, 0, 0, 0);
+
+  // Define caches.
+  MCCacheLevelInfo BigCoreCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     BigCacheLevelNames[BigL1],
+                     BigCacheLevelSizes[BigL1],
+                     BigCacheLevelLineSizes[BigL1],
+                     BigCacheLevelAssociativities[BigL1],
+                     BigCacheLevelLatencies[BigL1]),
+    MCCacheLevelInfo(ID++,
+                     BigCacheLevelNames[BigL2],
+                     BigCacheLevelSizes[BigL2],
+                     BigCacheLevelLineSizes[BigL2],
+                     BigCacheLevelAssociativities[BigL2],
+                     BigCacheLevelLatencies[BigL2]),
+  };
+
+  MCCacheLevelInfo LittleCoreCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     LittleCacheLevelNames[LittleL1],
+                     LittleCacheLevelSizes[LittleL1],
+                     LittleCacheLevelLineSizes[LittleL1],
+                     LittleCacheLevelAssociativities[LittleL1],
+                     LittleCacheLevelLatencies[LittleL1]),
+  };
+
+  MCCacheLevelInfo CPUCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     CPUCacheLevelNames[CPUL3],
+                     CPUCacheLevelSizes[CPUL3],
+                     CPUCacheLevelLineSizes[CPUL3],
+                     CPUCacheLevelAssociativities[CPUL3],
+                     CPUCacheLevelLatencies[CPUL3]),
+  };
+
+  // Each GPU core has a small cache.
+  MCCacheLevelInfo GPUCoreCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     GPUCoreCacheLevelNames[GPUCoreL1],
+                     GPUCoreCacheLevelSizes[GPUCoreL1],
+                     GPUCoreCacheLevelLineSizes[GPUCoreL1],
+                     GPUCoreCacheLevelAssociativities[GPUCoreL1],
+                     GPUCoreCacheLevelLatencies[GPUCoreL1]),
+  };
+
+  // All GPU cores share two higher levels of cache.
+  MCCacheLevelInfo GPUCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     GPUCacheLevelNames[GPUL2],
+                     GPUCacheLevelSizes[GPUL2],
+                     GPUCacheLevelLineSizes[GPUL2],
+                     GPUCacheLevelAssociativities[GPUL2],
+                     GPUCacheLevelLatencies[GPUL2]),
+    MCCacheLevelInfo(ID++,
+                     GPUCacheLevelNames[GPUL3],
+                     GPUCacheLevelSizes[GPUL3],
+                     GPUCacheLevelLineSizes[GPUL3],
+                     GPUCacheLevelAssociativities[GPUL3],
+                     GPUCacheLevelLatencies[GPUL3]),
+  };
+
+  // Define memory models.
+  MCMemoryModel BigMemModel(ID++,
+                            "BigMemModel",
+                            BigCoreCacheLevels,
+                            2,
+                            WCBufs,
+                            Prefetcher);
+
+  MCMemoryModel LittleMemModel(ID++,
+                               "LittleMemModel",
+                               LittleCoreCacheLevels,
+                               1,
+                               WCBufs,
+                               Prefetcher);
+
+  MCMemoryModel CPUMemModel(ID++,
+                            "CPUMemModel",
+                            CPUCacheLevels,
+                            1,
+                            NoWCBufs,
+                            NoPrefetcher);
+
+  MCMemoryModel GPUCoreMemModel(ID++,
+                                "GPUCoreMemModel",
+                                GPUCoreCacheLevels,
+                                1,
+                                NoWCBufs,
+                                NoPrefetcher);
+
+  MCMemoryModel GPUMemModel(ID++,
+                            "GPUMemModel",
+                            GPUCacheLevels,
+                            2,
+                            NoWCBufs,
+                            NoPrefetcher);
+
+  MCMemoryModel NoMemModel(ID++, "NoModel", nullptr, 0, NoWCBufs, NoPrefetcher);
+
+  // Define threads.
+  MCExecutionResource CommonThread(ID++, ThreadName, nullptr, 0, NoMemModel);
+
+  // Define cores.
+  MCExecutionResourceDesc BigThreadDesc(ID++,
+                                        "BigThreadDesc",
+                                        &CommonThread,
+                                        CPUThreadCounts[Big]);
+  MCExecutionResourceDesc LittleThreadDesc(ID++,
+                                           "LittleThreadDesc",
+                                           &CommonThread,
+                                           CPUThreadCounts[Little]);
+  MCExecutionResourceDesc GPUThreadDesc(ID++,
+                                        "GPUThreadDesc",
+                                        &CommonThread,
+                                        GPUThreadCounts[GPU]);
+
+  MCExecutionResourceDesc *BigThreadsList[] = { &BigThreadDesc };
+  MCExecutionResourceDesc *LittleThreadsList[] = { &LittleThreadDesc };
+  MCExecutionResourceDesc *GPUThreadsList[] = { &GPUThreadDesc };
+
+  MCExecutionResource BigCore(ID++,
+                              CPUCoreNames[Big],
+                              BigThreadsList,
+                              1,
+                              BigMemModel);
+
+  MCExecutionResource LittleCore(ID++,
+                                 CPUCoreNames[Little],
+                                 LittleThreadsList,
+                                 1,
+                                 LittleMemModel);
+
+  MCExecutionResource GPUCore(ID++,
+                              GPUCoreNames[GPU],
+                              GPUThreadsList,
+                              1,
+                              GPUCoreMemModel);
+
+  // Define sockets.
+  MCExecutionResourceDesc BigCoreDesc(ID++,
+                                      "BigCoreDesc",
+                                      &BigCore,
+                                      CPUCoreCounts[Big]);
+
+  MCExecutionResourceDesc LittleCoreDesc(ID++,
+                                         "LittleCoreDesc",
+                                         &LittleCore,
+                                         CPUCoreCounts[Little]);
+
+  MCExecutionResourceDesc GPUCoreDesc(ID++,
+                                      "GPUCoreDesc",
+                                      &GPUCore,
+                                      GPUCoreCounts[GPU]);
+
+  MCExecutionResourceDesc *CPUCoreList[] = { &BigCoreDesc, &LittleCoreDesc };
+  MCExecutionResourceDesc *GPUCoreList[] = { &GPUCoreDesc };
+
+  MCExecutionResource CPUEngine(ID++,
+                                SocketNames[CPUSocket],
+                                CPUCoreList,
+                                2,
+                                CPUMemModel);
+
+  MCExecutionResource GPUEngine(ID++,
+                                SocketNames[GPUSocket],
+                                GPUCoreList,
+                                1,
+                                GPUMemModel);
+
+  // Define a node consisting of a CPU socket and a GPU socket.
+  MCExecutionResourceDesc CPUSocketDesc(ID++, "CPUSocketDesc", &CPUEngine, 1);
+  MCExecutionResourceDesc GPUSocketDesc(ID++, "GPUSocketDesc", &GPUEngine, 1);
+
+  MCExecutionResourceDesc *SocketList[] = { &CPUSocketDesc, &GPUSocketDesc };
+
+  MCSystemModel Node(ID++, "Node", SocketList, 2);
+
+  // Test the topology.
+  EXPECT_EQ(Node.getNumExecutionResourceTypes(), 2u);
+
+  unsigned s = 0;
+  for (const auto &SocketDesc : Node) {
+    EXPECT_EQ(SocketDesc.getNumResources(), 1u);
+
+    const auto &Socket = SocketDesc.getResource();
+    EXPECT_STREQ(Socket.getName(), SocketNames[s]);
+    EXPECT_EQ(Socket.getNumContainedExecutionResourceTypes(),
+              CoreTypeCounts[s]);
+
+    unsigned *CoreCounts         = (s == CPUSocket ?
+                                    CPUCoreCounts   : GPUCoreCounts);
+    const char *const *CoreNames = (s == CPUSocket ?
+                                    CPUCoreNames    : GPUCoreNames);
+    unsigned *ThreadCounts       = (s == CPUSocket ?
+                                    CPUThreadCounts : GPUThreadCounts);
+
+    unsigned c = 0;
+    for (const auto &CoreDesc : Socket) {
+      EXPECT_EQ(CoreDesc.getNumResources(), CoreCounts[c]);
+
+      const auto &Core = CoreDesc.getResource();
+      EXPECT_STREQ(Core.getName(), CoreNames[c]);
+
+      EXPECT_EQ(Core.getNumContainedExecutionResourceTypes(), 1u);
+
+      const auto &ThreadDesc = Core.getResourceDescriptor(0);
+      EXPECT_EQ(ThreadDesc.getNumResources(), ThreadCounts[c]);
+
+      const auto &Thread = ThreadDesc.getResource();
+      EXPECT_STREQ(Thread.getName(), ThreadName);
+
+      EXPECT_EQ(Thread.getNumContainedExecutionResourceTypes(), 0u);
+
+      // Check thread-level caches.
+      unsigned NumThreadCacheLevels =
+        Thread.getMemoryModel().getNumCacheLevels();
+      EXPECT_EQ(NumThreadCacheLevels, 0u);
+
+      // Check core-level caches.
+      const char *const *CacheNames        = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelNames :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelNames :
+                                               GPUCoreCacheLevelNames));
+      const unsigned *CacheSizes           = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelSizes :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelSizes :
+                                               GPUCoreCacheLevelSizes));
+      const unsigned *CacheLineSizes       = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelLineSizes :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelLineSizes :
+                                               GPUCoreCacheLevelLineSizes));
+      const unsigned *CacheAssociativities = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelAssociativities :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelAssociativities :
+                                               GPUCoreCacheLevelAssociativities)
+                                              );
+      const unsigned *CacheLatencies       = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelLatencies :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelLatencies :
+                                               GPUCoreCacheLevelLatencies));
+
+      unsigned lvl = 0;
+      for (const auto &CacheLevel : Core.getMemoryModel()) {
+        EXPECT_STREQ(CacheLevel.getName(), CacheNames[lvl]);
+        EXPECT_EQ(CacheLevel.getSizeInBytes(), CacheSizes[lvl]);
+        EXPECT_EQ(CacheLevel.getLineSizeInBytes(), CacheLineSizes[lvl]);
+        EXPECT_EQ(CacheLevel.getAssociativity(), CacheAssociativities[lvl]);
+        EXPECT_EQ(CacheLevel.getLatency(), CacheLatencies[lvl]);
+
+        ++lvl;
+      }
+
+      ++c;
+    }
+
+    // Check socket-level caches.
+    const char *const *CacheNames        = (s == CPUSocket ?
+                                            CPUCacheLevelNames :
+                                            GPUCacheLevelNames);
+    const unsigned *CacheSizes           = (s == CPUSocket ?
+                                            CPUCacheLevelSizes :
+                                            GPUCacheLevelSizes);
+    const unsigned *CacheLineSizes       = (s == CPUSocket ?
+                                            CPUCacheLevelLineSizes :
+                                            GPUCacheLevelLineSizes);
+    const unsigned *CacheAssociativities = (s == CPUSocket ?
+                                            CPUCacheLevelAssociativities :
+                                            GPUCacheLevelAssociativities);
+    const unsigned *CacheLatencies       = (s == CPUSocket ?
+                                            CPUCacheLevelLatencies :
+                                            GPUCacheLevelLatencies);
+
+    unsigned lvl = 0;
+    for (const auto &CacheLevel : Socket.getMemoryModel()) {
+      EXPECT_STREQ(CacheLevel.getName(), CacheNames[lvl]);
+      EXPECT_EQ(CacheLevel.getSizeInBytes(), CacheSizes[lvl]);
+      EXPECT_EQ(CacheLevel.getLineSizeInBytes(), CacheLineSizes[lvl]);
+      EXPECT_EQ(CacheLevel.getAssociativity(), CacheAssociativities[lvl]);
+      EXPECT_EQ(CacheLevel.getLatency(), CacheLatencies[lvl]);
+
+      ++lvl;
+    }
+
+    ++s;
+  }
+
+  // Test the global system representation of the memory model.
+  const MCSystemModel::CacheLevelList *L1Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L1);
+  const MCSystemModel::CacheLevelList *L2Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L2);
+  const MCSystemModel::CacheLevelList *L3Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L3);
+  const MCSystemModel::CacheLevelList *L4Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L4);
+
+  const MCSystemModel::PrefetchConfigList &PrefetchConfigs =
+    Node.getSoftwarePrefetcherInfo();
+
+  EXPECT_NE(L1Levels, nullptr);
+  EXPECT_NE(L2Levels, nullptr);
+  EXPECT_NE(L3Levels, nullptr);
+  EXPECT_EQ(L4Levels, nullptr);
+
+  EXPECT_EQ(L1Levels->size(), 3u);
+  EXPECT_EQ(L2Levels->size(), 2u);
+  EXPECT_EQ(L3Levels->size(), 2u);
+  EXPECT_EQ(PrefetchConfigs.size(), 2u);
+
+  unsigned i = 0;
+  for (const auto L1Level : *L1Levels) {
+    const char *const *CacheNames        = (i == 0 ? BigCacheLevelNames :
+                                            i == 1 ? LittleCacheLevelNames :
+                                                     GPUCoreCacheLevelNames);
+    const unsigned *CacheSizes           = (i == 0 ? BigCacheLevelSizes :
+                                            i == 1 ? LittleCacheLevelSizes :
+                                                     GPUCoreCacheLevelSizes);
+    const unsigned *CacheLineSizes       = (i == 0 ? BigCacheLevelLineSizes :
+                                            i == 1 ? LittleCacheLevelLineSizes :
+                                                     GPUCoreCacheLevelLineSizes
+                                            );
+    const unsigned *CacheAssociativities = (i == 0 ?
+                                            BigCacheLevelAssociativities :
+                                            i == 1 ?
+                                            LittleCacheLevelAssociativities :
+                                            GPUCoreCacheLevelAssociativities);
+    const unsigned *CacheLatencies       = (i == 0 ? BigCacheLevelLatencies :
+                                            i == 1 ? LittleCacheLevelLatencies :
+                                                     GPUCoreCacheLevelLatencies
+                                            );
+
+    unsigned Index = (i == 0 ? BigL1 :
+                      i == 1 ? LittleL1 : GPUCoreL1);
+
+    EXPECT_STREQ(L1Level->getName(), CacheNames[Index]);
+    EXPECT_EQ(L1Level->getSizeInBytes(), CacheSizes[Index]);
+    EXPECT_EQ(L1Level->getLineSizeInBytes(), CacheLineSizes[Index]);
+    EXPECT_EQ(L1Level->getAssociativity(), CacheAssociativities[Index]);
+    EXPECT_EQ(L1Level->getLatency(), CacheLatencies[Index]);
+
+    ++i;
+  }
+
+  i = 0;
+  for (const auto L2Level : *L2Levels) {
+    const char *const *CacheNames        = (i == 0 ? BigCacheLevelNames :
+                                                     GPUCacheLevelNames);
+    const unsigned *CacheSizes           = (i == 0 ? BigCacheLevelSizes :
+                                                     GPUCacheLevelSizes);
+    const unsigned *CacheLineSizes       = (i == 0 ? BigCacheLevelLineSizes :
+                                                     GPUCacheLevelLineSizes);
+    const unsigned *CacheAssociativities = (i == 0 ?
+                                            BigCacheLevelAssociativities :
+                                            GPUCacheLevelAssociativities);
+    const unsigned *CacheLatencies       = (i == 0 ? BigCacheLevelLatencies :
+                                                     GPUCacheLevelLatencies);
+
+    unsigned Index = (i == 0 ? BigL2 : GPUL2);
+
+    EXPECT_STREQ(L2Level->getName(), CacheNames[Index]);
+    EXPECT_EQ(L2Level->getSizeInBytes(), CacheSizes[Index]);
+    EXPECT_EQ(L2Level->getLineSizeInBytes(), CacheLineSizes[Index]);
+    EXPECT_EQ(L2Level->getAssociativity(), CacheAssociativities[Index]);
+    EXPECT_EQ(L2Level->getLatency(), CacheLatencies[Index]);
+
+    ++i;
+  }
+
+  i = 0;
+  for (const auto L3Level : *L3Levels) {
+    const char *const *CacheNames        = (i == 0 ? CPUCacheLevelNames :
+                                                     GPUCacheLevelNames);
+    const unsigned *CacheSizes           = (i == 0 ? CPUCacheLevelSizes :
+                                                     GPUCacheLevelSizes);
+    const unsigned *CacheLineSizes       = (i == 0 ? CPUCacheLevelLineSizes :
+                                                     GPUCacheLevelLineSizes);
+    const unsigned *CacheAssociativities = (i == 0 ?
+                                            CPUCacheLevelAssociativities :
+                                            GPUCacheLevelAssociativities);
+    const unsigned *CacheLatencies       = (i == 0 ? CPUCacheLevelLatencies :
+                                                     GPUCacheLevelLatencies);
+
+    unsigned Index = (i == 0 ? CPUL3 : GPUL3);
+
+    EXPECT_STREQ(L3Level->getName(), CacheNames[Index]);
+    EXPECT_EQ(L3Level->getSizeInBytes(), CacheSizes[Index]);
+    EXPECT_EQ(L3Level->getLineSizeInBytes(), CacheLineSizes[Index]);
+    EXPECT_EQ(L3Level->getAssociativity(), CacheAssociativities[Index]);
+    EXPECT_EQ(L3Level->getLatency(), CacheLatencies[Index]);
+
+    ++i;
+  }
+}
+
+TEST(SystemModel, Topology2Tests) {
+  // Test this topology:
+  //
+  //              System
+  //              /    \
+  //             GPU   CPU (L3)
+  //              |   /     \
+  //         (L1) C  L (L1)  B (L1, L2)
+
+  const unsigned BigL1 = 0;
+  const unsigned BigL2 = 1;
+
+  const unsigned LittleL1 = 0;
+
+  const unsigned GPUCoreL1 = 0;
+
+  const unsigned CPUL3 = 0;
+
+  const unsigned Big = 0;
+  const unsigned Little = 1;
+
+  const unsigned GPU = 0;
+
+  const unsigned CPUSocket = 0;
+  const unsigned GPUSocket = 1;
+
+  // Define cache parameters.
+  const char *BigCacheLevelNames[]        = { "BigL1", "BigL2" };
+  unsigned BigCacheLevelSizes[]           = { 1024*16, 1024 * 1024*4 };
+  unsigned BigCacheLevelLineSizes[]       = { 32,      32 };
+  unsigned BigCacheLevelAssociativities[] = { 8,       24 };
+  unsigned BigCacheLevelLatencies[]       = { 2,       12 };
+
+  const char *LittleCacheLevelNames[]        = { "LittleL1" };
+  unsigned LittleCacheLevelSizes[]           = { 1024*8 };
+  unsigned LittleCacheLevelLineSizes[]       = { 32 };
+  unsigned LittleCacheLevelAssociativities[] = { 8 };
+  unsigned LittleCacheLevelLatencies[]       = { 2 };
+
+  const char *CPUCacheLevelNames[]        = { "CPUL3" };
+  unsigned CPUCacheLevelSizes[]           = { 1024*1024*8 };
+  unsigned CPUCacheLevelLineSizes[]       = { 32 };
+  unsigned CPUCacheLevelAssociativities[] = { 32 };
+  unsigned CPUCacheLevelLatencies[]       = { 50 };
+
+  const char *GPUCoreCacheLevelNames[]        = { "GPUCoreL1" };
+  unsigned GPUCoreCacheLevelSizes[]           = { 1024*32 };
+  unsigned GPUCoreCacheLevelLineSizes[]       = { 64 };
+  unsigned GPUCoreCacheLevelAssociativities[] = { 8 };
+  unsigned GPUCoreCacheLevelLatencies[]       = { 2 };
+
+  // Define thread parameters.
+  const char *ThreadName = "Thread";
+
+  // Define core parameters.
+  // The GPU has four cores with two thread team schedulers of vector
+  // length 64, for a total of 512 "threads."
+  const char *CPUCoreNames[] = { "BigCore", "LittleCore" };
+  unsigned CPUCoreCounts[]   = { 2,         8 };
+  unsigned CPUThreadCounts[] = { 4,         2 };
+
+  const char *GPUCoreNames[] = { "GPUCore" };
+  unsigned GPUCoreCounts[]   = { 4 };
+  // Threads in a core.  The GPU has two thread team schedulers, each
+  // team may be a vector length of, say, 64 which we don't model.
+  unsigned GPUThreadCounts[] = { 2 };
+
+  // Define socket parameters.
+  const char *SocketNames[] = { "CPU", "GPU" };
+  unsigned CoreTypeCounts[] = { 2,     1 };
+
+  unsigned ID = 0;
+
+  // Define write-combining buffers.
+  MCWriteCombiningBufferInfo WCBufs(ID++, "WCBufs", 4);
+  MCWriteCombiningBufferInfo NoWCBufs(ID++, "NoWCBufs", 0);
+
+  // Define software prefetchers.
+  MCSoftwarePrefetcherConfig Prefetcher(ID++, "Prefetcher", true, true, 1024,
+                                        512, 4096, 100, 4, 32);
+
+  MCSoftwarePrefetcherConfig NoPrefetcher(ID++, "NoPrefetcher", false, false, 0,
+                                          0, 0, 0, 0, 0);
+
+  // Define caches.
+  MCCacheLevelInfo BigCoreCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     BigCacheLevelNames[BigL1],
+                     BigCacheLevelSizes[BigL1],
+                     BigCacheLevelLineSizes[BigL1],
+                     BigCacheLevelAssociativities[BigL1],
+                     BigCacheLevelLatencies[BigL1]),
+    MCCacheLevelInfo(ID++,
+                     BigCacheLevelNames[BigL2],
+                     BigCacheLevelSizes[BigL2],
+                     BigCacheLevelLineSizes[BigL2],
+                     BigCacheLevelAssociativities[BigL2],
+                     BigCacheLevelLatencies[BigL2]),
+  };
+
+  MCCacheLevelInfo LittleCoreCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     LittleCacheLevelNames[LittleL1],
+                     LittleCacheLevelSizes[LittleL1],
+                     LittleCacheLevelLineSizes[LittleL1],
+                     LittleCacheLevelAssociativities[LittleL1],
+                     LittleCacheLevelLatencies[LittleL1]),
+  };
+
+  MCCacheLevelInfo CPUCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     CPUCacheLevelNames[CPUL3],
+                     CPUCacheLevelSizes[CPUL3],
+                     CPUCacheLevelLineSizes[CPUL3],
+                     CPUCacheLevelAssociativities[CPUL3],
+                     CPUCacheLevelLatencies[CPUL3]),
+  };
+
+  // Each GPU core has a small cache.
+  MCCacheLevelInfo GPUCoreCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     GPUCoreCacheLevelNames[GPUCoreL1],
+                     GPUCoreCacheLevelSizes[GPUCoreL1],
+                     GPUCoreCacheLevelLineSizes[GPUCoreL1],
+                     GPUCoreCacheLevelAssociativities[GPUCoreL1],
+                     GPUCoreCacheLevelLatencies[GPUCoreL1]),
+  };
+
+  // Define memory models.
+  MCMemoryModel BigMemModel(ID++,
+                            "BigMemModel",
+                            BigCoreCacheLevels,
+                            2,
+                            WCBufs,
+                            Prefetcher);
+
+  MCMemoryModel LittleMemModel(ID++,
+                               "LittleMemModel",
+                               LittleCoreCacheLevels,
+                               1,
+                               WCBufs,
+                               Prefetcher);
+
+  MCMemoryModel CPUMemModel(ID++,
+                            "CPUMemModel",
+                            CPUCacheLevels,
+                            1,
+                            NoWCBufs,
+                            NoPrefetcher);
+
+  MCMemoryModel GPUCoreMemModel(ID++,
+                                "GPUCoreMemModel",
+                                GPUCoreCacheLevels,
+                                1,
+                                NoWCBufs,
+                                NoPrefetcher);
+
+  MCMemoryModel NoMemModel(ID++, "NoModel", nullptr, 0, NoWCBufs, NoPrefetcher);
+
+  // Define threads.
+  MCExecutionResource CommonThread(ID++, ThreadName, nullptr, 0, NoMemModel);
+
+  // Define cores.
+  MCExecutionResourceDesc BigThreadDesc(ID++,
+                                        "BigThreadDesc",
+                                        &CommonThread,
+                                        CPUThreadCounts[Big]);
+  MCExecutionResourceDesc LittleThreadDesc(ID++,
+                                           "LittleThreadDesc",
+                                           &CommonThread,
+                                           CPUThreadCounts[Little]);
+  MCExecutionResourceDesc GPUThreadDesc(ID++,
+                                        "GPUThreadDesc",
+                                        &CommonThread,
+                                        GPUThreadCounts[GPU]);
+
+  MCExecutionResourceDesc *BigThreadsList[] = { &BigThreadDesc };
+  MCExecutionResourceDesc *LittleThreadsList[] = { &LittleThreadDesc };
+  MCExecutionResourceDesc *GPUThreadsList[] = { &GPUThreadDesc };
+
+  MCExecutionResource BigCore(ID++,
+                              CPUCoreNames[Big],
+                              BigThreadsList,
+                              1,
+                              BigMemModel);
+
+  MCExecutionResource LittleCore(ID++,
+                                 CPUCoreNames[Little],
+                                 LittleThreadsList,
+                                 1,
+                                 LittleMemModel);
+
+  MCExecutionResource GPUCore(ID++,
+                              GPUCoreNames[GPU],
+                              GPUThreadsList,
+                              1,
+                              GPUCoreMemModel);
+
+  // Define sockets.
+  MCExecutionResourceDesc BigCoreDesc(ID++,
+                                      "BigCoreDesc",
+                                      &BigCore,
+                                      CPUCoreCounts[Big]);
+
+  MCExecutionResourceDesc LittleCoreDesc(ID++,
+                                         "LittleCoreDesc",
+                                         &LittleCore,
+                                         CPUCoreCounts[Little]);
+
+  MCExecutionResourceDesc GPUCoreDesc(ID++,
+                                      "GPUCoreDesc",
+                                      &GPUCore,
+                                      GPUCoreCounts[GPU]);
+
+  MCExecutionResourceDesc *CPUCoreList[] = { &BigCoreDesc, &LittleCoreDesc };
+  MCExecutionResourceDesc *GPUCoreList[] = { &GPUCoreDesc };
+
+  MCExecutionResource CPUEngine(ID++,
+                                SocketNames[CPUSocket],
+                                CPUCoreList,
+                                2,
+                                CPUMemModel);
+
+  MCExecutionResource GPUEngine(ID++,
+                                SocketNames[GPUSocket],
+                                GPUCoreList,
+                                1,
+                                NoMemModel);
+
+  // Define a node consisting of a CPU socket and a GPU socket.
+  MCExecutionResourceDesc CPUSocketDesc(ID++, "CPUSocketDesc", &CPUEngine, 1);
+  MCExecutionResourceDesc GPUSocketDesc(ID++, "GPUSocketDesc", &GPUEngine, 1);
+
+  MCExecutionResourceDesc *SocketList[] = { &CPUSocketDesc, &GPUSocketDesc };
+
+  MCSystemModel Node(ID++, "Node", SocketList, 2);
+
+  // Test the topology.
+  EXPECT_EQ(Node.getNumExecutionResourceTypes(), 2u);
+
+  unsigned s = 0;
+  for (const auto &SocketDesc : Node) {
+    EXPECT_EQ(SocketDesc.getNumResources(), 1u);
+
+    const auto &Socket = SocketDesc.getResource();
+    EXPECT_STREQ(Socket.getName(), SocketNames[s]);
+    EXPECT_EQ(Socket.getNumContainedExecutionResourceTypes(),
+              CoreTypeCounts[s]);
+
+    unsigned *CoreCounts         = (s == 0 ? CPUCoreCounts   : GPUCoreCounts);
+    const char *const *CoreNames = (s == 0 ? CPUCoreNames    : GPUCoreNames);
+    unsigned *ThreadCounts       = (s == 0 ? CPUThreadCounts : GPUThreadCounts);
+
+    unsigned c = 0;
+    for (const auto &CoreDesc : Socket) {
+      EXPECT_EQ(CoreDesc.getNumResources(), CoreCounts[c]);
+
+      const auto &Core = CoreDesc.getResource();
+      EXPECT_STREQ(Core.getName(), CoreNames[c]);
+
+      EXPECT_EQ(Core.getNumContainedExecutionResourceTypes(), 1u);
+
+      const auto &ThreadDesc = Core.getResourceDescriptor(0);
+      EXPECT_EQ(ThreadDesc.getNumResources(), ThreadCounts[c]);
+
+      const auto &Thread = ThreadDesc.getResource();
+      EXPECT_STREQ(Thread.getName(), ThreadName);
+
+      EXPECT_EQ(Thread.getNumContainedExecutionResourceTypes(), 0u);
+
+      // Check thread-level caches.
+      unsigned NumThreadCacheLevels =
+        Thread.getMemoryModel().getNumCacheLevels();
+      EXPECT_EQ(NumThreadCacheLevels, 0u);
+
+      // Check core-level caches.
+      const char *const *CacheNames        = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelNames :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelNames :
+                                               GPUCoreCacheLevelNames));
+      const unsigned *CacheSizes           = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelSizes :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelSizes :
+                                               GPUCoreCacheLevelSizes));
+      const unsigned *CacheLineSizes       = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelLineSizes :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelLineSizes :
+                                               GPUCoreCacheLevelLineSizes));
+      const unsigned *CacheAssociativities = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelAssociativities :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelAssociativities :
+                                               GPUCoreCacheLevelAssociativities)
+                                              );
+      const unsigned *CacheLatencies       = (s == CPUSocket &&
+                                              c == Big ?
+                                              BigCacheLevelLatencies :
+                                              (s == CPUSocket &&
+                                               c == Little ?
+                                               LittleCacheLevelLatencies :
+                                               GPUCoreCacheLevelLatencies));
+
+      unsigned lvl = 0;
+      for (const auto &CacheLevel : Core.getMemoryModel()) {
+        EXPECT_STREQ(CacheLevel.getName(), CacheNames[lvl]);
+        EXPECT_EQ(CacheLevel.getSizeInBytes(), CacheSizes[lvl]);
+        EXPECT_EQ(CacheLevel.getLineSizeInBytes(), CacheLineSizes[lvl]);
+        EXPECT_EQ(CacheLevel.getAssociativity(), CacheAssociativities[lvl]);
+        EXPECT_EQ(CacheLevel.getLatency(), CacheLatencies[lvl]);
+
+        ++lvl;
+      }
+
+      ++c;
+    }
+
+    // Check socket-level caches.
+    const char *const *CacheNames        = CPUCacheLevelNames;
+    const unsigned *CacheSizes           = CPUCacheLevelSizes;
+    const unsigned *CacheLineSizes       = CPUCacheLevelLineSizes;
+    const unsigned *CacheAssociativities = CPUCacheLevelAssociativities;
+    const unsigned *CacheLatencies       = CPUCacheLevelLatencies;
+
+    if (s == GPUSocket) {
+      unsigned NumSocketCacheLevels =
+        Socket.getMemoryModel().getNumCacheLevels();
+      EXPECT_EQ(NumSocketCacheLevels, 0u);
+    }
+
+    unsigned lvl = 0;
+    for (const auto &CacheLevel : Socket.getMemoryModel()) {
+      EXPECT_STREQ(CacheLevel.getName(), CacheNames[lvl]);
+      EXPECT_EQ(CacheLevel.getSizeInBytes(), CacheSizes[lvl]);
+      EXPECT_EQ(CacheLevel.getLineSizeInBytes(), CacheLineSizes[lvl]);
+      EXPECT_EQ(CacheLevel.getAssociativity(), CacheAssociativities[lvl]);
+      EXPECT_EQ(CacheLevel.getLatency(), CacheLatencies[lvl]);
+
+      ++lvl;
+    }
+
+    ++s;
+  }
+
+  // Test the global system representation of the memory model.
+  const MCSystemModel::CacheLevelList *L1Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L1);
+  const MCSystemModel::CacheLevelList *L2Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L2);
+  const MCSystemModel::CacheLevelList *L3Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L3);
+  const MCSystemModel::CacheLevelList *L4Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L4);
+
+  const MCSystemModel::PrefetchConfigList &PrefetchConfigs =
+    Node.getSoftwarePrefetcherInfo();
+
+  EXPECT_NE(L1Levels, nullptr);
+  EXPECT_NE(L2Levels, nullptr);
+  EXPECT_NE(L3Levels, nullptr);
+  EXPECT_EQ(L4Levels, nullptr);
+
+  EXPECT_EQ(L1Levels->size(), 3u);
+  EXPECT_EQ(L2Levels->size(), 1u);
+  EXPECT_EQ(L3Levels->size(), 1u);
+  EXPECT_EQ(PrefetchConfigs.size(), 2u);
+
+  unsigned i = 0;
+  for (const auto L1Level : *L1Levels) {
+    const char *const *CacheNames        = (i == 0 ? BigCacheLevelNames :
+                                            i == 1 ? LittleCacheLevelNames :
+                                                     GPUCoreCacheLevelNames);
+    const unsigned *CacheSizes           = (i == 0 ? BigCacheLevelSizes :
+                                            i == 1 ? LittleCacheLevelSizes :
+                                                     GPUCoreCacheLevelSizes);
+    const unsigned *CacheLineSizes       = (i == 0 ? BigCacheLevelLineSizes :
+                                            i == 1 ? LittleCacheLevelLineSizes :
+                                                     GPUCoreCacheLevelLineSizes
+                                            );
+    const unsigned *CacheAssociativities = (i == 0 ?
+                                            BigCacheLevelAssociativities :
+                                            i == 1 ?
+                                            LittleCacheLevelAssociativities :
+                                            GPUCoreCacheLevelAssociativities);
+    const unsigned *CacheLatencies       = (i == 0 ? BigCacheLevelLatencies :
+                                            i == 1 ? LittleCacheLevelLatencies :
+                                                     GPUCoreCacheLevelLatencies
+                                            );
+
+    unsigned Index = (i == 0 ? BigL1 :
+                      i == 1 ? LittleL1 : GPUCoreL1);
+
+    EXPECT_STREQ(L1Level->getName(), CacheNames[Index]);
+    EXPECT_EQ(L1Level->getSizeInBytes(), CacheSizes[Index]);
+    EXPECT_EQ(L1Level->getLineSizeInBytes(), CacheLineSizes[Index]);
+    EXPECT_EQ(L1Level->getAssociativity(), CacheAssociativities[Index]);
+    EXPECT_EQ(L1Level->getLatency(), CacheLatencies[Index]);
+
+    ++i;
+  }
+
+  i = 0;
+  for (const auto L2Level : *L2Levels) {
+    const char *const *CacheNames        = BigCacheLevelNames;
+    const unsigned *CacheSizes           = BigCacheLevelSizes;
+    const unsigned *CacheLineSizes       = BigCacheLevelLineSizes;
+    const unsigned *CacheAssociativities = BigCacheLevelAssociativities;
+    const unsigned *CacheLatencies       = BigCacheLevelLatencies;
+
+    unsigned Index = BigL2;
+
+    EXPECT_STREQ(L2Level->getName(), CacheNames[Index]);
+    EXPECT_EQ(L2Level->getSizeInBytes(), CacheSizes[Index]);
+    EXPECT_EQ(L2Level->getLineSizeInBytes(), CacheLineSizes[Index]);
+    EXPECT_EQ(L2Level->getAssociativity(), CacheAssociativities[Index]);
+    EXPECT_EQ(L2Level->getLatency(), CacheLatencies[Index]);
+
+    ++i;
+  }
+
+  i = 0;
+  for (const auto L3Level : *L3Levels) {
+    const char *const *CacheNames        = CPUCacheLevelNames;
+    const unsigned *CacheSizes           = CPUCacheLevelSizes;
+    const unsigned *CacheLineSizes       = CPUCacheLevelLineSizes;
+    const unsigned *CacheAssociativities = CPUCacheLevelAssociativities;
+    const unsigned *CacheLatencies       = CPUCacheLevelLatencies;
+
+    unsigned Index = CPUL3;
+
+    EXPECT_STREQ(L3Level->getName(), CacheNames[Index]);
+    EXPECT_EQ(L3Level->getSizeInBytes(), CacheSizes[Index]);
+    EXPECT_EQ(L3Level->getLineSizeInBytes(), CacheLineSizes[Index]);
+    EXPECT_EQ(L3Level->getAssociativity(), CacheAssociativities[Index]);
+    EXPECT_EQ(L3Level->getLatency(), CacheLatencies[Index]);
+
+    ++i;
+  }
+}
+
+TEST(SystemModel, Topology3Tests) {
+  // Test this topology:
+  //
+  //              System
+  //              /    \
+  //        (L1) GPU   CPU (L3)
+  //              |   /     \
+  //              C  L (L1)  B (L1, L2)
+
+  const unsigned BigL1 = 0;
+  const unsigned BigL2 = 1;
+
+  const unsigned LittleL1 = 0;
+
+  const unsigned CPUL3 = 0;
+
+  const unsigned GPUL1 = 0;
+
+  const unsigned Big = 0;
+  const unsigned Little = 1;
+
+  const unsigned GPU = 0;
+
+  const unsigned CPUSocket = 0;
+  const unsigned GPUSocket = 1;
+
+  // Define cache parameters.
+  const char *BigCacheLevelNames[]        = { "BigL1", "BigL2" };
+  unsigned BigCacheLevelSizes[]           = { 1024*16, 1024 * 1024*4 };
+  unsigned BigCacheLevelLineSizes[]       = { 32,      32 };
+  unsigned BigCacheLevelAssociativities[] = { 8,       24 };
+  unsigned BigCacheLevelLatencies[]       = { 2,       12 };
+
+  const char *LittleCacheLevelNames[]        = { "LittleL1" };
+  unsigned LittleCacheLevelSizes[]           = { 1024*8 };
+  unsigned LittleCacheLevelLineSizes[]       = { 32 };
+  unsigned LittleCacheLevelAssociativities[] = { 8 };
+  unsigned LittleCacheLevelLatencies[]       = { 2 };
+
+  const char *CPUCacheLevelNames[]        = { "CPUL3" };
+  unsigned CPUCacheLevelSizes[]           = { 1024*1024*8 };
+  unsigned CPUCacheLevelLineSizes[]       = { 32 };
+  unsigned CPUCacheLevelAssociativities[] = { 32 };
+  unsigned CPUCacheLevelLatencies[]       = { 50 };
+
+  const char *GPUCacheLevelNames[]        = { "GPUL1" };
+  unsigned GPUCacheLevelSizes[]           = { 1024*64 };
+  unsigned GPUCacheLevelLineSizes[]       = { 64 };
+  unsigned GPUCacheLevelAssociativities[] = { 24 };
+  unsigned GPUCacheLevelLatencies[]       = { 12 };
+
+  // Define thread parameters.
+  const char *ThreadName = "Thread";
+
+  // Define core parameters.
+  // The GPU has four cores with two thread team schedulers of vector
+  // length 64, for a total of 512 "threads."
+  const char *CPUCoreNames[] = { "BigCore", "LittleCore" };
+  unsigned CPUCoreCounts[]   = { 2,         8 };
+  unsigned CPUThreadCounts[] = { 4,         2 };
+
+  const char *GPUCoreNames[] = { "GPUCore" };
+  unsigned GPUCoreCounts[]   = { 4 };
+  // Threads in a core.  The GPU has two thread team schedulers, each
+  // team may be a vector length of, say, 64 which we don't model.
+  unsigned GPUThreadCounts[] = { 2 };
+
+  // Define socket parameters.
+  const char *SocketNames[] = { "CPU", "GPU" };
+  unsigned CoreTypeCounts[] = { 2,     1 };
+
+  unsigned ID = 0;
+
+  // Define write-combining buffers.
+  MCWriteCombiningBufferInfo WCBufs(ID++, "WCBufs", 4);
+  MCWriteCombiningBufferInfo NoWCBufs(ID++, "NoWCBufs", 0);
+
+  // Define software prefetchers.
+  MCSoftwarePrefetcherConfig Prefetcher(ID++, "Prefetcher", true, true, 1024,
+                                        512, 4096, 100, 4, 32);
+
+  MCSoftwarePrefetcherConfig NoPrefetcher(ID++, "NoPrefetcher", false, false, 0,
+                                          0, 0, 0, 0, 0);
+
+  // Define caches.
+  MCCacheLevelInfo BigCoreCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     BigCacheLevelNames[BigL1],
+                     BigCacheLevelSizes[BigL1],
+                     BigCacheLevelLineSizes[BigL1],
+                     BigCacheLevelAssociativities[BigL1],
+                     BigCacheLevelLatencies[BigL1]),
+    MCCacheLevelInfo(ID++,
+                     BigCacheLevelNames[BigL2],
+                     BigCacheLevelSizes[BigL2],
+                     BigCacheLevelLineSizes[BigL2],
+                     BigCacheLevelAssociativities[BigL2],
+                     BigCacheLevelLatencies[BigL2]),
+  };
+
+  MCCacheLevelInfo LittleCoreCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     LittleCacheLevelNames[LittleL1],
+                     LittleCacheLevelSizes[LittleL1],
+                     LittleCacheLevelLineSizes[LittleL1],
+                     LittleCacheLevelAssociativities[LittleL1],
+                     LittleCacheLevelLatencies[LittleL1]),
+  };
+
+  MCCacheLevelInfo CPUCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     CPUCacheLevelNames[CPUL3],
+                     CPUCacheLevelSizes[CPUL3],
+                     CPUCacheLevelLineSizes[CPUL3],
+                     CPUCacheLevelAssociativities[CPUL3],
+                     CPUCacheLevelLatencies[CPUL3]),
+  };
+
+  // All GPU cores share one level of cache.
+  MCCacheLevelInfo GPUCacheLevels[] = {
+    MCCacheLevelInfo(ID++,
+                     GPUCacheLevelNames[GPUL1],
+                     GPUCacheLevelSizes[GPUL1],
+                     GPUCacheLevelLineSizes[GPUL1],
+                     GPUCacheLevelAssociativities[GPUL1],
+                     GPUCacheLevelLatencies[GPUL1]),
+  };
+
+  // Define memory models.
+  MCMemoryModel BigMemModel(ID++,
+                            "BigMemModel",
+                            BigCoreCacheLevels,
+                            2,
+                            WCBufs,
+                            Prefetcher);
+
+  MCMemoryModel LittleMemModel(ID++,
+                               "LittleMemModel",
+                               LittleCoreCacheLevels,
+                               1,
+                               WCBufs,
+                               Prefetcher);
+
+  MCMemoryModel CPUMemModel(ID++,
+                            "CPUMemModel",
+                            CPUCacheLevels,
+                            1,
+                            NoWCBufs,
+                            NoPrefetcher);
+
+  MCMemoryModel GPUMemModel(ID++,
+                            "GPUMemModel",
+                            GPUCacheLevels,
+                            1,
+                            NoWCBufs,
+                            NoPrefetcher);
+
+  MCMemoryModel NoMemModel(ID++, "NoModel", nullptr, 0, NoWCBufs, NoPrefetcher);
+
+  // Define threads.
+  MCExecutionResource CommonThread(ID++, ThreadName, nullptr, 0, NoMemModel);
+
+  // Define cores.
+  MCExecutionResourceDesc BigThreadDesc(ID++,
+                                        "BigThreadDesc",
+                                        &CommonThread,
+                                        CPUThreadCounts[Big]);
+  MCExecutionResourceDesc LittleThreadDesc(ID++,
+                                           "LittleThreadDesc",
+                                           &CommonThread,
+                                           CPUThreadCounts[Little]);
+  MCExecutionResourceDesc GPUThreadDesc(ID++,
+                                        "GPUThreadDesc",
+                                        &CommonThread,
+                                        GPUThreadCounts[GPU]);
+
+  MCExecutionResourceDesc *BigThreadsList[] = { &BigThreadDesc };
+  MCExecutionResourceDesc *LittleThreadsList[] = { &LittleThreadDesc };
+  MCExecutionResourceDesc *GPUThreadsList[] = { &GPUThreadDesc };
+
+  MCExecutionResource BigCore(ID++,
+                              CPUCoreNames[Big],
+                              BigThreadsList,
+                              1,
+                              BigMemModel);
+
+  MCExecutionResource LittleCore(ID++,
+                                 CPUCoreNames[Little],
+                                 LittleThreadsList,
+                                 1,
+                                 LittleMemModel);
+
+  MCExecutionResource GPUCore(ID++,
+                              GPUCoreNames[GPU],
+                              GPUThreadsList,
+                              1,
+                              NoMemModel);
+
+  // Define sockets.
+  MCExecutionResourceDesc BigCoreDesc(ID++,
+                                      "BigCoreDesc",
+                                      &BigCore,
+                                      CPUCoreCounts[Big]);
+
+  MCExecutionResourceDesc LittleCoreDesc(ID++,
+                                         "LittleCoreDesc",
+                                         &LittleCore,
+                                         CPUCoreCounts[Little]);
+
+  MCExecutionResourceDesc GPUCoreDesc(ID++,
+                                      "GPUCoreDesc",
+                                      &GPUCore,
+                                      GPUCoreCounts[GPU]);
+
+  MCExecutionResourceDesc *CPUCoreList[] = { &BigCoreDesc, &LittleCoreDesc };
+  MCExecutionResourceDesc *GPUCoreList[] = { &GPUCoreDesc };
+
+  MCExecutionResource CPUEngine(ID++,
+                                SocketNames[CPUSocket],
+                                CPUCoreList,
+                                2,
+                                CPUMemModel);
+
+  MCExecutionResource GPUEngine(ID++,
+                                SocketNames[GPUSocket],
+                                GPUCoreList,
+                                1,
+                                GPUMemModel);
+
+  // Define a node consisting of a CPU socket and a GPU socket.
+  MCExecutionResourceDesc CPUSocketDesc(ID++, "CPUSocketDesc", &CPUEngine, 1);
+  MCExecutionResourceDesc GPUSocketDesc(ID++, "GPUSocketDesc", &GPUEngine, 1);
+
+  MCExecutionResourceDesc *SocketList[] = { &CPUSocketDesc, &GPUSocketDesc };
+
+  MCSystemModel Node(ID++, "Node", SocketList, 2);
+
+  // Test the topology.
+  EXPECT_EQ(Node.getNumExecutionResourceTypes(), 2u);
+
+  unsigned s = 0;
+  for (const auto &SocketDesc : Node) {
+    EXPECT_EQ(SocketDesc.getNumResources(), 1u);
+
+    const auto &Socket = SocketDesc.getResource();
+    EXPECT_STREQ(Socket.getName(), SocketNames[s]);
+    EXPECT_EQ(Socket.getNumContainedExecutionResourceTypes(),
+              CoreTypeCounts[s]);
+
+    unsigned *CoreCounts         = (s == CPUSocket ?
+                                    CPUCoreCounts   : GPUCoreCounts);
+    const char *const *CoreNames = (s == CPUSocket ?
+                                    CPUCoreNames    : GPUCoreNames);
+    unsigned *ThreadCounts       = (s == CPUSocket ?
+                                    CPUThreadCounts : GPUThreadCounts);
+
+    unsigned c = 0;
+    for (const auto &CoreDesc : Socket) {
+      EXPECT_EQ(CoreDesc.getNumResources(), CoreCounts[c]);
+
+      const auto &Core = CoreDesc.getResource();
+      EXPECT_STREQ(Core.getName(), CoreNames[c]);
+
+      EXPECT_EQ(Core.getNumContainedExecutionResourceTypes(), 1u);
+
+      const auto &ThreadDesc = Core.getResourceDescriptor(0);
+      EXPECT_EQ(ThreadDesc.getNumResources(), ThreadCounts[c]);
+
+      const auto &Thread = ThreadDesc.getResource();
+      EXPECT_STREQ(Thread.getName(), ThreadName);
+
+      EXPECT_EQ(Thread.getNumContainedExecutionResourceTypes(), 0u);
+
+      // Check thread-level caches.
+      unsigned NumThreadCacheLevels =
+        Thread.getMemoryModel().getNumCacheLevels();
+      EXPECT_EQ(NumThreadCacheLevels, 0u);
+
+      // Check core-level caches.
+      if (s == GPUSocket) {
+        unsigned NumCoreCacheLevels =
+          Thread.getMemoryModel().getNumCacheLevels();
+        EXPECT_EQ(NumCoreCacheLevels, 0u);
+      }
+
+      const char *const *CacheNames        = (c == Big ?
+                                              BigCacheLevelNames :
+                                              LittleCacheLevelNames);
+      const unsigned *CacheSizes           = (c == Big ?
+                                              BigCacheLevelSizes :
+                                              LittleCacheLevelSizes);
+      const unsigned *CacheLineSizes       = (c == Big ?
+                                              BigCacheLevelLineSizes :
+                                              LittleCacheLevelLineSizes);
+      const unsigned *CacheAssociativities = (c == Big ?
+                                              BigCacheLevelAssociativities :
+                                              LittleCacheLevelAssociativities);
+      const unsigned *CacheLatencies       = (c == Big ?
+                                              BigCacheLevelLatencies :
+                                              LittleCacheLevelLatencies);
+
+      unsigned lvl = 0;
+      for (const auto &CacheLevel : Core.getMemoryModel()) {
+        EXPECT_STREQ(CacheLevel.getName(), CacheNames[lvl]);
+        EXPECT_EQ(CacheLevel.getSizeInBytes(), CacheSizes[lvl]);
+        EXPECT_EQ(CacheLevel.getLineSizeInBytes(), CacheLineSizes[lvl]);
+        EXPECT_EQ(CacheLevel.getAssociativity(), CacheAssociativities[lvl]);
+        EXPECT_EQ(CacheLevel.getLatency(), CacheLatencies[lvl]);
+
+        ++lvl;
+      }
+
+      ++c;
+    }
+
+    // Check socket-level caches.
+    const char *const *CacheNames        = (s == CPUSocket ?
+                                            CPUCacheLevelNames :
+                                            GPUCacheLevelNames);
+    const unsigned *CacheSizes           = (s == CPUSocket ?
+                                            CPUCacheLevelSizes :
+                                            GPUCacheLevelSizes);
+    const unsigned *CacheLineSizes       = (s == CPUSocket ?
+                                            CPUCacheLevelLineSizes :
+                                            GPUCacheLevelLineSizes);
+    const unsigned *CacheAssociativities = (s == CPUSocket ?
+                                            CPUCacheLevelAssociativities :
+                                            GPUCacheLevelAssociativities);
+    const unsigned *CacheLatencies       = (s == CPUSocket ?
+                                            CPUCacheLevelLatencies :
+                                            GPUCacheLevelLatencies);
+
+    unsigned lvl = 0;
+    for (const auto &CacheLevel : Socket.getMemoryModel()) {
+      EXPECT_STREQ(CacheLevel.getName(), CacheNames[lvl]);
+      EXPECT_EQ(CacheLevel.getSizeInBytes(), CacheSizes[lvl]);
+      EXPECT_EQ(CacheLevel.getLineSizeInBytes(), CacheLineSizes[lvl]);
+      EXPECT_EQ(CacheLevel.getAssociativity(), CacheAssociativities[lvl]);
+      EXPECT_EQ(CacheLevel.getLatency(), CacheLatencies[lvl]);
+
+      ++lvl;
+    }
+
+    ++s;
+  }
+
+  // Test the global system representation of the memory model.
+  const MCSystemModel::CacheLevelList *L1Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L1);
+  const MCSystemModel::CacheLevelList *L2Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L2);
+  const MCSystemModel::CacheLevelList *L3Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L3);
+  const MCSystemModel::CacheLevelList *L4Levels =
+    Node.getCacheLevelInfo(MCSystemModel::CacheLevel::L4);
+
+  const MCSystemModel::PrefetchConfigList &PrefetchConfigs =
+    Node.getSoftwarePrefetcherInfo();
+
+  EXPECT_NE(L1Levels, nullptr);
+  EXPECT_NE(L2Levels, nullptr);
+  EXPECT_NE(L3Levels, nullptr);
+  EXPECT_EQ(L4Levels, nullptr);
+
+  EXPECT_EQ(L1Levels->size(), 3u);
+  EXPECT_EQ(L2Levels->size(), 1u);
+  EXPECT_EQ(L3Levels->size(), 1u);
+  EXPECT_EQ(PrefetchConfigs.size(), 2u);
+
+  unsigned i = 0;
+  for (const auto L1Level : *L1Levels) {
+    const char *const *CacheNames        = (i == 0 ? BigCacheLevelNames :
+                                            i == 1 ? LittleCacheLevelNames :
+                                                     GPUCacheLevelNames);
+    const unsigned *CacheSizes           = (i == 0 ? BigCacheLevelSizes :
+                                            i == 1 ? LittleCacheLevelSizes :
+                                                     GPUCacheLevelSizes);
+    const unsigned *CacheLineSizes       = (i == 0 ? BigCacheLevelLineSizes :
+                                            i == 1 ? LittleCacheLevelLineSizes :
+                                                     GPUCacheLevelLineSizes);
+    const unsigned *CacheAssociativities = (i == 0 ?
+                                            BigCacheLevelAssociativities :
+                                            i == 1 ?
+                                            LittleCacheLevelAssociativities :
+                                            GPUCacheLevelAssociativities);
+    const unsigned *CacheLatencies       = (i == 0 ? BigCacheLevelLatencies :
+                                            i == 1 ? LittleCacheLevelLatencies :
+                                                     GPUCacheLevelLatencies);
+
+    unsigned Index = (i == 0 ? BigL1 :
+                      i == 1 ? LittleL1 : GPUL1);
+
+    EXPECT_STREQ(L1Level->getName(), CacheNames[Index]);
+    EXPECT_EQ(L1Level->getSizeInBytes(), CacheSizes[Index]);
+    EXPECT_EQ(L1Level->getLineSizeInBytes(), CacheLineSizes[Index]);
+    EXPECT_EQ(L1Level->getAssociativity(), CacheAssociativities[Index]);
+    EXPECT_EQ(L1Level->getLatency(), CacheLatencies[Index]);
+
+    ++i;
+  }
+
+  i = 0;
+  for (const auto L2Level : *L2Levels) {
+    const char *const *CacheNames        = BigCacheLevelNames;
+    const unsigned *CacheSizes           = BigCacheLevelSizes;
+    const unsigned *CacheLineSizes       = BigCacheLevelLineSizes;
+    const unsigned *CacheAssociativities = BigCacheLevelAssociativities;
+    const unsigned *CacheLatencies       = BigCacheLevelLatencies;
+
+    unsigned Index = BigL2;
+
+    EXPECT_STREQ(L2Level->getName(), CacheNames[Index]);
+    EXPECT_EQ(L2Level->getSizeInBytes(), CacheSizes[Index]);
+    EXPECT_EQ(L2Level->getLineSizeInBytes(), CacheLineSizes[Index]);
+    EXPECT_EQ(L2Level->getAssociativity(), CacheAssociativities[Index]);
+    EXPECT_EQ(L2Level->getLatency(), CacheLatencies[Index]);
+
+    ++i;
+  }
+
+  i = 0;
+  for (const auto L3Level : *L3Levels) {
+    const char *const *CacheNames        = CPUCacheLevelNames;
+    const unsigned *CacheSizes           = CPUCacheLevelSizes;
+    const unsigned *CacheLineSizes       = CPUCacheLevelLineSizes;
+    const unsigned *CacheAssociativities = CPUCacheLevelAssociativities;
+    const unsigned *CacheLatencies       = CPUCacheLevelLatencies;
+
+    unsigned Index = CPUL3;
+
+    EXPECT_STREQ(L3Level->getName(), CacheNames[Index]);
+    EXPECT_EQ(L3Level->getSizeInBytes(), CacheSizes[Index]);
+    EXPECT_EQ(L3Level->getLineSizeInBytes(), CacheLineSizes[Index]);
+    EXPECT_EQ(L3Level->getAssociativity(), CacheAssociativities[Index]);
+    EXPECT_EQ(L3Level->getLatency(), CacheLatencies[Index]);
+
+    ++i;
+  }
+}
+
+} // end namespace

llvm/utils/TableGen/SubtargetEmitter.cpp

 #include "llvm/Support/Format.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
+#include <functional>
 #include <iterator>
 #include <map>
 #include <string>
 #include <vector>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "subtarget-emitter"
class SubtargetEmitter {
   void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
   void emitSchedModelHelpersImpl(raw_ostream &OS,
                                  bool OnlyExpandMCInstPredicates = false);
   void emitGenMCSubtargetInfo(raw_ostream &OS);
   void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS);
 
   void EmitSchedModel(raw_ostream &OS);
   void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
+
+  void EmitCacheHierarchies(raw_ostream &OS, unsigned &ID);
+  void EmitWriteCombiningBuffers(raw_ostream &OS, unsigned &ID);
+  void EmitPrefetchConfigs(raw_ostream &OS, unsigned &ID);
+  void EmitMemoryModel(raw_ostream &OS, Record &M, unsigned &ID);
+  void EmitMemoryModels(raw_ostream &OS, unsigned &ID);
+  void EmitExecutionResource(raw_ostream &OS, Record &Resource, unsigned &ID,
+                             SmallPtrSetImpl<Record *> &Emitted);
+  void EmitExecutionResourceDesc(raw_ostream &OS, Record &ResourceDesc,
+                                 unsigned &ID,
+                                 SmallPtrSetImpl<Record *> &Emitted);
+  void EmitExecutionResourceDescResource(raw_ostream &OS, Record &ResourceDesc,
+                                         unsigned &ID,
+                                         SmallPtrSetImpl<Record *> &Emitted);
+  void EmitExecutionResourceList(raw_ostream &OS, StringRef ListName,
+                                 const ListInit &ResourceList,
+                                 unsigned &ID,
+                                 SmallPtrSetImpl<Record *> &Emitted);
+  void EmitSystemModel(raw_ostream &OS, Record &E, unsigned &ID,
+                       SmallPtrSetImpl<Record *> &Emitted);
+  void EmitSystemModels(raw_ostream &OS);
+
   void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
                              unsigned NumProcs);
 
 public:
   SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT)
     : TGT(TGT), Records(R), SchedModels(TGT.getSchedModels()),
       Target(TGT.getName()) {}
 
for (Record *Processor : ProcessorList) {
     OS << " { "
        << "\"" << Name << "\", ";
 
     printFeatureMask(OS, FeatureList, FeatureMap);
 
     // Emit the scheduler model pointer.
     const std::string &ProcModelName =
       SchedModels.getModelForProc(Processor).ModelName;
-    OS << ", &" << ProcModelName << " },\n";
+    OS << ", &" << ProcModelName;
+
+    // Emit the system model pointer.
+    const std::string &SystemModelName =
+      Processor->getValueAsDef("System")->getName();
+    OS << ", &" << SystemModelName << " },\n";
   }
 
   // End processor table
   OS << "};\n";
 
   return ProcessorList.size();
 }
 
void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName,
   for (unsigned M = 1, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {
     const HwMode &HM = CGH.getMode(M);
     OS << "  if (checkFeatures(\"" << HM.Features
        << "\")) return " << M << ";\n";
   }
   OS << "  return 0;\n}\n";
 }
 
+// EmitCacheHierarchies - Emits all cache hierarchy information.
+//
+void SubtargetEmitter::EmitCacheHierarchies(raw_ostream &OS, unsigned &ID) {
+  std::vector<Record*> CacheHierarchies =
+    Records.getAllDerivedDefinitions("CacheHierarchy");
+
+  for (const auto &CH : CacheHierarchies) {
+    RecordVal *Levels = CH->getValue("Levels");
+    const ListInit &LevelList = *cast<const ListInit>(Levels->getValue());
+
+    std::function<const char * ()>  Delimeter = [&]() -> const char * {
+      Delimeter = []() -> const char * {
+        return ",";
+      };
+      return "";
+    };
+
+    OS << "static const llvm::MCCacheLevelInfo " << CH->getName() << "[] = {";
+    for (const auto &L : LevelList) {
+      OS << Delimeter() << '\n';
+
+      const DefInit &LevelDef = *cast<const DefInit>(L);
+      Record *Level = LevelDef.getDef();
+
+      RecordVal *LevelSize     = Level->getValue("Size");
+      RecordVal *LevelLineSize = Level->getValue("LineSize");
+      RecordVal *LevelWays     = Level->getValue("Ways");
+      RecordVal *LevelLatency  = Level->getValue("Latency");
+
+      OS << "  llvm::MCCacheLevelInfo("
+         << ID++ << ", \""
+         << Level->getName() << "\", "
+         << LevelSize->getValue()->getAsString() << ", "
+         << LevelLineSize->getValue()->getAsString() << ", "
+         << LevelWays->getValue()->getAsString() << ", "
+         << LevelLatency->getValue()->getAsString() << ')';
+    }
+    if (LevelList.empty()) {
+      OS << "\n  llvm::MCCacheLevelInfo(0, \"Empty\", 0, 0, 0, 0)";
+    }
+    OS << "\n};  // " << CH->getName() << "\n\n";
+  }
+}
+
+// Emits all write-combining buffer information.
+//
+void SubtargetEmitter::EmitWriteCombiningBuffers(raw_ostream &OS,
+                                                 unsigned &ID) {
+  std::vector<Record*> WCBuffers =
+    Records.getAllDerivedDefinitions("WriteCombiningBuffer");
+
+  for (const auto &WCBuffer : WCBuffers) {
+    RecordVal *WCBuffers = WCBuffer->getValue("NumBuffers");
+
+    OS << "static const llvm::MCWriteCombiningBufferInfo " << WCBuffer->getName()
+       << "(";
+    OS << ID++ << ", \"" << WCBuffer->getName() << "\", ";
+    OS << WCBuffers->getValue()->getAsString() << ");\n\n";
+  }
+}
+
+// Emits all prefetcer information.
+//
+void SubtargetEmitter::EmitPrefetchConfigs(raw_ostream &OS, unsigned &ID) {
+  std::vector<Record*> Prefetchers =
+    Records.getAllDerivedDefinitions("SoftwarePrefetcher");
+
+  for (const auto &P : Prefetchers) {
+    RecordVal *EnabledForReads      = P->getValue("EnabledForWrites");
+    RecordVal *EnabledForWrites     = P->getValue("EnabledForReads");
+    RecordVal *ByteDistance         = P->getValue("BytesAhead");
+    RecordVal *MaxByteDistance      = P->getValue("MaxBytesAhead");
+    RecordVal *MinByteDistance      = P->getValue("MinBytesAhead");
+    RecordVal *InstructionDistance  = P->getValue("InstructionsAhead");
+    RecordVal *MaxIterationDistance = P->getValue("MaxIterationsAhead");
+    RecordVal *MinByteStride        = P->getValue("MinStride");
+
+    OS << "static const llvm::MCSoftwarePrefetcherConfig " << P->getName()
+       << "("
+       << ID++ << ", \"" << P->getName() << "\", "
+       << EnabledForReads->getValue()->getAsString() << ", "
+       << EnabledForWrites->getValue()->getAsString() << ", "
+       << ByteDistance->getValue()->getAsString() << ", "
+       << MinByteDistance->getValue()->getAsString() << ", "
+       << MaxByteDistance->getValue()->getAsString() << ", "
+       << InstructionDistance->getValue()->getAsString() << ", "
+       << MaxIterationDistance->getValue()->getAsString() << ", "
+       << MinByteStride->getValue()->getAsString() << ");\n\n";
+  }
+}
+
+// Emits one memory system definition.
+//
+void SubtargetEmitter::EmitMemoryModel(raw_ostream &OS, Record &M,
+                                       unsigned &ID) {
+  RecordVal *CacheHierarchyValue = M.getValue("Caches");
+  const DefInit &CacheHierarchyDef =
+    *cast<const DefInit >(CacheHierarchyValue->getValue());
+  Record *CacheHierarchy = CacheHierarchyDef.getDef();
+
+  // Get cache level information.
+  RecordVal *CacheLevelValue = CacheHierarchy->getValue("Levels");
+  const ListInit &CacheLevelsList =
+    *cast<const ListInit>(CacheLevelValue->getValue());
+  unsigned NumLevels = CacheLevelsList.size();
+
+  RecordVal *WCBufferValue = M.getValue("WCBuffers");
+  const DefInit &WCBufferDef =
+    *cast<const DefInit>(WCBufferValue->getValue());
+  Record *WCBuffer = WCBufferDef.getDef();
+
+  RecordVal *PrefetcherValue = M.getValue("Prefetcher");
+  const DefInit &PrefetcherDef =
+    *cast<const DefInit>(PrefetcherValue->getValue());
+  Record *Prefetcher = PrefetcherDef.getDef();
+
+  OS << "static const llvm::MCMemoryModel " << M.getName() << "("
+     << ID++ << ", \"" << M.getName() << "\", "
+     << CacheHierarchy->getName() << ", "
+     << NumLevels << ", "
+     << WCBuffer->getName() << ", "
+     << Prefetcher->getName() << ");\n\n";
+}
+
+// Emits all memory system information.
+//
+void SubtargetEmitter::EmitMemoryModels(raw_ostream &OS, unsigned &ID) {
+  std::vector<Record*> MemoryModels =
+    Records.getAllDerivedDefinitions("MemoryModel");
+
+  for (const auto &M : MemoryModels) {
+    EmitMemoryModel(OS, *M, ID);
+  }
+}
+
+// Emits all contained execution slices if not already emitted, then
+// emits this one.
+//
+void
+SubtargetEmitter::EmitExecutionResource(raw_ostream &OS,
+                                        Record &Resource,
+                                        unsigned &ID,
+                                        SmallPtrSetImpl<Record *> &Emitted) {
+  RecordVal *ContainedValue = Resource.getValue("Contained");
+  const ListInit &ContainedList =
+    *cast<const ListInit>(ContainedValue->getValue());
+  unsigned NumContained = ContainedList.size();
+
+  // Emit all contained resources.
+  std::string ListName(Resource.getName());
+  ListName += "Contained";
+  EmitExecutionResourceList(OS, ListName, ContainedList, ID, Emitted);
+
+  // Emit the memory model;
+  RecordVal *MemoryModelValue = Resource.getValue("MemModel");
+  const DefInit &MemoryModelDef =
+    *cast<const DefInit>(MemoryModelValue->getValue());
+  Record *MemoryModel = MemoryModelDef.getDef();
+
+  // Now emit this resource.
+  OS << "static const llvm::MCExecutionResource " << Resource.getName()
+     << "("
+     << ID++ << ", \""
+     << Resource.getName() << "\", "
+     << ListName << ", "
+     << NumContained << ", "
+     << MemoryModel->getName() << ");\n\n";
+}
+
+// Emits an execution resource descriptor, emitting all contained
+// resources.
+//
+void
+SubtargetEmitter::EmitExecutionResourceDesc(raw_ostream &OS,
+                                            Record &ResourceDesc,
+                                            unsigned &ID,
+                                            SmallPtrSetImpl<Record *> &Emitted) {
+  EmitExecutionResourceDescResource(OS, ResourceDesc, ID, Emitted);
+
+  RecordVal *ResourceValue = ResourceDesc.getValue("Resource");
+  const DefInit &ResourceDef =
+    *cast<const DefInit>(ResourceValue->getValue());
+  Record *ResourceRecord = ResourceDef.getDef();
+
+  RecordVal *NumValue = ResourceDesc.getValue("NumResources");
+  const IntInit &ResourceInt =
+    *cast<const IntInit>(NumValue->getValue());
+
+  OS << "static const llvm::MCExecutionResourceDesc " << ResourceDesc.getName()
+     << "("
+     << ID++ << ", \""
+     << ResourceDesc.getName() << "\", "
+     << '&' << ResourceRecord->getName() << ", "
+     << ResourceInt.getValue() << ");\n\n";
+}
+
+// Emit the resource referenced by this execution resource
+// descriptor.
+//
+void SubtargetEmitter::
+EmitExecutionResourceDescResource(raw_ostream &OS,
+                                  Record &ResourceDesc,
+                                  unsigned &ID,
+                                  SmallPtrSetImpl<Record *> &Emitted) {
+  RecordVal *ResourceValue = ResourceDesc.getValue("Resource");
+  const DefInit &ResourceDef =
+    *cast<const DefInit>(ResourceValue->getValue());
+  Record *ResourceRecord = ResourceDef.getDef();
+
+  if (Emitted.insert(ResourceRecord).second)
+    EmitExecutionResource(OS, *ResourceRecord, ID, Emitted);
+}
+
+// Emit an execution resource list, creating the
+// MCExecutionResourceDesc necessary to describe contained resources.
+//
+void SubtargetEmitter::
+EmitExecutionResourceList(raw_ostream &OS,
+                          StringRef ListName,
+                          const ListInit &ResourceList,
+                          unsigned &ID,
+                          SmallPtrSetImpl<Record *> &Emitted) {
+  // First, emit all contained resources.  We have to do this here
+  // because we don't want resource definitions to appear in the
+  // middle of the array below.
+
+  for (auto ResourceDesc : ResourceList) {
+    const DefInit &ResourceDescDef = *cast<const DefInit>(ResourceDesc);
+    Record *ResourceDescRecord = ResourceDescDef.getDef();
+
+    if (Emitted.insert(ResourceDescRecord).second) {
+      EmitExecutionResourceDesc(OS, *ResourceDescRecord, ID, Emitted);
+    }
+  }
+
+  // Now emit the actual lists of resource descriptors.
+  std::function<const char * ()>  Delimeter = [&]() -> const char * {
+    Delimeter = []() -> const char * {
+      return ",";
+    };
+    return "";
+  };
+
+  OS << "static const llvm::MCExecutionResourceDesc *" << ListName << "[] = {";
+  for (auto ResourceDesc : ResourceList) {
+    const DefInit &ResourceDescDef = *cast<const DefInit>(ResourceDesc);
+    Record *ResourceDescRecord = ResourceDescDef.getDef();
+
+    OS << Delimeter() << "\n  &" << ResourceDescRecord->getName();
+  }
+  if (ResourceList.empty()) {
+    OS << "\n  nullptr";
+  }
+  OS << "\n};\n\n";
+}
+
+// Emit an execution engine.
+//
+void SubtargetEmitter::EmitSystemModel(raw_ostream &OS, Record &E,
+                                       unsigned &ID,
+                                       SmallPtrSetImpl<Record *> &Emitted) {
+  RecordVal *ResourcesValue = E.getValue("Resources");
+  const ListInit &ResourceList =
+    *cast<const ListInit>(ResourcesValue->getValue());
+  unsigned NumResources = ResourceList.size();
+
+  std::string ResourceListName;
+  ResourceListName += E.getName();
+  ResourceListName += "Resources";
+
+  EmitExecutionResourceList(OS, ResourceListName, ResourceList, ID, Emitted);
+
+  OS << "static const llvm::MCSystemModel " << E.getName() << "("
+     << ID << ", \"" << E.getName() << "\", "
+     << ResourceListName << ", "
+     << NumResources << ");\n\n";
+}
+
+// Emits all memory model and execution resource information.
+//
+void SubtargetEmitter::EmitSystemModels(raw_ostream &OS) {
+  unsigned ID = 1;
+
+  OS << "// ===============================================================\n"
+     << "// System model components\n"
+     << "// ===============================================================\n"
+     << "//\n\n";
+
+  // Emit memory models.
+  OS << "// ===============================================================\n"
+     << "// Cache models\n"
+     << "//\n";
+
+  EmitCacheHierarchies(OS, ID);
+
+  OS << "// ===============================================================\n"
+     << "// Write-combining buffers\n"
+     << "//\n";
+
+  EmitWriteCombiningBuffers(OS, ID);
+
+  OS << "// ===============================================================\n"
+     << "// Software prefetch configs\n"
+     << "//\n";
+
+  EmitPrefetchConfigs(OS, ID);
+
+  OS << "// ===============================================================\n"
+     << "// Memory models\n"
+     << "//\n";
+
+  EmitMemoryModels(OS, ID);
+
+  // Emit execution engines.
+  OS << "// ===============================================================\n"
+     << "// System models\n"
+     << "//\n";
+
+  // Emit a resource list for this engine.
+  SmallPtrSet<Record*, 8> EmittedResources;
+
+  std::vector<Record*> Systems =
+    Records.getAllDerivedDefinitions("SystemModel");
+
+  for (const auto &S : Systems) {
+    EmitSystemModel(OS, *S, ID, EmittedResources);
+  }
+}
+
 //
 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
 // the subtarget features string.
 //
 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
                                              unsigned NumFeatures,
                                              unsigned NumProcs) {
   std::vector<Record*> Features =
void SubtargetEmitter::run(raw_ostream &OS) {
   OS << "namespace llvm {\n";
 #if 0
   OS << "namespace {\n";
 #endif
   unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap);
   OS << "\n";
   EmitSchedModel(OS);
   OS << "\n";
-  unsigned NumProcs = CPUKeyValues(OS, FeatureMap);
+  EmitSystemModels(OS);
   OS << "\n";
+  unsigned NumProcs = CPUKeyValues(OS, FeatureMap);
 #if 0
   OS << "} // end anonymous namespace\n\n";
 #endif
 
   // MCInstrInfo initialization routine.
   emitGenMCSubtargetInfo(OS);
 
   OS << "\nstatic inline MCSubtargetInfo *create" << Target
#endif
   OS << '\n'; OS.indent(22);
   OS << Target << "WriteProcResTable, "
      << Target << "WriteLatencyTable, "
      << Target << "ReadAdvanceTable, ";
   OS << '\n'; OS.indent(22);
   if (SchedModels.hasItineraries()) {
     OS << Target << "Stages, "
        << Target << "OperandCycles, "
-       << Target << "ForwardingPaths";
+       << Target << "ForwardingPaths, ";
   } else
     OS << "nullptr, nullptr, nullptr";
   OS << ");\n}\n\n";
 
   OS << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";