add riscv32e to the llvm

[xudaliang.pku]

Summary

1. reserved x16-x31reg
2. RV32E ABI
   1. calling convention support
   2. stack align
3. add riscv32e target( --target=riscv32e )

[rogfer01]

lib/Target/RISCV/RISCVISelLowering.cpp

42

I wonder if we can avoid this global variable and instead use Subtarget.isEmbed() where needed.

This will require passing a const RISCVSubtarget& to some functions (like CC_RISCV) but given that they are local to the file, I think that would be reasonable.

[simoncook]

lib/Support/Triple.cpp

46

This should be on the same line as the case statement, similar to the rest of the table.

lib/Target/RISCV/RISCVFrameLowering.cpp

27

I think this would be more readable as /*StackAlignment=*/ STI.isEmbed() ? 4 : 16,

lib/Target/RISCV/RISCVFrameLowering.h

24

Did you mean to put a 'T' on the end of this variable name?

[jrtc27]

Why do we need another triple? Can we not just use the feature flag in the few cases where the code needs to tell the difference? There's a whole lot of boilerplate here just to add the new triple.

[kito-cheng]

rv32e arch and ilp32e ABI is decoupling in GCC, that's mean rv32i with ilp32e is possible, so I would suggest separate two thing.

[brucehoult]

In D53291#1266082, @kito-cheng wrote:

rv32e arch and ilp32e ABI is decoupling is GCC, that's mean rv32i with ilp32e is possible, so I would suggest separate two thing.

Very true.

In embedded systems it can often make sense to use the ilp32e ABI even on CPUs with 32 registers because there are significantly fewer argument and temporary registers, making interrupt response time shorter. All the high 16 registers are callee-save, which means you can use them if required but you need to save them first and restore them after.

[asb]

Hi Daliang and welcome to the LLVM community.

Many thanks for your work on RV32E support. In our discussion on the sw-dev mailing list I suggested splitting this task into the MC layer, calling convention, and codegen support. I'd recommend preparing patches in a way that does this. Each of these elements should come along with tests.

You shouldn't need to have riscv32e as a new triple. Just rely on the SubtargetFeature - this should remove a lot of code from this patch.

[xudaliang.pku]

In D53291#1266087, @brucehoult wrote:

In D53291#1266082, @kito-cheng wrote:

rv32e arch and ilp32e ABI is decoupling is GCC, that's mean rv32i with ilp32e is possible, so I would suggest separate two thing.

Very true.

In embedded systems it can often make sense to use the ilp32e ABI even on CPUs with 32 registers because there are significantly fewer argument and temporary registers, making interrupt response time shorter. All the high 16 registers are callee-save, which means you can use them if required but you need to save them first and restore them after.

Thanks for your advice.
I think decouple the rv32e and ilp32e is great. I have not considered it before. I will do it later.
But, I was not sure what rv32e and ilp32e really meaans. There is still something not clearly. Is the march rv32e only means that the regs only contains x0-x15 ? And the ABI ilp32e means Stack Alignment and calling convention, etc (see in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#rv32e-calling-convention )?

[brucehoult]

In D53291#1266158, @xudaliang.pku wrote:

But, I was not sure what rv32e and ilp32e really meaans. There is still something not clearly. Is the march rv32e only means that the regs only contains x0-x15 ? And the ABI ilp32e means Stack Alignment and calling convention, etc (see in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#rv32e-calling-convention )?

That's correct.

rv32e is just about hardware. Registers x16-x31 do not exist.

ilp32e is just about software. The function call convention and stack layout, as you say.

The link you point to should have that section renamed.

[xudaliang.pku]

In D53291#1266088, @asb wrote:

Hi Daliang and welcome to the LLVM community.

Many thanks for your work on RV32E support. In our discussion on the sw-dev mailing list I suggested splitting this task into the MC layer, calling convention, and codegen support. I'd recommend preparing patches in a way that does this. Each of these elements should come along with tests.

You shouldn't need to have riscv32e as a new triple. Just rely on the SubtargetFeature - this should remove a lot of code from this patch.

I will spilt the patch later as you said. It is the first time I have upload my patch. So, maybe I consider too little about how to show my work.I will do better next time.
Just like you and kito-cheng @kito-cheng have said. I had not added the triple:riscv32e in my work until I found clang-side needed to use that triple:riscv32e in the discussion on the sw-dev mailing list. The code in clang is like that

class RISCVABIInfo : public DefaultABIInfo {
private:
  unsigned XLen; // Size of the integer ('x') registers in bits.
  static const int NumArgGPRs = 8;

public:
  RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
      : DefaultABIInfo(CGT), XLen(XLen) { }
};

Because the RISCVABIInfo can't get the SubtargetFeatures, NumArgGPRs will always be 8 int the RISCVABIInfo even if the march=rv32e. So I have no way except for adding the triple:riscv32e. you can also see what I have changed the clang in https://reviews.llvm.org/D53293 about How I changed the NumArgGPRs by using triple:target. I was very confused how to solve this problem.Maybe a better way later.

lib/Support/Triple.cpp

46

Because of the first time using this tools to upload my patch, I was not familiar with it.
I feel very sorry to have some stupid mistakes in my patch. that you have prososed to me. I will modify them soonly

lib/Target/RISCV/RISCVISelLowering.cpp

42

I was not sure whether passing an argument like const RISCVSubtarget& to the functions (like CC_RISCV) may change too much.
Because it change the interface of the function. I have considered that way before.
I will try it later

[xudaliang.pku]

In D53291#1266198, @brucehoult wrote:

That's correct.

rv32e is just about hardware. Registers x16-x31 do not exist.

ilp32e is just about software. The function call convention and stack layout, as you say.

The link you point to should have that section renamed.

OK , Thanks for your verify about the march and the mabi. I will do it soon.

[jrtc27]

In D53291#1266207, @xudaliang.pku wrote:

In D53291#1266088, @asb wrote:

Hi Daliang and welcome to the LLVM community.

Many thanks for your work on RV32E support. In our discussion on the sw-dev mailing list I suggested splitting this task into the MC layer, calling convention, and codegen support. I'd recommend preparing patches in a way that does this. Each of these elements should come along with tests.

You shouldn't need to have riscv32e as a new triple. Just rely on the SubtargetFeature - this should remove a lot of code from this patch.

I will spilt the patch later as you said. It is the first time I have upload my patch. So, maybe I consider too little about how to show my work.I will do better next time.
Just like you and kito-cheng @kito-cheng have said. I had not added the triple:riscv32e in my work until I found clang-side needed to use that triple:riscv32e in the discussion on the sw-dev mailing list. The code in clang is like that

class RISCVABIInfo : public DefaultABIInfo {
private:
  unsigned XLen; // Size of the integer ('x') registers in bits.
  static const int NumArgGPRs = 8;

public:
  RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
      : DefaultABIInfo(CGT), XLen(XLen) { }
};

Because the RISCVABIInfo can't get the SubtargetFeatures, NumArgGPRs will always be 8 int the RISCVABIInfo even if the march=rv32e. So I have no way except for adding the triple:riscv32e. you can also see what I have changed the clang in https://reviews.llvm.org/D53293 about How I changed the NumArgGPRs by using triple:target. I was very confused how to solve this problem.Maybe a better way later.

The RISCVABIInfo constructor is called by RISCVTargetCodeGenInfo's constructor, which in turn is called by CodeGenModule::getTargetCodeGenInfo. CodeGenModule has a getTarget() which should give you access to the feature flags?

[xudaliang.pku]

In D53291#1266649, @jrtc27 wrote:

The RISCVABIInfo constructor is called by RISCVTargetCodeGenInfo's constructor, which in turn is called by CodeGenModule::getTargetCodeGenInfo. CodeGenModule has a getTarget() which should give you access to the feature flags?

Thanks for your advice, I will check the CodeGenModule and RISCVTargetCodeGenInfo's code to solve that problem I have proposed. In that way , we can remove the triple:riscv32e. That will be great!

[StephenFan]

Are you have plans to promote the codegen of rv32e, if not, I want to try it

[lenary]

In D53291#2473489, @StephenFan wrote:

Are you have plans to promote the codegen of rv32e, if not, I want to try it

It was my plan to work on it further, but that won't happen. The place to start is with support for the ilp32e ABI, and then add rv32e support after that.

One thing we don't want, as I understand, is a separate triple to denote rv32e - the use of -march and -mabi should be enough to not need a separate triple.

[lenary]

In D53291#2479912, @lenary wrote:

In D53291#2473489, @StephenFan wrote:

Are you have plans to promote the codegen of rv32e, if not, I want to try it

It was my plan to work on it further, but that won't happen. The place to start is with support for the ilp32e ABI, and then add rv32e support after that.

My patch for ilp32e support is here: D70401 - I've found a little time to go over it this week, and am working on some improvements as we speak. Hopefully it will be ready to review by the end of the week.

One thing we don't want, as I understand, is a separate triple to denote rv32e - the use of -march and -mabi should be enough to not need a separate triple.

include/llvm/ADT/Triple.h

 ///
 /// See autoconf/config.guess for a glimpse into what configuration names
 /// look like in practice.
 class Triple {
 public:
   enum ArchType {
     UnknownArch,
 
-    arm,            // ARM (little endian): arm, armv.*, xscale
-    armeb,          // ARM (big endian): armeb
-    aarch64,        // AArch64 (little endian): aarch64
-    aarch64_be,     // AArch64 (big endian): aarch64_be
-    arc,            // ARC: Synopsys ARC
-    avr,            // AVR: Atmel AVR microcontroller
-    bpfel,          // eBPF or extended BPF or 64-bit BPF (little endian)
-    bpfeb,          // eBPF or extended BPF or 64-bit BPF (big endian)
-    hexagon,        // Hexagon: hexagon
-    mips,           // MIPS: mips, mipsallegrex, mipsr6
-    mipsel,         // MIPSEL: mipsel, mipsallegrexe, mipsr6el
-    mips64,         // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
-    mips64el,       // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
-    msp430,         // MSP430: msp430
-    nios2,          // NIOSII: nios2
-    ppc,            // PPC: powerpc
-    ppc64,          // PPC64: powerpc64, ppu
-    ppc64le,        // PPC64LE: powerpc64le
-    r600,           // R600: AMD GPUs HD2XXX - HD6XXX
-    amdgcn,         // AMDGCN: AMD GCN GPUs
-    riscv32,        // RISC-V (32-bit): riscv32
-    riscv64,        // RISC-V (64-bit): riscv64
-    sparc,          // Sparc: sparc
-    sparcv9,        // Sparcv9: Sparcv9
-    sparcel,        // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
-    systemz,        // SystemZ: s390x
-    tce,            // TCE (http://tce.cs.tut.fi/): tce
-    tcele,          // TCE little endian (http://tce.cs.tut.fi/): tcele
-    thumb,          // Thumb (little endian): thumb, thumbv.*
-    thumbeb,        // Thumb (big endian): thumbeb
-    x86,            // X86: i[3-9]86
-    x86_64,         // X86-64: amd64, x86_64
-    xcore,          // XCore: xcore
-    nvptx,          // NVPTX: 32-bit
-    nvptx64,        // NVPTX: 64-bit
-    le32,           // le32: generic little-endian 32-bit CPU (PNaCl)
-    le64,           // le64: generic little-endian 64-bit CPU (PNaCl)
-    amdil,          // AMDIL
-    amdil64,        // AMDIL with 64-bit pointers
-    hsail,          // AMD HSAIL
-    hsail64,        // AMD HSAIL with 64-bit pointers
-    spir,           // SPIR: standard portable IR for OpenCL 32-bit version
-    spir64,         // SPIR: standard portable IR for OpenCL 64-bit version
-    kalimba,        // Kalimba: generic kalimba
-    shave,          // SHAVE: Movidius vector VLIW processors
-    lanai,          // Lanai: Lanai 32-bit
-    wasm32,         // WebAssembly with 32-bit pointers
-    wasm64,         // WebAssembly with 64-bit pointers
+    arm,        // ARM (little endian): arm, armv.*, xscale
+    armeb,      // ARM (big endian): armeb
+    aarch64,    // AArch64 (little endian): aarch64
+    aarch64_be, // AArch64 (big endian): aarch64_be
+    arc,        // ARC: Synopsys ARC
+    avr,        // AVR: Atmel AVR microcontroller
+    bpfel,      // eBPF or extended BPF or 64-bit BPF (little endian)
+    bpfeb,      // eBPF or extended BPF or 64-bit BPF (big endian)
+    hexagon,    // Hexagon: hexagon
+    mips,       // MIPS: mips, mipsallegrex, mipsr6
+    mipsel,     // MIPSEL: mipsel, mipsallegrexe, mipsr6el
+    mips64,     // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
+    mips64el,   // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
+    msp430,     // MSP430: msp430
+    nios2,      // NIOSII: nios2
+    ppc,        // PPC: powerpc
+    ppc64,      // PPC64: powerpc64, ppu
+    ppc64le,    // PPC64LE: powerpc64le
+    r600,       // R600: AMD GPUs HD2XXX - HD6XXX
+    amdgcn,     // AMDGCN: AMD GCN GPUs
+    riscv32,    // RISC-V (32-bit): riscv32
+    riscv32e,   // RISC-V (Embed):  riscv32e
+    riscv64,    // RISC-V (64-bit): riscv64
+    sparc,      // Sparc: sparc
+    sparcv9,    // Sparcv9: Sparcv9
+    sparcel,    // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
+    systemz,    // SystemZ: s390x
+    tce,        // TCE (http://tce.cs.tut.fi/): tce
+    tcele,      // TCE little endian (http://tce.cs.tut.fi/): tcele
+    thumb,      // Thumb (little endian): thumb, thumbv.*
+    thumbeb,    // Thumb (big endian): thumbeb
+    x86,        // X86: i[3-9]86
+    x86_64,     // X86-64: amd64, x86_64
+    xcore,      // XCore: xcore
+    nvptx,      // NVPTX: 32-bit
+    nvptx64,    // NVPTX: 64-bit
+    le32,       // le32: generic little-endian 32-bit CPU (PNaCl)
+    le64,       // le64: generic little-endian 64-bit CPU (PNaCl)
+    amdil,      // AMDIL
+    amdil64,    // AMDIL with 64-bit pointers
+    hsail,      // AMD HSAIL
+    hsail64,    // AMD HSAIL with 64-bit pointers
+    spir,       // SPIR: standard portable IR for OpenCL 32-bit version
+    spir64,     // SPIR: standard portable IR for OpenCL 64-bit version
+    kalimba,    // Kalimba: generic kalimba
+    shave,      // SHAVE: Movidius vector VLIW processors
+    lanai,      // Lanai: Lanai 32-bit
+    wasm32,     // WebAssembly with 32-bit pointers
+    wasm64,     // WebAssembly with 64-bit pointers
     renderscript32, // 32-bit RenderScript
     renderscript64, // 64-bit RenderScript
     LastArchType = renderscript64
   };
   enum SubArchType {
     NoSubArch,
 
     ARMSubArch_v8_5a,

lib/Support/Triple.cpp

StringRef Triple::getArchTypeName(ArchType Kind) {
   case msp430:         return "msp430";
   case nios2:          return "nios2";
   case ppc64:          return "powerpc64";
   case ppc64le:        return "powerpc64le";
   case ppc:            return "powerpc";
   case r600:           return "r600";
   case amdgcn:         return "amdgcn";
   case riscv32:        return "riscv32";
+  case riscv32e:
+    return "riscv32e";
   case riscv64:        return "riscv64";
   case sparc:          return "sparc";
   case sparcv9:        return "sparcv9";
   case sparcel:        return "sparcel";
   case systemz:        return "s390x";
   case tce:            return "tce";
   case tcele:          return "tcele";
   case thumb:          return "thumb";
StringRef Triple::getArchTypePrefix(ArchType Kind) {
   case spir64:      return "spir";
   case kalimba:     return "kalimba";
   case lanai:       return "lanai";
   case shave:       return "shave";
   case wasm32:
   case wasm64:      return "wasm";
 
   case riscv32:
+  case riscv32e:
   case riscv64:     return "riscv";
   }
 }
 
 StringRef Triple::getVendorTypeName(VendorType Kind) {
   switch (Kind) {
   case UnknownVendor: return "unknown";
 
static Triple::ArchType parseBPFArch(StringRef ArchName) {
   } else {
     return Triple::UnknownArch;
   }
 }
 
 Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
   Triple::ArchType BPFArch(parseBPFArch(Name));
   return StringSwitch<Triple::ArchType>(Name)
       .Case("aarch64", aarch64)
       .Case("aarch64_be", aarch64_be)
       .Case("arc", arc)
       .Case("arm64", aarch64) // "arm64" is an alias for "aarch64"
       .Case("arm", arm)
       .Case("armeb", armeb)
       .Case("avr", avr)
       .StartsWith("bpf", BPFArch)
       .Case("mips", mips)
       .Case("mipsel", mipsel)
       .Case("mips64", mips64)
       .Case("mips64el", mips64el)
       .Case("msp430", msp430)
       .Case("nios2", nios2)
       .Case("ppc64", ppc64)
       .Case("ppc32", ppc)
       .Case("ppc", ppc)
       .Case("ppc64le", ppc64le)
       .Case("r600", r600)
       .Case("amdgcn", amdgcn)
       .Case("riscv32", riscv32)
+      .Case("riscve", riscv32e)
       .Case("riscv64", riscv64)
       .Case("hexagon", hexagon)
       .Case("sparc", sparc)
       .Case("sparcel", sparcel)
       .Case("sparcv9", sparcv9)
       .Case("systemz", systemz)
       .Case("tce", tce)
       .Case("tcele", tcele)
       .Case("thumb", thumb)
       .Case("thumbeb", thumbeb)
       .Case("x86", x86)
       .Case("x86-64", x86_64)
       .Case("xcore", xcore)
       .Case("nvptx", nvptx)
       .Case("nvptx64", nvptx64)
       .Case("le32", le32)
       .Case("le64", le64)
       .Case("amdil", amdil)
       .Case("amdil64", amdil64)
       .Case("hsail", hsail)
       .Case("hsail64", hsail64)
       .Case("spir", spir)
       .Case("spir64", spir64)
       .Case("kalimba", kalimba)
       .Case("lanai", lanai)
       .Case("shave", shave)
       .Case("wasm32", wasm32)
       .Case("wasm64", wasm64)
       .Case("renderscript32", renderscript32)
       .Case("renderscript64", renderscript64)
       .Default(UnknownArch);
 }
 
 static Triple::ArchType parseARMArch(StringRef ArchName) {
   ARM::ISAKind ISA = ARM::parseArchISA(ArchName);
   ARM::EndianKind ENDIAN = ARM::parseArchEndian(ArchName);
 
   Triple::ArchType arch = Triple::UnknownArch;
   switch (ENDIAN) {
else
       return Triple::thumb;
   }
 
   return arch;
 }
 
 static Triple::ArchType parseArch(StringRef ArchName) {
   auto AT = StringSwitch<Triple::ArchType>(ArchName)
                 .Cases("i386", "i486", "i586", "i686", Triple::x86)
                 // FIXME: Do we need to support these?
                 .Cases("i786", "i886", "i986", Triple::x86)
                 .Cases("amd64", "x86_64", "x86_64h", Triple::x86_64)
                 .Cases("powerpc", "ppc", "ppc32", Triple::ppc)
                 .Cases("powerpc64", "ppu", "ppc64", Triple::ppc64)
                 .Cases("powerpc64le", "ppc64le", Triple::ppc64le)
                 .Case("xscale", Triple::arm)
                 .Case("xscaleeb", Triple::armeb)
                 .Case("aarch64", Triple::aarch64)
                 .Case("aarch64_be", Triple::aarch64_be)
                 .Case("arc", Triple::arc)
                 .Case("arm64", Triple::aarch64)
                 .Case("arm", Triple::arm)
                 .Case("armeb", Triple::armeb)
                 .Case("thumb", Triple::thumb)
                 .Case("thumbeb", Triple::thumbeb)
                 .Case("avr", Triple::avr)
                 .Case("msp430", Triple::msp430)
                 .Cases("mips", "mipseb", "mipsallegrex", "mipsisa32r6",
                        "mipsr6", Triple::mips)
                 .Cases("mipsel", "mipsallegrexel", "mipsisa32r6el", "mipsr6el",
                        Triple::mipsel)
                 .Cases("mips64", "mips64eb", "mipsn32", "mipsisa64r6",
                        "mips64r6", "mipsn32r6", Triple::mips64)
                 .Cases("mips64el", "mipsn32el", "mipsisa64r6el", "mips64r6el",
                        "mipsn32r6el", Triple::mips64el)
                 .Case("nios2", Triple::nios2)
                 .Case("r600", Triple::r600)
                 .Case("amdgcn", Triple::amdgcn)
                 .Case("riscv32", Triple::riscv32)
+                .Case("riscv32e", Triple::riscv32e)
                 .Case("riscv64", Triple::riscv64)
                 .Case("hexagon", Triple::hexagon)
                 .Cases("s390x", "systemz", Triple::systemz)
                 .Case("sparc", Triple::sparc)
                 .Case("sparcel", Triple::sparcel)
                 .Cases("sparcv9", "sparc64", Triple::sparcv9)
                 .Case("tce", Triple::tce)
                 .Case("tcele", Triple::tcele)
                 .Case("xcore", Triple::xcore)
                 .Case("nvptx", Triple::nvptx)
                 .Case("nvptx64", Triple::nvptx64)
                 .Case("le32", Triple::le32)
                 .Case("le64", Triple::le64)
                 .Case("amdil", Triple::amdil)
                 .Case("amdil64", Triple::amdil64)
                 .Case("hsail", Triple::hsail)
                 .Case("hsail64", Triple::hsail64)
                 .Case("spir", Triple::spir)
                 .Case("spir64", Triple::spir64)
                 .StartsWith("kalimba", Triple::kalimba)
                 .Case("lanai", Triple::lanai)
                 .Case("shave", Triple::shave)
                 .Case("wasm32", Triple::wasm32)
                 .Case("wasm64", Triple::wasm64)
                 .Case("renderscript32", Triple::renderscript32)
                 .Case("renderscript64", Triple::renderscript64)
                 .Default(Triple::UnknownArch);
 
   // Some architectures require special parsing logic just to compute the
   // ArchType result.
   if (AT == Triple::UnknownArch) {
     if (ArchName.startswith("arm") || ArchName.startswith("thumb") ||
         ArchName.startswith("aarch64"))
       return parseARMArch(ArchName);
     if (ArchName.startswith("bpf"))
static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
   case Triple::nios2:
   case Triple::nvptx:
   case Triple::nvptx64:
   case Triple::ppc64le:
   case Triple::r600:
   case Triple::renderscript32:
   case Triple::renderscript64:
   case Triple::riscv32:
+  case Triple::riscv32e:
   case Triple::riscv64:
   case Triple::shave:
   case Triple::sparc:
   case Triple::sparcel:
   case Triple::sparcv9:
   case Triple::spir:
   case Triple::spir64:
   case Triple::systemz:
static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   case llvm::Triple::le32:
   case llvm::Triple::mips:
   case llvm::Triple::mipsel:
   case llvm::Triple::nios2:
   case llvm::Triple::nvptx:
   case llvm::Triple::ppc:
   case llvm::Triple::r600:
   case llvm::Triple::riscv32:
+  case llvm::Triple::riscv32e:
   case llvm::Triple::sparc:
   case llvm::Triple::sparcel:
   case llvm::Triple::tce:
   case llvm::Triple::tcele:
   case llvm::Triple::thumb:
   case llvm::Triple::thumbeb:
   case llvm::Triple::x86:
   case llvm::Triple::xcore:
Triple Triple::get32BitArchVariant() const {
   case Triple::le32:
   case Triple::mips:
   case Triple::mipsel:
   case Triple::nios2:
   case Triple::nvptx:
   case Triple::ppc:
   case Triple::r600:
   case Triple::riscv32:
+  case Triple::riscv32e:
   case Triple::sparc:
   case Triple::sparcel:
   case Triple::tce:
   case Triple::tcele:
   case Triple::thumb:
   case Triple::thumbeb:
   case Triple::x86:
   case Triple::xcore:
Triple Triple::get64BitArchVariant() const {
   case Triple::msp430:
   case Triple::nios2:
   case Triple::r600:
   case Triple::tce:
   case Triple::tcele:
   case Triple::xcore:
   case Triple::sparcel:
   case Triple::shave:
+  case Triple::riscv32e:
     T.setArch(UnknownArch);
     break;
 
   case Triple::aarch64:
   case Triple::aarch64_be:
   case Triple::bpfel:
   case Triple::bpfeb:
   case Triple::le64:
Triple Triple::getBigEndianArchVariant() const {
   case Triple::le32:
   case Triple::le64:
   case Triple::msp430:
   case Triple::nios2:
   case Triple::nvptx64:
   case Triple::nvptx:
   case Triple::r600:
   case Triple::riscv32:
+  case Triple::riscv32e:
   case Triple::riscv64:
   case Triple::shave:
   case Triple::spir64:
   case Triple::spir:
   case Triple::wasm32:
   case Triple::wasm64:
   case Triple::x86:
   case Triple::x86_64:
bool Triple::isLittleEndian() const {
   case Triple::mipsel:
   case Triple::msp430:
   case Triple::nios2:
   case Triple::nvptx64:
   case Triple::nvptx:
   case Triple::ppc64le:
   case Triple::r600:
   case Triple::riscv32:
+  case Triple::riscv32e:
   case Triple::riscv64:
   case Triple::shave:
   case Triple::sparcel:
   case Triple::spir64:
   case Triple::spir:
   case Triple::thumb:
   case Triple::wasm32:
   case Triple::wasm64:

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
 
   emitToStreamer(Out, Inst);
   return false;
 }
 
 extern "C" void LLVMInitializeRISCVAsmParser() {
   RegisterMCAsmParser<RISCVAsmParser> X(getTheRISCV32Target());
   RegisterMCAsmParser<RISCVAsmParser> Y(getTheRISCV64Target());
+  RegisterMCAsmParser<RISCVAsmParser> Z(getTheRISCV32ETarget());
 }

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

 }
 
 extern "C" void LLVMInitializeRISCVDisassembler() {
   // Register the disassembler for each target.
   TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
                                          createRISCVDisassembler);
   TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
                                          createRISCVDisassembler);
+  TargetRegistry::RegisterMCDisassembler(getTheRISCV32ETarget(),
+                                         createRISCVDisassembler);
 }
 
 static const unsigned GPRDecoderTable[] = {
   RISCV::X0,  RISCV::X1,  RISCV::X2,  RISCV::X3,
   RISCV::X4,  RISCV::X5,  RISCV::X6,  RISCV::X7,
   RISCV::X8,  RISCV::X9,  RISCV::X10, RISCV::X11,
   RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
   RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19,

lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h

 class StringRef;
 class Target;
 class Triple;
 class raw_ostream;
 class raw_pwrite_stream;
 
 Target &getTheRISCV32Target();
 Target &getTheRISCV64Target();
+Target &getTheRISCV32ETarget();
 
 MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
                                         MCContext &Ctx);
 
 MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
                                     const MCRegisterInfo &MRI,
                                     const MCTargetOptions &Options);

lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
                                        const Triple &TT) {
   return new RISCVMCAsmInfo(TT);
 }
 
 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
                                                    StringRef CPU, StringRef FS) {
   std::string CPUName = CPU;
-  if (CPUName.empty())
+  if (CPUName.empty()) {
+    if (TT.getArch() == llvm::Triple::riscv32e) {
+      CPUName = "generic-rv32e";
+    } else {
       CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
+    }
+  }
   return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
 }
 
 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,
                                                const MCRegisterInfo &MRI) {

 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
                                                       formatted_raw_ostream &OS,
                                                       MCInstPrinter *InstPrint,
                                                       bool isVerboseAsm) {
   return new RISCVTargetAsmStreamer(S, OS);
 }
 
 extern "C" void LLVMInitializeRISCVTargetMC() {
-  for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
+  for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target(),
+                    &getTheRISCV32ETarget()}) {
     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
     TargetRegistry::RegisterObjectTargetStreamer(
         *T, createRISCVObjectTargetStreamer);
 
     // Register the asm target streamer.
     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
   }
 }

lib/Target/RISCV/RISCV.td

def FeatureStdExtC
     : SubtargetFeature<"c", "HasStdExtC", "true",
                        "'C' (Compressed Instructions)">;
 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
                            AssemblerPredicate<"FeatureStdExtC">;
 
 
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
+def FeatureEmbed
+    : SubtargetFeature<"Embed", "HasEmbed", "true", "Implements RV32E">;
+
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<"Feature64Bit">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<"!Feature64Bit">;
+def IsRVEmbed : Predicate<"Subtarget->isEmbed()">,
+                       AssemblerPredicate<"FeatureEmbed">;
 
 def RV64           : HwMode<"+64bit">;
 def RV32           : HwMode<"-64bit">;
+def RV32E          : HwMode<"+Embed">;
 
 def FeatureRelax
     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
                        "Enable Linker relaxation.">;
 
 //===----------------------------------------------------------------------===//
 // Registers, calling conventions, instruction descriptions.
 //===----------------------------------------------------------------------===//

 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.
 //===----------------------------------------------------------------------===//
 
 def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
 
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 
+def : ProcessorModel<"generic-rv32e", NoSchedModel, [FeatureEmbed]>;
+
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.
 //===----------------------------------------------------------------------===//
 
 def RISCVInstrInfo : InstrInfo {
   let guessInstructionProperties = 0;
 }
 

lib/Target/RISCV/RISCVAsmPrinter.cpp

bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
 
   return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, AsmVariant, ExtraCode, OS);
 }
 
 // Force static initialization.
 extern "C" void LLVMInitializeRISCVAsmPrinter() {
   RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
   RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
+  RegisterAsmPrinter<RISCVAsmPrinter> Z(getTheRISCV32ETarget());
 }

lib/Target/RISCV/RISCVCallingConv.td

 // This describes the calling conventions for the RISCV architecture.
 //
 //===----------------------------------------------------------------------===//
 
 // The RISC-V calling convention is handled with custom code in
 // RISCVISelLowering.cpp (CC_RISCV).
 
 def CSR : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
+def CSR_E : CalleeSavedRegs<(add X1, X3, X4, X8, X9)>;
 
 // Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
 
 // Interrupt handler needs to save/restore all registers that are used,
 // both Caller and Callee saved registers.
 def CSR_Interrupt : CalleeSavedRegs<(add X1,
     (sequence "X%u", 3, 9),
     (sequence "X%u", 10, 11),
     (sequence "X%u", 12, 17),
     (sequence "X%u", 18, 27),
     (sequence "X%u", 28, 31))>;
+def CSR_E_Interrupt : CalleeSavedRegs<(add X1,
+    (sequence "X%u", 3, 9),
+    (sequence "X%u", 10, 11),
+    (sequence "X%u", 12, 15))>;
+
 
 // Same as CSR_Interrupt, but including all 32-bit FP registers.
 def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add X1,
     (sequence "X%u", 3, 9),
     (sequence "X%u", 10, 11),
     (sequence "X%u", 12, 17),
     (sequence "X%u", 18, 27),
     (sequence "X%u", 28, 31),

lib/Target/RISCV/RISCVFrameLowering.h

 
 #include "llvm/CodeGen/TargetFrameLowering.h"
 
 namespace llvm {
 class RISCVSubtarget;
 
 class RISCVFrameLowering : public TargetFrameLowering {
 public:
-  explicit RISCVFrameLowering(const RISCVSubtarget &STI)
-      : TargetFrameLowering(StackGrowsDown,
-                            /*StackAlignment=*/16,
-                            /*LocalAreaOffset=*/0),
-        STI(STI) {}
+  explicit RISCVFrameLowering(const RISCVSubtarget &STIT);
 
   void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   int getFrameIndexReference(const MachineFunction &MF, int FI,
                              unsigned &FrameReg) const override;
 
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,

lib/Target/RISCV/RISCVFrameLowering.cpp

 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 
 using namespace llvm;
 
+RISCVFrameLowering::RISCVFrameLowering(const RISCVSubtarget &STI)
+    : TargetFrameLowering(StackGrowsDown,
+                          STI.isEmbed() ? 4 : /*StackAlignment=*/16,
+                          /*LocalAreaOffset=*/0),
+      STI(STI) {}
+
 bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const {
   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
 
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
          RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
          MFI.isFrameAddressTaken();
 }

lib/Target/RISCV/RISCVISelLowering.cpp

 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-lower"
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 
+static bool isRVE = false;
+
 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                                          const RISCVSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
 
+  if (STI.isEmbed())
+    isRVE = true;
+  else
+    isRVE = false;
+
   MVT XLenVT = Subtarget.getXLenVT();
 
   // Set up the register classes.
   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
 
   if (Subtarget.hasStdExtF())
     addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
   if (Subtarget.hasStdExtD())

 // register-size fields in the same situations they would be for fixed
 // arguments.
 
 static const MCPhysReg ArgGPRs[] = {
   RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
   RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
 };
 
+static const MCPhysReg EArgGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
+                                     RISCV::X13, RISCV::X14, RISCV::X15};
+
 // Pass a 2*XLEN argument that has been split into two XLEN values through
 // registers or the stack as necessary.
 static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
                                 ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2,
                                 MVT ValVT2, MVT LocVT2,
                                 ISD::ArgFlagsTy ArgFlags2) {
+  if (isRVE) {
+    unsigned XLenInBytes = XLen / 8;
+    if (unsigned Reg = State.AllocateReg(EArgGPRs)) {
+      // At least one half can be passed via register.
+      State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
+                                       VA1.getLocVT(), CCValAssign::Full));
+    } else {
+      // Both halves must be passed on the stack, with proper alignment.
+      unsigned StackAlign = std::max(XLenInBytes, ArgFlags1.getOrigAlign());
+      State.addLoc(
+          CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(),
+                              State.AllocateStack(XLenInBytes, StackAlign),
+                              VA1.getLocVT(), CCValAssign::Full));
+      State.addLoc(CCValAssign::getMem(
+          ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
+          CCValAssign::Full));
+      return false;
+    }
+
+    if (unsigned Reg = State.AllocateReg(EArgGPRs)) {
+      // The second half can also be passed via register.
+      State.addLoc(
+          CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));
+    } else {
+      // The second half is passed via the stack, without additional alignment.
+      State.addLoc(CCValAssign::getMem(
+          ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
+          CCValAssign::Full));
+    }
+
+    return false;
+  } else {
     unsigned XLenInBytes = XLen / 8;
     if (unsigned Reg = State.AllocateReg(ArgGPRs)) {
       // At least one half can be passed via register.
       State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg,
                                        VA1.getLocVT(), CCValAssign::Full));
     } else {
       // Both halves must be passed on the stack, with proper alignment.
       unsigned StackAlign = std::max(XLenInBytes, ArgFlags1.getOrigAlign());
       State.addLoc(
           CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(),
                               State.AllocateStack(XLenInBytes, StackAlign),
                               VA1.getLocVT(), CCValAssign::Full));
       State.addLoc(CCValAssign::getMem(
           ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
           CCValAssign::Full));
       return false;
     }
 
     if (unsigned Reg = State.AllocateReg(ArgGPRs)) {
       // The second half can also be passed via register.
       State.addLoc(
           CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));
     } else {
       // The second half is passed via the stack, without additional alignment.
       State.addLoc(CCValAssign::getMem(
           ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2,
           CCValAssign::Full));
     }
 
     return false;
   }
+}
 
 // Implements the RISC-V calling convention. Returns true upon failure.
 static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT,
                      CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                      CCState &State, bool IsFixed, bool IsRet, Type *OrigTy) {
+  if (isRVE) {
+    unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
+    assert(XLen == 32 || XLen == 64);
+    MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
+    if (ValVT == MVT::f32) {
+      LocVT = MVT::i32;
+      LocInfo = CCValAssign::BCvt;
+    }
+
+    // Any return value split in to more than two values can't be returned
+    // directly.
+    if (IsRet && ValNo > 1)
+      return true;
+
+    // If this is a variadic argument, the RISC-V calling convention requires
+    // that it is assigned an 'even' or 'aligned' register if it has 8-byte
+    // alignment (RV32) or 16-byte alignment (RV64). An aligned register should
+    // be used regardless of whether the original argument was split during
+    // legalisation or not. The argument will not be passed by registers if the
+    // original type is larger than 2*XLEN, so the register alignment rule does
+    // not apply.
+    unsigned TwoXLenInBytes = (2 * XLen) / 8;
+    if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes &&
+        DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
+      unsigned RegIdx = State.getFirstUnallocated(EArgGPRs);
+      // Skip 'odd' register if necessary.
+      if (RegIdx != array_lengthof(EArgGPRs) && RegIdx % 2 == 1)
+        State.AllocateReg(EArgGPRs);
+    }
+
+    SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
+    SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
+        State.getPendingArgFlags();
+
+    assert(PendingLocs.size() == PendingArgFlags.size() &&
+           "PendingLocs and PendingArgFlags out of sync");
+
+    // Handle passing f64 on RV32D with a soft float ABI.
+    if (XLen == 32 && ValVT == MVT::f64) {
+      assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
+             "Can't lower f64 if it is split");
+      // Depending on available argument GPRS, f64 may be passed in a pair of
+      // GPRs, split between a GPR and the stack, or passed completely on the
+      // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
+      // cases.
+      unsigned Reg = State.AllocateReg(EArgGPRs);
+      LocVT = MVT::i32;
+      if (!Reg) {
+        unsigned StackOffset = State.AllocateStack(8, 8);
+        State.addLoc(
+            CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
+        return false;
+      }
+      if (!State.AllocateReg(EArgGPRs))
+        State.AllocateStack(4, 4);
+      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+      return false;
+    }
+
+    // Split arguments might be passed indirectly, so keep track of the pending
+    // values.
+    if (ArgFlags.isSplit() || !PendingLocs.empty()) {
+      LocVT = XLenVT;
+      LocInfo = CCValAssign::Indirect;
+      PendingLocs.push_back(
+          CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
+      PendingArgFlags.push_back(ArgFlags);
+      if (!ArgFlags.isSplitEnd()) {
+        return false;
+      }
+    }
+
+    // If the split argument only had two elements, it should be passed directly
+    // in registers or on the stack.
+    if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) {
+      assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()");
+      // Apply the normal calling convention rules to the first half of the
+      // split argument.
+      CCValAssign VA = PendingLocs[0];
+      ISD::ArgFlagsTy AF = PendingArgFlags[0];
+      PendingLocs.clear();
+      PendingArgFlags.clear();
+      return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT,
+                                 ArgFlags);
+    }
+
+    // Allocate to a register if possible, or else a stack slot.
+    unsigned Reg = State.AllocateReg(EArgGPRs);
+    unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, XLen / 8);
+
+    // If we reach this point and PendingLocs is non-empty, we must be at the
+    // end of a split argument that must be passed indirectly.
+    if (!PendingLocs.empty()) {
+      assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()");
+      assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()");
+
+      for (auto &It : PendingLocs) {
+        if (Reg)
+          It.convertToReg(Reg);
+        else
+          It.convertToMem(StackOffset);
+        State.addLoc(It);
+      }
+      PendingLocs.clear();
+      PendingArgFlags.clear();
+      return false;
+    }
+
+    assert(LocVT == XLenVT && "Expected an XLenVT at this stage");
+
+    if (Reg) {
+      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+      return false;
+    }
+
+    if (ValVT == MVT::f32) {
+      LocVT = MVT::f32;
+      LocInfo = CCValAssign::Full;
+    }
+    State.addLoc(
+        CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
+    return false;
+
+  } else {
     unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
     assert(XLen == 32 || XLen == 64);
     MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
     if (ValVT == MVT::f32) {
       LocVT = MVT::i32;
       LocInfo = CCValAssign::BCvt;
     }
 
     // Any return value split in to more than two values can't be returned
     // directly.
     if (IsRet && ValNo > 1)
       return true;
 
     // If this is a variadic argument, the RISC-V calling convention requires
     // that it is assigned an 'even' or 'aligned' register if it has 8-byte
     // alignment (RV32) or 16-byte alignment (RV64). An aligned register should
     // be used regardless of whether the original argument was split during
     // legalisation or not. The argument will not be passed by registers if the
     // original type is larger than 2*XLEN, so the register alignment rule does
     // not apply.
     unsigned TwoXLenInBytes = (2 * XLen) / 8;
     if (!IsFixed && ArgFlags.getOrigAlign() == TwoXLenInBytes &&
         DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
       unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
       // Skip 'odd' register if necessary.
       if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
         State.AllocateReg(ArgGPRs);
     }
 
     SmallVectorImpl<CCValAssign> &PendingLocs = State.getPendingLocs();
     SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
         State.getPendingArgFlags();
 
     assert(PendingLocs.size() == PendingArgFlags.size() &&
            "PendingLocs and PendingArgFlags out of sync");
 
     // Handle passing f64 on RV32D with a soft float ABI.
     if (XLen == 32 && ValVT == MVT::f64) {
       assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
              "Can't lower f64 if it is split");
       // Depending on available argument GPRS, f64 may be passed in a pair of
       // GPRs, split between a GPR and the stack, or passed completely on the
       // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
       // cases.
       unsigned Reg = State.AllocateReg(ArgGPRs);
       LocVT = MVT::i32;
       if (!Reg) {
         unsigned StackOffset = State.AllocateStack(8, 8);
         State.addLoc(
             CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
         return false;
       }
       if (!State.AllocateReg(ArgGPRs))
         State.AllocateStack(4, 4);
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
     }
 
     // Split arguments might be passed indirectly, so keep track of the pending
     // values.
     if (ArgFlags.isSplit() || !PendingLocs.empty()) {
       LocVT = XLenVT;
       LocInfo = CCValAssign::Indirect;
       PendingLocs.push_back(
           CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
       PendingArgFlags.push_back(ArgFlags);
       if (!ArgFlags.isSplitEnd()) {
         return false;
       }
     }
 
     // If the split argument only had two elements, it should be passed directly
     // in registers or on the stack.
     if (ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) {
       assert(PendingLocs.size() == 2 && "Unexpected PendingLocs.size()");
       // Apply the normal calling convention rules to the first half of the
       // split argument.
       CCValAssign VA = PendingLocs[0];
       ISD::ArgFlagsTy AF = PendingArgFlags[0];
       PendingLocs.clear();
       PendingArgFlags.clear();
       return CC_RISCVAssign2XLen(XLen, State, VA, AF, ValNo, ValVT, LocVT,
                                  ArgFlags);
     }
 
     // Allocate to a register if possible, or else a stack slot.
     unsigned Reg = State.AllocateReg(ArgGPRs);
     unsigned StackOffset = Reg ? 0 : State.AllocateStack(XLen / 8, XLen / 8);
 
     // If we reach this point and PendingLocs is non-empty, we must be at the
     // end of a split argument that must be passed indirectly.
     if (!PendingLocs.empty()) {
       assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()");
       assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()");
 
       for (auto &It : PendingLocs) {
         if (Reg)
           It.convertToReg(Reg);
         else
           It.convertToMem(StackOffset);
         State.addLoc(It);
       }
       PendingLocs.clear();
       PendingArgFlags.clear();
       return false;
     }
 
     assert(LocVT == XLenVT && "Expected an XLenVT at this stage");
 
     if (Reg) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
     }
 
     if (ValVT == MVT::f32) {
       LocVT = MVT::f32;
       LocInfo = CCValAssign::Full;
     }
-  State.addLoc(CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
+    State.addLoc(
+        CCValAssign::getMem(ValNo, ValVT, StackOffset, LocVT, LocInfo));
     return false;
   }
+}
 
 void RISCVTargetLowering::analyzeInputArgs(
     MachineFunction &MF, CCState &CCInfo,
     const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet) const {
   unsigned NumArgs = Ins.size();
   FunctionType *FType = MF.getFunction().getFunctionType();
 
   for (unsigned i = 0; i != NumArgs; ++i) {

lib/Target/RISCV/RISCVRegisterInfo.cpp

 
 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
                            /*PC*/0, HwMode) {}
 
 const MCPhysReg *
 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   if (MF->getFunction().hasFnAttribute("interrupt")) {
+    if (MF->getSubtarget<RISCVSubtarget>().isEmbed())
+      return CSR_E_Interrupt_SaveList;
     if (MF->getSubtarget<RISCVSubtarget>().hasStdExtD())
       return CSR_XLEN_F64_Interrupt_SaveList;
     if (MF->getSubtarget<RISCVSubtarget>().hasStdExtF())
       return CSR_XLEN_F32_Interrupt_SaveList;
     return CSR_Interrupt_SaveList;
   }
+  if (MF->getSubtarget<RISCVSubtarget>().isEmbed())
+    return CSR_E_SaveList;
   return CSR_SaveList;
 }
 
 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
 
   // Use markSuperRegs to ensure any register aliases are also reserved
   markSuperRegs(Reserved, RISCV::X0); // zero
   markSuperRegs(Reserved, RISCV::X1); // ra
   markSuperRegs(Reserved, RISCV::X2); // sp
   markSuperRegs(Reserved, RISCV::X3); // gp
   markSuperRegs(Reserved, RISCV::X4); // tp
   markSuperRegs(Reserved, RISCV::X8); // fp
+
+  // if rve , need to reserve x16-x31 reg
+  if (MF.getSubtarget<RISCVSubtarget>().isEmbed()) {
+    markSuperRegs(Reserved, RISCV::X16);
+    markSuperRegs(Reserved, RISCV::X17);
+    markSuperRegs(Reserved, RISCV::X18);
+    markSuperRegs(Reserved, RISCV::X19);
+    markSuperRegs(Reserved, RISCV::X20);
+    markSuperRegs(Reserved, RISCV::X21);
+    markSuperRegs(Reserved, RISCV::X22);
+    markSuperRegs(Reserved, RISCV::X23);
+    markSuperRegs(Reserved, RISCV::X24);
+    markSuperRegs(Reserved, RISCV::X25);
+    markSuperRegs(Reserved, RISCV::X26);
+    markSuperRegs(Reserved, RISCV::X27);
+    markSuperRegs(Reserved, RISCV::X28);
+    markSuperRegs(Reserved, RISCV::X29);
+    markSuperRegs(Reserved, RISCV::X30);
+    markSuperRegs(Reserved, RISCV::X31);
+  }
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 
 bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
   return PhysReg == RISCV::X0;
 }
 
unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = getFrameLowering(MF);
   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
 }
 
 const uint32_t *
 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
                                         CallingConv::ID /*CC*/) const {
   if (MF.getFunction().hasFnAttribute("interrupt")) {
+    if (MF.getSubtarget<RISCVSubtarget>().isEmbed())
+      return CSR_E_Interrupt_RegMask;
     if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD())
       return CSR_XLEN_F64_Interrupt_RegMask;
     if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF())
       return CSR_XLEN_F32_Interrupt_RegMask;
     return CSR_Interrupt_RegMask;
   }
+  if (MF.getSubtarget<RISCVSubtarget>().isEmbed())
+    return CSR_Interrupt_RegMask;
   return CSR_RegMask;
 }

lib/Target/RISCV/RISCVRegisterInfo.td

let RegAltNameIndices = [ABIRegAltName] in {
   def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>;
   def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>;
   def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>;
   def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>;
   def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>;
   }
 }
 
-def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
-                               [i32,  i64,  i32]>;
+def XLenVT : ValueTypeByHwMode<[RV32, RV64, RV32E, DefaultMode],
+                               [i32,  i64,  i32,   i32]>;
+
 
 // The order of registers represents the preferred allocation sequence.
 // Registers are listed in the order caller-save, callee-save, specials.
 def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
     (sequence "X%u", 10, 17),
     (sequence "X%u", 5, 7),
     (sequence "X%u", 28, 31),
     (sequence "X%u", 8, 9),
def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add
     (sequence "X%u", 10, 17),
     (sequence "X%u", 5, 7),
     (sequence "X%u", 28, 31),
     (sequence "X%u", 8, 9),
     (sequence "X%u", 18, 27),
     (sequence "X%u", 1, 4)
   )> {
   let RegInfos = RegInfoByHwMode<
-      [RV32,              RV64,              DefaultMode],
-      [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
+      [RV32,              RV64,              RV32E,             DefaultMode],
+      [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>, RegInfo<32,32,32>]>;
 }
 
 def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add
     (sequence "X%u", 10, 17),
     (sequence "X%u", 5, 7),
     (sequence "X%u", 28, 31),
     (sequence "X%u", 8, 9),
     (sequence "X%u", 18, 27),

lib/Target/RISCV/RISCVSubtarget.h

 class RISCVSubtarget : public RISCVGenSubtargetInfo {
   virtual void anchor();
   bool HasStdExtM = false;
   bool HasStdExtA = false;
   bool HasStdExtF = false;
   bool HasStdExtD = false;
   bool HasStdExtC = false;
   bool HasRV64 = false;
+  bool HasEmbed = false;
   bool EnableLinkerRelax = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
-                                                  bool Is64Bit);
+                                                  bool Is64Bit, bool IsEmbed);
 
 public:
   // Initializes the data members to match that of the specified triple.
   RISCVSubtarget(const Triple &TT, const std::string &CPU,
                  const std::string &FS, const TargetMachine &TM);
 
   // Parses features string setting specified subtarget options. The
   // definition of this function is auto-generated by tblgen.
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
   bool hasStdExtM() const { return HasStdExtM; }
   bool hasStdExtA() const { return HasStdExtA; }
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
   bool is64Bit() const { return HasRV64; }
+  bool isEmbed() const { return HasEmbed; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
 };
 } // End llvm namespace
 
 #endif

lib/Target/RISCV/RISCVSubtarget.cpp

 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "RISCVGenSubtargetInfo.inc"
 
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                                 StringRef FS,
-                                                                bool Is64Bit) {
+                                                                bool Is64Bit,
+                                                                bool IsEmbed) {
   // Determine default and user-specified characteristics
   std::string CPUName = CPU;
-  if (CPUName.empty())
+  if (CPUName.empty()) {
+    if (IsEmbed) {
+      CPUName = "generic-rv32e";
+    } else {
       CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
+    }
+  }
   ParseSubtargetFeatures(CPUName, FS);
   if (Is64Bit) {
     XLenVT = MVT::i64;
     XLen = 64;
   }
   return *this;
 }
 
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, const TargetMachine &TM)
     : RISCVGenSubtargetInfo(TT, CPU, FS),
-      FrameLowering(initializeSubtargetDependencies(CPU, FS, TT.isArch64Bit())),
+      FrameLowering(initializeSubtargetDependencies(
+          CPU, FS, TT.isArch64Bit(), TT.getArch() == llvm::Triple::riscv32e)),
       InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}

lib/Target/RISCV/RISCVTargetMachine.cpp

 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
 extern "C" void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
+  RegisterTargetMachine<RISCVTargetMachine> Z(getTheRISCV32ETarget());
   auto PR = PassRegistry::getPassRegistry();
   initializeRISCVExpandPseudoPass(*PR);
 }
 
 static std::string computeDataLayout(const Triple &TT) {
   if (TT.isArch64Bit()) {
     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
   } else {

lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp

Target &getTheRISCV32Target() {
   static Target TheRISCV32Target;
   return TheRISCV32Target;
 }
 
 Target &getTheRISCV64Target() {
   static Target TheRISCV64Target;
   return TheRISCV64Target;
 }
+
+Target &getTheRISCV32ETarget() {
+  static Target TheRISCV32ETarget;
+  return TheRISCV32ETarget;
+}
 }
 
 extern "C" void LLVMInitializeRISCVTargetInfo() {
   RegisterTarget<Triple::riscv32> X(getTheRISCV32Target(), "riscv32",
                                     "32-bit RISC-V", "RISCV");
   RegisterTarget<Triple::riscv64> Y(getTheRISCV64Target(), "riscv64",
                                     "64-bit RISC-V", "RISCV");
+  RegisterTarget<Triple::riscv32e> Z(getTheRISCV32ETarget(), "riscv32e",
+                                     "32-bit RISC-V embed", "RISCV");
 }