[LLVM][IR][LIT] support of 'no-overflow' flag for sdiv\udiv instructions

[magabari]

Summary

Following to the discussion made in RFC: https://groups.google.com/forum/#!msg/llvm-dev/eFtnCwpMMhs/eAHQj8rJCAAJ;context-place=searchin/llvm-dev/magabari%7Csort:date

This is an implementation of 'nof' flag for sdiv\udiv llvm instructions.
Please start reading the proposed RFC & changes in the LangRef.rst.

Adding this flag to integer div flag will allow us (later) to speculate div operation without a need to worry of divide by zero or overflow.

This patch contains llvm frontend changes only.

[MatzeB]

• Without any change in the backend (not even an abort) this will simply miscompile the no nof version on most targets.
• With the way you are modeling the new flag, means that existing bitcode/.ll files will change semantics when read with newer compilers. I'm not sure that is a good idea for this, in any way at the very least you have to provide AutoUpgrade logic for that.

[sanjoy]

This looks like something that will be better served by an intrinsic (llvm.safe_(s|u)div or something like that), at least to begin with. Experimental intrinsics are a low-cost preferred way of trying out ideas like this without changing fundamental IR semantics.

[magabari]

In D41944#973480, @MatzeB wrote:

• Without any change in the backend (not even an abort) this will simply miscompile the no nof version on most targets.
• With the way you are modeling the new flag, means that existing bitcode/.ll files will change semantics when read with newer compilers. I'm not sure that is a good idea for this, in any way at the very least you have to provide AutoUpgrade logic for that.

• I agree with the first point, but currently there is no such optimization that will generate the no nof version, so I assume that won't happen in the short term, Currently i am working on the backend side but at any case we can put some sanity check in the backend that sdiv\udiv come with the nof attribute now.

• As I know LLVM doesn't promise backward comparability so we tried following the correct solution (notice that another way is to suggest 'mayoverflow' attribute but it won't match other attributes in LLVM). Regarding the AutoUpgrade logic I will be glad if you can clarify more on what has to be done?

[magabari]

In D41944#974178, @sanjoy wrote:

This looks like something that will be better served by an intrinsic (llvm.safe_(s|u)div or something like that), at least to begin with. Experimental intrinsics are a low-cost preferred way of trying out ideas like this without changing fundamental IR semantics.

@sanjoy we tried that in our first RFC (https://groups.google.com/forum/#!msg/llvm-dev/ooMhG28jZG0/UP5GadYvCQAJ;context-place=msg/llvm-dev/eFtnCwpMMhs/eAHQj8rJCAAJ )
and it has been rejected with this recommendation.

[efriedma]

In D41944#974178, @sanjoy wrote:

This looks like something that will be better served by an intrinsic (llvm.safe_(s|u)div or something like that), at least to begin with. Experimental intrinsics are a low-cost preferred way of trying out ideas like this without changing fundamental IR semantics.

I was the one who originally suggested the nof flag. Using the same IR representation for the same computation is nice for many reasons, which is why we have, for example, nsw, or the boolean flag to llvm.ctlz. And I think it's pretty clearly the design we would have used if the IR weren't originally designed around the limitations of x86.

If we're not confident the non-nof div is actually useful, we could call it "llvm.experimental.safe_(s|u)div" instead for now, I guess. The lowering/SelectionDAG work required for that is almost identical, so it wouldn't be hard to switch later.

---

The initial patch should probably be "complete", in the sense of being able to lower the safe divide. All you need for that is an IR lowering pass to convert a potentially-overflowing divide into a control flow around a conventional udiv/sdiv. (We probably want that anyway, for approximately the same reasons we have the ScalarizeMaskedMemIntrin pass.)

[magabari]

added scalarization logic on codegen prepare (fixMayOverflowIntegerDiv) in case there is no support of may overflow div in the target.

[zvi]

In D41944#973480, @MatzeB wrote:

• With the way you are modeling the new flag, means that existing bitcode/.ll files will change semantics when read with newer compilers. I'm not sure that is a good idea for this, in any way at the very least you have to provide AutoUpgrade logic for that.

This seems like a real issue. With no version info in the module, how can AutoUpgrade tell if a divide with no 'nof' attribute is of the old form or new form? This is really a performance issue, because AutoUpgrade can always pessimistically not add 'nof' if the version of the incoming module is unknown. Possible solutions:

1. Introduce versioning to LLVM IR modules - will still require to add the version info to the legacy modules, which may be unacceptable to some users.
2. Similar to above, but instead of version add a keyword or metadata key that will flag divides as upgradable to 'nof'. Same con as #1, but we can deprecate this feature sometime in the future.
3. Pass a flag that is not embedded in the module to AutoUpgrade (e.g. opt/llc will add flags that will be propagated to AutoUpgrade)

[MatzeB]

• As I know LLVM doesn't promise backward comparability so we tried following the correct solution (notice that another way is to suggest 'mayoverflow' attribute but it won't match other attributes in LLVM). Regarding the AutoUpgrade logic I will be glad if you can clarify more on what has to be done?

That is not true, we do provide backward compatibility: https://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility

[MatzeB]

In D41944#976834, @zvi wrote:

In D41944#973480, @MatzeB wrote:

• With the way you are modeling the new flag, means that existing bitcode/.ll files will change semantics when read with newer compilers. I'm not sure that is a good idea for this, in any way at the very least you have to provide AutoUpgrade logic for that.

This seems like a real issue. With no version info in the module, how can AutoUpgrade tell if a divide with no 'nof' attribute is of the old form or new form? This is really a performance issue, because AutoUpgrade can always pessimistically not add 'nof' if the version of the incoming module is unknown. Possible solutions:

1. Introduce versioning to LLVM IR modules - will still require to add the version info to the legacy modules, which may be unacceptable to some users.
2. Similar to above, but instead of version add a keyword or metadata key that will flag divides as upgradable to 'nof'. Same con as #1, but we can deprecate this feature sometime in the future.
3. Pass a flag that is not embedded in the module to AutoUpgrade (e.g. opt/llc will add flags that will be propagated to AutoUpgrade)

Or change the logic so the new poison generating form requires a flag instead of the other way round.

[efriedma]

Or change the logic so the new poison generating form requires a flag instead of the other way round.

From the perspective of transformation passes, we want the flag be consistent with other flags like nsw. So we want the representation in memory and textual IR to work like it does in this patch.

That said, we don't have to use the same representation in bitcode; the bitcode reader/writer can invert the bit so divides in old bitcode files get deserialized to "sdiv nof".

lib/CodeGen/CodeGenPrepare.cpp

574 ↗

(On Diff #129925)

CodeGenPrepare doesn't run at -O0; you'll have to put this code somewhere else.

[craig.topper]

include/llvm/Analysis/TargetTransformInfo.h

490

Remove slash from end of line. Doxygen comment don't need the new line escaped.

include/llvm/IR/IRBuilder.h

1013

Can we just call BinaryOperator::Create(Instruction::UDiv, LHS, RHS) and then just call setIsNoOverflow and setIsExact on the result when needed? This would be similar to the CreateInsertNUWNSWBinOp private helper we have for NSW/NUW. You could make a new helper to be shared by sdiv/udiv.

lib/AsmParser/LLParser.cpp

3196

This only supports one order for the two keywords. I think you need to support both orders. See the nsw/nuw handling above.

5286

Need to support keywords being in the other order here too.

lib/CodeGen/CodeGenPrepare.cpp

573 ↗

(On Diff #129925)

upsupported->unsupported

595 ↗

(On Diff #129925)

Why is this initialized to Undef? Can't you just declare this where it's assigned below?

601 ↗

(On Diff #129925)

Can you write comments for what's happening in the signed case.

612 ↗

(On Diff #129925)

Should this be ConstantInt::getSigned? If the scalar type is larger than 64-bits that -1 will be padded with zeros by default.

617 ↗

(On Diff #129925)

Can you load the APInt into a temporary variable to shorten this line? It's pretty awful to read right now.

645 ↗

(On Diff #129925)

This could use some comments showing what the resulting IR should look like.

647 ↗

(On Diff #129925)

Is the starting value of PrevPhi ever expected to be used? Does it need to be undef?

662 ↗

(On Diff #129925)

If I'm reading this right we're create smallvectors contraining the same element repeatedly? Can we just use ConstantVector::getSplat which will take care of repeating an element?

682 ↗

(On Diff #129925)

IRBuilder has a CreateExtractElement that takes a uint64_t. You don't need to call getInt32. It will call getInt64 internally.

lib/IR/AsmWriter.cpp

1141

You can use "const auto *PO = dyn_cast..." the type is spelled out in the dyn_cast so we don't need to repeat it

lib/Transforms/InstCombine/InstructionCombining.cpp

940–941

Can you rename this variable to not say "FP"? I think the FP part was always speculative. It wasn' know FP until the isa<FPMathOperator> was called. But now it looks really confusing to have a variable named FPInst and we're checking a property that could only be set on an integer division.

[magabari]

I agree with Eli last comment, In fact we can solve compatibility in both text and bitcode.
Eli already suggested a way how to solve that in bitcode by inverting the bit (set will mean "mayOverflow" and unset means "NoOverflow")

We can use another approach in text, by adding "mayoveflow" or "nooverflow" to every sdiv instruction (always).

sdiv without any attribute will be the same like "sdiv nof" (backward compatibility)
sdiv that may overflow will be represented as "sdiv mof".

Later, we can add restriction that sdiv node should come with nof or mof keyword.

[nlopes]

Before accepting this patch, we really need to see benchmark results. I'm not going to change clang to start emitting non-UB divs if the perf is going to be horrible. We need data.
Otherwise I don't see the need for this poison version of division. Could you elaborate if your plan is to expose this somehow to the application developer?

I'm sorry if this questions have been properly answered in the past. If so, could you please link them here?

[magabari]

In D41944#978691, @nlopes wrote:

Before accepting this patch, we really need to see benchmark results. I'm not going to change clang to start emitting non-UB divs if the perf is going to be horrible. We need data.
Otherwise I don't see the need for this poison version of division. Could you elaborate if your plan is to expose this somehow to the application developer?

I'm sorry if this questions have been properly answered in the past. If so, could you please link them here?

In general the proposed feature allows compiler to start speculating div without worrying too much of div-by-zero etc. so for example you can do instruction hoisting or vectorizing predicated sdiv.
We are currently focused on vectorizing predicated div instruction and our implementation shows around 20-30% improvements on several tests of coremark-pro and denbench.

[nlopes]

In D41944#978753, @magabari wrote:

In D41944#978691, @nlopes wrote:

Before accepting this patch, we really need to see benchmark results. I'm not going to change clang to start emitting non-UB divs if the perf is going to be horrible. We need data.
Otherwise I don't see the need for this poison version of division. Could you elaborate if your plan is to expose this somehow to the application developer?

I'm sorry if this questions have been properly answered in the past. If so, could you please link them here?

In general the proposed feature allows compiler to start speculating div without worrying too much of div-by-zero etc. so for example you can do instruction hoisting or vectorizing predicated sdiv.
We are currently focused on vectorizing predicated div instruction and our implementation shows around 20-30% improvements on several tests of coremark-pro and denbench.

I believe that in micro benchmarks that can be vectorized you can get nice speedups. The question is what happens end-to-end to regular applications? Do I have a slowdown? Code size increase because now all my divisions are guarded?
Also, you could also guard those vectorizations around checks to ensure sdiv doesn't trap. This increases code size.

[magabari]

In D41944#978770, @nlopes wrote:

In D41944#978753, @magabari wrote:

In D41944#978691, @nlopes wrote:

Before accepting this patch, we really need to see benchmark results. I'm not going to change clang to start emitting non-UB divs if the perf is going to be horrible. We need data.
Otherwise I don't see the need for this poison version of division. Could you elaborate if your plan is to expose this somehow to the application developer?

I'm sorry if this questions have been properly answered in the past. If so, could you please link them here?

In general the proposed feature allows compiler to start speculating div without worrying too much of div-by-zero etc. so for example you can do instruction hoisting or vectorizing predicated sdiv.
We are currently focused on vectorizing predicated div instruction and our implementation shows around 20-30% improvements on several tests of coremark-pro and denbench.

I believe that in micro benchmarks that can be vectorized you can get nice speedups. The question is what happens end-to-end to regular applications? Do I have a slowdown? Code size increase because now all my divisions are guarded?
Also, you could also guard those vectorizations around checks to ensure sdiv doesn't trap. This increases code size.

Not all divisions should be guarded, In fact all divisions which comes from C\C++ should be with "nof" which means it can be lowered *without* guards. From now on Clang will emit "nof" attribute for each div which comes from the user. And this matches the C\C++ specification on the case of divide-by-zero.
In case that we want to do some optimization that will do some speculation of div calculation we should remove this attribute (which means that overflow may be introduced by the compiler) and in this case we need to guard the the div calculation just in case that the specific target don't have support for lowering this kind of div (I assume that when you decide to do some optimization you should be sure that it's good for your target and not to end up with increase of code size and guards). In fact guarding div calculation is just the default implementation for targets that don't have a support for div that may overflow. In X86 we choose to simulate that div calculation using FP div which seems to be more efficient in some cases.

[magabari]

@MatzeB @efriedma @sanjoy

Following to the raised comments about compatibility issues.
This update follows my prev. comment on how to solve it.

Please take a look on the tests i have added: (div_attrs.ll and div_not_allowed.ll)
nof, mof are exclusive attributes.

if you don't declare the kind of the div it will be assumed as "nof" (this will give us backward compatibility)
the assembler will emit nof or mof always.

I also inverted the meaning of the bit in the bitcode so 1 means may overflow and 0 means no overflow which will keep bitcode backward compatible.

[magabari]

lowering patch of 'nof' flag (for X86) is up:
https://reviews.llvm.org/D42353

[magabari]

fixed

lib/CodeGen/CodeGenPrepare.cpp

647 ↗

(On Diff #129925)

PrevPhi will be used at the first merge "undef" i think you meant VResult which can be uninitialized.

[magabari]

fixed craig notes
I also agree with Eli friedman note i will upload fix soon

[craig.topper]

lib/CodeGen/CodeGenPrepare.cpp

647 ↗

(On Diff #129925)

Isn't VResult consumed by the CreateInsertElement on the first iteration of the loop on line 731?

625 ↗

(On Diff #131451)

Why are all the arguments to ConstantInt::get on separate lines? It looks short enough for one line.

690 ↗

(On Diff #131451)

Remove commented out code.

703 ↗

(On Diff #131451)

I should of caught this early, but if you pass a vector type to ConstantInt::get it will automatically create a splat. So you don't even need to call ConstantVector::getSplat you just need to pass I.getType() to ConstantInt::get

718 ↗

(On Diff #131451)

What test file covers this code? I tried to look for one, but there are a lot of test updates and all I found was adding 'nof' to existing tests.

[magabari]

fixed craig and eli notes

lib/CodeGen/CodeGenPrepare.cpp

574 ↗

(On Diff #129925)

added new pass "ScalarizeMayOverflowDiv"

647 ↗

(On Diff #129925)

i think both can't be uninitialized.
VResult used in CreateInsertElement
PrevPhi used in Phi->addIncoming

625 ↗

(On Diff #131451)

created a new pass "scalarizeMayOverflowDiv" and passed clang-format

690 ↗

(On Diff #131451)

Sorry my fault

718 ↗

(On Diff #131451)

added "scalarize-may-overflow-div.ll"

[magabari]

added new pass 'ScalarizeMayOverflowDiv'
updated div attributes in LangRef
and fixed notes given by craig

[craig.topper]

lib/AsmParser/LLParser.cpp

3196

What happens if 'nof' and 'mof' are both present?

lib/CodeGen/ScalarizeMayOverflowDiv.cpp

221

Drop the "false".

222

Use "getSigned" and drop the true.

225

Weird formatting here.

266

If the vector only has 1 element, PrevPhi is undef. But that's not correct is it?

test/Transforms/ScalarizeMayOverflowDiv/scalarize-may-overflow-div.ll

2

Add a test case for a vector with only 1 element. i.e. <1 x i32>. That's the case where PrevPHI would be undef after the loop right?

[MatzeB]

So do we still need all the .ll file changes with the syntax nof/mof syntax changes?

[magabari]

In D41944#991137, @MatzeB wrote:

So do we still need all the .ll file changes with the syntax nof/mof syntax changes?

Technically No, any test which doesn't have 'mof' attribute (like: sdiv i32 %a, %b) will be treated as it have 'nof' attribute (backward compatibility).
I kept the changes to the lit tests only because I think it's more "correct" to declare explicitly that this divide has no overflow rather than relying on backward compatibility feature doing that.

[magabari]

lib/AsmParser/LLParser.cpp

3196

it will fail in the parsing phase.
as you see 'mof' and 'nof' are exculsive, look at test div_not_allowed.ll.

lib/CodeGen/ScalarizeMayOverflowDiv.cpp

266

No, it may happen.
also in the if (Idx > 0) you may notice that i use the PrevPhi before assigning new one so it should be defined.

[magabari]

fixed craig notes

[magabari]

ping

[magabari]

minimized the patch by removing changes to some lit tests (it will be committed later as NFC patch)

Currently i am adding only the tests which have CHECK line for sdiv\udiv because the "new" AsmWriter always emit nof\mof attribute with sdiv\udiv instruction

Guys, what do you think about this?

[magabari]

ping ^ 2

[spatel]

@magabari - what is the status of this patch?

We have another potential motivating example for ignoring overflow (specifically of sdiv by -1) in PR38239:
https://bugs.llvm.org/show_bug.cgi?id=38239

...because sdiv has that extra UB potential from a -1 divisor that doesn't exist for udiv, we can't do the sibling optimization that we did for udiv.

docs/LangRef.rst

 
 Syntax:
 """""""
 
 ::
 
       <result> = udiv <ty> <op1>, <op2>         ; yields ty:result
       <result> = udiv exact <ty> <op1>, <op2>   ; yields ty:result
+      <result> = udiv nof <ty> <op1>, <op2>     ; yields ty:result
+      <result> = udiv mof <ty> <op1>, <op2>     ; yields ty:result
 
 Overview:
 """""""""
 
 The '``udiv``' instruction returns the quotient of its two operands.
 
 Arguments:
 """"""""""
 
 The two arguments to the '``udiv``' instruction must be
 :ref:`integer <t_integer>` or :ref:`vector <t_vector>` of integer values. Both
 arguments must have identical types.
 
 Semantics:
 """"""""""
 
 The value produced is the unsigned integer quotient of the two operands.
 
 Note that unsigned integer division and signed integer division are
 distinct operations; for signed integer division, use '``sdiv``'.
 
-Division by zero is undefined behavior. For vectors, if any element
-of the divisor is zero, the operation has undefined behavior.
+See the description of the ``nof`` and ``mof`` keywords below for division by zero.
 
 
 If the ``exact`` keyword is present, the result value of the ``udiv`` is
 a :ref:`poison value <poisonvalues>` if %op1 is not a multiple of %op2 (as
 such, "((a udiv exact b) mul b) == a").
 
+``nof`` stands for “No Overflow”. If the ``nof`` keyword is present, the result is undefined behavior for division by zero. Currently for backward compatibility if ``udiv`` come without any attribute it will be treated the same as ``nof`` attribute exist.
+If the ``mof`` keyword is present, it means that the result "May Overflow" so division by zero results in poison value.
+For vectors, if any element of the divisor is zero, the behavior is same as for scalar division by zero.
+
 Example:
 """"""""
 
 .. code-block:: text
 
       <result> = udiv i32 4, %var          ; yields i32:result = 4 / %var
 
 '``sdiv``' Instruction
 ^^^^^^^^^^^^^^^^^^^^^^
 
 Syntax:
 """""""
 
 ::
 
       <result> = sdiv <ty> <op1>, <op2>         ; yields ty:result
       <result> = sdiv exact <ty> <op1>, <op2>   ; yields ty:result
+      <result> = sdiv nof <ty> <op1>, <op2>     ; yields ty:result
+      <result> = sdiv mof <ty> <op1>, <op2>     ; yields ty:result
 
 Overview:
 """""""""
 
 The '``sdiv``' instruction returns the quotient of its two operands.
 
 Arguments:
 """"""""""
 
 The two arguments to the '``sdiv``' instruction must be
 :ref:`integer <t_integer>` or :ref:`vector <t_vector>` of integer values. Both
 arguments must have identical types.
 
 Semantics:
 """"""""""
 
 The value produced is the signed integer quotient of the two operands
 rounded towards zero.
 
 Note that signed integer division and unsigned integer division are
 distinct operations; for unsigned integer division, use '``udiv``'.
 
-Division by zero is undefined behavior. For vectors, if any element
-of the divisor is zero, the operation has undefined behavior.
-Overflow also leads to undefined behavior; this is a rare case, but can
-occur, for example, by doing a 32-bit division of -2147483648 by -1.
+See the description of the ``nof`` and ``mof`` keywords below for division by zero and overflow.
 
 If the ``exact`` keyword is present, the result value of the ``sdiv`` is
 a :ref:`poison value <poisonvalues>` if the result would be rounded.
 
+``nof`` stands for “No Overflow”. If the ``nof`` keyword is present, the result is undefined behavior if overflow occurs. This may be result of division by zero or dividing the smallest representable integer of the type by -1. Currently for backward compatibility if ``sdiv`` come without any attribute it will be treated the same as ``nof`` attribute exist.
+If the ``mof`` keyword is present, it means that the result "May Overflow" so the overflow cases described above result in poison value.
+For vectors, if any element of the division causes overflow, the behavior is same as for scalar division with overflow.
+
 Example:
 """"""""
 
 .. code-block:: text
 
       <result> = sdiv i32 4, %var          ; yields i32:result = 4 / %var
 
 .. _i_fdiv:

include/llvm/Analysis/TargetFolder.h

public:
   }
   Constant *CreateMul(Constant *LHS, Constant *RHS,
                       bool HasNUW = false, bool HasNSW = false) const {
     return Fold(ConstantExpr::getMul(LHS, RHS, HasNUW, HasNSW));
   }
   Constant *CreateFMul(Constant *LHS, Constant *RHS) const {
     return Fold(ConstantExpr::getFMul(LHS, RHS));
   }
-  Constant *CreateUDiv(Constant *LHS, Constant *RHS, bool isExact = false)const{
-    return Fold(ConstantExpr::getUDiv(LHS, RHS, isExact));
-  }
-  Constant *CreateSDiv(Constant *LHS, Constant *RHS, bool isExact = false)const{
-    return Fold(ConstantExpr::getSDiv(LHS, RHS, isExact));
+  Constant *CreateUDiv(Constant *LHS, Constant *RHS, bool isExact = false,
+                       bool isNoOverflow = true) const {
+    return Fold(ConstantExpr::getUDiv(LHS, RHS, isExact, isNoOverflow));
+  }
+  Constant *CreateSDiv(Constant *LHS, Constant *RHS, bool isExact = false,
+                       bool isNoOverflow = true) const {
+    return Fold(ConstantExpr::getSDiv(LHS, RHS, isExact, isNoOverflow));
   }
   Constant *CreateFDiv(Constant *LHS, Constant *RHS) const {
     return Fold(ConstantExpr::getFDiv(LHS, RHS));
   }
   Constant *CreateURem(Constant *LHS, Constant *RHS) const {
     return Fold(ConstantExpr::getURem(LHS, RHS));
   }
   Constant *CreateSRem(Constant *LHS, Constant *RHS) const {

include/llvm/Analysis/TargetTransformInfo.h

public:
   bool isLegalMaskedLoad(Type *DataType) const;
 
   /// \brief Return true if the target supports masked gather/scatter
   /// AVX-512 fully supports gather and scatter for vectors with 32 and 64
   /// bits scalar type.
   bool isLegalMaskedScatter(Type *DataType) const;
   bool isLegalMaskedGather(Type *DataType) const;
 
+  /// \brief Return true if the target support div that may overflow
+  /// divide by zero without causing a side effect
+  bool isLegalMayOverflowUDiv(Type *DataType) const;
+  bool isLegalMayOverflowSDiv(Type *DataType) const;
+
   /// Return true if the target has a unified operation to calculate division
   /// and remainder. If so, the additional implicit multiplication and
   /// subtraction required to calculate a remainder from division are free. This
   /// can enable more aggressive transformations for division and remainder than
   /// would typically be allowed using throughput or size cost models.
   bool hasDivRemOp(Type *DataType, bool IsSigned) const;
 
   /// Return true if the given instruction (assumed to be a memory access
virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
                                      Instruction *I) = 0;
   virtual bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
                              TargetTransformInfo::LSRCost &C2) = 0;
   virtual bool canMacroFuseCmp() = 0;
   virtual bool isLegalMaskedStore(Type *DataType) = 0;
   virtual bool isLegalMaskedLoad(Type *DataType) = 0;
   virtual bool isLegalMaskedScatter(Type *DataType) = 0;
   virtual bool isLegalMaskedGather(Type *DataType) = 0;
+  virtual bool isLegalMayOverflowUDiv(Type *DataType) = 0;
+  virtual bool isLegalMayOverflowSDiv(Type *DataType) = 0;
   virtual bool hasDivRemOp(Type *DataType, bool IsSigned) = 0;
   virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0;
   virtual bool prefersVectorizedAddressing() = 0;
   virtual int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
                                    int64_t BaseOffset, bool HasBaseReg,
                                    int64_t Scale, unsigned AddrSpace) = 0;
   virtual bool LSRWithInstrQueries() = 0;
   virtual bool isTruncateFree(Type *Ty1, Type *Ty2) = 0;
bool isLegalMaskedLoad(Type *DataType) override {
     return Impl.isLegalMaskedLoad(DataType);
   }
   bool isLegalMaskedScatter(Type *DataType) override {
     return Impl.isLegalMaskedScatter(DataType);
   }
   bool isLegalMaskedGather(Type *DataType) override {
     return Impl.isLegalMaskedGather(DataType);
   }
+  bool isLegalMayOverflowUDiv(Type *DataType) override {
+    return Impl.isLegalMayOverflowUDiv(DataType);
+  }
+  bool isLegalMayOverflowSDiv(Type *DataType) override {
+    return Impl.isLegalMayOverflowSDiv(DataType);
+  }
   bool hasDivRemOp(Type *DataType, bool IsSigned) override {
     return Impl.hasDivRemOp(DataType, IsSigned);
   }
   bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) override {
     return Impl.hasVolatileVariant(I, AddrSpace);
   }
   bool prefersVectorizedAddressing() override {
     return Impl.prefersVectorizedAddressing();

include/llvm/Analysis/TargetTransformInfoImpl.h

public:
   bool isLegalMaskedStore(Type *DataType) { return false; }
 
   bool isLegalMaskedLoad(Type *DataType) { return false; }
 
   bool isLegalMaskedScatter(Type *DataType) { return false; }
 
   bool isLegalMaskedGather(Type *DataType) { return false; }
 
+  bool isLegalMayOverflowUDiv(Type *DataType) { return false; }
+
+  bool isLegalMayOverflowSDiv(Type *DataType) { return false; }
+
   bool hasDivRemOp(Type *DataType, bool IsSigned) { return false; }
 
   bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) { return false; }
 
   bool prefersVectorizedAddressing() { return true; }
 
   int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
                            bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {

include/llvm/Bitcode/LLVMBitCodes.h

enum OverflowingBinaryOperatorOptionalFlags {
   OBO_NO_UNSIGNED_WRAP = 0,
   OBO_NO_SIGNED_WRAP = 1
 };
 
 /// PossiblyExactOperatorOptionalFlags - Flags for serializing
 /// PossiblyExactOperator's SubclassOptionalData contents.
 enum PossiblyExactOperatorOptionalFlags { PEO_EXACT = 0 };
 
+/// PossiblyOverflowOperatorOptionalFlags - Flags for serializing
+/// PossiblyOverflowOperator's SubclassOptionalData contents
+enum PossiblyOverflowOperatorOptionalFlags { POO_MAY_OVERFLOW = 1 };
+
 /// Encoded AtomicOrdering values.
 enum AtomicOrderingCodes {
   ORDERING_NOTATOMIC = 0,
   ORDERING_UNORDERED = 1,
   ORDERING_MONOTONIC = 2,
   ORDERING_ACQUIRE = 3,
   ORDERING_RELEASE = 4,
   ORDERING_ACQREL = 5,

include/llvm/CodeGen/Passes.h

namespace llvm {
   /// createCodeGenPreparePass - Transform the code to expose more pattern
   /// matching during instruction selection.
   FunctionPass *createCodeGenPreparePass();
 
   /// createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather
   /// and scatter intrinsics with scalar code when target doesn't support them.
   FunctionPass *createScalarizeMaskedMemIntrinPass();
 
+  /// createScalarizeMayOverflowDivPass - Replace may overflow divisions
+  /// with a guarded scalar sequence when target doesn't support them
+  FunctionPass *createScalarizeMayOverflowDivPass();
+
   /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
   /// load-linked/store-conditional loops.
   extern char &AtomicExpandID;
 
   /// MachineLoopInfo - This pass is a loop analysis pass.
   extern char &MachineLoopInfoID;
 
   /// MachineDominators - This pass is a machine dominators analysis pass.

include/llvm/IR/ConstantFolder.h

Constant *CreateMul(Constant *LHS, Constant *RHS,
                       bool HasNUW = false, bool HasNSW = false) const {
     return ConstantExpr::getMul(LHS, RHS, HasNUW, HasNSW);
   }
 
   Constant *CreateFMul(Constant *LHS, Constant *RHS) const {
     return ConstantExpr::getFMul(LHS, RHS);
   }
 
-  Constant *CreateUDiv(Constant *LHS, Constant *RHS,
-                       bool isExact = false) const {
-    return ConstantExpr::getUDiv(LHS, RHS, isExact);
+  Constant *CreateUDiv(Constant *LHS, Constant *RHS, bool isExact = false,
+                       bool isNoOverflow = true) const {
+    return ConstantExpr::getUDiv(LHS, RHS, isExact, isNoOverflow);
   }
 
-  Constant *CreateSDiv(Constant *LHS, Constant *RHS,
-                       bool isExact = false) const {
-    return ConstantExpr::getSDiv(LHS, RHS, isExact);
+  Constant *CreateSDiv(Constant *LHS, Constant *RHS, bool isExact = false,
+                       bool isNoOverflow = true) const {
+    return ConstantExpr::getSDiv(LHS, RHS, isExact, isNoOverflow);
   }
 
   Constant *CreateFDiv(Constant *LHS, Constant *RHS) const {
     return ConstantExpr::getFDiv(LHS, RHS);
   }
 
   Constant *CreateURem(Constant *LHS, Constant *RHS) const {
     return ConstantExpr::getURem(LHS, RHS);

include/llvm/IR/Constants.h

static Constant *getAdd(Constant *C1, Constant *C2,
                           bool HasNUW = false, bool HasNSW = false);
   static Constant *getFAdd(Constant *C1, Constant *C2);
   static Constant *getSub(Constant *C1, Constant *C2,
                           bool HasNUW = false, bool HasNSW = false);
   static Constant *getFSub(Constant *C1, Constant *C2);
   static Constant *getMul(Constant *C1, Constant *C2,
                           bool HasNUW = false, bool HasNSW = false);
   static Constant *getFMul(Constant *C1, Constant *C2);
-  static Constant *getUDiv(Constant *C1, Constant *C2, bool isExact = false);
-  static Constant *getSDiv(Constant *C1, Constant *C2, bool isExact = false);
+  static Constant *getUDiv(Constant *C1, Constant *C2, bool isExact = false,
+                           bool isNoOverflow = true);
+  static Constant *getSDiv(Constant *C1, Constant *C2, bool isExact = false,
+                           bool isNoOverflow = true);
   static Constant *getFDiv(Constant *C1, Constant *C2);
   static Constant *getURem(Constant *C1, Constant *C2);
   static Constant *getSRem(Constant *C1, Constant *C2);
   static Constant *getFRem(Constant *C1, Constant *C2);
   static Constant *getAnd(Constant *C1, Constant *C2);
   static Constant *getOr(Constant *C1, Constant *C2);
   static Constant *getXor(Constant *C1, Constant *C2);
   static Constant *getShl(Constant *C1, Constant *C2,

include/llvm/IR/IRBuilder.h

BinaryOperator *CreateInsertNUWNSWBinOp(BinaryOperator::BinaryOps Opc,
                                           const Twine &Name,
                                           bool HasNUW, bool HasNSW) {
     BinaryOperator *BO = Insert(BinaryOperator::Create(Opc, LHS, RHS), Name);
     if (HasNUW) BO->setHasNoUnsignedWrap();
     if (HasNSW) BO->setHasNoSignedWrap();
     return BO;
   }
 
+  BinaryOperator *CreateInsertExactNofDivOp(BinaryOperator::BinaryOps Opc,
+                                            Value *LHS, Value *RHS,
+                                            const Twine &Name,
+                                            bool isExact, bool isNof) {
+    BinaryOperator *BO = Insert(BinaryOperator::Create(Opc, LHS, RHS), Name);
+    if (isExact) BO->setIsExact(isExact);
+    if (isNof)   BO->setIsNoOverflow(isNof);
+    return BO;
+  }                                            
+
   Instruction *AddFPMathAttributes(Instruction *I,
                                    MDNode *FPMathTag,
                                    FastMathFlags FMF) const {
     if (!FPMathTag)
       FPMathTag = DefaultFPMathTag;
     if (FPMathTag)
       I->setMetadata(LLVMContext::MD_fpmath, FPMathTag);
     I->setFastMathFlags(FMF);
Value *CreateFMul(Value *LHS, Value *RHS, const Twine &Name = "",
                     MDNode *FPMathTag = nullptr) {
     if (Constant *LC = dyn_cast<Constant>(LHS))
       if (Constant *RC = dyn_cast<Constant>(RHS))
         return Insert(Folder.CreateFMul(LC, RC), Name);
     return Insert(AddFPMathAttributes(BinaryOperator::CreateFMul(LHS, RHS),
                                       FPMathTag, FMF), Name);
   }
   Value *CreateUDiv(Value *LHS, Value *RHS, const Twine &Name = "",
-                    bool isExact = false) {
+                    bool isExact = false, bool isNoOverflow = true) {
+                    
     if (Constant *LC = dyn_cast<Constant>(LHS))
       if (Constant *RC = dyn_cast<Constant>(RHS))
-        return Insert(Folder.CreateUDiv(LC, RC, isExact), Name);
-    if (!isExact)
-      return Insert(BinaryOperator::CreateUDiv(LHS, RHS), Name);
-    return Insert(BinaryOperator::CreateExactUDiv(LHS, RHS), Name);
+        return Insert(Folder.CreateUDiv(LC, RC, isExact, isNoOverflow), Name);
+    return CreateInsertExactNofDivOp(Instruction::UDiv, LHS, RHS, Name,
+                                     isExact, isNoOverflow);
   }
   Value *CreateExactUDiv(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateUDiv(LHS, RHS, Name, true);
   }
+  Value *CreateMayOverflowUDiv(Value *LHS, Value *RHS, const Twine &Name = "") {
+    return CreateUDiv(LHS, RHS, Name, false, false);
+  }
+  Value *CreateExactMayOverflowUDiv(Value *LHS, Value *RHS,
+                                    const Twine &Name = "") {
+    return CreateUDiv(LHS, RHS, Name, true, false);
+  }
   Value *CreateSDiv(Value *LHS, Value *RHS, const Twine &Name = "",
-                    bool isExact = false) {
+                    bool isExact = false, bool isNoOverflow = true) {
+                    
     if (Constant *LC = dyn_cast<Constant>(LHS))
       if (Constant *RC = dyn_cast<Constant>(RHS))
-        return Insert(Folder.CreateSDiv(LC, RC, isExact), Name);
-    if (!isExact)
-      return Insert(BinaryOperator::CreateSDiv(LHS, RHS), Name);
-    return Insert(BinaryOperator::CreateExactSDiv(LHS, RHS), Name);
+        return Insert(Folder.CreateSDiv(LC, RC, isExact, isNoOverflow), Name);
+    return CreateInsertExactNofDivOp(Instruction::SDiv, LHS, RHS, Name,
+                                     isExact, isNoOverflow);
   }
   Value *CreateExactSDiv(Value *LHS, Value *RHS, const Twine &Name = "") {
     return CreateSDiv(LHS, RHS, Name, true);
   }
+  Value *CreateMayOverflowSDiv(Value *LHS, Value *RHS, const Twine &Name = "") {
+    return CreateSDiv(LHS, RHS, Name, false, false);
+  }
+  Value *CreateExactMayOverflowSDiv(Value *LHS, Value *RHS,
+                                    const Twine &Name = "") {
+    return CreateSDiv(LHS, RHS, Name, true, false);
+  }
   Value *CreateFDiv(Value *LHS, Value *RHS, const Twine &Name = "",
                     MDNode *FPMathTag = nullptr) {
     if (Constant *LC = dyn_cast<Constant>(LHS))
       if (Constant *RC = dyn_cast<Constant>(RHS))
         return Insert(Folder.CreateFDiv(LC, RC), Name);
     return Insert(AddFPMathAttributes(BinaryOperator::CreateFDiv(LHS, RHS),
                                       FPMathTag, FMF), Name);
   }

include/llvm/IR/InstrTypes.h

static BinaryOperator *CreateExact(BinaryOps Opc, Value *V1, Value *V2,
     return BO;
   }
   static BinaryOperator *CreateExact(BinaryOps Opc, Value *V1, Value *V2,
                                      const Twine &Name, Instruction *I) {
     BinaryOperator *BO = Create(Opc, V1, V2, Name, I);
     BO->setIsExact(true);
     return BO;
   }
+  static BinaryOperator *CreateNoOverflow(BinaryOps Opc, Value *V1, Value *V2,
+                                          const Twine &Name = "") {
+    BinaryOperator *BO = Create(Opc, V1, V2, Name);
+    BO->setIsNoOverflow(true);
+    return BO;
+  }
+  static BinaryOperator *CreateNoOverflow(BinaryOps Opc, Value *V1, Value *V2,
+                                          const Twine &Name, BasicBlock *BB) {
+    BinaryOperator *BO = Create(Opc, V1, V2, Name, BB);
+    BO->setIsNoOverflow(true);
+    return BO;
+  }
+  static BinaryOperator *CreateNoOverflow(BinaryOps Opc, Value *V1, Value *V2,
+                                          const Twine &Name, Instruction *I) {
+    BinaryOperator *BO = Create(Opc, V1, V2, Name, I);
+    BO->setIsNoOverflow(true);
+    return BO;
+  }
+  static BinaryOperator *CreateExactNoOverflow(BinaryOps Opc, Value *V1,
+                                               Value *V2,
+                                               const Twine &Name = "") {
+    BinaryOperator *BO = Create(Opc, V1, V2, Name);
+    BO->setIsExact(true);
+    BO->setIsNoOverflow(true);
+    return BO;
+  }
+  static BinaryOperator *CreateExactNoOverflow(BinaryOps Opc, Value *V1,
+                                               Value *V2, const Twine &Name,
+                                               BasicBlock *BB) {
+    BinaryOperator *BO = Create(Opc, V1, V2, Name, BB);
+    BO->setIsExact(true);
+    BO->setIsNoOverflow(true);
+    return BO;
+  }
+  static BinaryOperator *CreateExactNoOverflow(BinaryOps Opc, Value *V1,
+                                               Value *V2, const Twine &Name,
+                                               Instruction *I) {
+    BinaryOperator *BO = Create(Opc, V1, V2, Name, I);
+    BO->setIsExact(true);
+    BO->setIsNoOverflow(true);
+    return BO;
+  }
 
 #define DEFINE_HELPERS(OPC, NUWNSWEXACT)                                       \
   static BinaryOperator *Create##NUWNSWEXACT##OPC(Value *V1, Value *V2,        \
                                                   const Twine &Name = "") {    \
     return Create##NUWNSWEXACT(Instruction::OPC, V1, V2, Name);                \
   }                                                                            \
   static BinaryOperator *Create##NUWNSWEXACT##OPC(                             \
       Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) {               \
#define DEFINE_HELPERS(OPC, NUWNSWEXACT)                                       \
   DEFINE_HELPERS(Shl, NSW) // CreateNSWShl
   DEFINE_HELPERS(Shl, NUW) // CreateNUWShl
 
   DEFINE_HELPERS(SDiv, Exact)  // CreateExactSDiv
   DEFINE_HELPERS(UDiv, Exact)  // CreateExactUDiv
   DEFINE_HELPERS(AShr, Exact)  // CreateExactAShr
   DEFINE_HELPERS(LShr, Exact)  // CreateExactLShr
 
+  DEFINE_HELPERS(SDiv, NoOverflow)  // CreateNoOverflowSDiv
+  DEFINE_HELPERS(UDiv, NoOverflow)  // CreateNoOverflowUDiv
+
+  DEFINE_HELPERS(SDiv, ExactNoOverflow)  // CreateExactNoOverflowSDiv
+  DEFINE_HELPERS(UDiv, ExactNoOverflow)  // CreateExactNoOverflowUDiv
+
 #undef DEFINE_HELPERS
 
   /// Helper functions to construct and inspect unary operations (NEG and NOT)
   /// via binary operators SUB and XOR:
   ///
   /// Create the NEG and NOT instructions out of SUB and XOR instructions.
   ///
   static BinaryOperator *CreateNeg(Value *Op, const Twine &Name = "",

include/llvm/IR/Instruction.h

public:
   /// Set or clear the nsw flag on this instruction, which must be an operator
   /// which supports this flag. See LangRef.html for the meaning of this flag.
   void setHasNoSignedWrap(bool b = true);
 
   /// Set or clear the exact flag on this instruction, which must be an operator
   /// which supports this flag. See LangRef.html for the meaning of this flag.
   void setIsExact(bool b = true);
 
+  /// Set or clear the divide-by-zero\overflow flag on this instruction, which
+  /// must be an operator which supports this flag. See LangRef.html for the 
+  /// meaning of this flag.
+  void setIsNoOverflow(bool b = true);
+
   /// Determine whether the no unsigned wrap flag is set.
   bool hasNoUnsignedWrap() const;
 
   /// Determine whether the no signed wrap flag is set.
   bool hasNoSignedWrap() const;
 
   /// Drops flags that may cause this instruction to evaluate to poison despite
   /// having non-poison inputs.
   void dropPoisonGeneratingFlags();
 
   /// Determine whether the exact flag is set.
   bool isExact() const;
 
+  /// Determine whether the no-overflow flag is set.
+  bool isNoOverflow() const;
+
   /// Set or clear all fast-math-flags on this instruction, which must be an
   /// operator which supports this flag. See LangRef.html for the meaning of
   /// this flag.
   void setFast(bool B);
 
   /// Set or clear the reassociation flag on this instruction, which must be
   /// an operator which supports this flag. See LangRef.html for the meaning of
   /// this flag.

include/llvm/IR/NoFolder.h

public:
   Instruction *CreateNUWMul(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateNUWMul(LHS, RHS);
   }
 
   Instruction *CreateFMul(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateFMul(LHS, RHS);
   }
 
-  Instruction *CreateUDiv(Constant *LHS, Constant *RHS,
-                          bool isExact = false) const {
-    if (!isExact)
+  Instruction *CreateUDiv(Constant *LHS, Constant *RHS, bool isExact = false,
+                          bool isNoOverflow = true) const {
+    if (!isExact && !isNoOverflow)
       return BinaryOperator::CreateUDiv(LHS, RHS);
+    if (!isExact)
+      return BinaryOperator::CreateNoOverflowUDiv(LHS, RHS);
+    if (!isNoOverflow)
       return BinaryOperator::CreateExactUDiv(LHS, RHS);
+    return BinaryOperator::CreateExactNoOverflowUDiv(LHS, RHS);
+  }
+
+  Instruction *CreateNoOverflowUDiv(Constant *LHS, Constant *RHS) const {
+    return BinaryOperator::CreateNoOverflowUDiv(LHS, RHS);
   }
 
   Instruction *CreateExactUDiv(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateExactUDiv(LHS, RHS);
   }
 
-  Instruction *CreateSDiv(Constant *LHS, Constant *RHS,
-                          bool isExact = false) const {
-    if (!isExact)
+  Instruction *CreateExactNoOverflowUDiv(Constant *LHS, Constant *RHS) const {
+    return BinaryOperator::CreateExactNoOverflowUDiv(LHS, RHS);
+  }
+
+  Instruction *CreateSDiv(Constant *LHS, Constant *RHS, bool isExact = false,
+                          bool isNoOverflow = true) const {
+    if (!isExact && !isNoOverflow)
       return BinaryOperator::CreateSDiv(LHS, RHS);
+    if (!isExact)
+      return BinaryOperator::CreateNoOverflowSDiv(LHS, RHS);
+    if (!isNoOverflow)
       return BinaryOperator::CreateExactSDiv(LHS, RHS);
+    return BinaryOperator::CreateExactNoOverflowSDiv(LHS, RHS);
+  }
+
+  Instruction *CreateNoOverflowSDiv(Constant *LHS, Constant *RHS) const {
+    return BinaryOperator::CreateNoOverflowSDiv(LHS, RHS);
   }
 
   Instruction *CreateExactSDiv(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateExactSDiv(LHS, RHS);
   }
 
+  Instruction *CreateExactNoOverflowSDiv(Constant *LHS, Constant *RHS) const {
+    return BinaryOperator::CreateExactNoOverflowSDiv(LHS, RHS);
+  }
+
   Instruction *CreateFDiv(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateFDiv(LHS, RHS);
   }
 
   Instruction *CreateURem(Constant *LHS, Constant *RHS) const {
     return BinaryOperator::CreateURem(LHS, RHS);
   }
 

include/llvm/IR/Operator.h

static bool classof(const Instruction *I) {
     return isPossiblyExactOpcode(I->getOpcode());
   }
   static bool classof(const Value *V) {
     return (isa<Instruction>(V) && classof(cast<Instruction>(V))) ||
            (isa<ConstantExpr>(V) && classof(cast<ConstantExpr>(V)));
   }
 };
 
+/// A udiv or sdiv instruction, which can be marked as "nof",
+/// indicating that the operand values are safe and overflow
+/// or div by zero not expected to occur
+class PossiblyOverflowOperator : public PossiblyExactOperator {
+public:
+  enum { MayOverflow = (1 << 1) };
+
+private:
+  friend class Instruction;
+  friend class ConstantExpr;
+
+  void setIsNoOverflow(bool B) {
+    unsigned bit = B ? 0 : MayOverflow;
+    SubclassOptionalData =
+        (SubclassOptionalData & ~MayOverflow) | bit;
+  }
+
+public:
+  /// Test whether this division is known to be with no-overflow or
+  /// div by zero or not
+  bool isNoOverflow() const { return !(SubclassOptionalData & MayOverflow); }
+
+  static bool isPossiblyOverflowOpcode(unsigned OpC) {
+    return OpC == Instruction::SDiv || OpC == Instruction::UDiv;
+  }
+
+  static bool classof(const ConstantExpr *CE) {
+    return isPossiblyOverflowOpcode(CE->getOpcode());
+  }
+  static bool classof(const Instruction *I) {
+    return isPossiblyOverflowOpcode(I->getOpcode());
+  }
+  static bool classof(const Value *V) {
+    return (isa<Instruction>(V) && classof(cast<Instruction>(V))) ||
+           (isa<ConstantExpr>(V) && classof(cast<ConstantExpr>(V)));
+  }
+};
+
 /// Convenience struct for specifying and reasoning about fast-math flags.
 class FastMathFlags {
 private:
   friend class FPMathOperator;
 
   unsigned Flags = 0;
 
   FastMathFlags(unsigned F) {

 class MulOperator
   : public ConcreteOperator<OverflowingBinaryOperator, Instruction::Mul> {
 };
 class ShlOperator
   : public ConcreteOperator<OverflowingBinaryOperator, Instruction::Shl> {
 };
 
 class SDivOperator
-  : public ConcreteOperator<PossiblyExactOperator, Instruction::SDiv> {
+  : public ConcreteOperator<PossiblyOverflowOperator, Instruction::SDiv> {
 };
 class UDivOperator
-  : public ConcreteOperator<PossiblyExactOperator, Instruction::UDiv> {
+  : public ConcreteOperator<PossiblyOverflowOperator, Instruction::UDiv> {
 };
 class AShrOperator
   : public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> {
 };
 class LShrOperator
   : public ConcreteOperator<PossiblyExactOperator, Instruction::LShr> {
 };
 

include/llvm/InitializePasses.h

 void initializeSCEVAAWrapperPassPass(PassRegistry&);
 void initializeSLPVectorizerPass(PassRegistry&);
 void initializeSROALegacyPassPass(PassRegistry&);
 void initializeSafeStackLegacyPassPass(PassRegistry&);
 void initializeSampleProfileLoaderLegacyPassPass(PassRegistry&);
 void initializeSanitizerCoverageModulePass(PassRegistry&);
 void initializeScalarEvolutionWrapperPassPass(PassRegistry&);
 void initializeScalarizeMaskedMemIntrinPass(PassRegistry&);
+void initializeScalarizeMayOverflowDivPass(PassRegistry&);
 void initializeScalarizerPass(PassRegistry&);
 void initializeScavengerTestPass(PassRegistry&);
 void initializeScopedNoAliasAAWrapperPassPass(PassRegistry&);
 void initializeSeparateConstOffsetFromGEPPass(PassRegistry&);
 void initializeShadowStackGCLoweringPass(PassRegistry&);
 void initializeShrinkWrapPass(PassRegistry&);
 void initializeSimpleInlinerPass(PassRegistry&);
 void initializeSimpleLoopUnswitchLegacyPassPass(PassRegistry&);

include/llvm/LinkAllPasses.h

ForcePassLinking() {
       (void) llvm::createSpeculativeExecutionPass();
       (void) llvm::createSpeculativeExecutionIfHasBranchDivergencePass();
       (void) llvm::createRewriteSymbolsPass();
       (void) llvm::createStraightLineStrengthReducePass();
       (void) llvm::createMemDerefPrinter();
       (void) llvm::createFloat2IntPass();
       (void) llvm::createEliminateAvailableExternallyPass();
       (void) llvm::createScalarizeMaskedMemIntrinPass();
+      (void) llvm::createScalarizeMayOverflowDivPass();
 
       (void)new llvm::IntervalPartition();
       (void)new llvm::ScalarEvolutionWrapperPass();
       llvm::Function::Create(nullptr, llvm::GlobalValue::ExternalLinkage)->viewCFGOnly();
       llvm::RGPassManager RGM;
       llvm::TargetLibraryInfoImpl TLII;
       llvm::TargetLibraryInfo TLI(TLII);
       llvm::AliasAnalysis AA(TLI);

lib/Analysis/TargetTransformInfo.cpp

 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType) const {
   return TTIImpl->isLegalMaskedGather(DataType);
 }
 
 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType) const {
   return TTIImpl->isLegalMaskedScatter(DataType);
 }
 
+bool TargetTransformInfo::isLegalMayOverflowUDiv(Type *DataType) const {
+  return TTIImpl->isLegalMayOverflowUDiv(DataType);
+}
+
+bool TargetTransformInfo::isLegalMayOverflowSDiv(Type *DataType) const {
+  return TTIImpl->isLegalMayOverflowSDiv(DataType);
+}
+
 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
   return TTIImpl->hasDivRemOp(DataType, IsSigned);
 }
 
 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
                                              unsigned AddrSpace) const {
   return TTIImpl->hasVolatileVariant(I, AddrSpace);
 }

lib/AsmParser/LLLexer.cpp

#define KEYWORD(STR)                                                           \
   KEYWORD(arcp);
   KEYWORD(contract);
   KEYWORD(reassoc);
   KEYWORD(afn);
   KEYWORD(fast);
   KEYWORD(nuw);
   KEYWORD(nsw);
   KEYWORD(exact);
+  KEYWORD(nof);
+  KEYWORD(mof);
   KEYWORD(inbounds);
   KEYWORD(inrange);
   KEYWORD(align);
   KEYWORD(addrspace);
   KEYWORD(section);
   KEYWORD(alias);
   KEYWORD(ifunc);
   KEYWORD(module);

lib/AsmParser/LLParser.cpp

bool LLParser::ParseValID(ValID &ID, PerFunctionState *PFS) {
   case lltok::kw_srem:
   case lltok::kw_frem:
   case lltok::kw_shl:
   case lltok::kw_lshr:
   case lltok::kw_ashr: {
     bool NUW = false;
     bool NSW = false;
     bool Exact = false;
+    bool NOF = true;
     unsigned Opc = Lex.getUIntVal();
     Constant *Val0, *Val1;
     Lex.Lex();
     LocTy ModifierLoc = Lex.getLoc();
     if (Opc == Instruction::Add || Opc == Instruction::Sub ||
         Opc == Instruction::Mul || Opc == Instruction::Shl) {
       if (EatIfPresent(lltok::kw_nuw))
         NUW = true;
       if (EatIfPresent(lltok::kw_nsw)) {
         NSW = true;
         if (EatIfPresent(lltok::kw_nuw))
           NUW = true;
       }
     } else if (Opc == Instruction::SDiv || Opc == Instruction::UDiv ||
                Opc == Instruction::LShr || Opc == Instruction::AShr) {
       if (EatIfPresent(lltok::kw_exact))
         Exact = true;
+      if (Opc == Instruction::SDiv || Opc == Instruction::UDiv) {
+        if (EatIfPresent(lltok::kw_nof)) {
+          NOF = true;
+          if (EatIfPresent(lltok::kw_exact))
+            Exact = true;
+        }
+        else if (EatIfPresent(lltok::kw_mof)) {
+          NOF = false;
+          if (EatIfPresent(lltok::kw_exact))
+            Exact = true;
+        }
+      }  
     }
     if (ParseToken(lltok::lparen, "expected '(' in binary constantexpr") ||
         ParseGlobalTypeAndValue(Val0) ||
         ParseToken(lltok::comma, "expected comma in binary constantexpr") ||
         ParseGlobalTypeAndValue(Val1) ||
         ParseToken(lltok::rparen, "expected ')' in binary constantexpr"))
       return true;
     if (Val0->getType() != Val1->getType())
case Instruction::FRem:
         return Error(ID.Loc, "constexpr requires fp operands");
       break;
     default: llvm_unreachable("Unknown binary operator!");
     }
     unsigned Flags = 0;
     if (NUW)   Flags |= OverflowingBinaryOperator::NoUnsignedWrap;
     if (NSW)   Flags |= OverflowingBinaryOperator::NoSignedWrap;
     if (Exact) Flags |= PossiblyExactOperator::IsExact;
+    if (!NOF)  Flags |= PossiblyOverflowOperator::MayOverflow;
     Constant *C = ConstantExpr::get(Opc, Val0, Val1, Flags);
     ID.ConstantVal = C;
     ID.Kind = ValID::t_Constant;
     return false;
   }
 
   // Logical Operations
   case lltok::kw_and:
case lltok::kw_frem: {
     return 0;
   }
 
   case lltok::kw_sdiv:
   case lltok::kw_udiv:
   case lltok::kw_lshr:
   case lltok::kw_ashr: {
     bool Exact = EatIfPresent(lltok::kw_exact);
+    bool NOF   = true;
+
+    if (Token == lltok::kw_sdiv || Token == lltok::kw_udiv) {
+      if (EatIfPresent(lltok::kw_nof)) {
+        if (EatIfPresent(lltok::kw_exact))
+          Exact = true;
+      } 
+      else if (EatIfPresent(lltok::kw_mof)) {
+        NOF = false;
+        if (EatIfPresent(lltok::kw_exact))
+          Exact = true;
+      }
+    }  
 
     if (ParseArithmetic(Inst, PFS, KeywordVal, 1)) return true;
     if (Exact) cast<BinaryOperator>(Inst)->setIsExact(true);
+    if (!NOF) cast<BinaryOperator>(Inst)->setIsNoOverflow(false);
     return false;
   }
 
   case lltok::kw_urem:
   case lltok::kw_srem:   return ParseArithmetic(Inst, PFS, KeywordVal, 1);
   case lltok::kw_and:
   case lltok::kw_or:
   case lltok::kw_xor:    return ParseLogical(Inst, PFS, KeywordVal);

lib/AsmParser/LLToken.h

enum Kind {
   kw_arcp,
   kw_contract,
   kw_reassoc,
   kw_afn,
   kw_fast,
   kw_nuw,
   kw_nsw,
   kw_exact,
+  kw_nof,
+  kw_mof,
   kw_inbounds,
   kw_inrange,
   kw_align,
   kw_addrspace,
   kw_section,
   kw_alias,
   kw_ifunc,
   kw_module,

lib/Bitcode/Reader/BitcodeReader.cpp

case bitc::CST_CODE_CE_BINOP: {  // CE_BINOP: [opcode, opval, opval]
             if (Record[3] & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
               Flags |= OverflowingBinaryOperator::NoUnsignedWrap;
           } else if (Opc == Instruction::SDiv ||
                      Opc == Instruction::UDiv ||
                      Opc == Instruction::LShr ||
                      Opc == Instruction::AShr) {
             if (Record[3] & (1 << bitc::PEO_EXACT))
               Flags |= SDivOperator::IsExact;
+            if (Opc == Instruction::SDiv ||
+                Opc == Instruction::UDiv) {
+              if (Record[3] & (1 << bitc::POO_MAY_OVERFLOW))
+                Flags |= SDivOperator::MayOverflow;
+            }    
           }
         }
         V = ConstantExpr::get(Opc, LHS, RHS, Flags);
       }
       break;
     }
     case bitc::CST_CODE_CE_CAST: {  // CE_CAST: [opcode, opty, opval]
       if (Record.size() < 3)
case bitc::FUNC_CODE_INST_BINOP: {    // BINOP: [opval, ty, opval, opcode]
           if (Record[OpNum] & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
             cast<BinaryOperator>(I)->setHasNoUnsignedWrap(true);
         } else if (Opc == Instruction::SDiv ||
                    Opc == Instruction::UDiv ||
                    Opc == Instruction::LShr ||
                    Opc == Instruction::AShr) {
           if (Record[OpNum] & (1 << bitc::PEO_EXACT))
             cast<BinaryOperator>(I)->setIsExact(true);
+          if (Opc == Instruction::SDiv ||
+              Opc == Instruction::UDiv) {
+            if (Record[OpNum] & (1 << bitc::POO_MAY_OVERFLOW))
+              cast<BinaryOperator>(I)->setIsNoOverflow(false);
+            else
+              cast<BinaryOperator>(I)->setIsNoOverflow(true);
+          }    
         } else if (isa<FPMathOperator>(I)) {
           FastMathFlags FMF = getDecodedFastMathFlags(Record[OpNum]);
           if (FMF.any())
             I->setFastMathFlags(FMF);
         }
 
       }
       break;

lib/Bitcode/Writer/BitcodeWriter.cpp

static uint64_t getOptimizationFlags(const Value *V) {
   if (const auto *OBO = dyn_cast<OverflowingBinaryOperator>(V)) {
     if (OBO->hasNoSignedWrap())
       Flags |= 1 << bitc::OBO_NO_SIGNED_WRAP;
     if (OBO->hasNoUnsignedWrap())
       Flags |= 1 << bitc::OBO_NO_UNSIGNED_WRAP;
   } else if (const auto *PEO = dyn_cast<PossiblyExactOperator>(V)) {
     if (PEO->isExact())
       Flags |= 1 << bitc::PEO_EXACT;
+    if (const auto *POO = dyn_cast<PossiblyOverflowOperator>(V)) {
+      // flag is set when "MayOverflow" and unset when "NoOverflow" 
+      if (!POO->isNoOverflow())
+        Flags |= 1 << bitc::POO_MAY_OVERFLOW; // TODO: rename the constant
+    }
   } else if (const auto *FPMO = dyn_cast<FPMathOperator>(V)) {
     if (FPMO->hasAllowReassoc())
       Flags |= FastMathFlags::AllowReassoc;
     if (FPMO->hasNoNaNs())
       Flags |= FastMathFlags::NoNaNs;
     if (FPMO->hasNoInfs())
       Flags |= FastMathFlags::NoInfs;
     if (FPMO->hasNoSignedZeros())

lib/CodeGen/CMakeLists.txt

add_llvm_library(LLVMCodeGen
   RegisterUsageInfo.cpp
   RegUsageInfoCollector.cpp
   RegUsageInfoPropagate.cpp
   ResetMachineFunctionPass.cpp
   SafeStack.cpp
   SafeStackColoring.cpp
   SafeStackLayout.cpp
   ScalarizeMaskedMemIntrin.cpp
+  ScalarizeMayOverflowDiv.cpp
   ScheduleDAG.cpp
   ScheduleDAGInstrs.cpp
   ScheduleDAGPrinter.cpp
   ScoreboardHazardRecognizer.cpp
   ShadowStackGCLowering.cpp
   ShrinkWrap.cpp
   SjLjEHPrepare.cpp
   SlotIndexes.cpp

lib/CodeGen/CodeGen.cpp

void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeProcessImplicitDefsPass(Registry);
   initializeRABasicPass(Registry);
   initializeRegAllocFastPass(Registry);
   initializeRAGreedyPass(Registry);
   initializeRegisterCoalescerPass(Registry);
   initializeRenameIndependentSubregsPass(Registry);
   initializeSafeStackLegacyPassPass(Registry);
   initializeScalarizeMaskedMemIntrinPass(Registry);
+  initializeScalarizeMayOverflowDivPass(Registry);
   initializeShrinkWrapPass(Registry);
   initializeSlotIndexesPass(Registry);
   initializeStackColoringPass(Registry);
   initializeStackMapLivenessPass(Registry);
   initializeStackProtectorPass(Registry);
   initializeStackSlotColoringPass(Registry);
   initializeTailDuplicatePass(Registry);
   initializeTargetPassConfigPass(Registry);

lib/CodeGen/ScalarizeMayOverflowDiv.cpp

+//===- ScalarizeMayOverflowDiv.cpp - Scalarize unsupported may overflow ---===//
+//                                   integer division
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass replaces may overflow divisions - when unsupported by the target
+// - with a sequence of gaurded no overflowing divisions
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/Twine.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/BasicBlock.h"
+#include "llvm/IR/Constant.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/InstrTypes.h"
+#include "llvm/IR/Instruction.h"
+#include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/Value.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
+#include <algorithm>
+#include <cassert>
+
+using namespace llvm;
+
+#define DEBUG_TYPE "scalarize-may-overflow-div"
+
+namespace {
+
+class ScalarizeMayOverflowDiv : public FunctionPass {
+  const TargetTransformInfo *TTI = nullptr;
+
+public:
+  static char ID; // Pass identification, replacement for typeid
+
+  explicit ScalarizeMayOverflowDiv() : FunctionPass(ID) {
+    initializeScalarizeMayOverflowDivPass(*PassRegistry::getPassRegistry());
+  }
+
+  bool runOnFunction(Function &F) override;
+
+  StringRef getPassName() const override {
+    return "Scalarize May Overflow Div";
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.addRequired<TargetTransformInfoWrapperPass>();
+  }
+
+private:
+  bool fixMayOverflowIntegerDiv(Instruction &I, bool isSigned);
+};
+
+} // end anonymous namespace
+
+char ScalarizeMayOverflowDiv::ID = 0;
+
+INITIALIZE_PASS(ScalarizeMayOverflowDiv, DEBUG_TYPE,
+                "Scalarize unsupported may overflow divisions", false, false)
+
+FunctionPass *llvm::createScalarizeMayOverflowDivPass() {
+  return new ScalarizeMayOverflowDiv();
+}
+
+bool ScalarizeMayOverflowDiv::runOnFunction(Function &F) {
+  if (skipFunction(F))
+    return false;
+
+  bool EverMadeChange = false;
+  TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
+  /// Search for unsupported may overflow division and replace it with 'nof'
+  /// integer division sequence
+  SmallVector<Instruction *, 2> SDivInsts;
+  SmallVector<Instruction *, 2> UDivInsts;
+  for (BasicBlock &BB : F) {
+    for (Instruction &I : BB) {
+      if (I.getOpcode() == Instruction::SDiv && !I.isNoOverflow() &&
+          !TTI->isLegalMayOverflowSDiv(I.getType()))
+        SDivInsts.push_back(&I);
+      if (I.getOpcode() == Instruction::UDiv && !I.isNoOverflow() &&
+          !TTI->isLegalMayOverflowUDiv(I.getType()))
+        UDivInsts.push_back(&I);
+    }
+  }
+  for (auto &I : SDivInsts)
+    EverMadeChange |= fixMayOverflowIntegerDiv(*I, true);
+  for (auto &I : UDivInsts)
+    EverMadeChange |= fixMayOverflowIntegerDiv(*I, false);
+  return EverMadeChange;
+}
+
+/// replace the unsupported division with a scalar safe code
+bool ScalarizeMayOverflowDiv::fixMayOverflowIntegerDiv(Instruction &I,
+                                                       bool isSigned) {
+  assert((I.getOpcode() == Instruction::SDiv ||
+          I.getOpcode() == Instruction::UDiv) &&
+         "unexpected instruction");
+
+  IRBuilder<> Builder(I.getContext());
+  Instruction *InsertPt = &I;
+  BasicBlock *IfBlock = I.getParent();
+  BasicBlock *CondBlock = nullptr;
+  BasicBlock *PrevIfBlock = I.getParent();
+
+  Builder.SetInsertPoint(InsertPt);
+  Builder.SetCurrentDebugLocation(I.getDebugLoc());
+
+  Value *B = I.getOperand(0);
+  Value *C = I.getOperand(1);
+  Value *UndefVal = UndefValue::get(I.getType());
+  PHINode *Phi = nullptr;
+
+  // scalar version case
+  if (!I.getType()->isVectorTy()) {
+    // %a = sdiv mof Ty %b, %c ; may overflow or div by zero
+    //
+    // can be transformmed to:
+    //
+    // BB.cond (unsigned version):
+    //   %cmp = icmp ne Ty %c, 0
+    //   br %cmp, %BB.true, %BB.merge
+    //
+    // BB.cond (signed version):
+    //   %cmp1= icmp ne Ty %c, 0
+    //   %cmp2= icmp ne Ty %c, -1
+    //   %cmp3= icmp ne Ty %b, MIN_SIGNED_Ty ;(-2147483648 in case of i32)
+    //                                       ; NOTE: -2147483648/-1 Overflow
+    //   %overflowcheck = or i1 %cmp2, %cmp3 ; false means we have overflow
+    //   %cmp = and i1 %cmp1, %overflowcheck
+    //   br %cmp, %BB.true, %BB.merge
+    // BB.true:
+    //     %a.1 = sdiv nof Ty %b, %c
+    //     br %BB.merge
+    // BB.merge:
+    //   %a = phi [Ty %a.1, %BB.true] [Ty undef, %BB.cond]
+    Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_NE, C,
+                                    ConstantInt::get(C->getType(), 0));
+    if (isSigned) {
+      APInt MinVal =
+          APInt::getSignedMinValue(B->getType()->getIntegerBitWidth());
+      Value *CmpPart2 = Builder.CreateICmp(
+          ICmpInst::ICMP_NE, C, ConstantInt::getSigned(C->getType(), -1));
+      Value *CmpPart3 = Builder.CreateICmp(
+          ICmpInst::ICMP_NE, B, ConstantInt::get(B->getType(), MinVal));
+      Value *OverflowCheck = Builder.CreateOr(CmpPart2, CmpPart3);
+      Cmp = Builder.CreateAnd(OverflowCheck, Cmp);
+    }
+    CondBlock = IfBlock->splitBasicBlock(InsertPt->getIterator(), "cond.div");
+    Builder.SetInsertPoint(InsertPt);
+
+    Value *Result = isSigned ? Builder.CreateSDiv(B, C, "", I.isExact())
+                             : Builder.CreateUDiv(B, C, "", I.isExact());
+
+    // Create "else" block, fill it in the next iteration
+    BasicBlock *NewIfBlock =
+        CondBlock->splitBasicBlock(InsertPt->getIterator(), "else");
+    Builder.SetInsertPoint(InsertPt);
+
+    Instruction *OldBr = IfBlock->getTerminator();
+    BranchInst::Create(CondBlock, NewIfBlock, Cmp, OldBr);
+    OldBr->eraseFromParent();
+
+    Phi = Builder.CreatePHI(I.getType(), 2, "res.phi.select");
+    Phi->addIncoming(Result, CondBlock);
+    Phi->addIncoming(UndefVal, IfBlock);
+    I.replaceAllUsesWith(Phi);
+    I.eraseFromParent();
+
+    return true;
+  }
+
+  // Vector Case:
+  // Similar to scalar we start by computing overflowing lanes, after that
+  // on each lane that has an overflow case we put undef in the relevant
+  // result lane otherwise we perform scalar nof div operation
+  //
+  // output example: (signed version)
+  // base:
+  // ...
+  // %cmp1= icmp ne <VF x Ty> %c, zeroinitializer
+  // %cmp2= icmp ne <VF x Ty> %c, <Ty -1, ..., Ty -1>
+  // %cmp3= icmp ne <VF x Ty> %b, <Ty MIN_SIGNED .. , Ty MIN_SIGNED>
+  // %overflow = or <VF x i1> %cmp2, %cmp3
+  // %cmp = and <VF x i1> %overflow, %cmp1 ; contains overflow status
+  //                                       ; for each lane
+  // %cmp.idx.0 =  extractelement <VF x i1> %cmp, i32 0 ; 1st lane status
+  // br i1 %cmp.idx, label %cond.div.0, label %else.0
+  //
+  // cond.div.0:
+  // %b.0 = extractelement <VF x Ty> %b, i32 0
+  // %c.0 = extractelement <VF x Ty> %c, i32 0
+  // %a.0 = sdiv nof %b.0, %c.0
+  // %tmp = insertelement <VF x Ty> undef, %a.0, 0
+  // br label %else.0
+  //
+  // else.0:
+  // %res.phi.else = phi <4 x i32> [ %tmp, %cond.div ], [ undef, %base ]
+  // %cmp.idx.1 =  extractelement <VF x i1> %cmp, i32 1 ; 2nd lane status
+  // br i1 %cmp.idx.1, label %cond.div.1, label %else.1
+  //
+  //  ...
+  //
+  Value *VResult = UndefVal;
+  Value *PrevPhi = UndefVal;
+  unsigned VectorWidth = I.getType()->getVectorNumElements();
+  Type *ElementTy = I.getType()->getVectorElementType();
+  Value *ZeroVector = ConstantInt::get(I.getType(), 0);
+  Value *MinusOneVector = ConstantInt::getSigned(I.getType(), -1);
+  Value *SignedMinVector = ConstantInt::get(
+      I.getType(), APInt::getSignedMinValue(ElementTy->getIntegerBitWidth()));
+  Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_NE, C, ZeroVector);
+  if (isSigned) {
+    Value *CmpPart2 = Builder.CreateICmp(ICmpInst::ICMP_NE, C, MinusOneVector);
+    Value *CmpPart3 = Builder.CreateICmp(ICmpInst::ICMP_NE, B, SignedMinVector);
+    Value *OverflowCheck = Builder.CreateOr(CmpPart2, CmpPart3);
+    Cmp = Builder.CreateAnd(OverflowCheck, Cmp);
+  }
+
+  for (unsigned Idx = 0; Idx < VectorWidth; ++Idx) {
+    if (Idx > 0) {
+      Phi = Builder.CreatePHI(I.getType(), 2, "res.phi.else");
+      Phi->addIncoming(VResult, CondBlock);
+      Phi->addIncoming(PrevPhi, PrevIfBlock);
+      PrevPhi = Phi;
+      VResult = Phi;
+    }
+
+    Value *CmpIdx = Builder.CreateExtractElement(Cmp, Idx);
+    CondBlock = IfBlock->splitBasicBlock(InsertPt->getIterator(), "cond.div");
+    Builder.SetInsertPoint(InsertPt);
+    Value *BIdx = Builder.CreateExtractElement(B, Idx);
+    Value *CIdx = Builder.CreateExtractElement(C, Idx);
+    Value *EltDiv = isSigned ? Builder.CreateSDiv(BIdx, CIdx, "", I.isExact())
+                             : Builder.CreateUDiv(BIdx, CIdx, "", I.isExact());
+    VResult = Builder.CreateInsertElement(VResult, EltDiv, Idx);
+
+    // Create "else" block, fill it in the next iteration
+    BasicBlock *NewIfBlock =
+        CondBlock->splitBasicBlock(InsertPt->getIterator(), "else");
+    Builder.SetInsertPoint(InsertPt);
+    Instruction *OldBr = IfBlock->getTerminator();
+    BranchInst::Create(CondBlock, NewIfBlock, CmpIdx, OldBr);
+    OldBr->eraseFromParent();
+
+    PrevIfBlock = IfBlock;
+    IfBlock = NewIfBlock;
+  }
+  Phi = Builder.CreatePHI(I.getType(), 2, "res.phi.select");
+  Phi->addIncoming(VResult, CondBlock);
+  Phi->addIncoming(PrevPhi, PrevIfBlock);
+  I.replaceAllUsesWith(Phi);
+  I.eraseFromParent();
+
+  return true;
+}

lib/CodeGen/TargetPassConfig.cpp

 static cl::opt<CFLAAType> UseCFLAA(
     "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
     cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
     cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
                clEnumValN(CFLAAType::Steensgaard, "steens",
                           "Enable unification-based CFL-AA"),
                clEnumValN(CFLAAType::Andersen, "anders",
                           "Enable inclusion-based CFL-AA"),
-               clEnumValN(CFLAAType::Both, "both", 
+               clEnumValN(CFLAAType::Both, "both",
                           "Enable both variants of CFL-AA")));
 
 /// Option names for limiting the codegen pipeline.
 /// Those are used in error reporting and we didn't want
 /// to duplicate their names all over the place.
 const char *StartAfterOptName = "start-after";
 const char *StartBeforeOptName = "start-before";
 const char *StopAfterOptName = "stop-after";
void TargetPassConfig::addIRPasses() {
   // Instrument function entry and exit, e.g. with calls to mcount().
   addPass(createPostInlineEntryExitInstrumenterPass());
 
   // Add scalarization of target's unsupported masked memory intrinsics pass.
   // the unsupported intrinsic will be replaced with a chain of basic blocks,
   // that stores/loads element one-by-one if the appropriate mask bit is set.
   addPass(createScalarizeMaskedMemIntrinPass());
 
+  // Add scalarization of target's unsupported may overflow integer divisions.
+  // the unsupported instruction will be replace with a chain of basic blocks,
+  // that divide element one-by-one if the appropriate lane is has safe values.
+  addPass(createScalarizeMayOverflowDivPass());
+
   // Expand reduction intrinsics into shuffle sequences if the target wants to.
   addPass(createExpandReductionsPass());
 }
 
 /// Turn exception handling constructs into something the code generators can
 /// handle.
 void TargetPassConfig::addPassesToHandleExceptions() {
   const MCAsmInfo *MCAI = TM->getMCAsmInfo();

lib/IR/AsmWriter.cpp

if (const OverflowingBinaryOperator *OBO =
     if (OBO->hasNoUnsignedWrap())
       Out << " nuw";
     if (OBO->hasNoSignedWrap())
       Out << " nsw";
   } else if (const PossiblyExactOperator *Div =
                dyn_cast<PossiblyExactOperator>(U)) {
     if (Div->isExact())
       Out << " exact";
+    if (const auto *PO = dyn_cast<PossiblyOverflowOperator>(U)) {
+      if (PO->isNoOverflow())
+        Out << " nof";
+      else
+        Out << " mof";
+    }      
   } else if (const GEPOperator *GEP = dyn_cast<GEPOperator>(U)) {
     if (GEP->isInBounds())
       Out << " inbounds";
+  } else if (const auto *PO = dyn_cast<PossiblyOverflowOperator>(U)) {
+    if (PO->isNoOverflow())
+      Out << " nof";
+    else
+      Out << " mof";
   }
 }
 
 static void WriteConstantInternal(raw_ostream &Out, const Constant *CV,
                                   TypePrinting &TypePrinter,
                                   SlotTracker *Machine,
                                   const Module *Context) {
   if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {

lib/IR/Constants.cpp

unsigned Flags = (HasNUW ? OverflowingBinaryOperator::NoUnsignedWrap : 0) |
                    (HasNSW ? OverflowingBinaryOperator::NoSignedWrap   : 0);
   return get(Instruction::Mul, C1, C2, Flags);
 }
 
 Constant *ConstantExpr::getFMul(Constant *C1, Constant *C2) {
   return get(Instruction::FMul, C1, C2);
 }
 
-Constant *ConstantExpr::getUDiv(Constant *C1, Constant *C2, bool isExact) {
-  return get(Instruction::UDiv, C1, C2,
-             isExact ? PossiblyExactOperator::IsExact : 0);
+Constant *ConstantExpr::getUDiv(Constant *C1, Constant *C2, bool isExact,
+                                bool isNoOverflow) {
+  unsigned Flags = (isExact ? PossiblyExactOperator::IsExact : 0) |
+                   (isNoOverflow ? 0 : PossiblyOverflowOperator::MayOverflow);
+  return get(Instruction::UDiv, C1, C2, Flags);
 }
 
-Constant *ConstantExpr::getSDiv(Constant *C1, Constant *C2, bool isExact) {
-  return get(Instruction::SDiv, C1, C2,
-             isExact ? PossiblyExactOperator::IsExact : 0);
+Constant *ConstantExpr::getSDiv(Constant *C1, Constant *C2, bool isExact,
+                                bool isNoOverflow) {
+  unsigned Flags = (isExact ? PossiblyExactOperator::IsExact : 0) |
+                   (isNoOverflow ? 0 : PossiblyOverflowOperator::MayOverflow);
+  return get(Instruction::SDiv, C1, C2, Flags);
 }
 
 Constant *ConstantExpr::getFDiv(Constant *C1, Constant *C2) {
   return get(Instruction::FDiv, C1, C2);
 }
 
 Constant *ConstantExpr::getURem(Constant *C1, Constant *C2) {
   return get(Instruction::URem, C1, C2);
default:
     if (isa<OverflowingBinaryOperator>(BO)) {
       BO->setHasNoUnsignedWrap(SubclassOptionalData &
                                OverflowingBinaryOperator::NoUnsignedWrap);
       BO->setHasNoSignedWrap(SubclassOptionalData &
                              OverflowingBinaryOperator::NoSignedWrap);
     }
     if (isa<PossiblyExactOperator>(BO))
       BO->setIsExact(SubclassOptionalData & PossiblyExactOperator::IsExact);
+    if (isa<PossiblyOverflowOperator>(BO))
+      BO->setIsNoOverflow(!(SubclassOptionalData &
+                          PossiblyOverflowOperator::MayOverflow));
     return BO;
   }
 }

lib/IR/Instruction.cpp

 void Instruction::setHasNoSignedWrap(bool b) {
   cast<OverflowingBinaryOperator>(this)->setHasNoSignedWrap(b);
 }
 
 void Instruction::setIsExact(bool b) {
   cast<PossiblyExactOperator>(this)->setIsExact(b);
 }
 
+void Instruction::setIsNoOverflow(bool b) {
+  cast<PossiblyOverflowOperator>(this)->setIsNoOverflow(b);
+}
+
 bool Instruction::hasNoUnsignedWrap() const {
   return cast<OverflowingBinaryOperator>(this)->hasNoUnsignedWrap();
 }
 
 bool Instruction::hasNoSignedWrap() const {
   return cast<OverflowingBinaryOperator>(this)->hasNoSignedWrap();
 }
 
 void Instruction::dropPoisonGeneratingFlags() {
   switch (getOpcode()) {
   case Instruction::Add:
   case Instruction::Sub:
   case Instruction::Mul:
   case Instruction::Shl:
     cast<OverflowingBinaryOperator>(this)->setHasNoUnsignedWrap(false);
     cast<OverflowingBinaryOperator>(this)->setHasNoSignedWrap(false);
     break;
 
   case Instruction::UDiv:
   case Instruction::SDiv:
+    cast<PossiblyOverflowOperator>(this)->setIsNoOverflow(true);
   case Instruction::AShr:
   case Instruction::LShr:
     cast<PossiblyExactOperator>(this)->setIsExact(false);
     break;
 
   case Instruction::GetElementPtr:
     cast<GetElementPtrInst>(this)->setIsInBounds(false);
     break;
   }
 }
 
 bool Instruction::isExact() const {
   return cast<PossiblyExactOperator>(this)->isExact();
 }
 
+bool Instruction::isNoOverflow() const {
+  return cast<PossiblyOverflowOperator>(this)->isNoOverflow();
+}  
+
 void Instruction::setFast(bool B) {
   assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
   cast<FPMathOperator>(this)->setFast(B);
 }
 
 void Instruction::setHasAllowReassoc(bool B) {
   assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
   cast<FPMathOperator>(this)->setHasAllowReassoc(B);
if (IncludeWrapFlags && isa<OverflowingBinaryOperator>(this)) {
     }
   }
 
   // Copy the exact flag.
   if (auto *PE = dyn_cast<PossiblyExactOperator>(V))
     if (isa<PossiblyExactOperator>(this))
       setIsExact(PE->isExact());
 
+  // Copy the no-overflow flag
+  if (auto *PO = dyn_cast<PossiblyOverflowOperator>(V))
+    if (isa<PossiblyOverflowOperator>(this))
+      setIsNoOverflow(PO->isNoOverflow());
+
   // Copy the fast-math flags.
   if (auto *FP = dyn_cast<FPMathOperator>(V))
     if (isa<FPMathOperator>(this))
       copyFastMathFlags(FP->getFastMathFlags());
 
   if (auto *SrcGEP = dyn_cast<GetElementPtrInst>(V))
     if (auto *DestGEP = dyn_cast<GetElementPtrInst>(this))
       DestGEP->setIsInBounds(SrcGEP->isInBounds() | DestGEP->isInBounds());
 }
 
 void Instruction::andIRFlags(const Value *V) {
   if (auto *OB = dyn_cast<OverflowingBinaryOperator>(V)) {
     if (isa<OverflowingBinaryOperator>(this)) {
       setHasNoSignedWrap(hasNoSignedWrap() & OB->hasNoSignedWrap());
       setHasNoUnsignedWrap(hasNoUnsignedWrap() & OB->hasNoUnsignedWrap());
     }
   }
 
   if (auto *PE = dyn_cast<PossiblyExactOperator>(V))
     if (isa<PossiblyExactOperator>(this))
       setIsExact(isExact() & PE->isExact());
 
+  if (auto *PO = dyn_cast<PossiblyOverflowOperator>(V))
+    if (isa<PossiblyOverflowOperator>(this))
+      setIsNoOverflow(isNoOverflow() & PO->isNoOverflow());
+
   if (auto *FP = dyn_cast<FPMathOperator>(V)) {
     if (isa<FPMathOperator>(this)) {
       FastMathFlags FM = getFastMathFlags();
       FM &= FP->getFastMathFlags();
       copyFastMathFlags(FM);
     }
   }
 

lib/Target/X86/X86TargetTransformInfo.h

int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
                     Type *Ty);
   bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
                      TargetTransformInfo::LSRCost &C2);
   bool canMacroFuseCmp();
   bool isLegalMaskedLoad(Type *DataType);
   bool isLegalMaskedStore(Type *DataType);
   bool isLegalMaskedGather(Type *DataType);
   bool isLegalMaskedScatter(Type *DataType);
+  bool isLegalMayOverflowUDiv(Type *DataType);
+  bool isLegalMayOverflowSDiv(Type *DataType);
   bool hasDivRemOp(Type *DataType, bool IsSigned);
   bool isFCmpOrdCheaperThanFCmpZero(Type *Ty);
   bool areInlineCompatible(const Function *Caller,
                            const Function *Callee) const;
   const TTI::MemCmpExpansionOptions *enableMemCmpExpansion(
       bool IsZeroCmp) const;
   bool enableInterleavedAccessVectorization();
 private:

lib/Target/X86/X86TargetTransformInfo.cpp

 
 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) {
   // AVX2 doesn't support scatter
   if (!ST->hasAVX512())
     return false;
   return isLegalMaskedGather(DataType);
 }
 
+bool X86TTIImpl::isLegalMayOverflowUDiv(Type *DataType) {
+  return false;
+}
+
+bool X86TTIImpl::isLegalMayOverflowSDiv(Type *DataType) {
+  return isLegalMayOverflowUDiv(DataType);
+}
+
 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
   EVT VT = TLI->getValueType(DL, DataType);
   return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
 }
 
 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
   return false;
 }

lib/Transforms/InstCombine/InstCombineAddSub.cpp

if (Op1->hasOneUse()) {
 
     // (X - (X & Y))   -->   (X & ~Y)
     if (match(Op1, m_c_And(m_Value(Y), m_Specific(Op0))))
       return BinaryOperator::CreateAnd(Op0,
                                   Builder.CreateNot(Y, Y->getName() + ".not"));
 
     // 0 - (X sdiv C)  -> (X sdiv -C)  provided the negation doesn't overflow.
     if (match(Op1, m_SDiv(m_Value(X), m_Constant(C))) && match(Op0, m_Zero()) &&
-        C->isNotMinSignedValue() && !C->isOneValue())
-      return BinaryOperator::CreateSDiv(X, ConstantExpr::getNeg(C));
+        C->isNotMinSignedValue() && !C->isOneValue()) {
+      Instruction *BinOp = BinaryOperator::CreateSDiv(X, ConstantExpr::getNeg(C));
+      BinOp->setIsNoOverflow(cast<BinaryOperator>(Op1)->isNoOverflow());
+      return BinOp;
+    }
 
     // 0 - (X << Y)  -> (-X << Y)   when X is freely negatable.
     if (match(Op1, m_Shl(m_Value(X), m_Value(Y))) && match(Op0, m_Zero()))
       if (Value *XNeg = dyn_castNegVal(X))
         return BinaryOperator::CreateShl(XNeg, Y);
 
     // Subtracting -1/0 is the same as adding 1/0:
     // sub [nsw] Op0, sext(bool Y) -> add [nsw] Op0, zext(bool Y)

lib/Transforms/InstCombine/InstCombineMulDivRem.cpp

if (Instruction *LHS = dyn_cast<Instruction>(Op0)) {
     if (match(Op1, m_APInt(C2))) {
       Value *X;
       const APInt *C1;
 
       // (X / C1) / C2  -> X / (C1*C2)
       if ((IsSigned && match(LHS, m_SDiv(m_Value(X), m_APInt(C1)))) ||
           (!IsSigned && match(LHS, m_UDiv(m_Value(X), m_APInt(C1))))) {
         APInt Product(C1->getBitWidth(), /*Val=*/0ULL, IsSigned);
-        if (!MultiplyOverflows(*C1, *C2, Product, IsSigned))
-          return BinaryOperator::Create(I.getOpcode(), X,
-                                        ConstantInt::get(I.getType(), Product));
+        if (!MultiplyOverflows(*C1, *C2, Product, IsSigned)) {
+          Instruction *BinOp = BinaryOperator::Create(
+              I.getOpcode(), X, ConstantInt::get(I.getType(), Product));
+          BinOp->setIsNoOverflow(I.isNoOverflow() && LHS->isNoOverflow());
+          return BinOp;
+        }
       }
 
       if ((IsSigned && match(LHS, m_NSWMul(m_Value(X), m_APInt(C1)))) ||
           (!IsSigned && match(LHS, m_NUWMul(m_Value(X), m_APInt(C1))))) {
         APInt Quotient(C1->getBitWidth(), /*Val=*/0ULL, IsSigned);
 
         // (X * C1) / C2 -> X / (C2 / C1) if C2 is a multiple of C1.
         if (IsMultiple(*C2, *C1, Quotient, IsSigned)) {
           BinaryOperator *BO = BinaryOperator::Create(
               I.getOpcode(), X, ConstantInt::get(X->getType(), Quotient));
           BO->setIsExact(I.isExact());
+          BO->setIsNoOverflow(I.isNoOverflow());
           return BO;
         }
 
         // (X * C1) / C2 -> X * (C1 / C2) if C1 is a multiple of C2.
         if (IsMultiple(*C1, *C2, Quotient, IsSigned)) {
           BinaryOperator *BO = BinaryOperator::Create(
               Instruction::Mul, X, ConstantInt::get(X->getType(), Quotient));
           BO->setHasNoUnsignedWrap(
if (match(Op1, m_APInt(C2))) {
         APInt C1Shifted = APInt::getOneBitSet(
             C1->getBitWidth(), static_cast<unsigned>(C1->getLimitedValue()));
 
         // (X << C1) / C2 -> X / (C2 >> C1) if C2 is a multiple of C1.
         if (IsMultiple(*C2, C1Shifted, Quotient, IsSigned)) {
           BinaryOperator *BO = BinaryOperator::Create(
               I.getOpcode(), X, ConstantInt::get(X->getType(), Quotient));
           BO->setIsExact(I.isExact());
+          BO->setIsNoOverflow(I.isNoOverflow());
           return BO;
         }
 
         // (X << C1) / C2 -> X * (C2 >> C1) if C1 is a multiple of C2.
         if (IsMultiple(C1Shifted, *C2, Quotient, IsSigned)) {
           BinaryOperator *BO = BinaryOperator::Create(
               Instruction::Mul, X, ConstantInt::get(X->getType(), Quotient));
           BO->setHasNoUnsignedWrap(
Instruction *InstCombiner::commonIDivTransforms(BinaryOperator &I) {
   // See if we can fold away this div instruction.
   if (SimplifyDemandedInstructionBits(I))
     return &I;
 
   // (X - (X rem Y)) / Y -> X / Y; usually originates as ((X / Y) * Y) / Y
   Value *X, *Z;
   if (match(Op0, m_Sub(m_Value(X), m_Value(Z)))) // (X - Z) / Y; Y = Op1
     if ((IsSigned && match(Z, m_SRem(m_Specific(X), m_Specific(Op1)))) ||
-        (!IsSigned && match(Z, m_URem(m_Specific(X), m_Specific(Op1)))))
-      return BinaryOperator::Create(I.getOpcode(), X, Op1);
+        (!IsSigned && match(Z, m_URem(m_Specific(X), m_Specific(Op1))))) {
+      Instruction *BinOp = BinaryOperator::Create(I.getOpcode(), X, Op1);
+      BinOp->setIsNoOverflow(I.isNoOverflow());
+      return BinOp;
+    }
 
   // (X << Y) / X -> 1 << Y
   Value *Y;
   if (IsSigned && match(Op0, m_NSWShl(m_Specific(Op1), m_Value(Y))))
     return BinaryOperator::CreateNSWShl(ConstantInt::get(I.getType(), 1), Y);
   if (!IsSigned && match(Op0, m_NUWShl(m_Specific(Op1), m_Value(Y))))
     return BinaryOperator::CreateNUWShl(ConstantInt::get(I.getType(), 1), Y);
 
static Instruction *narrowUDivURem(BinaryOperator &I,
   Value *D = I.getOperand(1);
   Type *Ty = I.getType();
   Value *X, *Y;
   if (match(N, m_ZExt(m_Value(X))) && match(D, m_ZExt(m_Value(Y))) &&
       X->getType() == Y->getType() && (N->hasOneUse() || D->hasOneUse())) {
     // udiv (zext X), (zext Y) --> zext (udiv X, Y)
     // urem (zext X), (zext Y) --> zext (urem X, Y)
     Value *NarrowOp = Builder.CreateBinOp(Opcode, X, Y);
+    Instruction *BinOp = dyn_cast<Instruction>(NarrowOp);
+    if (BinOp && isa<PossiblyOverflowOperator>(NarrowOp)) 
+      BinOp->setIsNoOverflow(I.isNoOverflow());
     return new ZExtInst(NarrowOp, Ty);
   }
 
   Constant *C;
   if ((match(N, m_OneUse(m_ZExt(m_Value(X)))) && match(D, m_Constant(C))) ||
       (match(D, m_OneUse(m_ZExt(m_Value(X)))) && match(N, m_Constant(C)))) {
     // If the constant is the same in the smaller type, use the narrow version.
     Constant *TruncC = ConstantExpr::getTrunc(C, X->getType());
     if (ConstantExpr::getZExt(TruncC, Ty) != C)
       return nullptr;
 
     // udiv (zext X), C --> zext (udiv X, C')
     // urem (zext X), C --> zext (urem X, C')
     // udiv C, (zext X) --> zext (udiv C', X)
     // urem C, (zext X) --> zext (urem C', X)
     Value *NarrowOp = isa<Constant>(D) ? Builder.CreateBinOp(Opcode, X, TruncC)
                                        : Builder.CreateBinOp(Opcode, TruncC, X);
+    Instruction *BinOp = dyn_cast<Instruction>(NarrowOp);
+    if (BinOp && isa<PossiblyOverflowOperator>(NarrowOp))
+      BinOp->setIsNoOverflow(I.isNoOverflow());
     return new ZExtInst(NarrowOp, Ty);
   }
 
   return nullptr;
 }
 
 Instruction *InstCombiner::visitUDiv(BinaryOperator &I) {
   Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
if (match(Op0, m_LShr(m_Value(X), m_APInt(C1))) &&
       bool Overflow;
       APInt C2ShlC1 = C2->ushl_ov(*C1, Overflow);
       if (!Overflow) {
         bool IsExact = I.isExact() && match(Op0, m_Exact(m_Value()));
         BinaryOperator *BO = BinaryOperator::CreateUDiv(
             X, ConstantInt::get(X->getType(), C2ShlC1));
         if (IsExact)
           BO->setIsExact();
+        BO->setIsNoOverflow(I.isNoOverflow());  
         return BO;
       }
     }
   }
 
   if (Instruction *NarrowDiv = narrowUDivURem(I, Builder))
     return NarrowDiv;
 
if (Constant *RHS = dyn_cast<Constant>(Op1)) {
     if (RHS->isMinSignedValue())
       return new ZExtInst(Builder.CreateICmpEQ(Op0, Op1), I.getType());
 
     // -X/C  -->  X/-C  provided the negation doesn't overflow.
     Value *X;
     if (match(Op0, m_NSWSub(m_Zero(), m_Value(X)))) {
       auto *BO = BinaryOperator::CreateSDiv(X, ConstantExpr::getNeg(RHS));
       BO->setIsExact(I.isExact());
+      BO->setIsNoOverflow(I.isNoOverflow());
       return BO;
     }
   }
 
   // If the sign bits of both operands are zero (i.e. we can prove they are
   // unsigned inputs), turn this into a udiv.
   APInt Mask(APInt::getSignMask(I.getType()->getScalarSizeInBits()));
   if (MaskedValueIsZero(Op0, Mask, 0, &I)) {
     if (MaskedValueIsZero(Op1, Mask, 0, &I)) {
       // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set
       auto *BO = BinaryOperator::CreateUDiv(Op0, Op1, I.getName());
       BO->setIsExact(I.isExact());
+      BO->setIsNoOverflow(I.isNoOverflow());
       return BO;
     }
 
     if (isKnownToBeAPowerOfTwo(Op1, /*OrZero*/ true, 0, &I)) {
       // X sdiv (1 << Y) -> X udiv (1 << Y) ( -> X u>> Y)
       // Safe because the only negative value (1 << Y) can take on is
       // INT_MIN, and X sdiv INT_MIN == X udiv INT_MIN == 0 if X doesn't have
       // the sign bit set.
       auto *BO = BinaryOperator::CreateUDiv(Op0, Op1, I.getName());
       BO->setIsExact(I.isExact());
+      BO->setIsNoOverflow(I.isNoOverflow());
       return BO;
     }
   }
 
   return nullptr;
 }
 
 /// CvtFDivConstToReciprocal tries to convert X/C into X*1/C if C not a special

lib/Transforms/InstCombine/InstCombineVectorOps.cpp

case Instruction::Xor: {
                                  NewOps[0], NewOps[1], "", BO);
       if (isa<OverflowingBinaryOperator>(BO)) {
         New->setHasNoUnsignedWrap(BO->hasNoUnsignedWrap());
         New->setHasNoSignedWrap(BO->hasNoSignedWrap());
       }
       if (isa<PossiblyExactOperator>(BO)) {
         New->setIsExact(BO->isExact());
       }
+      if (isa<PossiblyOverflowOperator>(BO)) {
+        New->setIsNoOverflow(BO->isNoOverflow());
+      }
       if (isa<FPMathOperator>(BO))
         New->copyFastMathFlags(I);
       return New;
     }
     case Instruction::ICmp:
       assert(NewOps.size() == 2 && "icmp with #ops != 2");
       return new ICmpInst(I, cast<ICmpInst>(I)->getPredicate(),
                           NewOps[0], NewOps[1]);

lib/Transforms/InstCombine/InstructionCombining.cpp

if (ConstIsRHS)
       return ConstantExpr::get(I->getOpcode(), InC, C);
     return ConstantExpr::get(I->getOpcode(), C, InC);
   }
 
   Value *Op0 = InV, *Op1 = C;
   if (!ConstIsRHS)
     std::swap(Op0, Op1);
 
   Value *RI = Builder.CreateBinOp(I->getOpcode(), Op0, Op1, "phitmp");
-  auto *FPInst = dyn_cast<Instruction>(RI);
-  if (FPInst && isa<FPMathOperator>(FPInst))
-    FPInst->copyFastMathFlags(I);
+  auto *Inst = dyn_cast<Instruction>(RI);
+  if (Inst && isa<PossiblyOverflowOperator>(RI)) 
+    Inst->setIsNoOverflow(I->isNoOverflow());
+  if (Inst && isa<FPMathOperator>(Inst))
+    Inst->copyFastMathFlags(I);
   return RI;
 }
 
 Instruction *InstCombiner::foldOpIntoPhi(Instruction &I, PHINode *PN) {
   unsigned NumPHIValues = PN->getNumIncomingValues();
   if (NumPHIValues == 0)
     return nullptr;
 

lib/Transforms/Scalar/CorrelatedValuePropagation.cpp

static bool processSDiv(BinaryOperator *SDI, LazyValueInfo *LVI) {
   if (SDI->getType()->isVectorTy() ||
       !hasPositiveOperands(SDI, LVI))
     return false;
 
   ++NumSDivs;
   auto *BO = BinaryOperator::CreateUDiv(SDI->getOperand(0), SDI->getOperand(1),
                                         SDI->getName(), SDI);
   BO->setIsExact(SDI->isExact());
+  BO->setIsNoOverflow(SDI->isNoOverflow());
   SDI->replaceAllUsesWith(BO);
   SDI->eraseFromParent();
 
   return true;
 }
 
 static bool processAShr(BinaryOperator *SDI, LazyValueInfo *LVI) {
   if (SDI->getType()->isVectorTy())

lib/Transforms/Utils/SimplifyIndVar.cpp

bool SimplifyIndvar::eliminateSDiv(BinaryOperator *SDiv) {
   D = SE->getSCEVAtScope(D, L);
 
   // Replace sdiv by udiv if both of the operands are non-negative
   if (SE->isKnownNonNegative(N) && SE->isKnownNonNegative(D)) {
     auto *UDiv = BinaryOperator::Create(
         BinaryOperator::UDiv, SDiv->getOperand(0), SDiv->getOperand(1),
         SDiv->getName() + ".udiv", SDiv);
     UDiv->setIsExact(SDiv->isExact());
+    UDiv->setIsNoOverflow(SDiv->isNoOverflow());
     SDiv->replaceAllUsesWith(UDiv);
     DEBUG(dbgs() << "INDVARS: Simplified sdiv: " << *SDiv << '\n');
     ++NumSimplifiedSDiv;
     Changed = true;
     DeadInsts.push_back(SDiv);
     return true;
   }
 

test/Analysis/CostModel/SystemZ/div-pow2.ll

 ; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z13 | FileCheck %s
 
 ; Scalar sdiv
 
 define i64 @fun0(i64 %a) {
-  %r = sdiv i64 %a, 2
+  %r = sdiv nof i64 %a, 2
   ret i64 %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv i64 %a, 2
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof i64 %a, 2
 }
 
 define i64 @fun1(i64 %a) {
-  %r = sdiv i64 %a, -4
+  %r = sdiv nof i64 %a, -4
   ret i64 %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv i64 %a, -4
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof i64 %a, -4
 }
 
 define i32 @fun2(i32 %a) {
-  %r = sdiv i32 %a, 8
+  %r = sdiv nof i32 %a, 8
   ret i32 %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv i32 %a, 8
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof i32 %a, 8
 }
 
 define i32 @fun3(i32 %a) {
-  %r = sdiv i32 %a, -16
+  %r = sdiv nof i32 %a, -16
   ret i32 %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv i32 %a, -16
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof i32 %a, -16
 }
 
 define i16 @fun4(i16 %a) {
-  %r = sdiv i16 %a, 32
+  %r = sdiv nof i16 %a, 32
   ret i16 %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv i16 %a, 32
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof i16 %a, 32
 }
 
 define i16 @fun5(i16 %a) {
-  %r = sdiv i16 %a, -64
+  %r = sdiv nof i16 %a, -64
   ret i16 %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv i16 %a, -64
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof i16 %a, -64
 }
 
 define i8 @fun6(i8 %a) {
-  %r = sdiv i8 %a, 64
+  %r = sdiv nof i8 %a, 64
   ret i8 %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv i8 %a, 64
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof i8 %a, 64
 }
 
 define i8 @fun7(i8 %a) {
-  %r = sdiv i8 %a, -128
+  %r = sdiv nof i8 %a, -128
   ret i8 %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv i8 %a, -128
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof i8 %a, -128
 }
 
 
 ; Vector sdiv
 
 define <2 x i64> @fun8(<2 x i64> %a) {
-  %r = sdiv <2 x i64> %a, <i64 2, i64 2>
+  %r = sdiv nof <2 x i64> %a, <i64 2, i64 2>
   ret <2 x i64> %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv <2 x i64> %a, <i64 2, i64 2>
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof <2 x i64> %a, <i64 2, i64 2>
 }
 
 define <2 x i64> @fun9(<2 x i64> %a) {
-  %r = sdiv <2 x i64> %a, <i64 -4, i64 -4>
+  %r = sdiv nof <2 x i64> %a, <i64 -4, i64 -4>
   ret <2 x i64> %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv <2 x i64> %a, <i64 -4, i64 -4>
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof <2 x i64> %a, <i64 -4, i64 -4>
 }
 
 define <4 x i32> @fun10(<4 x i32> %a) {
-  %r = sdiv <4 x i32> %a, <i32 8, i32 8, i32 8, i32 8>
+  %r = sdiv nof <4 x i32> %a, <i32 8, i32 8, i32 8, i32 8>
   ret <4 x i32> %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv <4 x i32> %a, <i32 8, i32 8, i32 8, i32 8>
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof <4 x i32> %a, <i32 8, i32 8, i32 8, i32 8>
 }
 
 define <4 x i32> @fun11(<4 x i32> %a) {
-  %r = sdiv <4 x i32> %a, <i32 -16, i32 -16, i32 -16, i32 -16>
+  %r = sdiv nof <4 x i32> %a, <i32 -16, i32 -16, i32 -16, i32 -16>
   ret <4 x i32> %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv <4 x i32> %a, <i32 -16
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof <4 x i32> %a, <i32 -16
 }
 
 define <8 x i16> @fun12(<8 x i16> %a) {
-  %r = sdiv <8 x i16> %a, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
+  %r = sdiv nof <8 x i16> %a, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
   ret <8 x i16> %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv <8 x i16> %a, <i16 32
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof <8 x i16> %a, <i16 32
 }
 
 define <8 x i16> @fun13(<8 x i16> %a) {
-  %r = sdiv <8 x i16> %a, <i16 -64, i16 -64, i16 -64, i16 -64, i16 -64, i16 -64, i16 -64, i16 -64>
+  %r = sdiv nof <8 x i16> %a, <i16 -64, i16 -64, i16 -64, i16 -64, i16 -64, i16 -64, i16 -64, i16 -64>
   ret <8 x i16> %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv <8 x i16> %a, <i16 -64
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof <8 x i16> %a, <i16 -64
 }
 
 define <16 x i8> @fun14(<16 x i8> %a) {
-  %r = sdiv <16 x i8> %a, <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
+  %r = sdiv nof <16 x i8> %a, <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>
   ret <16 x i8> %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv <16 x i8> %a, <i8 64
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof <16 x i8> %a, <i8 64
 }
 
 define <16 x i8> @fun15(<16 x i8> %a) {
-  %r = sdiv <16 x i8> %a, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
+  %r = sdiv nof <16 x i8> %a, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
   ret <16 x i8> %r
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv <16 x i8> %a, <i8 -128
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %r = sdiv nof <16 x i8> %a, <i8 -128
 }
 
 ; Scalar udiv
 
 define i64 @fun16(i64 %a) {
-  %r = udiv i64 %a, 2
+  %r = udiv nof i64 %a, 2
   ret i64 %r
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv i64 %a, 2
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv nof i64 %a, 2
 }
 
 define i32 @fun17(i32 %a) {
-  %r = udiv i32 %a, 8
+  %r = udiv nof i32 %a, 8
   ret i32 %r
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv i32 %a, 8
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv nof i32 %a, 8
 }
 
 define i16 @fun18(i16 %a) {
-  %r = udiv i16 %a, 32
+  %r = udiv nof i16 %a, 32
   ret i16 %r
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv i16 %a, 32
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv nof i16 %a, 32
 }
 
 define i8 @fun19(i8 %a) {
-  %r = udiv i8 %a, 128
+  %r = udiv nof i8 %a, 128
   ret i8 %r
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv i8 %a, -128
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv nof i8 %a, -128
 }
 
 ; Vector udiv
 
 define <2 x i64> @fun20(<2 x i64> %a) {
-  %r = udiv <2 x i64> %a, <i64 2, i64 2>
+  %r = udiv nof <2 x i64> %a, <i64 2, i64 2>
   ret <2 x i64> %r
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv <2 x i64> %a, <i64 2
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv nof <2 x i64> %a, <i64 2
 }
 
 define <4 x i32> @fun21(<4 x i32> %a) {
-  %r = udiv <4 x i32> %a, <i32 8, i32 8, i32 8, i32 8>
+  %r = udiv nof <4 x i32> %a, <i32 8, i32 8, i32 8, i32 8>
   ret <4 x i32> %r
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv <4 x i32> %a, <i32 8
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv nof <4 x i32> %a, <i32 8
 }
 
 define <8 x i16> @fun22(<8 x i16> %a) {
-  %r = udiv <8 x i16> %a, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
+  %r = udiv nof <8 x i16> %a, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
   ret <8 x i16> %r
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv <8 x i16> %a, <i16 32
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv nof <8 x i16> %a, <i16 32
 }
 
 define <16 x i8> @fun23(<16 x i8> %a) {
-  %r = udiv <16 x i8> %a, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
+  %r = udiv nof <16 x i8> %a, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
   ret <16 x i8> %r
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv <16 x i8> %a, <i8 -128
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %r = udiv nof <16 x i8> %a, <i8 -128
 }

test/Analysis/CostModel/SystemZ/int-arith.ll

 ; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %res17 = mul <16 x i16> undef, undef
 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %res18 = mul <16 x i32> undef, undef
 ; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %res19 = mul <16 x i64> undef, undef
 
   ret void;
 }
 
 define void @sdiv() {
-  %res0 = sdiv i8 undef, undef
-  %res1 = sdiv i16 undef, undef
-  %res2 = sdiv i32 undef, undef
-  %res3 = sdiv i64 undef, undef
-  %res4 = sdiv <2 x i8> undef, undef
-  %res5 = sdiv <2 x i16> undef, undef
-  %res6 = sdiv <2 x i32> undef, undef
-  %res7 = sdiv <2 x i64> undef, undef
-  %res8 = sdiv <4 x i8> undef, undef
-  %res9 = sdiv <4 x i16> undef, undef
-  %res10 = sdiv <4 x i32> undef, undef
-  %res11 = sdiv <4 x i64> undef, undef
-  %res12 = sdiv <8 x i8> undef, undef
-  %res13 = sdiv <8 x i16> undef, undef
-  %res14 = sdiv <8 x i32> undef, undef
-  %res15 = sdiv <8 x i64> undef, undef
-  %res16 = sdiv <16 x i8> undef, undef
-  %res17 = sdiv <16 x i16> undef, undef
-  %res18 = sdiv <16 x i32> undef, undef
-  %res19 = sdiv <16 x i64> undef, undef
-
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %res0 = sdiv i8 undef, undef
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %res1 = sdiv i16 undef, undef
-; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %res2 = sdiv i32 undef, undef
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %res3 = sdiv i64 undef, undef
-; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res4 = sdiv <2 x i8> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res5 = sdiv <2 x i16> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %res6 = sdiv <2 x i32> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 3 for instruction:   %res7 = sdiv <2 x i64> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res8 = sdiv <4 x i8> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res9 = sdiv <4 x i16> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %res10 = sdiv <4 x i32> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %res11 = sdiv <4 x i64> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res12 = sdiv <8 x i8> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res13 = sdiv <8 x i16> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %res14 = sdiv <8 x i32> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %res15 = sdiv <8 x i64> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 80 for instruction:   %res16 = sdiv <16 x i8> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 80 for instruction:   %res17 = sdiv <16 x i16> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %res18 = sdiv <16 x i32> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %res19 = sdiv <16 x i64> undef, undef
+  %res0 = sdiv nof i8 undef, undef
+  %res1 = sdiv nof i16 undef, undef
+  %res2 = sdiv nof i32 undef, undef
+  %res3 = sdiv nof i64 undef, undef
+  %res4 = sdiv nof <2 x i8> undef, undef
+  %res5 = sdiv nof <2 x i16> undef, undef
+  %res6 = sdiv nof <2 x i32> undef, undef
+  %res7 = sdiv nof <2 x i64> undef, undef
+  %res8 = sdiv nof <4 x i8> undef, undef
+  %res9 = sdiv nof <4 x i16> undef, undef
+  %res10 = sdiv nof <4 x i32> undef, undef
+  %res11 = sdiv nof <4 x i64> undef, undef
+  %res12 = sdiv nof <8 x i8> undef, undef
+  %res13 = sdiv nof <8 x i16> undef, undef
+  %res14 = sdiv nof <8 x i32> undef, undef
+  %res15 = sdiv nof <8 x i64> undef, undef
+  %res16 = sdiv nof <16 x i8> undef, undef
+  %res17 = sdiv nof <16 x i16> undef, undef
+  %res18 = sdiv nof <16 x i32> undef, undef
+  %res19 = sdiv nof <16 x i64> undef, undef
+
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %res0 = sdiv nof i8 undef, undef
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %res1 = sdiv nof i16 undef, undef
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %res2 = sdiv nof i32 undef, undef
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %res3 = sdiv nof i64 undef, undef
+; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res4 = sdiv nof <2 x i8> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res5 = sdiv nof <2 x i16> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %res6 = sdiv nof <2 x i32> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 3 for instruction:   %res7 = sdiv nof <2 x i64> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res8 = sdiv nof <4 x i8> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res9 = sdiv nof <4 x i16> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %res10 = sdiv nof <4 x i32> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %res11 = sdiv nof <4 x i64> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res12 = sdiv nof <8 x i8> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res13 = sdiv nof <8 x i16> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %res14 = sdiv nof <8 x i32> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %res15 = sdiv nof <8 x i64> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 80 for instruction:   %res16 = sdiv nof <16 x i8> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 80 for instruction:   %res17 = sdiv nof <16 x i16> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %res18 = sdiv nof <16 x i32> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %res19 = sdiv nof <16 x i64> undef, undef
 
   ret void;
 }
 
 define void @srem() {
   %res0 = srem i8 undef, undef
   %res1 = srem i16 undef, undef
   %res2 = srem i32 undef, undef

 ; CHECK: Cost Model: Found an estimated cost of 80 for instruction:   %res17 = srem <16 x i16> undef, undef
 ; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %res18 = srem <16 x i32> undef, undef
 ; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %res19 = srem <16 x i64> undef, undef
 
   ret void;
 }
 
 define void @udiv() {
-  %res0 = udiv i8 undef, undef
-  %res1 = udiv i16 undef, undef
-  %res2 = udiv i32 undef, undef
-  %res3 = udiv i64 undef, undef
-  %res4 = udiv <2 x i8> undef, undef
-  %res5 = udiv <2 x i16> undef, undef
-  %res6 = udiv <2 x i32> undef, undef
-  %res7 = udiv <2 x i64> undef, undef
-  %res8 = udiv <4 x i8> undef, undef
-  %res9 = udiv <4 x i16> undef, undef
-  %res10 = udiv <4 x i32> undef, undef
-  %res11 = udiv <4 x i64> undef, undef
-  %res12 = udiv <8 x i8> undef, undef
-  %res13 = udiv <8 x i16> undef, undef
-  %res14 = udiv <8 x i32> undef, undef
-  %res15 = udiv <8 x i64> undef, undef
-  %res16 = udiv <16 x i8> undef, undef
-  %res17 = udiv <16 x i16> undef, undef
-  %res18 = udiv <16 x i32> undef, undef
-  %res19 = udiv <16 x i64> undef, undef
-
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %res0 = udiv i8 undef, undef
-; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %res1 = udiv i16 undef, undef
-; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %res2 = udiv i32 undef, undef
-; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %res3 = udiv i64 undef, undef
-; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res4 = udiv <2 x i8> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res5 = udiv <2 x i16> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %res6 = udiv <2 x i32> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 5 for instruction:   %res7 = udiv <2 x i64> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res8 = udiv <4 x i8> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res9 = udiv <4 x i16> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %res10 = udiv <4 x i32> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res11 = udiv <4 x i64> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res12 = udiv <8 x i8> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res13 = udiv <8 x i16> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %res14 = udiv <8 x i32> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res15 = udiv <8 x i64> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 80 for instruction:   %res16 = udiv <16 x i8> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 80 for instruction:   %res17 = udiv <16 x i16> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %res18 = udiv <16 x i32> undef, undef
-; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res19 = udiv <16 x i64> undef, undef
+  %res0 = udiv nof i8 undef, undef
+  %res1 = udiv nof i16 undef, undef
+  %res2 = udiv nof i32 undef, undef
+  %res3 = udiv nof i64 undef, undef
+  %res4 = udiv nof <2 x i8> undef, undef
+  %res5 = udiv nof <2 x i16> undef, undef
+  %res6 = udiv nof <2 x i32> undef, undef
+  %res7 = udiv nof <2 x i64> undef, undef
+  %res8 = udiv nof <4 x i8> undef, undef
+  %res9 = udiv nof <4 x i16> undef, undef
+  %res10 = udiv nof <4 x i32> undef, undef
+  %res11 = udiv nof <4 x i64> undef, undef
+  %res12 = udiv nof <8 x i8> undef, undef
+  %res13 = udiv nof <8 x i16> undef, undef
+  %res14 = udiv nof <8 x i32> undef, undef
+  %res15 = udiv nof <8 x i64> undef, undef
+  %res16 = udiv nof <16 x i8> undef, undef
+  %res17 = udiv nof <16 x i16> undef, undef
+  %res18 = udiv nof <16 x i32> undef, undef
+  %res19 = udiv nof <16 x i64> undef, undef
+
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %res0 = udiv nof i8 undef, undef
+; CHECK: Cost Model: Found an estimated cost of 4 for instruction:   %res1 = udiv nof i16 undef, undef
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %res2 = udiv nof i32 undef, undef
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %res3 = udiv nof i64 undef, undef
+; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res4 = udiv nof <2 x i8> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res5 = udiv nof <2 x i16> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 6 for instruction:   %res6 = udiv nof <2 x i32> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 5 for instruction:   %res7 = udiv nof <2 x i64> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res8 = udiv nof <4 x i8> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res9 = udiv nof <4 x i16> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 12 for instruction:   %res10 = udiv nof <4 x i32> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 10 for instruction:   %res11 = udiv nof <4 x i64> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res12 = udiv nof <8 x i8> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res13 = udiv nof <8 x i16> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 24 for instruction:   %res14 = udiv nof <8 x i32> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 20 for instruction:   %res15 = udiv nof <8 x i64> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 80 for instruction:   %res16 = udiv nof <16 x i8> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 80 for instruction:   %res17 = udiv nof <16 x i16> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 48 for instruction:   %res18 = udiv nof <16 x i32> undef, undef
+; CHECK: Cost Model: Found an estimated cost of 40 for instruction:   %res19 = udiv nof <16 x i64> undef, undef
 
   ret void;
 }
 
 define void @urem() {
   %res0 = urem i8 undef, undef
   %res1 = urem i16 undef, undef
   %res2 = urem i32 undef, undef

test/Analysis/CostModel/SystemZ/memop-folding-int-arith.ll

 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %3 = mul i64 %li64, undef
 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %li64_0 = load i64, i64* undef
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %li64_1 = load i64, i64* undef
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %4 = mul i64 %li64_0, %li64_1
 }
 
 define void @sdiv() {
   %li32 = load i32, i32* undef
-  sdiv i32 %li32, undef
+  sdiv nof i32 %li32, undef
 
   %li32_0 = load i32, i32* undef
   %li32_1 = load i32, i32* undef
-  sdiv i32 %li32_0, %li32_1
+  sdiv nof i32 %li32_0, %li32_1
 
   %li64 = load i64, i64* undef
-  sdiv i64 %li64, undef
+  sdiv nof i64 %li64, undef
 
   %li64_0 = load i64, i64* undef
   %li64_1 = load i64, i64* undef
-  sdiv i64 %li64_0, %li64_1
+  sdiv nof i64 %li64_0, %li64_1
 
   ret void;
 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %li32 = load i32, i32* undef
-; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %1 = sdiv i32 %li32, undef
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %1 = sdiv nof i32 %li32, undef
 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %li32_0 = load i32, i32* undef
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %li32_1 = load i32, i32* undef
-; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %2 = sdiv i32 %li32_0, %li32_1
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %2 = sdiv nof i32 %li32_0, %li32_1
 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %li64 = load i64, i64* undef
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %3 = sdiv i64 %li64, undef
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %3 = sdiv nof i64 %li64, undef
 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %li64_0 = load i64, i64* undef
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %li64_1 = load i64, i64* undef
-; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %4 = sdiv i64 %li64_0, %li64_1
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %4 = sdiv nof i64 %li64_0, %li64_1
 }
 
 define void @udiv() {
   %li32 = load i32, i32* undef
-  udiv i32 %li32, undef
+  udiv nof i32 %li32, undef
 
   %li32_0 = load i32, i32* undef
   %li32_1 = load i32, i32* undef
-  udiv i32 %li32_0, %li32_1
+  udiv nof i32 %li32_0, %li32_1
 
   %li64 = load i64, i64* undef
-  udiv i64 %li64, undef
+  udiv nof i64 %li64, undef
 
   %li64_0 = load i64, i64* undef
   %li64_1 = load i64, i64* undef
-  udiv i64 %li64_0, %li64_1
+  udiv nof i64 %li64_0, %li64_1
 
   ret void;
 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %li32 = load i32, i32* undef
-; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %1 = udiv i32 %li32, undef
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %1 = udiv nof i32 %li32, undef
 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %li32_0 = load i32, i32* undef
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %li32_1 = load i32, i32* undef
-; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %2 = udiv i32 %li32_0, %li32_1
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %2 = udiv nof i32 %li32_0, %li32_1
 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %li64 = load i64, i64* undef
-; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %3 = udiv i64 %li64, undef
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %3 = udiv nof i64 %li64, undef
 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %li64_0 = load i64, i64* undef
 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %li64_1 = load i64, i64* undef
-; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %4 = udiv i64 %li64_0, %li64_1
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %4 = udiv nof i64 %li64_0, %li64_1
 }
 
 define void @and() {
   %li32 = load i32, i32* undef
   and i32 %li32, undef
 
   %li32_0 = load i32, i32* undef
   %li32_1 = load i32, i32* undef

test/Analysis/Lint/check-zero-divide.ll

 ; RUN: opt -lint -disable-output %s 2>&1 | FileCheck %s
 
 define <2 x i32> @use_vector_sdiv(<2 x i32> %a) nounwind {
-  %b = sdiv <2 x i32> %a, <i32 5, i32 8>
+  %b = sdiv nof <2 x i32> %a, <i32 5, i32 8>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @use_vector_srem(<2 x i32> %a) nounwind {
   %b = srem <2 x i32> %a, <i32 5, i32 8>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @use_vector_udiv(<2 x i32> %a) nounwind {
-  %b = udiv <2 x i32> %a, <i32 5, i32 8>
+  %b = udiv nof <2 x i32> %a, <i32 5, i32 8>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @use_vector_urem(<2 x i32> %a) nounwind {
   %b = urem <2 x i32> %a, <i32 5, i32 8>
   ret <2 x i32> %b
 }
 
 define i32 @use_sdiv_by_zero(i32 %a) nounwind {
 ; CHECK: Undefined behavior: Division by zero
-; CHECK-NEXT: %b = sdiv i32 %a, 0
-  %b = sdiv i32 %a, 0
+; CHECK-NEXT: %b = sdiv nof i32 %a, 0
+  %b = sdiv nof i32 %a, 0
   ret i32 %b
 }
 
 define i32 @use_sdiv_by_zeroinitializer(i32 %a) nounwind {
 ; CHECK: Undefined behavior: Division by zero
-; CHECK-NEXT: %b = sdiv i32 %a, 0
-  %b = sdiv i32 %a, zeroinitializer
+; CHECK-NEXT: %b = sdiv nof i32 %a, 0
+  %b = sdiv nof i32 %a, zeroinitializer
    ret i32 %b
 }
 
 define <2 x i32> @use_vector_sdiv_by_zero_x(<2 x i32> %a) nounwind {
 ; CHECK: Undefined behavior: Division by zero
-; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 0, i32 5>
-  %b = sdiv <2 x i32> %a, <i32 0, i32 5>
+; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, <i32 0, i32 5>
+  %b = sdiv nof <2 x i32> %a, <i32 0, i32 5>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @use_vector_sdiv_by_zero_y(<2 x i32> %a) nounwind {
 ; CHECK: Undefined behavior: Division by zero
-; CHECK-NEXT:  %b = sdiv <2 x i32> %a, <i32 4, i32 0>
-  %b = sdiv <2 x i32> %a, <i32 4, i32 0>
+; CHECK-NEXT:  %b = sdiv nof <2 x i32> %a, <i32 4, i32 0>
+  %b = sdiv nof <2 x i32> %a, <i32 4, i32 0>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @use_vector_sdiv_by_zero_xy(<2 x i32> %a) nounwind {
 ; CHECK: Undefined behavior: Division by zero
-; CHECK-NEXT: %b = sdiv <2 x i32> %a, zeroinitializer
-  %b = sdiv <2 x i32> %a, <i32 0, i32 0>
+; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, zeroinitializer
+  %b = sdiv nof <2 x i32> %a, <i32 0, i32 0>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @use_vector_sdiv_by_undef_x(<2 x i32> %a) nounwind {
 ; CHECK: Undefined behavior: Division by zero
-; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 undef, i32 5>
-  %b = sdiv <2 x i32> %a, <i32 undef, i32 5>
+; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, <i32 undef, i32 5>
+  %b = sdiv nof <2 x i32> %a, <i32 undef, i32 5>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @use_vector_sdiv_by_undef_y(<2 x i32> %a) nounwind {
 ; CHECK: Undefined behavior: Division by zero
-; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 5, i32 undef>
-  %b = sdiv <2 x i32> %a, <i32 5, i32 undef>
+; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, <i32 5, i32 undef>
+  %b = sdiv nof <2 x i32> %a, <i32 5, i32 undef>
   ret <2 x i32> %b
 }
 
 define <2 x i32> @use_vector_sdiv_by_undef_xy(<2 x i32> %a) nounwind {
 ; CHECK: Undefined behavior: Division by zero
-; CHECK-NEXT: %b = sdiv <2 x i32> %a, undef
-  %b = sdiv <2 x i32> %a, <i32 undef, i32 undef>
+; CHECK-NEXT: %b = sdiv nof <2 x i32> %a, undef
+  %b = sdiv nof <2 x i32> %a, <i32 undef, i32 undef>
   ret <2 x i32> %b
 }
 

test/Assembler/div_attrs.ll

+; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s
+
+define void @div_attrs(i8 %op1, i8 %op2) {
+  ; default
+  udiv i8 %op1, %op2
+  sdiv i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
+
+  ; nof
+  udiv nof i8 %op1, %op2
+  sdiv nof i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
+
+  ; mof
+  udiv mof i8 %op1, %op2
+  sdiv mof i8 %op1, %op2
+  ; CHECK: udiv mof i8 %op1, %op2
+  ; CHECK: sdiv mof i8 %op1, %op2
+
+  ; exact
+  udiv exact i8 %op1, %op2
+  sdiv exact i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
+
+  ; exact nof
+  udiv exact nof i8 %op1, %op2
+  sdiv exact nof i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
+
+  ; nof exact
+  udiv nof exact i8 %op1, %op2
+  sdiv nof exact i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
+
+  ; exact mof
+  udiv exact mof i8 %op1, %op2
+  sdiv exact mof i8 %op1, %op2
+  ; CHECK: udiv exact mof i8 %op1, %op2
+  ; CHECK: sdiv exact mof i8 %op1, %op2
+
+  ; mof exact
+  udiv mof exact i8 %op1, %op2
+  sdiv mof exact i8 %op1, %op2
+  ; CHECK: udiv exact mof i8 %op1, %op2
+  ; CHECK: sdiv exact mof i8 %op1, %op2
+
+  ret void
+}

test/Assembler/div_not_allowed.ll

+; XFAIL: *
+; This test should fail always nof/mof attributes cann't come together
+; RUN: llvm-as  %s -o - 2>&1 | FileCheck %s
+
+define void @div_attrs(i8 %op1, i8 %op2) {
+  ; default
+  udiv nof mof i8 %op1, %op2
+
+  ret void
+}

test/Assembler/flags.ll

 
 define i64 @shl_both(i64 %x, i64 %y) {
 ; CHECK: %z = shl nuw nsw i64 %x, %y
   %z = shl nuw nsw i64 %x, %y
   ret i64 %z
 }
 
 define i64 @sdiv_exact(i64 %x, i64 %y) {
-; CHECK: %z = sdiv exact i64 %x, %y
-  %z = sdiv exact i64 %x, %y
+; CHECK: %z = sdiv exact nof i64 %x, %y
+  %z = sdiv exact nof i64 %x, %y
   ret i64 %z
 }
 
 define i64 @sdiv_plain(i64 %x, i64 %y) {
-; CHECK: %z = sdiv i64 %x, %y
-  %z = sdiv i64 %x, %y
+; CHECK: %z = sdiv nof i64 %x, %y
+  %z = sdiv nof i64 %x, %y
   ret i64 %z
 }
 
 define i64 @udiv_exact(i64 %x, i64 %y) {
-; CHECK: %z = udiv exact i64 %x, %y
-  %z = udiv exact i64 %x, %y
+; CHECK: %z = udiv exact nof i64 %x, %y
+  %z = udiv exact nof i64 %x, %y
   ret i64 %z
 }
 
 define i64 @udiv_plain(i64 %x, i64 %y) {
-; CHECK: %z = udiv i64 %x, %y
-  %z = udiv i64 %x, %y
+; CHECK: %z = udiv nof i64 %x, %y
+  %z = udiv nof i64 %x, %y
   ret i64 %z
 }
 
 define i64 @ashr_plain(i64 %x, i64 %y) {
 ; CHECK: %z = ashr i64 %x, %y
   %z = ashr i64 %x, %y
   ret i64 %z
 }

 }
 
 define i64 @mul_both_ce() {
 ; CHECK: ret i64 mul nuw nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
   ret i64 mul nuw nsw (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @sdiv_exact_ce() {
-; CHECK: ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
-  ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 sdiv exact nof (i64 ptrtoint (i64* @addr to i64), i64 91)
+  ret i64 sdiv exact nof (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @udiv_exact_ce() {
-; CHECK: ret i64 udiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
-  ret i64 udiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 udiv exact nof (i64 ptrtoint (i64* @addr to i64), i64 91)
+  ret i64 udiv exact nof (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @ashr_exact_ce() {
 ; CHECK: ret i64 ashr exact (i64 ptrtoint (i64* @addr to i64), i64 9)
   ret i64 ashr exact (i64 ptrtoint (i64* @addr to i64), i64 9)
 }
 
 define i64 @lshr_exact_ce() {

 }
 
 define i64 @mul_plain_ce() {
 ; CHECK: ret i64 mul (i64 ptrtoint (i64* @addr to i64), i64 91)
   ret i64 mul (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @sdiv_plain_ce() {
-; CHECK: ret i64 sdiv (i64 ptrtoint (i64* @addr to i64), i64 91)
-  ret i64 sdiv (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 sdiv nof (i64 ptrtoint (i64* @addr to i64), i64 91)
+  ret i64 sdiv nof (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64* @gep_plain_ce() {
 ; CHECK: ret i64* getelementptr (i64, i64* @addr, i64 171)
         ret i64* getelementptr (i64, i64* @addr, i64 171)
 }
 
 define i64 @add_both_reversed_ce() {

test/Bitcode/binaryIntInstructions.3.2.ll

 ; CHECK: %res1 = mul i8 %x1, %x1
   %res1 = mul i8 %x1, %x1
 
   ret void
 }
 
 define void @udiv(i8 %x1){
 entry:
-; CHECK: %res1 = udiv i8 %x1, %x1
+; CHECK: %res1 = udiv nof i8 %x1, %x1
   %res1 = udiv i8 %x1, %x1
 
-; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1
+; CHECK-NEXT: %res2 = udiv exact nof i8 %x1, %x1
   %res2 = udiv exact i8 %x1, %x1
 
   ret void
 }
 
 define void @sdiv(i8 %x1){
 entry:
-; CHECK: %res1 = sdiv i8 %x1, %x1
+; CHECK: %res1 = sdiv nof i8 %x1, %x1
   %res1 = sdiv i8 %x1, %x1
 
-; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1
+; CHECK-NEXT: %res2 = sdiv exact nof i8 %x1, %x1
   %res2 = sdiv exact i8 %x1, %x1
 
   ret void
 }
 
 define void @urem(i32 %x1){
 entry:
 ; CHECK: %res1 = urem i32 %x1, %x1

test/Bitcode/compatibility-3.6.ll

define void @instructions.binops(i8 %op1, i8 %op2) {
   ; CHECK: mul nuw i8 %op1, %op2
   mul nsw i8 %op1, %op2
   ; CHECK: mul nsw i8 %op1, %op2
   mul nuw nsw i8 %op1, %op2
   ; CHECK: mul nuw nsw i8 %op1, %op2
 
   ; exact
   udiv i8 %op1, %op2
-  ; CHECK: udiv i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
   udiv exact i8 %op1, %op2
-  ; CHECK: udiv exact i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
   sdiv i8 %op1, %op2
-  ; CHECK: sdiv i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
   sdiv exact i8 %op1, %op2
-  ; CHECK: sdiv exact i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
 
   ; none
   urem i8 %op1, %op2
   ; CHECK: urem i8 %op1, %op2
   srem i8 %op1, %op2
   ; CHECK: srem i8 %op1, %op2
 
   ret void

test/Bitcode/compatibility-3.7.ll

define void @instructions.binops(i8 %op1, i8 %op2) {
   ; CHECK: mul nuw i8 %op1, %op2
   mul nsw i8 %op1, %op2
   ; CHECK: mul nsw i8 %op1, %op2
   mul nuw nsw i8 %op1, %op2
   ; CHECK: mul nuw nsw i8 %op1, %op2
 
   ; exact
   udiv i8 %op1, %op2
-  ; CHECK: udiv i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
   udiv exact i8 %op1, %op2
-  ; CHECK: udiv exact i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
   sdiv i8 %op1, %op2
-  ; CHECK: sdiv i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
   sdiv exact i8 %op1, %op2
-  ; CHECK: sdiv exact i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
 
   ; none
   urem i8 %op1, %op2
   ; CHECK: urem i8 %op1, %op2
   srem i8 %op1, %op2
   ; CHECK: srem i8 %op1, %op2
 
   ret void

test/Bitcode/compatibility-3.8.ll

define void @instructions.binops(i8 %op1, i8 %op2) {
   ; CHECK: mul nuw i8 %op1, %op2
   mul nsw i8 %op1, %op2
   ; CHECK: mul nsw i8 %op1, %op2
   mul nuw nsw i8 %op1, %op2
   ; CHECK: mul nuw nsw i8 %op1, %op2
 
   ; exact
   udiv i8 %op1, %op2
-  ; CHECK: udiv i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
   udiv exact i8 %op1, %op2
-  ; CHECK: udiv exact i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
   sdiv i8 %op1, %op2
-  ; CHECK: sdiv i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
   sdiv exact i8 %op1, %op2
-  ; CHECK: sdiv exact i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
 
   ; none
   urem i8 %op1, %op2
   ; CHECK: urem i8 %op1, %op2
   srem i8 %op1, %op2
   ; CHECK: srem i8 %op1, %op2
 
   ret void

test/Bitcode/compatibility-3.9.ll

define void @instructions.binops(i8 %op1, i8 %op2) {
   ; CHECK: mul nuw i8 %op1, %op2
   mul nsw i8 %op1, %op2
   ; CHECK: mul nsw i8 %op1, %op2
   mul nuw nsw i8 %op1, %op2
   ; CHECK: mul nuw nsw i8 %op1, %op2
 
   ; exact
   udiv i8 %op1, %op2
-  ; CHECK: udiv i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
   udiv exact i8 %op1, %op2
-  ; CHECK: udiv exact i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
   sdiv i8 %op1, %op2
-  ; CHECK: sdiv i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
   sdiv exact i8 %op1, %op2
-  ; CHECK: sdiv exact i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
 
   ; none
   urem i8 %op1, %op2
   ; CHECK: urem i8 %op1, %op2
   srem i8 %op1, %op2
   ; CHECK: srem i8 %op1, %op2
 
   ret void

test/Bitcode/compatibility-4.0.ll

define void @instructions.binops(i8 %op1, i8 %op2) {
   ; CHECK: mul nuw i8 %op1, %op2
   mul nsw i8 %op1, %op2
   ; CHECK: mul nsw i8 %op1, %op2
   mul nuw nsw i8 %op1, %op2
   ; CHECK: mul nuw nsw i8 %op1, %op2
 
   ; exact
   udiv i8 %op1, %op2
-  ; CHECK: udiv i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
   udiv exact i8 %op1, %op2
-  ; CHECK: udiv exact i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
   sdiv i8 %op1, %op2
-  ; CHECK: sdiv i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
   sdiv exact i8 %op1, %op2
-  ; CHECK: sdiv exact i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
 
   ; none
   urem i8 %op1, %op2
   ; CHECK: urem i8 %op1, %op2
   srem i8 %op1, %op2
   ; CHECK: srem i8 %op1, %op2
 
   ret void

test/Bitcode/compatibility-5.0.ll

define void @instructions.binops(i8 %op1, i8 %op2) {
   ; CHECK: mul nuw i8 %op1, %op2
   mul nsw i8 %op1, %op2
   ; CHECK: mul nsw i8 %op1, %op2
   mul nuw nsw i8 %op1, %op2
   ; CHECK: mul nuw nsw i8 %op1, %op2
 
   ; exact
   udiv i8 %op1, %op2
-  ; CHECK: udiv i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
   udiv exact i8 %op1, %op2
-  ; CHECK: udiv exact i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
   sdiv i8 %op1, %op2
-  ; CHECK: sdiv i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
   sdiv exact i8 %op1, %op2
-  ; CHECK: sdiv exact i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
 
   ; none
   urem i8 %op1, %op2
   ; CHECK: urem i8 %op1, %op2
   srem i8 %op1, %op2
   ; CHECK: srem i8 %op1, %op2
 
   ret void

test/Bitcode/compatibility.ll

define void @instructions.binops(i8 %op1, i8 %op2) {
   ; CHECK: mul nuw i8 %op1, %op2
   mul nsw i8 %op1, %op2
   ; CHECK: mul nsw i8 %op1, %op2
   mul nuw nsw i8 %op1, %op2
   ; CHECK: mul nuw nsw i8 %op1, %op2
 
   ; exact
   udiv i8 %op1, %op2
-  ; CHECK: udiv i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
   udiv exact i8 %op1, %op2
-  ; CHECK: udiv exact i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
   sdiv i8 %op1, %op2
-  ; CHECK: sdiv i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
   sdiv exact i8 %op1, %op2
-  ; CHECK: sdiv exact i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
+
+  ; nof
+  udiv nof i8 %op1, %op2
+  ; CHECK: udiv nof i8 %op1, %op2
+  udiv exact nof i8 %op1, %op2
+  ; CHECK: udiv exact nof i8 %op1, %op2
+  sdiv nof i8 %op1, %op2
+  ; CHECK: sdiv nof i8 %op1, %op2
+  sdiv exact nof i8 %op1, %op2
+  ; CHECK: sdiv exact nof i8 %op1, %op2
 
   ; none
   urem i8 %op1, %op2
   ; CHECK: urem i8 %op1, %op2
   srem i8 %op1, %op2
   ; CHECK: srem i8 %op1, %op2
 
   ret void

test/CodeGen/ARM/vector-promotion.ll

 }
 
 ; Check that we promote we a splat constant when this is a division.
 ; The NORMAL mode does not promote anything as divisions are not legal.
 ; IR-BOTH-LABEL: @udivCase
 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; Scalar version:
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
-; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7
+; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv nof i32 [[EXTRACT]], 7
 ; Vector version:
-; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = udiv <2 x i32> [[LOAD]], <i32 7, i32 7>
+; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = udiv nof <2 x i32> [[LOAD]], <i32 7, i32 7>
 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1
 ;
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret
 define void @udivCase(<2 x i32>* %addr1, i32* %dest) {
   %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
-  %out = udiv i32 %extract, 7
+  %out = udiv nof i32 %extract, 7
   store i32 %out, i32* %dest, align 4
   ret void
 }
 
 ; IR-BOTH-LABEL: @uremCase
 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; Scalar version:
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
define void @uremCase(<2 x i32>* %addr1, i32* %dest) {
   store i32 %out, i32* %dest, align 4
   ret void
 }
 
 ; IR-BOTH-LABEL: @sdivCase
 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; Scalar version:
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
-; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7
+; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv nof i32 [[EXTRACT]], 7
 ; Vector version:
-; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = sdiv <2 x i32> [[LOAD]], <i32 7, i32 7>
+; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = sdiv nof <2 x i32> [[LOAD]], <i32 7, i32 7>
 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1
 ;
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret 
 define void @sdivCase(<2 x i32>* %addr1, i32* %dest) {
   %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
-  %out = sdiv i32 %extract, 7
+  %out = sdiv nof i32 %extract, 7
   store i32 %out, i32* %dest, align 4
   ret void
 }
 
 ; IR-BOTH-LABEL: @sremCase
 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; Scalar version:
 ; IR-NORMAL-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
define void @fremCase(<2 x float>* %addr1, float* %dest) {
   ret void
 }
 
 ; Check that we do not promote when we may introduce undefined behavior
 ; like division by zero.
 ; IR-BOTH-LABEL: @undefDivCase
 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 1
-; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 7, [[EXTRACT]]
+; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv nof i32 7, [[EXTRACT]]
 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
 ; IR-BOTH-NEXT: ret
 define void @undefDivCase(<2 x i32>* %addr1, i32* %dest) {
   %in1 = load <2 x i32>, <2 x i32>* %addr1, align 8
   %extract = extractelement <2 x i32> %in1, i32 1
-  %out = udiv i32 7, %extract
+  %out = udiv nof i32 7, %extract
   store i32 %out, i32* %dest, align 4
   ret void
 }
 
 
 ; Check that we do not promote when we may introduce undefined behavior
 ; like division by zero.
 ; IR-BOTH-LABEL: @undefRemCase

test/CodeGen/X86/O0-pipeline.ll

 ; CHECK-NEXT:       Dominator Tree Construction
 ; CHECK-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; CHECK-NEXT:       Module Verifier
 ; CHECK-NEXT:       Lower Garbage Collection Instructions
 ; CHECK-NEXT:       Shadow Stack GC Lowering
 ; CHECK-NEXT:       Remove unreachable blocks from the CFG
 ; CHECK-NEXT:       Instrument function entry/exit with calls to e.g. mcount() (post inlining)
 ; CHECK-NEXT:       Scalarize Masked Memory Intrinsics
+; CHECK-NEXT:       Scalarize May Overflow Div
 ; CHECK-NEXT:       Expand reduction intrinsics
 ; CHECK-NEXT:       Expand indirectbr instructions
 ; CHECK-NEXT:     Rewrite Symbols
 ; CHECK-NEXT:     FunctionPass Manager
 ; CHECK-NEXT:       Dominator Tree Construction
 ; CHECK-NEXT:       Exception handling preparation
 ; CHECK-NEXT:       Safe Stack instrumentation pass
 ; CHECK-NEXT:       Insert stack protectors

test/Instrumentation/DataFlowSanitizer/arith.ll

define i8 @mul(i8 %a, i8 %b) {
   ret i8 %c
 }
 
 define i8 @sdiv(i8 %a, i8 %b) {
   ; CHECK: @"dfs$sdiv"
   ; CHECK: load{{.*}}__dfsan_arg_tls
   ; CHECK: load{{.*}}__dfsan_arg_tls
   ; CHECK: call{{.*}}__dfsan_union
-  ; CHECK: sdiv i8
+  ; CHECK: sdiv nof i8
   ; CHECK: store{{.*}}__dfsan_retval_tls
   ; CHECK: ret i8
-  %c = sdiv i8 %a, %b
+  %c = sdiv nof i8 %a, %b
   ret i8 %c
 }
 
 define i8 @udiv(i8 %a, i8 %b) {
   ; CHECK: @"dfs$udiv"
   ; CHECK: load{{.*}}__dfsan_arg_tls
   ; CHECK: load{{.*}}__dfsan_arg_tls
   ; CHECK: call{{.*}}__dfsan_union
-  ; CHECK: udiv i8
+  ; CHECK: udiv nof i8
   ; CHECK: store{{.*}}__dfsan_retval_tls
   ; CHECK: ret i8
-  %c = udiv i8 %a, %b
+  %c = udiv nof i8 %a, %b
   ret i8 %c
 }

test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-constant-numerator.ll

 ; RUN: opt -S -codegenprepare < %s | FileCheck %s
 
 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
 target triple = "nvptx64-nvidia-cuda"
 
 ; When we bypass slow div with a constant numerator which fits into the bypass
 ; width, we still emit the bypass code, but we don't 'or' the numerator with
 ; the denominator.
 ; CHECK-LABEL: @small_constant_numer
 define i64 @small_constant_numer(i64 %a) {
   ; CHECK: [[AND:%[0-9]+]] = and i64 %a, -4294967296
   ; CHECK: icmp eq i64 [[AND]], 0
 
   ; CHECK: [[TRUNC:%[0-9]+]] = trunc i64 %a to i32
-  ; CHECK: udiv i32 -1, [[TRUNC]]
-  %d = sdiv i64 4294967295, %a  ; 0xffff'ffff
+  ; CHECK: udiv nof i32 -1, [[TRUNC]]
+  %d = sdiv nof i64 4294967295, %a  ; 0xffff'ffff
   ret i64 %d
 }
 
 ; When we try to bypass slow div with a constant numerator which *doesn't* fit
 ; into the bypass width, leave it as a plain 64-bit div with no bypass.
 ; CHECK-LABEL: @large_constant_numer
 define i64 @large_constant_numer(i64 %a) {
-  ; CHECK-NOT: udiv i32
-  %d = sdiv i64 4294967296, %a  ; 0x1'0000'0000
+  ; CHECK-NOT: udiv nof i32
+  %d = sdiv nof i64 4294967296, %a  ; 0x1'0000'0000
   ret i64 %d
 }
 
 ; For good measure, try a value larger than 2^32.
 ; CHECK-LABEL: @larger_constant_numer
 define i64 @larger_constant_numer(i64 %a) {
-  ; CHECK-NOT: udiv i32
-  %d = sdiv i64 5000000000, %a
+  ; CHECK-NOT: udiv nof i32
+  %d = sdiv nof i64 5000000000, %a
   ret i64 %d
 }

test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-not-exact.ll

 ; RUN: opt -S -codegenprepare < %s | FileCheck %s
 
 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
 target triple = "nvptx64-nvidia-cuda"
 
 ; Check that the smaller-width division that the BypassSlowDivision pass
 ; creates is not marked as "exact" (that is, it doesn't claim that the
 ; numerator is a multiple of the denominator).
 ;
 ; CHECK-LABEL: @test
 define void @test(i64 %a, i64 %b, i64* %retptr) {
-  ; CHECK: udiv i32
-  %d = sdiv i64 %a, %b
+  ; CHECK: udiv nof i32
+  %d = sdiv nof i64 %a, %b
   store i64 %d, i64* %retptr
   ret void
 }

test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div-special-cases.ll

 define void @Test_check_one_operand(i64 %a, i32 %b, i64* %retptr) {
 ; CHECK-LABEL: @Test_check_one_operand(
 ; CHECK-NEXT:    [[B_1:%.*]] = zext i32 [[B:%.*]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[A:%.*]], -4294967296
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP8:%.*]]
 ; CHECK:         [[TMP4:%.*]] = trunc i64 [[B_1]] to i32
 ; CHECK-NEXT:    [[TMP5:%.*]] = trunc i64 [[A]] to i32
-; CHECK-NEXT:    [[TMP6:%.*]] = udiv i32 [[TMP5]], [[TMP4]]
+; CHECK-NEXT:    [[TMP6:%.*]] = udiv nof i32 [[TMP5]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
 ; CHECK-NEXT:    br label [[TMP10:%.*]]
-; CHECK:         [[TMP9:%.*]] = sdiv i64 [[A]], [[B_1]]
+; CHECK:         [[TMP9:%.*]] = sdiv nof i64 [[A]], [[B_1]]
 ; CHECK-NEXT:    br label [[TMP10]]
 ; CHECK:         [[TMP11:%.*]] = phi i64 [ [[TMP7]], [[TMP3]] ], [ [[TMP9]], [[TMP8]] ]
 ; CHECK-NEXT:    store i64 [[TMP11]], i64* [[RETPTR:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %b.1 = zext i32 %b to i64
-  %res = sdiv i64 %a, %b.1
+  %res = sdiv nof i64 %a, %b.1
   store i64 %res, i64* %retptr
   ret void
 }
 
 ; If both operands are known to fit into 32 bits, then replace the division
 ; in-place without CFG modification.
 define void @Test_check_none(i64 %a, i32 %b, i64* %retptr) {
 ; CHECK-LABEL: @Test_check_none(
 ; CHECK-NEXT:    [[A_1:%.*]] = and i64 [[A:%.*]], 4294967295
 ; CHECK-NEXT:    [[B_1:%.*]] = zext i32 [[B:%.*]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[A_1]] to i32
 ; CHECK-NEXT:    [[TMP2:%.*]] = trunc i64 [[B_1]] to i32
-; CHECK-NEXT:    [[TMP3:%.*]] = udiv i32 [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP3:%.*]] = udiv nof i32 [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
 ; CHECK-NEXT:    store i64 [[TMP4]], i64* [[RETPTR:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %a.1 = and i64 %a, 4294967295
   %b.1 = zext i32 %b to i64
-  %res = udiv i64 %a.1, %b.1
+  %res = udiv nof i64 %a.1, %b.1
   store i64 %res, i64* %retptr
   ret void
 }
 
 ; In case of unsigned long division with a short dividend,
 ; the long division is not needed any more.
 define void @Test_special_case(i32 %a, i64 %b, i64* %retptr) {
 ; CHECK-LABEL: @Test_special_case(
 ; CHECK-NEXT:    [[A_1:%.*]] = zext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp uge i64 [[A_1]], [[B:%.*]]
 ; CHECK-NEXT:    br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP9:%.*]]
 ; CHECK:         [[TMP3:%.*]] = trunc i64 [[B]] to i32
 ; CHECK-NEXT:    [[TMP4:%.*]] = trunc i64 [[A_1]] to i32
-; CHECK-NEXT:    [[TMP5:%.*]] = udiv i32 [[TMP4]], [[TMP3]]
+; CHECK-NEXT:    [[TMP5:%.*]] = udiv nof i32 [[TMP4]], [[TMP3]]
 ; CHECK-NEXT:    [[TMP6:%.*]] = urem i32 [[TMP4]], [[TMP3]]
 ; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP5]] to i64
 ; CHECK-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP6]] to i64
 ; CHECK-NEXT:    br label [[TMP9]]
 ; CHECK:         [[TMP10:%.*]] = phi i64 [ [[TMP7]], [[TMP2]] ], [ 0, [[TMP0:%.*]] ]
 ; CHECK-NEXT:    [[TMP11:%.*]] = phi i64 [ [[TMP8]], [[TMP2]] ], [ [[A_1]], [[TMP0]] ]
 ; CHECK-NEXT:    [[RES:%.*]] = add i64 [[TMP10]], [[TMP11]]
 ; CHECK-NEXT:    store i64 [[RES]], i64* [[RETPTR:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %a.1 = zext i32 %a to i64
-  %div = udiv i64 %a.1, %b
+  %div = udiv nof i64 %a.1, %b
   %rem = urem i64 %a.1, %b
   %res = add i64 %div, %rem
   store i64 %res, i64* %retptr
   ret void
 }
 
 
 ; Do not bypass a division if one of the operands looks like a hash value.
 define void @Test_dont_bypass_xor(i64 %a, i64 %b, i64 %l, i64* %retptr) {
 ; CHECK-LABEL: @Test_dont_bypass_xor(
 ; CHECK-NEXT:    [[C:%.*]] = xor i64 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[RES:%.*]] = udiv i64 [[C]], [[L:%.*]]
+; CHECK-NEXT:    [[RES:%.*]] = udiv nof i64 [[C]], [[L:%.*]]
 ; CHECK-NEXT:    store i64 [[RES]], i64* [[RETPTR:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %c = xor i64 %a, %b
-  %res = udiv i64 %c, %l
+  %res = udiv nof i64 %c, %l
   store i64 %res, i64* %retptr
   ret void
 }
 
 define void @Test_dont_bypass_phi_xor(i64 %a, i64 %b, i64 %l, i64* %retptr) {
 ; CHECK-LABEL: @Test_dont_bypass_phi_xor(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i64 [[B:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[MERGE:%.*]], label [[XORPATH:%.*]]
 ; CHECK:       xorpath:
 ; CHECK-NEXT:    [[C:%.*]] = xor i64 [[A:%.*]], [[B]]
 ; CHECK-NEXT:    br label [[MERGE]]
 ; CHECK:       merge:
 ; CHECK-NEXT:    [[E:%.*]] = phi i64 [ undef, [[ENTRY:%.*]] ], [ [[C]], [[XORPATH]] ]
-; CHECK-NEXT:    [[RES:%.*]] = sdiv i64 [[E]], [[L:%.*]]
+; CHECK-NEXT:    [[RES:%.*]] = sdiv nof i64 [[E]], [[L:%.*]]
 ; CHECK-NEXT:    store i64 [[RES]], i64* [[RETPTR:%.*]]
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %cmp = icmp eq i64 %b, 0
   br i1 %cmp, label %merge, label %xorpath
 
 xorpath:
   %c = xor i64 %a, %b
   br label %merge
 
 merge:
   %e = phi i64 [ undef, %entry ], [ %c, %xorpath ]
-  %res = sdiv i64 %e, %l
+  %res = sdiv nof i64 %e, %l
   store i64 %res, i64* %retptr
   ret void
 }
 
 define void @Test_dont_bypass_mul_long_const(i64 %a, i64 %l, i64* %retptr) {
 ; CHECK-LABEL: @Test_dont_bypass_mul_long_const(
 ; CHECK-NEXT:    [[C:%.*]] = mul i64 [[A:%.*]], 5229553307
 ; CHECK-NEXT:    [[RES:%.*]] = urem i64 [[C]], [[L:%.*]]

 ; CHECK:       merge:
 ; CHECK-NEXT:    [[LHS:%.*]] = phi i64 [ 42, [[BRANCH]] ], [ [[A_MUL]], [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    [[TMP0:%.*]] = or i64 [[LHS]], [[B]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], -4294967296
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP8:%.*]]
 ; CHECK:         [[TMP4:%.*]] = trunc i64 [[B]] to i32
 ; CHECK-NEXT:    [[TMP5:%.*]] = trunc i64 [[LHS]] to i32
-; CHECK-NEXT:    [[TMP6:%.*]] = udiv i32 [[TMP5]], [[TMP4]]
+; CHECK-NEXT:    [[TMP6:%.*]] = udiv nof i32 [[TMP5]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
 ; CHECK-NEXT:    br label [[TMP10:%.*]]
-; CHECK:         [[TMP9:%.*]] = sdiv i64 [[LHS]], [[B]]
+; CHECK:         [[TMP9:%.*]] = sdiv nof i64 [[LHS]], [[B]]
 ; CHECK-NEXT:    br label [[TMP10]]
 ; CHECK:         [[TMP11:%.*]] = phi i64 [ [[TMP7]], [[TMP3]] ], [ [[TMP9]], [[TMP8]] ]
 ; CHECK-NEXT:    store i64 [[TMP11]], i64* [[RETPTR:%.*]]
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %a.mul = mul nsw i64 %a, 34806414968801
   %p = icmp sgt i64 %a, %b
   br i1 %p, label %branch, label %merge
 
 branch:
   br label %merge
 
 merge:
   %lhs = phi i64 [ 42, %branch ], [ %a.mul, %entry ]
-  %res = sdiv i64 %lhs, %b
+  %res = sdiv nof i64 %lhs, %b
   store i64 %res, i64* %retptr
   ret void
 }
 
 define void @Test_bypass_mul_short_const(i64 %a, i64 %l, i64* %retptr) {
 ; CHECK-LABEL: @Test_bypass_mul_short_const(
 ; CHECK-NEXT:    [[C:%.*]] = mul i64 [[A:%.*]], -42
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i64 [[C]], [[L:%.*]]

test/Transforms/CodeGenPrepare/NVPTX/bypass-slow-div.ll

 ; RUN: opt -S -codegenprepare < %s | FileCheck %s
 
 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
 target triple = "nvptx64-nvidia-cuda"
 
 ; We only use the div instruction -- the rem should be DCE'ed.
 ; CHECK-LABEL: @div_only
 define void @div_only(i64 %a, i64 %b, i64* %retptr) {
-  ; CHECK: udiv i32
+  ; CHECK: udiv nof i32
   ; CHECK-NOT: urem
-  ; CHECK: sdiv i64
+  ; CHECK: sdiv nof i64
   ; CHECK-NOT: rem
-  %d = sdiv i64 %a, %b
+  %d = sdiv nof i64 %a, %b
   store i64 %d, i64* %retptr
   ret void
 }
 
 ; We only use the rem instruction -- the div should be DCE'ed.
 ; CHECK-LABEL: @rem_only
 define void @rem_only(i64 %a, i64 %b, i64* %retptr) {
   ; CHECK-NOT: div
   ; CHECK: urem i32
   ; CHECK-NOT: div
   ; CHECK: rem i64
   ; CHECK-NOT: div
   %d = srem i64 %a, %b
   store i64 %d, i64* %retptr
   ret void
 }
 
 ; CHECK-LABEL: @udiv_by_constant(
 define i64 @udiv_by_constant(i32 %a) {
 ; CHECK-NEXT:    [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[A_ZEXT]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = udiv i32 [[TMP1]], 50
+; CHECK-NEXT:    [[TMP2:%.*]] = udiv nof i32 [[TMP1]], 50
 ; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
 ; CHECK-NEXT:    ret i64 [[TMP3]]
 
   %a.zext = zext i32 %a to i64
-  %wide.div = udiv i64 %a.zext, 50
+  %wide.div = udiv nof i64 %a.zext, 50
   ret i64 %wide.div
 }
 
 ; CHECK-LABEL: @urem_by_constant(
 define i64 @urem_by_constant(i32 %a) {
 ; CHECK-NEXT:    [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[A_ZEXT]] to i32
 ; CHECK-NEXT:    [[TMP2:%.*]] = urem i32 [[TMP1]], 50
 ; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
 ; CHECK-NEXT:    ret i64 [[TMP3]]
 
   %a.zext = zext i32 %a to i64
   %wide.div = urem i64 %a.zext, 50
   ret i64 %wide.div
 }
 
 ; Negative test: instead of emitting a runtime check on %a, we prefer to let the
 ; DAGCombiner transform this division by constant into a multiplication (with a
 ; "magic constant").
 ;
 ; CHECK-LABEL: @udiv_by_constant_negative_0(
 define i64 @udiv_by_constant_negative_0(i64 %a) {
-; CHECK-NEXT:    [[WIDE_DIV:%.*]] = udiv i64 [[A:%.*]], 50
+; CHECK-NEXT:    [[WIDE_DIV:%.*]] = udiv nof i64 [[A:%.*]], 50
 ; CHECK-NEXT:    ret i64 [[WIDE_DIV]]
 
-  %wide.div = udiv i64 %a, 50
+  %wide.div = udiv nof i64 %a, 50
   ret i64 %wide.div
 }
 
 ; Negative test: while we know the dividend is short, the divisor isn't.  This
 ; test is here for completeness, but instcombine will optimize this to return 0.
 ;
 ; CHECK-LABEL: @udiv_by_constant_negative_1(
 define i64 @udiv_by_constant_negative_1(i32 %a) {
 ; CHECK-NEXT:    [[A_ZEXT:%.*]] = zext i32 [[A:%.*]] to i64
-; CHECK-NEXT:    [[WIDE_DIV:%.*]] = udiv i64 [[A_ZEXT]], 8589934592
+; CHECK-NEXT:    [[WIDE_DIV:%.*]] = udiv nof i64 [[A_ZEXT]], 8589934592
 ; CHECK-NEXT:    ret i64 [[WIDE_DIV]]
 
   %a.zext = zext i32 %a to i64
-  %wide.div = udiv i64 %a.zext, 8589934592 ;; == 1 << 33
+  %wide.div = udiv nof i64 %a.zext, 8589934592 ;; == 1 << 33
   ret i64 %wide.div
 }
 
 ; URem version of udiv_by_constant_negative_0
 ;
 ; CHECK-LABEL: @urem_by_constant_negative_0(
 define i64 @urem_by_constant_negative_0(i64 %a) {
 ; CHECK-NEXT:    [[WIDE_DIV:%.*]] = urem i64 [[A:%.*]], 50

test/Transforms/CodeGenPrepare/X86/select.ll

;
   %call2 = call i64* @baz(i32 1, i32 2, i32 3)
   %tobool = icmp ne i32 %in, 0
   %sel = select i1 %tobool, i64* %call1, i64* %call2
   ret i64* %sel
 }
 
 define i32 @sdiv_no_sink(i32 %a, i32 %b) {
 ; CHECK-LABEL: @sdiv_no_sink(
-; CHECK-NEXT:    [[DIV1:%.*]] = sdiv i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[DIV2:%.*]] = sdiv i32 [[B]], [[A]]
+; CHECK-NEXT:    [[DIV1:%.*]] = sdiv nof i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[DIV2:%.*]] = sdiv nof i32 [[B]], [[A]]
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[A]], 5
 ; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[DIV1]], i32 [[DIV2]]
 ; CHECK-NEXT:    ret i32 [[SEL]]
 ;
-  %div1 = sdiv i32 %a, %b
-  %div2 = sdiv i32 %b, %a
+  %div1 = sdiv nof i32 %a, %b
+  %div2 = sdiv nof i32 %b, %a
   %cmp = icmp sgt i32 %a, 5
   %sel = select i1 %cmp, i32 %div1, i32 %div2
   ret i32 %sel
 }
 

test/Transforms/ConstantHoisting/ARM/bad-cases.ll

 default:
   ret void
 }
 
 ; We don't want to convert constant divides because the benefit from converting
 ; them to a mul in the backend is larget than constant materialization savings.
 define void @signed_const_division(i32 %in1, i32 %in2, i32* %addr) {
 ; CHECK-LABEL: @signed_const_division
-; CHECK: %res1 = sdiv i32 %l1, 1000000000
+; CHECK: %res1 = sdiv nof i32 %l1, 1000000000
 ; CHECK: %res2 = srem i32 %l2, 1000000000
 entry:
   br label %loop
 
 loop:
   %l1 = phi i32 [%res1, %loop], [%in1, %entry]
   %l2 = phi i32 [%res2, %loop], [%in2, %entry]
-  %res1 = sdiv i32 %l1, 1000000000
+  %res1 = sdiv nof i32 %l1, 1000000000
   store volatile i32 %res1, i32* %addr
   %res2 = srem i32 %l2, 1000000000
   store volatile i32 %res2, i32* %addr
   %again = icmp eq i32 %res1, %res2
   br i1 %again, label %loop, label %end
 
 end:
   ret void
 }
 
 define void @unsigned_const_division(i32 %in1, i32 %in2, i32* %addr) {
 ; CHECK-LABEL: @unsigned_const_division
-; CHECK: %res1 = udiv i32 %l1, 1000000000
+; CHECK: %res1 = udiv nof i32 %l1, 1000000000
 ; CHECK: %res2 = urem i32 %l2, 1000000000
 
 entry:
   br label %loop
 
 loop:
   %l1 = phi i32 [%res1, %loop], [%in1, %entry]
   %l2 = phi i32 [%res2, %loop], [%in2, %entry]
-  %res1 = udiv i32 %l1, 1000000000
+  %res1 = udiv nof i32 %l1, 1000000000
   store volatile i32 %res1, i32* %addr
   %res2 = urem i32 %l2, 1000000000
   store volatile i32 %res2, i32* %addr
   %again = icmp eq i32 %res1, %res2
   br i1 %again, label %loop, label %end
 
 end:
   ret void

test/Transforms/CorrelatedValuePropagation/sdiv.ll

 ; RUN: opt < %s -correlated-propagation -S | FileCheck %s
 
 ; CHECK-LABEL: @test0(
 define void @test0(i32 %n) {
 entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.body, %entry
   %j.0 = phi i32 [ %n, %entry ], [ %div, %for.body ]
   %cmp = icmp sgt i32 %j.0, 1
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-; CHECK: %div1 = udiv i32 %j.0, 2
-  %div = sdiv i32 %j.0, 2
+; CHECK: %div1 = udiv nof i32 %j.0, 2
+  %div = sdiv nof i32 %j.0, 2
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
   ret void
 }
 
 ; CHECK-LABEL: @test1(
 define void @test1(i32 %n) {
 entry:
   br label %for.cond
 
 for.cond:                                         ; preds = %for.body, %entry
   %j.0 = phi i32 [ %n, %entry ], [ %div, %for.body ]
   %cmp = icmp sgt i32 %j.0, -2
   br i1 %cmp, label %for.body, label %for.end
 
 for.body:                                         ; preds = %for.cond
-; CHECK: %div = sdiv i32 %j.0, 2
-  %div = sdiv i32 %j.0, 2
+; CHECK: %div = sdiv nof i32 %j.0, 2
+  %div = sdiv nof i32 %j.0, 2
   br label %for.cond
 
 for.end:                                          ; preds = %for.cond
   ret void
 }
 
 ; CHECK-LABEL: @test2(
 define void @test2(i32 %n) {
 entry:
   %cmp = icmp sgt i32 %n, 1
   br i1 %cmp, label %bb, label %exit
 
 bb:
-; CHECK: %div1 = udiv i32 %n, 2 
-  %div = sdiv i32 %n, 2
+; CHECK: %div1 = udiv nof i32 %n, 2 
+  %div = sdiv nof i32 %n, 2
   br label %exit
 
 exit:
   ret void
 }
 
 ; looping case where loop has exactly one block
 ; at the point of sdiv, we know that %a is always greater than 0,
 ; because of the guard before it, so we can transform it to udiv.
 declare void @llvm.experimental.guard(i1,...)
 ; CHECK-LABEL: @test4
 define void @test4(i32 %n) {
 entry:
   %cmp = icmp sgt i32 %n, 0
   br i1 %cmp, label %loop, label %exit
 
 loop:
-; CHECK: udiv i32 %a, 6
+; CHECK: udiv nof i32 %a, 6
   %a = phi i32 [ %n, %entry ], [ %div, %loop ]
   %cond = icmp sgt i32 %a, 4
   call void(i1,...) @llvm.experimental.guard(i1 %cond) [ "deopt"() ]
-  %div = sdiv i32 %a, 6
+  %div = sdiv nof i32 %a, 6
   br i1 %cond, label %loop, label %exit
 
 exit:
   ret void
 }
 
 ; same test as above with assume instead of guard.
 declare void @llvm.assume(i1)
 ; CHECK-LABEL: @test5
 define void @test5(i32 %n) {
 entry:
   %cmp = icmp sgt i32 %n, 0
   br i1 %cmp, label %loop, label %exit
 
 loop:
-; CHECK: udiv i32 %a, 6
+; CHECK: udiv nof i32 %a, 6
   %a = phi i32 [ %n, %entry ], [ %div, %loop ]
   %cond = icmp sgt i32 %a, 4
   call void @llvm.assume(i1 %cond)
-  %div = sdiv i32 %a, 6
+  %div = sdiv nof i32 %a, 6
   %loopcond = icmp sgt i32 %div, 8
   br i1 %loopcond, label %loop, label %exit
 
 exit:
   ret void
 }

test/Transforms/DivRemPairs/PowerPC/div-rem-pairs.ll

 ; RUN: opt < %s -div-rem-pairs -S -mtriple=powerpc64-unknown-unknown | FileCheck %s
 
 declare void @foo(i32, i32)
 
 define void @decompose_illegal_srem_same_block(i32 %a, i32 %b) {
 ; CHECK-LABEL: @decompose_illegal_srem_same_block(
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, %b
 ; CHECK-NEXT:    [[TMP1:%.*]] = mul i32 [[DIV]], %b
 ; CHECK-NEXT:    [[TMP2:%.*]] = sub i32 %a, [[TMP1]]
 ; CHECK-NEXT:    call void @foo(i32 [[TMP2]], i32 [[DIV]])
 ; CHECK-NEXT:    ret void
 ;
   %rem = srem i32 %a, %b
-  %div = sdiv i32 %a, %b
+  %div = sdiv nof i32 %a, %b
   call void @foo(i32 %rem, i32 %div)
   ret void
 }
 
 define void @decompose_illegal_urem_same_block(i32 %a, i32 %b) {
 ; CHECK-LABEL: @decompose_illegal_urem_same_block(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 %a, %b
 ; CHECK-NEXT:    [[TMP1:%.*]] = mul i32 [[DIV]], %b
 ; CHECK-NEXT:    [[TMP2:%.*]] = sub i32 %a, [[TMP1]]
 ; CHECK-NEXT:    call void @foo(i32 [[TMP2]], i32 [[DIV]])
 ; CHECK-NEXT:    ret void
 ;
-  %div = udiv i32 %a, %b
+  %div = udiv nof i32 %a, %b
   %rem = urem i32 %a, %b
   call void @foo(i32 %rem, i32 %div)
   ret void
 }
 
-; Hoist and optionally decompose the sdiv because it's safe and free.
+; Hoist and optionally decompose the sdiv nof because it's safe and free.
 ; PR31028 - https://bugs.llvm.org/show_bug.cgi?id=31028
 
 define i32 @hoist_sdiv(i32 %a, i32 %b) {
 ; CHECK-LABEL: @hoist_sdiv(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, %b
 ; CHECK-NEXT:    [[TMP0:%.*]] = mul i32 [[DIV]], %b
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 %a, [[TMP0]]
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP1]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i32 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
 entry:
   %rem = srem i32 %a, %b
   %cmp = icmp eq i32 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = sdiv i32 %a, %b
+  %div = sdiv nof i32 %a, %b
   br label %end
 
 end:
   %ret = phi i32 [ %div, %if ], [ 3, %entry ]
   ret i32 %ret
 }
 
-; Hoist and optionally decompose the udiv because it's safe and free.
+; Hoist and optionally decompose the udiv nof because it's safe and free.
 
 define i64 @hoist_udiv(i64 %a, i64 %b) {
 ; CHECK-LABEL: @hoist_udiv(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i64 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i64 %a, %b
 ; CHECK-NEXT:    [[TMP0:%.*]] = mul i64 [[DIV]], %b
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i64 %a, [[TMP0]]
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i64 [[TMP1]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i64 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i64 [[RET]]
 ;
 entry:
   %rem = urem i64 %a, %b
   %cmp = icmp eq i64 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = udiv i64 %a, %b
+  %div = udiv nof i64 %a, %b
   br label %end
 
 end:
   %ret = phi i64 [ %div, %if ], [ 3, %entry ]
   ret i64 %ret
 }
 
 ; Hoist the srem if it's safe and free, otherwise decompose it.
 
 define i16 @hoist_srem(i16 %a, i16 %b) {
 ; CHECK-LABEL: @hoist_srem(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i16 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i16 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i16 [[DIV]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    [[TMP0:%.*]] = mul i16 [[DIV]], %b
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i16 %a, [[TMP0]]
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i16 [ [[TMP1]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i16 [[RET]]
 ;
 entry:
-  %div = sdiv i16 %a, %b
+  %div = sdiv nof i16 %a, %b
   %cmp = icmp eq i16 %div, 42
   br i1 %cmp, label %if, label %end
 
 if:
   %rem = srem i16 %a, %b
   br label %end
 
 end:
   %ret = phi i16 [ %rem, %if ], [ 3, %entry ]
   ret i16 %ret
 }
 
 ; Hoist the urem if it's safe and free, otherwise decompose it.
 
 define i8 @hoist_urem(i8 %a, i8 %b) {
 ; CHECK-LABEL: @hoist_urem(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i8 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[DIV]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    [[TMP0:%.*]] = mul i8 [[DIV]], %b
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i8 %a, [[TMP0]]
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i8 [ [[TMP1]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i8 [[RET]]
 ;
 entry:
-  %div = udiv i8 %a, %b
+  %div = udiv nof i8 %a, %b
   %cmp = icmp eq i8 %div, 42
   br i1 %cmp, label %if, label %end
 
 if:
   %rem = urem i8 %a, %b
   br label %end
 
 end:
   %ret = phi i8 [ %rem, %if ], [ 3, %entry ]
   ret i8 %ret
 }
 
 ; If the ops don't match, don't do anything: signedness.
 
 define i32 @dont_hoist_udiv(i32 %a, i32 %b) {
 ; CHECK-LABEL: @dont_hoist_udiv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[REM]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i32 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
 entry:
   %rem = srem i32 %a, %b
   %cmp = icmp eq i32 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = udiv i32 %a, %b
+  %div = udiv nof i32 %a, %b
   br label %end
 
 end:
   %ret = phi i32 [ %div, %if ], [ 3, %entry ]
   ret i32 %ret
 }
 
 ; If the ops don't match, don't do anything: operation.

 
 define i32 @dont_hoist_sdiv(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: @dont_hoist_sdiv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[REM]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, %c
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, %c
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i32 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
 entry:
   %rem = srem i32 %a, %b
   %cmp = icmp eq i32 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = sdiv i32 %a, %c
+  %div = sdiv nof i32 %a, %c
   br label %end
 
 end:
   %ret = phi i32 [ %div, %if ], [ 3, %entry ]
   ret i32 %ret
 }
 
 ; If the target doesn't have a unified div/rem op for the type, decompose rem in-place to mul+sub.
 
 define i128 @dont_hoist_urem(i128 %a, i128 %b) {
 ; CHECK-LABEL: @dont_hoist_urem(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i128 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i128 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i128 [[DIV]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    [[TMP0:%.*]] = mul i128 [[DIV]], %b
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i128 %a, [[TMP0]]
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i128 [ [[TMP1]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i128 [[RET]]
 ;
 entry:
-  %div = udiv i128 %a, %b
+  %div = udiv nof i128 %a, %b
   %cmp = icmp eq i128 %div, 42
   br i1 %cmp, label %if, label %end
 
 if:
   %rem = urem i128 %a, %b
   br label %end
 
 end:
   %ret = phi i128 [ %rem, %if ], [ 3, %entry ]
   ret i128 %ret
 }
 
 ; We don't hoist if one op does not dominate the other,
 ; but we could hoist both ops to the common predecessor block?
 
 define i32 @no_domination(i1 %cmp, i32 %a, i32 %b) {
 ; CHECK-LABEL: @no_domination(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 %cmp, label %if, label %else
 ; CHECK:       if:
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       else:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i32 [ [[DIV]], %if ], [ [[REM]], %else ]
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
 entry:
   br i1 %cmp, label %if, label %else
 
 if:
-  %div = sdiv i32 %a, %b
+  %div = sdiv nof i32 %a, %b
   br label %end
 
 else:
   %rem = srem i32 %a, %b
   br label %end
 
 end:
   %ret = phi i32 [ %div, %if ], [ %rem, %else ]
   ret i32 %ret
 }
 

test/Transforms/DivRemPairs/X86/div-rem-pairs.ll

 ; RUN: opt < %s -div-rem-pairs -S -mtriple=x86_64-unknown-unknown    | FileCheck %s
 
 declare void @foo(i32, i32)
 
 define void @decompose_illegal_srem_same_block(i32 %a, i32 %b) {
 ; CHECK-LABEL: @decompose_illegal_srem_same_block(
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 %a, %b
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, %b
 ; CHECK-NEXT:    call void @foo(i32 [[REM]], i32 [[DIV]])
 ; CHECK-NEXT:    ret void
 ;
   %rem = srem i32 %a, %b
-  %div = sdiv i32 %a, %b
+  %div = sdiv nof i32 %a, %b
   call void @foo(i32 %rem, i32 %div)
   ret void
 }
 
 define void @decompose_illegal_urem_same_block(i32 %a, i32 %b) {
 ; CHECK-LABEL: @decompose_illegal_urem_same_block(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 %a, %b
 ; CHECK-NEXT:    [[REM:%.*]] = urem i32 %a, %b
 ; CHECK-NEXT:    call void @foo(i32 [[REM]], i32 [[DIV]])
 ; CHECK-NEXT:    ret void
 ;
-  %div = udiv i32 %a, %b
+  %div = udiv nof i32 %a, %b
   %rem = urem i32 %a, %b
   call void @foo(i32 %rem, i32 %div)
   ret void
 }
 
-; Hoist and optionally decompose the sdiv because it's safe and free.
+; Hoist and optionally decompose the sdiv nof because it's safe and free.
 ; PR31028 - https://bugs.llvm.org/show_bug.cgi?id=31028
 
 define i32 @hoist_sdiv(i32 %a, i32 %b) {
 ; CHECK-LABEL: @hoist_sdiv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 %a, %b
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[REM]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i32 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
 entry:
   %rem = srem i32 %a, %b
   %cmp = icmp eq i32 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = sdiv i32 %a, %b
+  %div = sdiv nof i32 %a, %b
   br label %end
 
 end:
   %ret = phi i32 [ %div, %if ], [ 3, %entry ]
   ret i32 %ret
 }
 
-; Hoist and optionally decompose the udiv because it's safe and free.
+; Hoist and optionally decompose the udiv nof because it's safe and free.
 
 define i64 @hoist_udiv(i64 %a, i64 %b) {
 ; CHECK-LABEL: @hoist_udiv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[REM:%.*]] = urem i64 %a, %b
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i64 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i64 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i64 [[REM]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i64 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i64 [[RET]]
 ;
 entry:
   %rem = urem i64 %a, %b
   %cmp = icmp eq i64 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = udiv i64 %a, %b
+  %div = udiv nof i64 %a, %b
   br label %end
 
 end:
   %ret = phi i64 [ %div, %if ], [ 3, %entry ]
   ret i64 %ret
 }
 
 ; Hoist the srem if it's safe and free, otherwise decompose it.
 
 define i16 @hoist_srem(i16 %a, i16 %b) {
 ; CHECK-LABEL: @hoist_srem(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i16 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i16 %a, %b
 ; CHECK-NEXT:    [[REM:%.*]] = srem i16 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i16 [[DIV]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i16 [ [[REM]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i16 [[RET]]
 ;
 entry:
-  %div = sdiv i16 %a, %b
+  %div = sdiv nof i16 %a, %b
   %cmp = icmp eq i16 %div, 42
   br i1 %cmp, label %if, label %end
 
 if:
   %rem = srem i16 %a, %b
   br label %end
 
 end:
   %ret = phi i16 [ %rem, %if ], [ 3, %entry ]
   ret i16 %ret
 }
 
 ; Hoist the urem if it's safe and free, otherwise decompose it.
 
 define i8 @hoist_urem(i8 %a, i8 %b) {
 ; CHECK-LABEL: @hoist_urem(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i8 %a, %b
 ; CHECK-NEXT:    [[REM:%.*]] = urem i8 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[DIV]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i8 [ [[REM]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i8 [[RET]]
 ;
 entry:
-  %div = udiv i8 %a, %b
+  %div = udiv nof i8 %a, %b
   %cmp = icmp eq i8 %div, 42
   br i1 %cmp, label %if, label %end
 
 if:
   %rem = urem i8 %a, %b
   br label %end
 
 end:
   %ret = phi i8 [ %rem, %if ], [ 3, %entry ]
   ret i8 %ret
 }
 
 ; If the ops don't match, don't do anything: signedness.
 
 define i32 @dont_hoist_udiv(i32 %a, i32 %b) {
 ; CHECK-LABEL: @dont_hoist_udiv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[REM]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i32 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
 entry:
   %rem = srem i32 %a, %b
   %cmp = icmp eq i32 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = udiv i32 %a, %b
+  %div = udiv nof i32 %a, %b
   br label %end
 
 end:
   %ret = phi i32 [ %div, %if ], [ 3, %entry ]
   ret i32 %ret
 }
 
 ; If the ops don't match, don't do anything: operation.

 
 define i32 @dont_hoist_sdiv(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: @dont_hoist_sdiv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[REM]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, %c
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, %c
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i32 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
 entry:
   %rem = srem i32 %a, %b
   %cmp = icmp eq i32 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = sdiv i32 %a, %c
+  %div = sdiv nof i32 %a, %c
   br label %end
 
 end:
   %ret = phi i32 [ %div, %if ], [ 3, %entry ]
   ret i32 %ret
 }
 
 ; If the target doesn't have a unified div/rem op for the type, decompose rem in-place to mul+sub.
 
 define i128 @dont_hoist_urem(i128 %a, i128 %b) {
 ; CHECK-LABEL: @dont_hoist_urem(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i128 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i128 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i128 [[DIV]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    [[TMP0:%.*]] = mul i128 [[DIV]], %b
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i128 %a, [[TMP0]]
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i128 [ [[TMP1]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i128 [[RET]]
 ;
 entry:
-  %div = udiv i128 %a, %b
+  %div = udiv nof i128 %a, %b
   %cmp = icmp eq i128 %div, 42
   br i1 %cmp, label %if, label %end
 
 if:
   %rem = urem i128 %a, %b
   br label %end
 
 end:
   %ret = phi i128 [ %rem, %if ], [ 3, %entry ]
   ret i128 %ret
 }
 
 ; We don't hoist if one op does not dominate the other,
 ; but we could hoist both ops to the common predecessor block?
 
 define i32 @no_domination(i1 %cmp, i32 %a, i32 %b) {
 ; CHECK-LABEL: @no_domination(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 %cmp, label %if, label %else
 ; CHECK:       if:
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       else:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i32 [ [[DIV]], %if ], [ [[REM]], %else ]
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
 entry:
   br i1 %cmp, label %if, label %else
 
 if:
-  %div = sdiv i32 %a, %b
+  %div = sdiv nof i32 %a, %b
   br label %end
 
 else:
   %rem = srem i32 %a, %b
   br label %end
 
 end:
   %ret = phi i32 [ %div, %if ], [ %rem, %else ]
   ret i32 %ret
 }
 

test/Transforms/GVN/calls-readonly.ll

 ; RUN: opt < %s -basicaa -gvn -S | FileCheck %s
 ; Should delete the second call to strlen even though the intervening strchr call exists.
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin7"
 
 define i8* @test(i8* %P, i8* %Q, i32 %x, i32 %y) nounwind readonly {
 entry:
   %0 = tail call i32 @strlen(i8* %P)              ; <i32> [#uses=2]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
-  %2 = sdiv i32 %x, %y                            ; <i32> [#uses=1]
+  %2 = sdiv nof i32 %x, %y                            ; <i32> [#uses=1]
   br label %bb1
 
 bb1:                                              ; preds = %bb, %entry
   %x_addr.0 = phi i32 [ %2, %bb ], [ %x, %entry ] ; <i32> [#uses=1]
   %3 = tail call i8* @strchr(i8* %Q, i32 97)      ; <i8*> [#uses=1]
   %4 = tail call i32 @strlen(i8* %P)              ; <i32> [#uses=1]
   %5 = add i32 %x_addr.0, %0                      ; <i32> [#uses=1]
   %.sum = sub i32 %5, %4                          ; <i32> [#uses=1]
   %6 = getelementptr i8, i8* %3, i32 %.sum            ; <i8*> [#uses=1]
   ret i8* %6
 }
 
 ; CHECK: define i8* @test(i8* %P, i8* %Q, i32 %x, i32 %y) #0 {
 ; CHECK: entry:
 ; CHECK-NEXT:   %0 = tail call i32 @strlen(i8* %P)
 ; CHECK-NEXT:   %1 = icmp eq i32 %0, 0
 ; CHECK-NEXT:   br i1 %1, label %bb, label %bb1
 ; CHECK: bb:
-; CHECK-NEXT:   %2 = sdiv i32 %x, %y
+; CHECK-NEXT:   %2 = sdiv nof i32 %x, %y
 ; CHECK-NEXT:   br label %bb1
 ; CHECK: bb1:
 ; CHECK-NEXT:   %x_addr.0 = phi i32 [ %2, %bb ], [ %x, %entry ]
 ; CHECK-NEXT:   %3 = tail call i8* @strchr(i8* %Q, i32 97)
 ; CHECK-NEXT:   %4 = add i32 %x_addr.0, %0
 ; CHECK-NEXT:   %5 = getelementptr i8, i8* %3, i32 %x_addr.0
 ; CHECK-NEXT:   ret i8* %5
 ; CHECK: }
 
 declare i32 @strlen(i8*) nounwind readonly
 
 declare i8* @strchr(i8*, i32) nounwind readonly

test/Transforms/IRCE/bad_expander.ll

exit:                                       ; preds = %guarded, %loop
   ret void
 
 loop:                                      ; preds = %guarded, %entry
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %guarded ]
   %iv.next = add nuw nsw i64 %iv, 1
   br i1 %maybe_exit, label %range_check, label %exit
 
 range_check:
-  %div_result = udiv i64 %num, %denom
+  %div_result = udiv nof i64 %num, %denom
   %rc = icmp slt i64 %iv.next, %div_result
   br i1 %rc, label %guarded, label %exit
 
 guarded:
   %gep = getelementptr i64, i64* %p1, i64 %iv.next
   %loaded = load i64, i64* %gep, align 4
   %tmp7 = icmp slt i64 %iv.next, 1000
   br i1 %tmp7, label %loop, label %exit
 }
 
 define void @test_03(i64* %p1, i64* %p2, i1 %maybe_exit) {
 
 ; Show that IRCE would hit test_02 if the division was safe (denom not zero).
 
 ; CHECK-LABEL: test_03
 ; CHECK:       entry:
 ; CHECK-NEXT:    %num = load i64, i64* %p1, align 4
-; CHECK-NEXT:    [[DIV:%[^ ]+]] = udiv i64 %num, 13
+; CHECK-NEXT:    [[DIV:%[^ ]+]] = udiv nof i64 %num, 13
 ; CHECK-NEXT:    [[DIV_MINUS_1:%[^ ]+]] = add i64 [[DIV]], -1
 ; CHECK-NEXT:    [[COMP1:%[^ ]+]] = icmp sgt i64 [[DIV_MINUS_1]], 0
 ; CHECK-NEXT:    %exit.mainloop.at = select i1 [[COMP1]], i64 [[DIV_MINUS_1]], i64 0
 ; CHECK-NEXT:    [[COMP2:%[^ ]+]] = icmp slt i64 0, %exit.mainloop.at
 ; CHECK-NEXT:    br i1 [[COMP2]], label %loop.preheader, label %main.pseudo.exit
 ; CHECK-NOT:     preloop
 ; CHECK:       loop:
 ; CHECK-NEXT:    %iv = phi i64 [ %iv.next, %guarded ], [ 0, %loop.preheader ]
exit:                                       ; preds = %guarded, %loop
   ret void
 
 loop:                                      ; preds = %guarded, %entry
   %iv = phi i64 [ 0, %entry ], [ %iv.next, %guarded ]
   %iv.next = add nuw nsw i64 %iv, 1
   br i1 %maybe_exit, label %range_check, label %exit
 
 range_check:
-  %div_result = udiv i64 %num, 13
+  %div_result = udiv nof i64 %num, 13
   %rc = icmp slt i64 %iv.next, %div_result
   br i1 %rc, label %guarded, label %exit
 
 guarded:
   %gep = getelementptr i64, i64* %p1, i64 %iv.next
   %loaded = load i64, i64* %gep, align 4
   %tmp7 = icmp slt i64 %iv.next, 1000
   br i1 %tmp7, label %loop, label %exit
 }
 
 !0 = !{i64 0, i64 100}

test/Transforms/IndVarSimplify/iv-widen-elim-ext.ll

 ; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV:%.*]].next, %for.inc ], [ 0, %for.body.lr.ph ]
 ; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* %B, i64 [[INDVARS_IV]]
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
 ; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* %C, i64 [[TMP1]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX2]], align 4
 ; CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP0]], [[TMP2]]
 ; CHECK-NEXT:    [[TRUNC0:%.*]] = trunc i64 [[TMP1]] to i32
-; CHECK-NEXT:    [[DIV0:%.*]] = udiv i32 5, [[TRUNC0]]
+; CHECK-NEXT:    [[DIV0:%.*]] = udiv nof i32 5, [[TRUNC0]]
 ; CHECK-NEXT:    [[ADD4:%.*]] = add nsw i32 [[ADD3]], [[DIV0]]
 ; CHECK-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* %A, i64 [[INDVARS_IV]]
 ; CHECK-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX5]], align 4
 ; CHECK-NEXT:    br label %for.inc
 ; CHECK:       for.inc:
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = zext i32 %N to i64
 ; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
for.body:                                         ; preds = %for.body.lr.ph, %for.inc
   %idxprom = sext i32 %i.02 to i64
   %arrayidx = getelementptr inbounds i32, i32* %B, i64 %idxprom
   %0 = load i32, i32* %arrayidx, align 4
   %add = add nsw i32 %i.02, 2
   %idxprom1 = zext i32 %add to i64
   %arrayidx2 = getelementptr inbounds i32, i32* %C, i64 %idxprom1
   %1 = load i32, i32* %arrayidx2, align 4
   %add3 = add nsw i32 %0, %1
-  %div0 = udiv i32 5, %add
+  %div0 = udiv nof i32 5, %add
   %add4 = add nsw i32 %add3, %div0
   %idxprom4 = zext i32 %i.02 to i64
   %arrayidx5 = getelementptr inbounds i32, i32* %A, i64 %idxprom4
   store i32 %add4, i32* %arrayidx5, align 4
   br label %for.inc
 
 for.inc:                                          ; preds = %for.body
   %inc = add nsw i32 %i.02, 1

test/Transforms/InstCombine/2008-02-16-SDivOverflow2.ll

-; RUN: opt < %s -instcombine -S | grep "sdiv i8 \%a, 9"
+; RUN: opt < %s -instcombine -S | grep "sdiv nof i8 \%a, 9"
 ; PR2048
 
 define i8 @i(i8 %a) {
-  %tmp1 = sdiv i8 %a, -3
-  %tmp2 = sdiv i8 %tmp1, -3
+  %tmp1 = sdiv exact nof i8 %a, -3
+  %tmp2 = sdiv exact nof i8 %tmp1, -3
   ret i8 %tmp2
 }
 

test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll

 ; RUN: opt -S -instcombine < %s | FileCheck %s
 
 ; rdar://12182093
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
 ; CHECK-LABEL: @udiv400(
-; CHECK: udiv i32 %x, 400
+; CHECK: udiv nof i32 %x, 400
 ; CHECK: ret
 define i32 @udiv400(i32 %x) {
 entry:
   %div = lshr i32 %x, 2
-  %div1 = udiv i32 %div, 100
+  %div1 = udiv nof i32 %div, 100
   ret i32 %div1
 }
 
 
 ; CHECK-LABEL: @udiv400_no(
 ; CHECK: ashr
 ; CHECK: div
 ; CHECK: ret
 define i32 @udiv400_no(i32 %x) {
 entry:
   %div = ashr i32 %x, 2
-  %div1 = udiv i32 %div, 100
+  %div1 = udiv nof i32 %div, 100
   ret i32 %div1
 }
 
 ; CHECK-LABEL: @sdiv400_yes(
-; CHECK: udiv i32 %x, 400
+; CHECK: udiv nof i32 %x, 400
 ; CHECK: ret
 define i32 @sdiv400_yes(i32 %x) {
 entry:
   %div = lshr i32 %x, 2
   ; The sign bits of both operands are zero (i.e. we can prove they are
   ; unsigned inputs), turn this into a udiv.
   ; Next, optimize this just like sdiv.
-  %div1 = sdiv i32 %div, 100
+  %div1 = sdiv nof i32 %div, 100
   ret i32 %div1
 }
 
 
 ; CHECK-LABEL: @udiv_i80(
-; CHECK: udiv i80 %x, 400
+; CHECK: udiv nof i80 %x, 400
 ; CHECK: ret
 define i80 @udiv_i80(i80 %x) {
   %div = lshr i80 %x, 2
-  %div1 = udiv i80 %div, 100
+  %div1 = udiv nof i80 %div, 100
   ret i80 %div1
 }
 
 define i32 @no_crash_notconst_udiv(i32 %x, i32 %notconst) {
   %div = lshr i32 %x, %notconst
-  %div1 = udiv i32 %div, 100
+  %div1 = udiv nof i32 %div, 100
   ret i32 %div1
 }

test/Transforms/InstCombine/apint-add.ll

 
 ; Multiple uses of the operands don't prevent the fold.
 
 define i4 @sext_multiuse(i4 %x) {
 ; CHECK-LABEL: @sext_multiuse(
 ; CHECK-NEXT:    [[XOR:%.*]] = xor i4 %x, -8
 ; CHECK-NEXT:    [[ZEXT:%.*]] = zext i4 [[XOR]] to i7
 ; CHECK-NEXT:    [[ADD:%.*]] = sext i4 %x to i7
-; CHECK-NEXT:    [[MUL:%.*]] = sdiv i7 [[ZEXT]], [[ADD]]
+; CHECK-NEXT:    [[MUL:%.*]] = sdiv nof i7 [[ZEXT]], [[ADD]]
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i7 [[MUL]] to i4
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i4 [[TRUNC]], [[XOR]]
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i4 [[TRUNC]], [[XOR]]
 ; CHECK-NEXT:    ret i4 [[DIV]]
 ;
   %xor = xor i4 %x, -8
   %zext = zext i4 %xor to i7
   %add = add nsw i7 %zext, -8
-  %mul = sdiv i7 %zext, %add
+  %mul = sdiv nof i7 %zext, %add
   %trunc = trunc i7 %mul to i4
-  %div = sdiv i4 %trunc, %xor
+  %div = sdiv nof i4 %trunc, %xor
   ret i4 %div
 }
 
 ; Tests for Integer BitWidth > 64 && BitWidth <= 1024.
 
 ;; Flip sign bit then add INT_MIN -> nop.
 define i111 @test5(i111 %x) {
 ; CHECK-LABEL: @test5(

test/Transforms/InstCombine/apint-shift.ll

;
   ret <2 x i7> %sh2
 }
 
 ; In general, we would need an 'and' for this transform, but the masked-off bits are known zero.
 ; lshr (shl X, C1), C2 -->  shl X, C1 - C2
 
 define <2 x i7> @shl_lshr_splat_vec(<2 x i7> %X) {
 ; CHECK-LABEL: @shl_lshr_splat_vec(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i7> %X, <i7 9, i7 9>
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof <2 x i7> %X, <i7 9, i7 9>
 ; CHECK-NEXT:    [[SH1:%.*]] = shl nuw nsw <2 x i7> [[DIV]], <i7 1, i7 1>
 ; CHECK-NEXT:    ret <2 x i7> [[SH1]]
 ;
-  %div = udiv <2 x i7> %X, <i7 9, i7 9>
+  %div = udiv nof <2 x i7> %X, <i7 9, i7 9>
   %sh1 = shl nuw <2 x i7> %div, <i7 3, i7 3>
   %sh2 = lshr exact <2 x i7> %sh1, <i7 2, i7 2>
   ret <2 x i7> %sh2
 }
 
 ; Don't hide the shl from scalar evolution. DAGCombine will get it.
 define i23 @test11(i23 %A) {
 ; CHECK-LABEL: @test11(

test/Transforms/InstCombine/apint-sub.ll

;
   %B = lshr i1024 %A, 1023
   %C = bitcast i1024 %B to i1024
   %D = sub i1024 0, %C
   ret i1024 %D
 }
 
 define i51 @test16(i51 %A) {
 ; CHECK-LABEL: @test16(
-; CHECK-NEXT:    [[Y:%.*]] = sdiv i51 %A, -1123
+; CHECK-NEXT:    [[Y:%.*]] = sdiv nof i51 %A, -1123
 ; CHECK-NEXT:    ret i51 [[Y]]
 ;
-  %X = sdiv i51 %A, 1123
+  %X = sdiv nof i51 %A, 1123
   %Y = sub i51 0, %X
   ret i51 %Y
 }
 
 ; Can't fold subtract here because negation might overflow.
 ; PR3142
 define i25 @test17(i25 %Aok) {
 ; CHECK-LABEL: @test17(
 ; CHECK-NEXT:    [[B:%.*]] = sub i25 0, %Aok
-; CHECK-NEXT:    [[C:%.*]] = sdiv i25 [[B]], 1234
+; CHECK-NEXT:    [[C:%.*]] = sdiv nof i25 [[B]], 1234
 ; CHECK-NEXT:    ret i25 [[C]]
 ;
   %B = sub i25 0, %Aok
-  %C = sdiv i25 %B, 1234
+  %C = sdiv nof i25 %B, 1234
   ret i25 %C
 }
 
 define i128 @test18(i128 %Y) {
 ; CHECK-LABEL: @test18(
 ; CHECK-NEXT:    ret i128 0
 ;
   %t1 = shl i128 %Y, 2

test/Transforms/InstCombine/demorgan.ll

 ; ~(~A | B) --> (A & ~B) - what if we use one of the intermediate results?
 
 define i8 @demorgan_nor_use2a(i8 %A, i8 %B) {
 ; CHECK-LABEL: @demorgan_nor_use2a(
 ; CHECK-NEXT:    [[NOTA:%.*]] = xor i8 %A, -1
 ; CHECK-NEXT:    [[USE2A:%.*]] = mul i8 [[NOTA]], 23
 ; CHECK-NEXT:    [[B_NOT:%.*]] = xor i8 %B, -1
 ; CHECK-NEXT:    [[NOTC:%.*]] = and i8 [[B_NOT]], %A
-; CHECK-NEXT:    [[R:%.*]] = sdiv i8 [[NOTC]], [[USE2A]]
+; CHECK-NEXT:    [[R:%.*]] = sdiv nof i8 [[NOTC]], [[USE2A]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %nota = xor i8 %A, -1
   %use2a = mul i8 %nota, 23
   %c = or i8 %nota, %B
   %notc = xor i8 %c, -1
-  %r = sdiv i8 %notc, %use2a
+  %r = sdiv nof i8 %notc, %use2a
   ret i8 %r
 }
 
 ; ~(~A | B) --> (A & ~B) - what if we use one of the intermediate results?
 
 define i8 @demorgan_nor_use2b(i8 %A, i8 %B) {
 ; CHECK-LABEL: @demorgan_nor_use2b(
 ; CHECK-NEXT:    [[USE2B:%.*]] = mul i8 %B, 23
 ; CHECK-NEXT:    [[B_NOT:%.*]] = xor i8 %B, -1
 ; CHECK-NEXT:    [[NOTC:%.*]] = and i8 [[B_NOT]], %A
-; CHECK-NEXT:    [[R:%.*]] = sdiv i8 [[NOTC]], [[USE2B]]
+; CHECK-NEXT:    [[R:%.*]] = sdiv nof i8 [[NOTC]], [[USE2B]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %use2b = mul i8 %B, 23
   %nota = xor i8 %A, -1
   %c = or i8 %nota, %B
   %notc = xor i8 %c, -1
-  %r = sdiv i8 %notc, %use2b
+  %r = sdiv nof i8 %notc, %use2b
   ret i8 %r
 }
 
 ; ~(~A | B) --> (A & ~B) - what if we use one of the intermediate results?
 
 define i8 @demorgan_nor_use2c(i8 %A, i8 %B) {
 ; CHECK-LABEL: @demorgan_nor_use2c(
 ; CHECK-NEXT:    [[NOTA:%.*]] = xor i8 %A, -1
 ; CHECK-NEXT:    [[C:%.*]] = or i8 [[NOTA]], %B
 ; CHECK-NEXT:    [[USE2C:%.*]] = mul i8 [[C]], 23
 ; CHECK-NEXT:    [[NOTC:%.*]] = xor i8 [[C]], -1
-; CHECK-NEXT:    [[R:%.*]] = sdiv i8 [[NOTC]], [[USE2C]]
+; CHECK-NEXT:    [[R:%.*]] = sdiv nof i8 [[NOTC]], [[USE2C]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %nota = xor i8 %A, -1
   %c = or i8 %nota, %B
   %use2c = mul i8 %c, 23
   %notc = xor i8 %c, -1
-  %r = sdiv i8 %notc, %use2c
+  %r = sdiv nof i8 %notc, %use2c
   ret i8 %r
 }
 
 ; ~(~A | B) --> (A & ~B) - what if we use two of the intermediate results?
 
 define i8 @demorgan_nor_use2ab(i8 %A, i8 %B) {
 ; CHECK-LABEL: @demorgan_nor_use2ab(
 ; CHECK-NEXT:    [[USE2B:%.*]] = mul i8 %B, 23
 ; CHECK-NEXT:    [[NOTA:%.*]] = xor i8 %A, -1
 ; CHECK-NEXT:    [[USE2A:%.*]] = mul i8 [[NOTA]], 17
 ; CHECK-NEXT:    [[B_NOT:%.*]] = xor i8 %B, -1
 ; CHECK-NEXT:    [[NOTC:%.*]] = and i8 [[B_NOT]], %A
-; CHECK-NEXT:    [[R1:%.*]] = sdiv i8 [[NOTC]], [[USE2B]]
-; CHECK-NEXT:    [[R2:%.*]] = sdiv i8 [[R1]], [[USE2A]]
+; CHECK-NEXT:    [[R1:%.*]] = sdiv nof i8 [[NOTC]], [[USE2B]]
+; CHECK-NEXT:    [[R2:%.*]] = sdiv nof i8 [[R1]], [[USE2A]]
 ; CHECK-NEXT:    ret i8 [[R2]]
 ;
   %use2b = mul i8 %B, 23
   %nota = xor i8 %A, -1
   %use2a = mul i8 %nota, 17
   %c = or i8 %nota, %B
   %notc = xor i8 %c, -1
-  %r1 = sdiv i8 %notc, %use2b
-  %r2 = sdiv i8 %r1, %use2a
+  %r1 = sdiv nof i8 %notc, %use2b
+  %r2 = sdiv nof i8 %r1, %use2a
   ret i8 %r2
 }
 
 ; ~(~A | B) --> (A & ~B) - what if we use two of the intermediate results?
 
 define i8 @demorgan_nor_use2ac(i8 %A, i8 %B) {
 ; CHECK-LABEL: @demorgan_nor_use2ac(
 ; CHECK-NEXT:    [[NOTA:%.*]] = xor i8 %A, -1
 ; CHECK-NEXT:    [[USE2A:%.*]] = mul i8 [[NOTA]], 17
 ; CHECK-NEXT:    [[C:%.*]] = or i8 [[NOTA]], %B
 ; CHECK-NEXT:    [[USE2C:%.*]] = mul i8 [[C]], 23
 ; CHECK-NEXT:    [[NOTC:%.*]] = xor i8 [[C]], -1
-; CHECK-NEXT:    [[R1:%.*]] = sdiv i8 [[NOTC]], [[USE2C]]
-; CHECK-NEXT:    [[R2:%.*]] = sdiv i8 [[R1]], [[USE2A]]
+; CHECK-NEXT:    [[R1:%.*]] = sdiv nof i8 [[NOTC]], [[USE2C]]
+; CHECK-NEXT:    [[R2:%.*]] = sdiv nof i8 [[R1]], [[USE2A]]
 ; CHECK-NEXT:    ret i8 [[R2]]
 ;
   %nota = xor i8 %A, -1
   %use2a = mul i8 %nota, 17
   %c = or i8 %nota, %B
   %use2c = mul i8 %c, 23
   %notc = xor i8 %c, -1
-  %r1 = sdiv i8 %notc, %use2c
-  %r2 = sdiv i8 %r1, %use2a
+  %r1 = sdiv nof i8 %notc, %use2c
+  %r2 = sdiv nof i8 %r1, %use2a
   ret i8 %r2
 }
 
 ; ~(~A | B) --> (A & ~B) - what if we use two of the intermediate results?
 
 define i8 @demorgan_nor_use2bc(i8 %A, i8 %B) {
 ; CHECK-LABEL: @demorgan_nor_use2bc(
 ; CHECK-NEXT:    [[USE2B:%.*]] = mul i8 %B, 23
 ; CHECK-NEXT:    [[NOTA:%.*]] = xor i8 %A, -1
 ; CHECK-NEXT:    [[C:%.*]] = or i8 [[NOTA]], %B
 ; CHECK-NEXT:    [[USE2C:%.*]] = mul i8 [[C]], 23
 ; CHECK-NEXT:    [[NOTC:%.*]] = xor i8 [[C]], -1
-; CHECK-NEXT:    [[R1:%.*]] = sdiv i8 [[NOTC]], [[USE2C]]
-; CHECK-NEXT:    [[R2:%.*]] = sdiv i8 [[R1]], [[USE2B]]
+; CHECK-NEXT:    [[R1:%.*]] = sdiv nof i8 [[NOTC]], [[USE2C]]
+; CHECK-NEXT:    [[R2:%.*]] = sdiv nof i8 [[R1]], [[USE2B]]
 ; CHECK-NEXT:    ret i8 [[R2]]
 ;
   %use2b = mul i8 %B, 23
   %nota = xor i8 %A, -1
   %c = or i8 %nota, %B
   %use2c = mul i8 %c, 23
   %notc = xor i8 %c, -1
-  %r1 = sdiv i8 %notc, %use2c
-  %r2 = sdiv i8 %r1, %use2b
+  %r1 = sdiv nof i8 %notc, %use2c
+  %r2 = sdiv nof i8 %r1, %use2b
   ret i8 %r2
 }
 
 ; Do not apply DeMorgan's Law to constants. We prefer 'not' ops.
 
 define i32 @demorganize_constant1(i32 %a) {
 ; CHECK-LABEL: @demorganize_constant1(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %a, 15

test/Transforms/InstCombine/div-shift.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @t1(i16 zeroext %x, i32 %y) {
 ; CHECK-LABEL: @t1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CONV:%.*]] = zext i16 [[X:%.*]] to i32
 ; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[Y:%.*]], 1
 ; CHECK-NEXT:    [[D:%.*]] = lshr i32 [[CONV]], [[TMP0]]
 ; CHECK-NEXT:    ret i32 [[D]]
 ;
 entry:
   %conv = zext i16 %x to i32
   %s = shl i32 2, %y
-  %d = sdiv i32 %conv, %s
+  %d = sdiv nof i32 %conv, %s
   ret i32 %d
 }
 
 define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @t1vec(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i32>
 ; CHECK-NEXT:    [[TMP0:%.*]] = add <2 x i32> [[Y:%.*]], <i32 1, i32 1>
 ; CHECK-NEXT:    [[D:%.*]] = lshr <2 x i32> [[CONV]], [[TMP0]]
 ; CHECK-NEXT:    ret <2 x i32> [[D]]
 ;
 entry:
   %conv = zext <2 x i16> %x to <2 x i32>
   %s = shl <2 x i32> <i32 2, i32 2>, %y
-  %d = sdiv <2 x i32> %conv, %s
+  %d = sdiv nof <2 x i32> %conv, %s
   ret <2 x i32> %d
 }
 
 ; rdar://11721329
 define i64 @t2(i64 %x, i32 %y) {
 ; CHECK-LABEL: @t2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[Y:%.*]] to i64
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i64 [[X:%.*]], [[TMP1]]
 ; CHECK-NEXT:    ret i64 [[TMP2]]
 ;
   %1 = shl i32 1, %y
   %2 = zext i32 %1 to i64
-  %3 = udiv i64 %x, %2
+  %3 = udiv nof i64 %x, %2
   ret i64 %3
 }
 
 ; PR13250
 define i64 @t3(i64 %x, i32 %y) {
 ; CHECK-LABEL: @t3(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[Y:%.*]], 2
 ; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
 ; CHECK-NEXT:    [[TMP3:%.*]] = lshr i64 [[X:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret i64 [[TMP3]]
 ;
   %1 = shl i32 4, %y
   %2 = zext i32 %1 to i64
-  %3 = udiv i64 %x, %2
+  %3 = udiv nof i64 %x, %2
   ret i64 %3
 }
 
 define i32 @t4(i32 %x, i32 %y) {
 ; CHECK-LABEL: @t4(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[Y:%.*]], 5
 ; CHECK-NEXT:    [[DOTV:%.*]] = select i1 [[TMP1]], i32 [[Y]], i32 5
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[X:%.*]], [[DOTV]]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %1 = shl i32 1, %y
   %2 = icmp ult i32 %1, 32
   %3 = select i1 %2, i32 32, i32 %1
-  %4 = udiv i32 %x, %3
+  %4 = udiv nof i32 %x, %3
   ret i32 %4
 }
 
 define i32 @t5(i1 %x, i1 %y, i32 %V) {
 ; CHECK-LABEL: @t5(
 ; CHECK-NEXT:    [[DOTV:%.*]] = select i1 [[X:%.*]], i32 5, i32 6
 ; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[V:%.*]], [[DOTV]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[Y:%.*]], i32 [[TMP1]], i32 0
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %1 = shl i32 1, %V
   %2 = select i1 %x, i32 32, i32 64
   %3 = select i1 %y, i32 %2, i32 %1
-  %4 = udiv i32 %V, %3
+  %4 = udiv nof i32 %V, %3
   ret i32 %4
 }
 
 define i32 @t6(i32 %x, i32 %z) {
 ; CHECK-LABEL: @t6(
 ; CHECK-NEXT:    [[X_IS_ZERO:%.*]] = icmp eq i32 [[X:%.*]], 0
 ; CHECK-NEXT:    [[DIVISOR:%.*]] = select i1 [[X_IS_ZERO]], i32 1, i32 [[X]]
-; CHECK-NEXT:    [[Y:%.*]] = udiv i32 [[Z:%.*]], [[DIVISOR]]
+; CHECK-NEXT:    [[Y:%.*]] = udiv nof i32 [[Z:%.*]], [[DIVISOR]]
 ; CHECK-NEXT:    ret i32 [[Y]]
 ;
   %x_is_zero = icmp eq i32 %x, 0
   %divisor = select i1 %x_is_zero, i32 1, i32 %x
-  %y = udiv i32 %z, %divisor
+  %y = udiv nof i32 %z, %divisor
   ret i32 %y
 }
 
 ; (X << C1) / X -> 1 << C1 optimizations
 
 define i32 @t7(i32 %x) {
 ; CHECK-LABEL: @t7(
 ; CHECK-NEXT:    ret i32 4
 ;
   %shl = shl nsw i32 %x, 2
-  %r = sdiv i32 %shl, %x
+  %r = sdiv nof i32 %shl, %x
   ret i32 %r
 }
 
 ; make sure the previous opt doesn't take place for wrapped shifts
 
 define i32 @t8(i32 %x) {
 ; CHECK-LABEL: @t8(
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], 2
-; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[SHL]], [[X]]
+; CHECK-NEXT:    [[R:%.*]] = sdiv nof i32 [[SHL]], [[X]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %shl = shl i32 %x, 2
-  %r = sdiv i32 %shl, %x
+  %r = sdiv nof i32 %shl, %x
   ret i32 %r
 }
 
 define <2 x i32> @t9(<2 x i32> %x) {
 ; CHECK-LABEL: @t9(
 ; CHECK-NEXT:    ret <2 x i32> <i32 4, i32 8>
 ;
   %shl = shl nsw <2 x i32> %x, <i32 2, i32 3>
-  %r = sdiv <2 x i32> %shl, %x
+  %r = sdiv nof <2 x i32> %shl, %x
   ret <2 x i32> %r
 }
 
 define i32 @t10(i32 %x, i32 %y) {
 ; CHECK-LABEL: @t10(
 ; CHECK-NEXT:    [[R:%.*]] = shl nsw i32 1, [[Y:%.*]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %shl = shl nsw i32 %x, %y
-  %r = sdiv i32 %shl, %x
+  %r = sdiv nof i32 %shl, %x
   ret i32 %r
 }
 
 define <2 x i32> @t11(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @t11(
 ; CHECK-NEXT:    [[R:%.*]] = shl nsw <2 x i32> <i32 1, i32 1>, [[Y:%.*]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %shl = shl nsw <2 x i32> %x, %y
-  %r = sdiv <2 x i32> %shl, %x
+  %r = sdiv nof <2 x i32> %shl, %x
   ret <2 x i32> %r
 }
 
 define i32 @t12(i32 %x) {
 ; CHECK-LABEL: @t12(
 ; CHECK-NEXT:    ret i32 4
 ;
   %shl = shl nuw i32 %x, 2
-  %r = udiv i32 %shl, %x
+  %r = udiv nof i32 %shl, %x
   ret i32 %r
 }
 
 ; make sure the previous opt doesn't take place for wrapped shifts
 
 define i32 @t13(i32 %x) {
 ; CHECK-LABEL: @t13(
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], 2
-; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[SHL]], [[X]]
+; CHECK-NEXT:    [[R:%.*]] = udiv nof i32 [[SHL]], [[X]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %shl = shl i32 %x, 2
-  %r = udiv i32 %shl, %x
+  %r = udiv nof i32 %shl, %x
   ret i32 %r
 }
 
 define <2 x i32> @t14(<2 x i32> %x) {
 ; CHECK-LABEL: @t14(
 ; CHECK-NEXT:    ret <2 x i32> <i32 4, i32 8>
 ;
   %shl = shl nuw <2 x i32> %x, <i32 2, i32 3>
-  %r = udiv <2 x i32> %shl, %x
+  %r = udiv nof <2 x i32> %shl, %x
   ret <2 x i32> %r
 }
 
 define i32 @t15(i32 %x, i32 %y) {
 ; CHECK-LABEL: @t15(
 ; CHECK-NEXT:    [[R:%.*]] = shl nuw i32 1, [[Y:%.*]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %shl = shl nuw i32 %x, %y
-  %r = udiv i32 %shl, %x
+  %r = udiv nof i32 %shl, %x
   ret i32 %r
 }
 
 define <2 x i32> @t16(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @t16(
 ; CHECK-NEXT:    [[R:%.*]] = shl nuw <2 x i32> <i32 1, i32 1>, [[Y:%.*]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %shl = shl nuw <2 x i32> %x, %y
-  %r = udiv <2 x i32> %shl, %x
+  %r = udiv nof <2 x i32> %shl, %x
   ret <2 x i32> %r
 }

test/Transforms/InstCombine/div.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; This test makes sure that div instructions are properly eliminated.
 
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @test1(i32 %A) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    ret i32 %A
 ;
-  %B = sdiv i32 %A, 1             ; <i32> [#uses=1]
+  %B = sdiv nof i32 %A, 1             ; <i32> [#uses=1]
   ret i32 %B
 }
 
 define i32 @test2(i32 %A) {
         ; => Shift
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    [[B:%.*]] = lshr i32 %A, 3
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
-  %B = udiv i32 %A, 8             ; <i32> [#uses=1]
+  %B = udiv nof i32 %A, 8             ; <i32> [#uses=1]
   ret i32 %B
 }
 
 define i32 @test3(i32 %A) {
         ; => 0, don't need to keep traps
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:    ret i32 0
 ;
-  %B = sdiv i32 0, %A             ; <i32> [#uses=1]
+  %B = sdiv nof i32 0, %A             ; <i32> [#uses=1]
   ret i32 %B
 }
 
 define i32 @test4(i32 %A) {
         ; 0-A
 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:    [[B:%.*]] = sub i32 0, %A
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
-  %B = sdiv i32 %A, -1            ; <i32> [#uses=1]
+  %B = sdiv nof i32 %A, -1            ; <i32> [#uses=1]
   ret i32 %B
 }
 
 define i32 @test5(i32 %A) {
 ; CHECK-LABEL: @test5(
 ; CHECK-NEXT:    ret i32 0
 ;
-  %B = udiv i32 %A, -16           ; <i32> [#uses=1]
-  %C = udiv i32 %B, -4            ; <i32> [#uses=1]
+  %B = udiv nof i32 %A, -16           ; <i32> [#uses=1]
+  %C = udiv nof i32 %B, -4            ; <i32> [#uses=1]
   ret i32 %C
 }
 
 define i1 @test6(i32 %A) {
 ; CHECK-LABEL: @test6(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 %A, 123
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %B = udiv i32 %A, 123           ; <i32> [#uses=1]
+  %B = udiv nof i32 %A, 123           ; <i32> [#uses=1]
   ; A < 123
   %C = icmp eq i32 %B, 0          ; <i1> [#uses=1]
   ret i1 %C
 }
 
 define i1 @test7(i32 %A) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:    [[A_OFF:%.*]] = add i32 %A, -20
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[A_OFF]], 10
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %B = udiv i32 %A, 10            ; <i32> [#uses=1]
+  %B = udiv nof i32 %A, 10            ; <i32> [#uses=1]
   ; A >= 20 && A < 30
   %C = icmp eq i32 %B, 2          ; <i1> [#uses=1]
   ret i1 %C
 }
 
 define <2 x i1> @test7vec(<2 x i32> %A) {
 ; CHECK-LABEL: @test7vec(
 ; CHECK-NEXT:    [[A_OFF:%.*]] = add <2 x i32> %A, <i32 -20, i32 -20>
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult <2 x i32> [[A_OFF]], <i32 10, i32 10>
 ; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
-  %B = udiv <2 x i32> %A, <i32 10, i32 10>
+  %B = udiv nof <2 x i32> %A, <i32 10, i32 10>
   %C = icmp eq <2 x i32> %B, <i32 2, i32 2>
   ret <2 x i1> %C
 }
 
 define i1 @test8(i8 %A) {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:    [[C:%.*]] = icmp ugt i8 %A, -11
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
-  %B = udiv i8 %A, 123            ; <i8> [#uses=1]
+  %B = udiv nof i8 %A, 123            ; <i8> [#uses=1]
   ; A >= 246
   %C = icmp eq i8 %B, 2           ; <i1> [#uses=1]
   ret i1 %C
 }
 
 define <2 x i1> @test8vec(<2 x i8> %A) {
 ; CHECK-LABEL: @test8vec(
 ; CHECK-NEXT:    [[C:%.*]] = icmp ugt <2 x i8> %A, <i8 -11, i8 -11>
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
-  %B = udiv <2 x i8> %A, <i8 123, i8 123>
+  %B = udiv nof <2 x i8> %A, <i8 123, i8 123>
   %C = icmp eq <2 x i8> %B, <i8 2, i8 2>
   ret <2 x i1> %C
 }
 
 define i1 @test9(i8 %A) {
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:    [[C:%.*]] = icmp ult i8 %A, -10
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
-  %B = udiv i8 %A, 123            ; <i8> [#uses=1]
+  %B = udiv nof i8 %A, 123            ; <i8> [#uses=1]
   ; A < 246
   %C = icmp ne i8 %B, 2           ; <i1> [#uses=1]
   ret i1 %C
 }
 
 define <2 x i1> @test9vec(<2 x i8> %A) {
 ; CHECK-LABEL: @test9vec(
 ; CHECK-NEXT:    [[C:%.*]] = icmp ult <2 x i8> %A, <i8 -10, i8 -10>
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
-  %B = udiv <2 x i8> %A, <i8 123, i8 123>
+  %B = udiv nof <2 x i8> %A, <i8 123, i8 123>
   %C = icmp ne <2 x i8> %B, <i8 2, i8 2>
   ret <2 x i1> %C
 }
 
 define i32 @test10(i32 %X, i1 %C) {
 ; CHECK-LABEL: @test10(
 ; CHECK-NEXT:    [[R_V:%.*]] = select i1 %C, i32 6, i32 3
 ; CHECK-NEXT:    [[R:%.*]] = lshr i32 %X, [[R:%.*]].v
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %V = select i1 %C, i32 64, i32 8                ; <i32> [#uses=1]
-  %R = udiv i32 %X, %V            ; <i32> [#uses=1]
+  %R = udiv nof i32 %X, %V            ; <i32> [#uses=1]
   ret i32 %R
 }
 
 define i32 @test11(i32 %X, i1 %C) {
 ; CHECK-LABEL: @test11(
 ; CHECK-NEXT:    [[B_V:%.*]] = select i1 %C, i32 10, i32 5
 ; CHECK-NEXT:    [[B:%.*]] = lshr i32 %X, [[B:%.*]].v
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %A = select i1 %C, i32 1024, i32 32             ; <i32> [#uses=1]
-  %B = udiv i32 %X, %A            ; <i32> [#uses=1]
+  %B = udiv nof i32 %X, %A            ; <i32> [#uses=1]
   ret i32 %B
 }
 
 ; PR2328
 define i32 @test12(i32 %x) nounwind  {
 ; CHECK-LABEL: @test12(
 ; CHECK-NEXT:    ret i32 1
 ;
-  %tmp3 = udiv i32 %x, %x   ; 1
+  %tmp3 = udiv nof i32 %x, %x    ; 1
   ret i32 %tmp3
 }
 
 define i32 @test13(i32 %x) nounwind  {
 ; CHECK-LABEL: @test13(
 ; CHECK-NEXT:    ret i32 1
 ;
-  %tmp3 = sdiv i32 %x, %x   ; 1
+  %tmp3 = sdiv nof i32 %x, %x    ; 1
   ret i32 %tmp3
 }
 
 define i32 @test14(i8 %x) nounwind {
 ; CHECK-LABEL: @test14(
 ; CHECK-NEXT:    ret i32 0
 ;
   %zext = zext i8 %x to i32
-  %div = udiv i32 %zext, 257  ; 0
+  %div = udiv nof i32 %zext, 257  ; 0
   ret i32 %div
 }
 
 ; PR9814
 define i32 @test15(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: @test15(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 %b, -2
 ; CHECK-NEXT:    [[DIV2:%.*]] = lshr i32 %a, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[DIV2]]
 ;
   %shl = shl i32 1, %b
   %div = lshr i32 %shl, 2
-  %div2 = udiv i32 %a, %div
+  %div2 = udiv nof i32 %a, %div
   ret i32 %div2
 }
 
 define <2 x i64> @test16(<2 x i64> %x) nounwind {
 ; CHECK-LABEL: @test16(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i64> %x, <i64 192, i64 192>
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof <2 x i64> %x, <i64 192, i64 192>
 ; CHECK-NEXT:    ret <2 x i64> [[DIV]]
 ;
   %shr = lshr <2 x i64> %x, <i64 5, i64 5>
-  %div = udiv <2 x i64> %shr, <i64 6, i64 6>
+  %div = udiv nof <2 x i64> %shr, <i64 6, i64 6>
   ret <2 x i64> %div
 }
 
 define <2 x i64> @test17(<2 x i64> %x) nounwind {
 ; CHECK-LABEL: @test17(
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv <2 x i64> %x, <i64 -3, i64 -4>
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof <2 x i64> %x, <i64 -3, i64 -4>
 ; CHECK-NEXT:    ret <2 x i64> [[DIV]]
 ;
   %neg = sub nsw <2 x i64> zeroinitializer, %x
-  %div = sdiv <2 x i64> %neg, <i64 3, i64 4>
+  %div = sdiv nof <2 x i64> %neg, <i64 3, i64 4>
   ret <2 x i64> %div
 }
 
 define <2 x i64> @test18(<2 x i64> %x) nounwind {
 ; CHECK-LABEL: @test18(
 ; CHECK-NEXT:    [[DIV:%.*]] = sub <2 x i64> zeroinitializer, %x
 ; CHECK-NEXT:    ret <2 x i64> [[DIV]]
 ;
-  %div = sdiv <2 x i64> %x, <i64 -1, i64 -1>
+  %div = sdiv nof <2 x i64> %x, <i64 -1, i64 -1>
   ret <2 x i64> %div
 }
 
 define i32 @test19(i32 %x) {
 ; CHECK-LABEL: @test19(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 %x, 1
 ; CHECK-NEXT:    [[A:%.*]] = zext i1 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[A]]
 ;
-  %A = udiv i32 1, %x
+  %A = udiv nof i32 1, %x
   ret i32 %A
 }
 
 define <2 x i32> @test19vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test19vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i32> [[X:%.*]], <i32 1, i32 1>
 ; CHECK-NEXT:    [[A:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[A]]
 ;
-  %A = udiv <2 x i32> <i32 1, i32 1>, %x
+  %A = udiv nof <2 x i32> <i32 1, i32 1>, %x
   ret <2 x i32> %A
 }
 
 define i32 @test20(i32 %x) {
 ; CHECK-LABEL: @test20(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 %x, 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
 ; CHECK-NEXT:    [[A:%.*]] = select i1 [[TMP2]], i32 %x, i32 0
 ; CHECK-NEXT:    ret i32 [[A]]
 ;
-  %A = sdiv i32 1, %x
+  %A = sdiv nof i32 1, %x
   ret i32 %A
 }
 
 define <2 x i32> @test20vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test20vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 1, i32 1>
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 3, i32 3>
 ; CHECK-NEXT:    [[A:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[X]], <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i32> [[A]]
 ;
-  %A = sdiv <2 x i32> <i32 1, i32 1>, %x
+  %A = sdiv nof <2 x i32> <i32 1, i32 1>, %x
   ret <2 x i32> %A
 }
 
 define i32 @test21(i32 %a) {
 ; CHECK-LABEL: @test21(
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, 3
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, 3
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %shl = shl nsw i32 %a, 2
-  %div = sdiv i32 %shl, 12
+  %div = sdiv nof i32 %shl, 12
   ret i32 %div
 }
 
 define i32 @test22(i32 %a) {
 ; CHECK-LABEL: @test22(
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, 4
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, 4
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %mul = mul nsw i32 %a, 3
-  %div = sdiv i32 %mul, 12
+  %div = sdiv nof i32 %mul, 12
   ret i32 %div
 }
 
 define i32 @test23(i32 %a) {
 ; CHECK-LABEL: @test23(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 %a, 3
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 %a, 3
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %shl = shl nuw i32 %a, 2
-  %div = udiv i32 %shl, 12
+  %div = udiv nof i32 %shl, 12
   ret i32 %div
 }
 
 define i32 @test24(i32 %a) {
 ; CHECK-LABEL: @test24(
 ; CHECK-NEXT:    [[DIV:%.*]] = lshr i32 %a, 2
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %mul = mul nuw i32 %a, 3
-  %div = udiv i32 %mul, 12
+  %div = udiv nof i32 %mul, 12
   ret i32 %div
 }
 
 define i32 @test25(i32 %a) {
 ; CHECK-LABEL: @test25(
 ; CHECK-NEXT:    [[DIV:%.*]] = shl nsw i32 %a, 1
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %shl = shl nsw i32 %a, 2
-  %div = sdiv i32 %shl, 2
+  %div = sdiv nof i32 %shl, 2
   ret i32 %div
 }
 
 define i32 @test26(i32 %a) {
 ; CHECK-LABEL: @test26(
 ; CHECK-NEXT:    [[DIV:%.*]] = shl nsw i32 %a, 2
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %mul = mul nsw i32 %a, 12
-  %div = sdiv i32 %mul, 3
+  %div = sdiv nof i32 %mul, 3
   ret i32 %div
 }
 
 define i32 @test27(i32 %a) {
 ; CHECK-LABEL: @test27(
 ; CHECK-NEXT:    [[DIV:%.*]] = shl nuw i32 %a, 1
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %shl = shl nuw i32 %a, 2
-  %div = udiv i32 %shl, 2
+  %div = udiv nof i32 %shl, 2
   ret i32 %div
 }
 
 define i32 @test28(i32 %a) {
 ; CHECK-LABEL: @test28(
 ; CHECK-NEXT:    [[DIV:%.*]] = mul nuw i32 %a, 12
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %mul = mul nuw i32 %a, 36
-  %div = udiv i32 %mul, 3
+  %div = udiv nof i32 %mul, 3
   ret i32 %div
 }
 
 define i32 @test29(i32 %a) {
 ; CHECK-LABEL: @test29(
 ; CHECK-NEXT:    [[MUL_LOBIT:%.*]] = and i32 %a, 1
 ; CHECK-NEXT:    ret i32 [[MUL_LOBIT]]
 ;
   %mul = shl nsw i32 %a, 31
-  %div = sdiv i32 %mul, -2147483648
+  %div = sdiv nof i32 %mul, -2147483648
   ret i32 %div
 }
 
 define i32 @test30(i32 %a) {
 ; CHECK-LABEL: @test30(
 ; CHECK-NEXT:    ret i32 %a
 ;
   %mul = shl nuw i32 %a, 31
-  %div = udiv i32 %mul, -2147483648
+  %div = udiv nof i32 %mul, -2147483648
   ret i32 %div
 }
 
 define <2 x i32> @test31(<2 x i32> %x) {
 ; CHECK-LABEL: @test31(
 ; CHECK-NEXT:    ret <2 x i32> zeroinitializer
 ;
   %shr = lshr <2 x i32> %x, <i32 31, i32 31>
-  %div = udiv <2 x i32> %shr, <i32 2147483647, i32 2147483647>
+  %div = udiv nof <2 x i32> %shr, <i32 2147483647, i32 2147483647>
   ret <2 x i32> %div
 }
 
 define i32 @test32(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test32(
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 2, %b
 ; CHECK-NEXT:    [[DIV:%.*]] = lshr i32 [[SHL]], 2
-; CHECK-NEXT:    [[DIV2:%.*]] = udiv i32 %a, [[DIV]]
+; CHECK-NEXT:    [[DIV2:%.*]] = udiv nof i32 %a, [[DIV]]
 ; CHECK-NEXT:    ret i32 [[DIV2]]
 ;
   %shl = shl i32 2, %b
   %div = lshr i32 %shl, 2
-  %div2 = udiv i32 %a, %div
+  %div2 = udiv nof i32 %a, %div
   ret i32 %div2
 }
 
 define <2 x i64> @test33(<2 x i64> %x) nounwind {
 ; CHECK-LABEL: @test33(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv exact <2 x i64> %x, <i64 192, i64 192>
+; CHECK-NEXT:    [[DIV:%.*]] = udiv exact nof <2 x i64> %x, <i64 192, i64 192>
 ; CHECK-NEXT:    ret <2 x i64> [[DIV]]
 ;
   %shr = lshr exact <2 x i64> %x, <i64 5, i64 5>
-  %div = udiv exact <2 x i64> %shr, <i64 6, i64 6>
+  %div = udiv exact nof <2 x i64> %shr, <i64 6, i64 6>
   ret <2 x i64> %div
 }
 
 define <2 x i64> @test34(<2 x i64> %x) nounwind {
 ; CHECK-LABEL: @test34(
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv exact <2 x i64> %x, <i64 -3, i64 -4>
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv exact nof <2 x i64> %x, <i64 -3, i64 -4>
 ; CHECK-NEXT:    ret <2 x i64> [[DIV]]
 ;
   %neg = sub nsw <2 x i64> zeroinitializer, %x
-  %div = sdiv exact <2 x i64> %neg, <i64 3, i64 4>
+  %div = sdiv exact nof <2 x i64> %neg, <i64 3, i64 4>
   ret <2 x i64> %div
 }
 
 define i32 @test35(i32 %A) {
 ; CHECK-LABEL: @test35(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %A, 2147483647
-; CHECK-NEXT:    [[MUL:%.*]] = udiv exact i32 [[AND]], 2147483647
+; CHECK-NEXT:    [[MUL:%.*]] = udiv exact nof i32 [[AND]], 2147483647
 ; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %A, 2147483647
-  %mul = sdiv exact i32 %and, 2147483647
+  %mul = sdiv exact nof i32 %and, 2147483647
   ret i32 %mul
 }
 
 define <2 x i32> @test35vec(<2 x i32> %A) {
 ; CHECK-LABEL: @test35vec(
 ; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
-; CHECK-NEXT:    [[MUL:%.*]] = udiv exact <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    [[MUL:%.*]] = udiv exact nof <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
 ; CHECK-NEXT:    ret <2 x i32> [[MUL]]
 ;
   %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
-  %mul = sdiv exact <2 x i32> %and, <i32 2147483647, i32 2147483647>
+  %mul = sdiv exact nof <2 x i32> %and, <i32 2147483647, i32 2147483647>
   ret <2 x i32> %mul
 }
 
 define i32 @test36(i32 %A) {
 ; CHECK-LABEL: @test36(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %A, 2147483647
 ; CHECK-NEXT:    [[MUL:%.*]] = lshr exact i32 [[AND]], %A
 ; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %A, 2147483647
   %shl = shl nsw i32 1, %A
-  %mul = sdiv exact i32 %and, %shl
+  %mul = sdiv exact nof i32 %and, %shl
   ret i32 %mul
 }
 
 define <2 x i32> @test36vec(<2 x i32> %A) {
 ; CHECK-LABEL: @test36vec(
 ; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
 ; CHECK-NEXT:    [[MUL:%.*]] = lshr exact <2 x i32> [[AND]], [[A]]
 ; CHECK-NEXT:    ret <2 x i32> [[MUL]]
 ;
   %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
   %shl = shl nsw <2 x i32> <i32 1, i32 1>, %A
-  %mul = sdiv exact <2 x i32> %and, %shl
+  %mul = sdiv exact nof <2 x i32> %and, %shl
   ret <2 x i32> %mul
 }
 
 define i32 @test37(i32* %b) {
 ; CHECK-LABEL: @test37(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    store i32 0, i32* %b, align 4
 ; CHECK-NEXT:    br i1 undef, label %lor.rhs, label %lor.end
 ; CHECK:       lor.rhs:
 ; CHECK-NEXT:    br label %lor.end
 ; CHECK:       lor.end:
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   store i32 0, i32* %b, align 4
   %0 = load i32, i32* %b, align 4
   br i1 undef, label %lor.rhs, label %lor.end
 
 lor.rhs:                                          ; preds = %entry
   %mul = mul nsw i32 undef, %0
   br label %lor.end
 
 lor.end:                                          ; preds = %lor.rhs, %entry
   %t.0 = phi i32 [ %0, %entry ], [ %mul, %lor.rhs ]
-  %div = sdiv i32 %t.0, 2
+  %div = sdiv nof i32 %t.0, 2
   ret i32 %div
 }
 
 ; We can perform the division in the smaller type.
 
 define i32 @shrink(i8 %x) {
 ; CHECK-LABEL: @shrink(
-; CHECK-NEXT:    [[TMP1:%.*]] = sdiv i8 %x, 127
+; CHECK-NEXT:    [[TMP1:%.*]] = sdiv nof i8 %x, 127
 ; CHECK-NEXT:    [[DIV:%.*]] = sext i8 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %conv = sext i8 %x to i32
-  %div = sdiv i32 %conv, 127
+  %div = sdiv nof i32 %conv, 127
   ret i32 %div
 }
 
 ; Division in the smaller type can lead to more optimizations.
 
 define i32 @zap(i8 %x) {
 ; CHECK-LABEL: @zap(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i8 %x, -128
 ; CHECK-NEXT:    [[DIV:%.*]] = zext i1 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %conv = sext i8 %x to i32
-  %div = sdiv i32 %conv, -128
+  %div = sdiv nof i32 %conv, -128
   ret i32 %div
 }
 
 ; Splat constant divisors should get the same folds.
 
 define <3 x i32> @shrink_vec(<3 x i8> %x) {
 ; CHECK-LABEL: @shrink_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = sdiv <3 x i8> %x, <i8 127, i8 127, i8 127>
+; CHECK-NEXT:    [[TMP1:%.*]] = sdiv nof <3 x i8> %x, <i8 127, i8 127, i8 127>
 ; CHECK-NEXT:    [[DIV:%.*]] = sext <3 x i8> [[TMP1]] to <3 x i32>
 ; CHECK-NEXT:    ret <3 x i32> [[DIV]]
 ;
   %conv = sext <3 x i8> %x to <3 x i32>
-  %div = sdiv <3 x i32> %conv, <i32 127, i32 127, i32 127>
+  %div = sdiv nof <3 x i32> %conv, <i32 127, i32 127, i32 127>
   ret <3 x i32> %div
 }
 
 define <2 x i32> @zap_vec(<2 x i8> %x) {
 ; CHECK-LABEL: @zap_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i8> %x, <i8 -128, i8 -128>
 ; CHECK-NEXT:    [[DIV:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[DIV]]
 ;
   %conv = sext <2 x i8> %x to <2 x i32>
-  %div = sdiv <2 x i32> %conv, <i32 -128, i32 -128>
+  %div = sdiv nof <2 x i32> %conv, <i32 -128, i32 -128>
   ret <2 x i32> %div
 }
 
 ; But we can't do this if the signed constant won't fit in the original type.
 
 define i32 @shrink_no(i8 %x) {
 ; CHECK-LABEL: @shrink_no(
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i8 %x to i32
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[CONV]], 128
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[CONV]], 128
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %conv = sext i8 %x to i32
-  %div = sdiv i32 %conv, 128
+  %div = sdiv nof i32 %conv, 128
   ret i32 %div
 }
 
 ; When the divisor is known larger than the quotient,
 ; InstSimplify should kill it before InstCombine sees it.
 
 define i32 @shrink_no2(i8 %x) {
 ; CHECK-LABEL: @shrink_no2(
 ; CHECK-NEXT:    ret i32 0
 ;
   %conv = sext i8 %x to i32
-  %div = sdiv i32 %conv, -129
+  %div = sdiv nof i32 %conv, -129
   ret i32 %div
 }
 
 define i32 @shrink_no3(i16 %x) {
 ; CHECK-LABEL: @shrink_no3(
 ; CHECK-NEXT:    ret i32 0
 ;
   %conv = sext i16 %x to i32
-  %div = sdiv i32 %conv, 65535
+  %div = sdiv nof i32 %conv, 65535
   ret i32 %div
 }
 
 ; This previously crashed when trying to simplify the zext/icmp this becomes.
 define <2 x i8> @PR34841(<2 x i8> %x) {
 ; CHECK-LABEL: @PR34841(
 ; CHECK-NEXT:    ret <2 x i8> zeroinitializer
 ;
   %neg = and <2 x i8> %x, <i8 2, i8 2>
-  %div = udiv <2 x i8> <i8 1, i8 1>, %neg
+  %div = udiv nof <2 x i8> <i8 1, i8 1>, %neg
   ret <2 x i8> %div
 }
 
 ; X / (X * Y) -> 1 / Y if the multiplication does not overflow
 
 define i8 @div_factor_signed(i8 %x, i8 %y) {
 ; CHECK-LABEL: @div_factor_signed(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[Y:%.*]], 1

test/Transforms/InstCombine/exact.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @sdiv1(i32 %x) {
 ; CHECK-LABEL: @sdiv1(
-; CHECK-NEXT:    [[Y:%.*]] = sdiv i32 %x, 8
+; CHECK-NEXT:    [[Y:%.*]] = sdiv nof i32 %x, 8
 ; CHECK-NEXT:    ret i32 [[Y]]
 ;
-  %y = sdiv i32 %x, 8
+  %y = sdiv nof i32 %x, 8
   ret i32 %y
 }
 
 define i32 @sdiv2(i32 %x) {
 ; CHECK-LABEL: @sdiv2(
 ; CHECK-NEXT:    [[Y:%.*]] = ashr exact i32 %x, 3
 ; CHECK-NEXT:    ret i32 [[Y]]
 ;
-  %y = sdiv exact i32 %x, 8
+  %y = sdiv exact nof i32 %x, 8
   ret i32 %y
 }
 
 define <2 x i32> @sdiv2_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @sdiv2_vec(
 ; CHECK-NEXT:    [[Y:%.*]] = ashr exact <2 x i32> %x, <i32 7, i32 7>
 ; CHECK-NEXT:    ret <2 x i32> [[Y]]
 ;
-  %y = sdiv exact <2 x i32> %x, <i32 128, i32 128>
+  %y = sdiv exact nof <2 x i32> %x, <i32 128, i32 128>
   ret <2 x i32> %y
 }
 
 define i32 @sdiv3(i32 %x) {
 ; CHECK-LABEL: @sdiv3(
 ; CHECK-NEXT:    [[Y:%.*]] = srem i32 %x, 3
 ; CHECK-NEXT:    [[Z:%.*]] = sub i32 %x, [[Y]]
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
-  %y = sdiv i32 %x, 3
+  %y = sdiv nof i32 %x, 3
   %z = mul i32 %y, 3
   ret i32 %z
 }
 
 define i32 @sdiv4(i32 %x) {
 ; CHECK-LABEL: @sdiv4(
 ; CHECK-NEXT:    ret i32 %x
 ;
-  %y = sdiv exact i32 %x, 3
+  %y = sdiv exact nof i32 %x, 3
   %z = mul i32 %y, 3
   ret i32 %z
 }
 
 define i32 @sdiv5(i32 %x) {
 ; CHECK-LABEL: @sdiv5(
 ; CHECK-NEXT:    [[Y:%.*]] = srem i32 %x, 3
 ; CHECK-NEXT:    [[Z:%.*]] = sub i32 [[Y]], %x
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
-  %y = sdiv i32 %x, 3
+  %y = sdiv nof i32 %x, 3
   %z = mul i32 %y, -3
   ret i32 %z
 }
 
 define i32 @sdiv6(i32 %x) {
 ; CHECK-LABEL: @sdiv6(
 ; CHECK-NEXT:    [[Z:%.*]] = sub i32 0, %x
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
-  %y = sdiv exact i32 %x, 3
+  %y = sdiv exact nof i32 %x, 3
   %z = mul i32 %y, -3
   ret i32 %z
 }
 
 define i32 @udiv1(i32 %x, i32 %w) {
 ; CHECK-LABEL: @udiv1(
 ; CHECK-NEXT:    ret i32 %x
 ;
-  %y = udiv exact i32 %x, %w
+  %y = udiv exact nof i32 %x, %w
   %z = mul i32 %y, %w
   ret i32 %z
 }
 
 define i32 @udiv2(i32 %x, i32 %w) {
 ; CHECK-LABEL: @udiv2(
 ; CHECK-NEXT:    [[Z:%.*]] = lshr exact i32 %x, %w
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
   %y = shl i32 1, %w
-  %z = udiv exact i32 %x, %y
+  %z = udiv exact nof i32 %x, %y
   ret i32 %z
 }
 
 define i64 @ashr1(i64 %X) {
 ; CHECK-LABEL: @ashr1(
 ; CHECK-NEXT:    [[A:%.*]] = shl i64 %X, 8
 ; CHECK-NEXT:    [[B:%.*]] = ashr exact i64 [[A]], 2
 ; CHECK-NEXT:    ret i64 [[B]]
;
   ret <2 x i1> %Z
 }
 
 define i1 @udiv_icmp1(i64 %X) {
 ; CHECK-LABEL: @udiv_icmp1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne i64 %X, 0
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %A = udiv exact i64 %X, 5   ; X/5
+  %A = udiv exact nof i64 %X, 5   ; X/5
   %B = icmp ne i64 %A, 0
   ret i1 %B
 }
 
 define <2 x i1> @udiv_icmp1_vec(<2 x i64> %X) {
 ; CHECK-LABEL: @udiv_icmp1_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <2 x i64> %X, zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
-  %A = udiv exact <2 x i64> %X, <i64 5, i64 5>
+  %A = udiv exact nof <2 x i64> %X, <i64 5, i64 5>
   %B = icmp ne <2 x i64> %A, zeroinitializer
   ret <2 x i1> %B
 }
 
 define i1 @udiv_icmp2(i64 %X) {
 ; CHECK-LABEL: @udiv_icmp2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 %X, 0
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %A = udiv exact i64 %X, 5   ; X/5 == 0 --> x == 0
+  %A = udiv exact nof i64 %X, 5   ; X/5 == 0 --> x == 0
   %B = icmp eq i64 %A, 0
   ret i1 %B
 }
 
 define <2 x i1> @udiv_icmp2_vec(<2 x i64> %X) {
 ; CHECK-LABEL: @udiv_icmp2_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i64> %X, zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
-  %A = udiv exact <2 x i64> %X, <i64 5, i64 5>
+  %A = udiv exact nof <2 x i64> %X, <i64 5, i64 5>
   %B = icmp eq <2 x i64> %A, zeroinitializer
   ret <2 x i1> %B
 }
 
 define i1 @sdiv_icmp1(i64 %X) {
 ; CHECK-LABEL: @sdiv_icmp1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 %X, 0
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %A = sdiv exact i64 %X, 5   ; X/5 == 0 --> x == 0
+  %A = sdiv exact nof i64 %X, 5   ; X/5 == 0 --> x == 0
   %B = icmp eq i64 %A, 0
   ret i1 %B
 }
 
 define <2 x i1> @sdiv_icmp1_vec(<2 x i64> %X) {
 ; CHECK-LABEL: @sdiv_icmp1_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i64> %X, zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
-  %A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
+  %A = sdiv exact nof <2 x i64> %X, <i64 5, i64 5>
   %B = icmp eq <2 x i64> %A, zeroinitializer
   ret <2 x i1> %B
 }
 
 define i1 @sdiv_icmp2(i64 %X) {
 ; CHECK-LABEL: @sdiv_icmp2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 %X, 5
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %A = sdiv exact i64 %X, 5   ; X/5 == 1 --> x == 5
+  %A = sdiv exact nof i64 %X, 5   ; X/5 == 1 --> x == 5
   %B = icmp eq i64 %A, 1
   ret i1 %B
 }
 
 define <2 x i1> @sdiv_icmp2_vec(<2 x i64> %X) {
 ; CHECK-LABEL: @sdiv_icmp2_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 5, i64 5>
 ; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
-  %A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
+  %A = sdiv exact nof <2 x i64> %X, <i64 5, i64 5>
   %B = icmp eq <2 x i64> %A, <i64 1, i64 1>
   ret <2 x i1> %B
 }
 
 define i1 @sdiv_icmp3(i64 %X) {
 ; CHECK-LABEL: @sdiv_icmp3(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 %X, -5
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %A = sdiv exact i64 %X, 5   ; X/5 == -1 --> x == -5
+  %A = sdiv exact nof i64 %X, 5   ; X/5 == -1 --> x == -5
   %B = icmp eq i64 %A, -1
   ret i1 %B
 }
 
 define <2 x i1> @sdiv_icmp3_vec(<2 x i64> %X) {
 ; CHECK-LABEL: @sdiv_icmp3_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 -5, i64 -5>
 ; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
-  %A = sdiv exact <2 x i64> %X, <i64 5, i64 5>
+  %A = sdiv exact nof <2 x i64> %X, <i64 5, i64 5>
   %B = icmp eq <2 x i64> %A, <i64 -1, i64 -1>
   ret <2 x i1> %B
 }
 
 define i1 @sdiv_icmp4(i64 %X) {
 ; CHECK-LABEL: @sdiv_icmp4(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 %X, 0
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %A = sdiv exact i64 %X, -5   ; X/-5 == 0 --> x == 0
+  %A = sdiv exact nof i64 %X, -5   ; X/-5 == 0 --> x == 0
   %B = icmp eq i64 %A, 0
   ret i1 %B
 }
 
 define <2 x i1> @sdiv_icmp4_vec(<2 x i64> %X) {
 ; CHECK-LABEL: @sdiv_icmp4_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i64> %X, zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
-  %A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
+  %A = sdiv exact nof <2 x i64> %X, <i64 -5, i64 -5>
   %B = icmp eq <2 x i64> %A, zeroinitializer
   ret <2 x i1> %B
 }
 
 define i1 @sdiv_icmp5(i64 %X) {
 ; CHECK-LABEL: @sdiv_icmp5(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 %X, -5
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %A = sdiv exact i64 %X, -5   ; X/-5 == 1 --> x == -5
+  %A = sdiv exact nof i64 %X, -5   ; X/-5 == 1 --> x == -5
   %B = icmp eq i64 %A, 1
   ret i1 %B
 }
 
 define <2 x i1> @sdiv_icmp5_vec(<2 x i64> %X) {
 ; CHECK-LABEL: @sdiv_icmp5_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 -5, i64 -5>
 ; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
-  %A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
+  %A = sdiv exact nof <2 x i64> %X, <i64 -5, i64 -5>
   %B = icmp eq <2 x i64> %A, <i64 1, i64 1>
   ret <2 x i1> %B
 }
 
 define i1 @sdiv_icmp6(i64 %X) {
 ; CHECK-LABEL: @sdiv_icmp6(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i64 %X, 5
 ; CHECK-NEXT:    ret i1 [[TMP1]]
 ;
-  %A = sdiv exact i64 %X, -5   ; X/-5 == -1 --> x == 5
+  %A = sdiv exact nof i64 %X, -5   ; X/-5 == -1 --> x == 5
   %B = icmp eq i64 %A, -1
   ret i1 %B
 }
 
 define <2 x i1> @sdiv_icmp6_vec(<2 x i64> %X) {
 ; CHECK-LABEL: @sdiv_icmp6_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i64> %X, <i64 5, i64 5>
 ; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
 ;
-  %A = sdiv exact <2 x i64> %X, <i64 -5, i64 -5>
+  %A = sdiv exact nof <2 x i64> %X, <i64 -5, i64 -5>
   %B = icmp eq <2 x i64> %A, <i64 -1, i64 -1>
   ret <2 x i1> %B
 }
 

test/Transforms/InstCombine/getelementptr.ll

 ; CHECK-NEXT:  [[SUB:%.*]] = sub i64 [[PTRTOINT2]], [[PTRTOINT1]]
 ; CHECK-NEXT:  [[INTTOPTR:%.*]] = inttoptr i64 [[SUB]] to i16*
 ; CHECK-NEXT:  ret i16* [[INTTOPTR]]
 }
 
 define %struct.C* @test44(%struct.C* %c1, %struct.C* %c2) {
   %ptrtoint = ptrtoint %struct.C* %c1 to i64
   %sub = sub i64 0, %ptrtoint
-  %shr = sdiv i64 %sub, 7
+  %shr = sdiv nof i64 %sub, 7
   %gep = getelementptr inbounds %struct.C, %struct.C* %c2, i64 %shr
   ret %struct.C* %gep
 
 ; CHECK-LABEL: @test44(
 ; CHECK-NEXT:  [[PTRTOINT1:%.*]] = ptrtoint %struct.C* %c1 to i64
 ; CHECK-NEXT:  [[PTRTOINT2:%.*]] = ptrtoint %struct.C* %c2 to i64
 ; CHECK-NEXT:  [[SUB:%.*]] = sub i64 [[PTRTOINT2]], [[PTRTOINT1]]
 ; CHECK-NEXT:  [[INTTOPTR:%.*]] = inttoptr i64 [[SUB]] to %struct.C*
 ; CHECK-NEXT:  ret %struct.C* [[INTTOPTR]]
 }
 
 define %struct.C* @test45(%struct.C* %c1, %struct.C** %c2) {
   %ptrtoint1 = ptrtoint %struct.C* %c1 to i64
   %ptrtoint2 = ptrtoint %struct.C** %c2 to i64
   %sub = sub i64 %ptrtoint2, %ptrtoint1 ; C2 - C1
-  %shr = sdiv i64 %sub, 7
+  %shr = sdiv nof i64 %sub, 7
   %gep = getelementptr inbounds %struct.C, %struct.C* %c1, i64 %shr ; C1 + (C2 - C1)
   ret %struct.C* %gep
 
 ; CHECK-LABEL: @test45(
 ; CHECK-NEXT:  [[BITCAST:%.*]] = bitcast %struct.C** %c2 to %struct.C*
 ; CHECK-NEXT:  ret %struct.C* [[BITCAST]]
 }
 
 define %struct.C* @test46(%struct.C* %c1, %struct.C* %c2, i64 %N) {
   %ptrtoint = ptrtoint %struct.C* %c1 to i64
   %sub = sub i64 0, %ptrtoint
-  %sdiv = sdiv i64 %sub, %N
+  %sdiv = sdiv nof i64 %sub, %N
   %gep = getelementptr inbounds %struct.C, %struct.C* %c2, i64 %sdiv
   ret %struct.C* %gep
 
 ; CHECK-LABEL: @test46(
 ; CHECK-NEXT:  [[PTRTOINT:%.*]] = ptrtoint %struct.C* %c1 to i64
 ; CHECK-NEXT:  [[SUB:%.*]] = sub i64 0, [[PTRTOINT]]
-; CHECK-NEXT:  [[SDIV:%.*]] = sdiv i64 [[SUB]], %N
+; CHECK-NEXT:  [[SDIV:%.*]] = sdiv nof i64 [[SUB]], %N
 ; CHECK-NEXT:  [[GEP:%.*]] = getelementptr inbounds %struct.C, %struct.C* %c2, i64 %sdiv
 ; CHECK-NEXT:  ret %struct.C* [[GEP]]
 }
 
 define i32* @test47(i32* %I, i64 %C, i64 %D) {
   %sub = sub i64 %D, %C
   %A = getelementptr i32, i32* %I, i64 %C
   %B = getelementptr i32, i32* %A, i64 %sub

test/Transforms/InstCombine/hoist_instr.ll

 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 ;; This tests that the div is hoisted into the then block.
 define i32 @foo(i1 %C, i32 %A, i32 %B) {
 entry:
         br i1 %C, label %then, label %endif
 
 then:           ; preds = %entry
 ; CHECK: then:
-; CHECK-NEXT: sdiv i32
+; CHECK-NEXT: sdiv nof i32
         br label %endif
 
 endif:          ; preds = %then, %entry
         %X = phi i32 [ %A, %then ], [ 15, %entry ]              ; <i32> [#uses=1]
-        %Y = sdiv i32 %X, 42            ; <i32> [#uses=1]
+        %Y = sdiv nof i32 %X, 42            ; <i32> [#uses=1]
         ret i32 %Y
 }
 

test/Transforms/InstCombine/icmp.ll

 }
 
 ; PR2740
 define i1 @test23(i32 %x) {
 ; CHECK-LABEL: @test23(
 ; CHECK-NEXT:    [[I4:%.*]] = icmp sgt i32 %x, 1328634634
 ; CHECK-NEXT:    ret i1 [[I4]]
 ;
-  %i3 = sdiv i32 %x, -1328634635
+  %i3 = sdiv nof i32 %x, -1328634635
   %i4 = icmp eq i32 %i3, -1
   ret i1 %i4
 }
 
 define <2 x i1> @test23vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test23vec(
 ; CHECK-NEXT:    [[I4:%.*]] = icmp sgt <2 x i32> %x, <i32 1328634634, i32 1328634634>
 ; CHECK-NEXT:    ret <2 x i1> [[I4]]
 ;
-  %i3 = sdiv <2 x i32> %x, <i32 -1328634635, i32 -1328634635>
+  %i3 = sdiv nof <2 x i32> %x, <i32 -1328634635, i32 -1328634635>
   %i4 = icmp eq <2 x i32> %i3, <i32 -1, i32 -1>
   ret <2 x i1> %i4
 }
 
 @X = global [1000 x i32] zeroinitializer
 
 ; PR8882
 define i1 @test24(i64 %i) {

 }
 
 ; PR9343 #8
 define i1 @test48(i32 %X, i32 %Y, i32 %Z) {
 ; CHECK-LABEL: @test48(
 ; CHECK-NEXT:    [[C:%.*]] = icmp eq i32 %X, %Y
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
-  %A = sdiv exact i32 %X, %Z
-  %B = sdiv exact i32 %Y, %Z
+  %A = sdiv exact nof i32 %X, %Z
+  %B = sdiv exact nof i32 %Y, %Z
   %C = icmp eq i32 %A, %B
   ret i1 %C
 }
 
 ; The above transform only works for equality predicates.
 
 define i1 @PR32949(i32 %X, i32 %Y, i32 %Z) {
 ; CHECK-LABEL: @PR32949(
-; CHECK-NEXT:    [[A:%.*]] = sdiv exact i32 %X, %Z
-; CHECK-NEXT:    [[B:%.*]] = sdiv exact i32 %Y, %Z
+; CHECK-NEXT:    [[A:%.*]] = sdiv exact nof i32 %X, %Z
+; CHECK-NEXT:    [[B:%.*]] = sdiv exact nof i32 %Y, %Z
 ; CHECK-NEXT:    [[C:%.*]] = icmp sgt i32 [[A]], [[B]]
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
-  %A = sdiv exact i32 %X, %Z
-  %B = sdiv exact i32 %Y, %Z
+  %A = sdiv exact nof i32 %X, %Z
+  %B = sdiv exact nof i32 %Y, %Z
   %C = icmp sgt i32 %A, %B
   ret i1 %C
 }
 
 ; PR8469
 define <2 x i1> @test49(<2 x i32> %tmp3) {
 ; CHECK-LABEL: @test49(
 ; CHECK-NEXT:  entry:
;
 
   %A = and i1 %cmp, %cmp15
   ret i1 %A
 }
 
 ; PR9838
 define i1 @test53(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test53(
-; CHECK-NEXT:    [[X:%.*]] = sdiv exact i32 %a, 30
-; CHECK-NEXT:    [[Y:%.*]] = sdiv i32 %b, 30
+; CHECK-NEXT:    [[X:%.*]] = sdiv exact nof i32 %a, 30
+; CHECK-NEXT:    [[Y:%.*]] = sdiv nof i32 %b, 30
 ; CHECK-NEXT:    [[Z:%.*]] = icmp eq i32 [[X]], [[Y]]
 ; CHECK-NEXT:    ret i1 [[Z]]
 ;
-  %x = sdiv exact i32 %a, 30
-  %y = sdiv i32 %b, 30
+  %x = sdiv exact nof i32 %a, 30
+  %y = sdiv nof i32 %b, 30
   %z = icmp eq i32 %x, %y
   ret i1 %z
 }
 
 define i1 @test54(i8 %a) {
 ; CHECK-LABEL: @test54(
 ; CHECK-NEXT:    [[AND:%.*]] = and i8 %a, -64
 ; CHECK-NEXT:    [[RET:%.*]] = icmp eq i8 [[AND]], -128

test/Transforms/InstCombine/nsw.ll

 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 ; CHECK-LABEL: @sub1(
 ; CHECK: %y = sub i32 0, %x
-; CHECK: %z = sdiv i32 %y, 337
+; CHECK: %z = sdiv nof i32 %y, 337
 ; CHECK: ret i32 %z
 define i32 @sub1(i32 %x) {
   %y = sub i32 0, %x
-  %z = sdiv i32 %y, 337
+  %z = sdiv nof i32 %y, 337
   ret i32 %z
 }
 
 ; CHECK-LABEL: @sub2(
-; CHECK: %z = sdiv i32 %x, -337
+; CHECK: %z = sdiv nof i32 %x, -337
 ; CHECK: ret i32 %z
 define i32 @sub2(i32 %x) {
   %y = sub nsw i32 0, %x
-  %z = sdiv i32 %y, 337
+  %z = sdiv nof i32 %y, 337
   ret i32 %z
 }
 
 ; CHECK-LABEL: @shl_icmp(
 ; CHECK: %B = icmp eq i64 %X, 0
 ; CHECK: ret i1 %B
 define i1 @shl_icmp(i64 %X) nounwind {
   %A = shl nuw i64 %X, 2   ; X/4

test/Transforms/InstCombine/preserve-sminmax.ll

 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-; Instcombine normally would fold the sdiv into the comparison,
-; making "icmp slt i32 %h, 2", but in this case the sdiv has
+; Instcombine normally would fold the sdiv nof into the comparison,
+; making "icmp slt i32 %h, 2", but in this case the sdiv nof has
 ; another use, so it wouldn't a big win, and it would also
 ; obfuscate an otherise obvious smax pattern to the point where
 ; other analyses wouldn't recognize it.
 
 define i32 @foo(i32 %h) {
-  %sd = sdiv i32 %h, 2
+  %sd = sdiv nof i32 %h, 2
   %t = icmp slt i32 %sd, 1
   %r = select i1 %t, i32 %sd, i32 1
   ret i32 %r
 }
 
-; CHECK:  %sd = sdiv i32 %h, 2
+; CHECK:  %sd = sdiv nof i32 %h, 2
 ; CHECK:  %t = icmp slt i32 %sd, 1
 ; CHECK:  %r = select i1 %t, i32 %sd, i32 1
 ; CHECK:  ret i32 %r
 
 define i32 @bar(i32 %h) {
-  %sd = sdiv i32 %h, 2
+  %sd = sdiv nof i32 %h, 2
   %t = icmp sgt i32 %sd, 1
   %r = select i1 %t, i32 %sd, i32 1
   ret i32 %r
 }
 
-; CHECK:  %sd = sdiv i32 %h, 2
+; CHECK:  %sd = sdiv nof i32 %h, 2
 ; CHECK:  %t = icmp sgt i32 %sd, 1
 ; CHECK:  %r = select i1 %t, i32 %sd, i32 1
 ; CHECK:  ret i32 %r
 

test/Transforms/InstCombine/rem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i64 @rem_signed(i64 %x1, i64 %y2) {
 ; CHECK-LABEL: @rem_signed(
 ; CHECK-NEXT:    [[R:%.*]] = srem i64 %x1, %y2
 ; CHECK-NEXT:    ret i64 [[R]]
 ;
-  %r = sdiv i64 %x1, %y2
+  %r = sdiv nof i64 %x1, %y2
   %r7 = mul i64 %r, %y2
   %r8 = sub i64 %x1, %r7
   ret i64 %r8
 }
 
 define <4 x i32> @rem_signed_vec(<4 x i32> %t, <4 x i32> %u) {
 ; CHECK-LABEL: @rem_signed_vec(
 ; CHECK-NEXT:    [[K:%.*]] = srem <4 x i32> %t, %u
 ; CHECK-NEXT:    ret <4 x i32> [[K]]
 ;
-  %k = sdiv <4 x i32> %t, %u
+  %k = sdiv nof <4 x i32> %t, %u
   %l = mul <4 x i32> %k, %u
   %m = sub <4 x i32> %t, %l
   ret <4 x i32> %m
 }
 
 define i64 @rem_unsigned(i64 %x1, i64 %y2) {
 ; CHECK-LABEL: @rem_unsigned(
 ; CHECK-NEXT:    [[R:%.*]] = urem i64 %x1, %y2
 ; CHECK-NEXT:    ret i64 [[R]]
 ;
-  %r = udiv i64 %x1, %y2
+  %r = udiv nof i64 %x1, %y2
   %r7 = mul i64 %r, %y2
   %r8 = sub i64 %x1, %r7
   ret i64 %r8
 }
 
 ; PR28672 - https://llvm.org/bugs/show_bug.cgi?id=28672
 
 define i8 @big_divisor(i8 %x) {
;
   ret <2 x i4> %rem
 }
 
 define i8 @urem1(i8 %x, i8 %y) {
 ; CHECK-LABEL: @urem1(
 ; CHECK-NEXT:    [[A:%.*]] = urem i8 %x, %y
 ; CHECK-NEXT:    ret i8 [[A]]
 ;
-  %A = udiv i8 %x, %y
+  %A = udiv nof i8 %x, %y
   %B = mul i8 %A, %y
   %C = sub i8 %x, %B
   ret i8 %C
 }
 
 define i8 @srem1(i8 %x, i8 %y) {
 ; CHECK-LABEL: @srem1(
 ; CHECK-NEXT:    [[A:%.*]] = srem i8 %x, %y
 ; CHECK-NEXT:    ret i8 [[A]]
 ;
-  %A = sdiv i8 %x, %y
+  %A = sdiv nof i8 %x, %y
   %B = mul i8 %A, %y
   %C = sub i8 %x, %B
   ret i8 %C
 }
 
 define i8 @urem2(i8 %x, i8 %y) {
 ; CHECK-LABEL: @urem2(
 ; CHECK-NEXT:    [[A:%.*]] = urem i8 %x, %y
 ; CHECK-NEXT:    [[C:%.*]] = sub i8 0, [[A]]
 ; CHECK-NEXT:    ret i8 [[C]]
 ;
-  %A = udiv i8 %x, %y
+  %A = udiv nof i8 %x, %y
   %B = mul i8 %A, %y
   %C = sub i8 %B, %x
   ret i8 %C
 }
 
 define i8 @urem3(i8 %x) {
 ; CHECK-LABEL: @urem3(
 ; CHECK-NEXT:    [[A:%.*]] = urem i8 %x, 3
 ; CHECK-NEXT:    [[B1:%.*]] = sub i8 %x, [[A]]
 ; CHECK-NEXT:    [[C:%.*]] = add i8 [[B1]], %x
 ; CHECK-NEXT:    ret i8 [[C]]
 ;
-  %A = udiv i8 %x, 3
+  %A = udiv nof i8 %x, 3
   %B = mul i8 %A, -3
   %C = sub i8 %x, %B
   ret i8 %C
 }
 
 ; (((X / Y) * Y) / Y) -> X / Y
 
 define i32 @sdiv_mul_sdiv(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sdiv_mul_sdiv(
-; CHECK-NEXT:    [[R:%.*]] = sdiv i32 %x, %y
+; CHECK-NEXT:    [[R:%.*]] = sdiv nof i32 %x, %y
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
-  %div = sdiv i32 %x, %y
+  %div = sdiv nof i32 %x, %y
   %mul = mul i32 %div, %y
-  %r = sdiv i32 %mul, %y
+  %r = sdiv nof i32 %mul, %y
   ret i32 %r
 }
 
 ; (((X / Y) * Y) / Y) -> X / Y
 
 define i32 @udiv_mul_udiv(i32 %x, i32 %y) {
 ; CHECK-LABEL: @udiv_mul_udiv(
-; CHECK-NEXT:    [[R:%.*]] = udiv i32 %x, %y
+; CHECK-NEXT:    [[R:%.*]] = udiv nof i32 %x, %y
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
-  %div = udiv i32 %x, %y
+  %div = udiv nof i32 %x, %y
   %mul = mul i32 %div, %y
-  %r = udiv i32 %mul, %y
+  %r = udiv nof i32 %mul, %y
   ret i32 %r
 }
 
 define i32 @test1(i32 %A) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    ret i32 0
 ;
   %B = srem i32 %A, 1 ; ISA constant 0

test/Transforms/InstCombine/select.ll

 ; CHECK: icmp eq i32* %X, null
 ; CHECK: xor i1 %C, true
 ; CHECK: %RV = or i1
 ; CHECK: ret i1 %RV
 }
 
 define i32 @test18(i32 %X, i32 %Y, i1 %C) {
         %R = select i1 %C, i32 %X, i32 0
-        %V = sdiv i32 %Y, %R
+        %V = sdiv nof i32 %Y, %R
         ret i32 %V
 ; CHECK-LABEL: @test18(
-; CHECK: %V = sdiv i32 %Y, %X
+; CHECK: %V = sdiv nof i32 %Y, %X
 ; CHECK: ret i32 %V
 }
 
 define i32 @test19(i32 %x) {
         %tmp = icmp ugt i32 %x, 2147483647
         %retval = select i1 %tmp, i32 -1, i32 0
         ret i32 %retval
 ; CHECK-LABEL: @test19(

 lor.rhs:
   %p.addr.0.extract.trunc = trunc i32 %p.addr.0.insert.mask to i16
   %phitmp = zext i16 %p.addr.0.extract.trunc to i32
   br label %lor.end
 
 lor.end:
   %t.1 = phi i32 [ 0, %entry ], [ %phitmp, %lor.rhs ]
   %conv6 = zext i16 %b to i32
-  %div = udiv i32 %conv6, %t.1
+  %div = udiv nof i32 %conv6, %t.1
   %tobool8 = icmp eq i32 %div, 0
   %cmp = icmp eq i32 %t.1, 0
   %cmp12 = icmp ult i32 %conv2, 2
   %cmp.sink = select i1 %tobool8, i1 %cmp12, i1 %cmp
   br i1 %cmp.sink, label %cond.end17, label %cond.false16
 
 cond.false16:
   br label %cond.end17

test/Transforms/InstCombine/sext.ll

 ;
   %t = call i32 @llvm.cttz.i32(i32 %x, i1 true)
   %s = sext i32 %t to i64
   ret i64 %s
 }
 
 define i64 @test4(i32 %x) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    [[T:%.*]] = udiv i32 %x, 3
+; CHECK-NEXT:    [[T:%.*]] = udiv nof i32 %x, 3
 ; CHECK-NEXT:    [[S1:%.*]] = zext i32 [[T]] to i64
 ; CHECK-NEXT:    ret i64 [[S1]]
 ;
-  %t = udiv i32 %x, 3
+  %t = udiv nof i32 %x, 3
   %s = sext i32 %t to i64
   ret i64 %s
 }
 
 define i64 @test5(i32 %x) {
 ; CHECK-LABEL: @test5(
 ; CHECK-NEXT:    [[T:%.*]] = urem i32 %x, 30000
 ; CHECK-NEXT:    [[S1:%.*]] = zext i32 [[T]] to i64

test/Transforms/InstCombine/shift.ll

 }
 
 ;; ((A >>s 6) << 6 === (A & FFFFFFC0)
 define i8 @shishi(i8 %x) {
 ; CHECK-LABEL: @shishi(
 ; CHECK-NEXT:    [[A:%.*]] = ashr i8 [[X:%.*]], 6
 ; CHECK-NEXT:    [[B:%.*]] = and i8 [[X]], -64
 ; CHECK-NEXT:    [[EXTRA_USE_OF_A:%.*]] = mul nsw i8 [[A]], 5
-; CHECK-NEXT:    [[R:%.*]] = sdiv i8 [[EXTRA_USE_OF_A]], [[B]]
+; CHECK-NEXT:    [[R:%.*]] = sdiv nof i8 [[EXTRA_USE_OF_A]], [[B]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %a = ashr i8 %x, 6
   %b = shl i8 %a, 6
   %extra_use_of_a = mul i8 %a, 5
-  %r = sdiv i8 %extra_use_of_a, %b
+  %r = sdiv nof i8 %extra_use_of_a, %b
   ret i8 %r
 }
 
 ;; This transformation is deferred to DAGCombine:
 ;; (A >> 3) << 4 === (A & -8) * 2
 ;; The shl may be valuable to scalar evolution.
 define i8 @test13(i8 %A) {
 ; CHECK-LABEL: @test13(

 define i32 @test40(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: @test40(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 %b, 2
 ; CHECK-NEXT:    [[DIV:%.*]] = lshr i32 %a, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %shl1 = shl i32 1, %b
   %shl2 = shl i32 %shl1, 2
-  %div = udiv i32 %a, %shl2
+  %div = udiv nof i32 %a, %shl2
   ret i32 %div
 }
 
 define i32 @test41(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: @test41(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 8, %b
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %1 = shl i32 1, %b
   %2 = shl i32 %1, 3
   ret i32 %2
 }
 
 define i32 @test42(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: @test42(
 ; CHECK-NEXT:    [[DIV:%.*]] = lshr exact i32 4096, %b
-; CHECK-NEXT:    [[DIV2:%.*]] = udiv i32 %a, [[DIV]]
+; CHECK-NEXT:    [[DIV2:%.*]] = udiv nof i32 %a, [[DIV]]
 ; CHECK-NEXT:    ret i32 [[DIV2]]
 ;
   %div = lshr i32 4096, %b    ; must be exact otherwise we'd divide by zero
-  %div2 = udiv i32 %a, %div
+  %div2 = udiv nof i32 %a, %div
   ret i32 %div2
 }
 
 define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: @test42vec(
 ; CHECK-NEXT:    [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, %b
-; CHECK-NEXT:    [[DIV2:%.*]] = udiv <2 x i32> %a, [[DIV]]
+; CHECK-NEXT:    [[DIV2:%.*]] = udiv nof <2 x i32> %a, [[DIV]]
 ; CHECK-NEXT:    ret <2 x i32> [[DIV2]]
 ;
   %div = lshr <2 x i32> <i32 4096, i32 4096>, %b    ; must be exact otherwise we'd divide by zero
-  %div2 = udiv <2 x i32> %a, %div
+  %div2 = udiv nof <2 x i32> %a, %div
   ret <2 x i32> %div2
 }
 
 define i32 @test43(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: @test43(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 %b, 12
 ; CHECK-NEXT:    [[DIV2:%.*]] = lshr i32 %a, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[DIV2]]
 ;
   %div = shl i32 4096, %b    ; must be exact otherwise we'd divide by zero
-  %div2 = udiv i32 %a, %div
+  %div2 = udiv nof i32 %a, %div
   ret i32 %div2
 }
 
 define i32 @test44(i32 %a) nounwind {
 ; CHECK-LABEL: @test44(
 ; CHECK-NEXT:    [[Y:%.*]] = shl i32 %a, 5
 ; CHECK-NEXT:    ret i32 [[Y]]
 ;

test/Transforms/InstCombine/sink_instruction.ll

 ; RUN: opt -instcombine -S < %s | FileCheck %s
 
 ;; This tests that the instructions in the entry blocks are sunk into each
 ;; arm of the 'if'.
 
 define i32 @test1(i1 %C, i32 %A, i32 %B) {
 ; CHECK-LABEL: @test1(
 entry:
-        %tmp.2 = sdiv i32 %A, %B                ; <i32> [#uses=1]
+        %tmp.2 = sdiv nof i32 %A, %B                ; <i32> [#uses=1]
         %tmp.9 = add i32 %B, %A         ; <i32> [#uses=1]
         br i1 %C, label %then, label %endif
 
 then:           ; preds = %entry
         ret i32 %tmp.9
 
 endif:          ; preds = %entry
-; CHECK: sdiv i32
+; CHECK: sdiv nof i32
 ; CHECK-NEXT: ret i32
         ret i32 %tmp.2
 }
 
 
 ;; PHI use, sink divide before call.
 define i32 @test2(i32 %x) nounwind ssp {
 ; CHECK-LABEL: @test2(
-; CHECK-NOT: sdiv i32
+; CHECK-NOT: sdiv nof i32
 entry:
   br label %bb
 
 bb:                                               ; preds = %bb2, %entry
   %x_addr.17 = phi i32 [ %x, %entry ], [ %x_addr.0, %bb2 ] ; <i32> [#uses=4]
   %i.06 = phi i32 [ 0, %entry ], [ %4, %bb2 ]     ; <i32> [#uses=1]
   %0 = add nsw i32 %x_addr.17, 1                  ; <i32> [#uses=1]
-  %1 = sdiv i32 %0, %x_addr.17                    ; <i32> [#uses=1]
+  %1 = sdiv nof i32 %0, %x_addr.17                    ; <i32> [#uses=1]
   %2 = icmp eq i32 %x_addr.17, 0                  ; <i1> [#uses=1]
   br i1 %2, label %bb1, label %bb2
 
 bb1:                                              ; preds = %bb
 ; CHECK: bb1:
 ; CHECK-NEXT: add nsw i32 %x_addr.17, 1
-; CHECK-NEXT: sdiv i32
+; CHECK-NEXT: sdiv nof i32
 ; CHECK-NEXT: tail call i32 @bar()
   %3 = tail call i32 @bar() nounwind       ; <i32> [#uses=0]
   br label %bb2
 
 bb2:                                              ; preds = %bb, %bb1
   %x_addr.0 = phi i32 [ %1, %bb1 ], [ %x_addr.17, %bb ] ; <i32> [#uses=2]
   %4 = add nsw i32 %i.06, 1                       ; <i32> [#uses=2]
   %exitcond = icmp eq i32 %4, 1000000             ; <i1> [#uses=1]

test/Transforms/InstCombine/sub.ll

 ;
   %C = sub i32 0, %A
   %D = srem i32 %B, %C
   ret i32 %D
 }
 
 define i32 @test16(i32 %A) {
 ; CHECK-LABEL: @test16(
-; CHECK-NEXT:    [[Y:%.*]] = sdiv i32 [[A:%.*]], -1123
+; CHECK-NEXT:    [[Y:%.*]] = sdiv nof i32 [[A:%.*]], -1123
 ; CHECK-NEXT:    ret i32 [[Y]]
 ;
-  %X = sdiv i32 %A, 1123
+  %X = sdiv nof i32 %A, 1123
   %Y = sub i32 0, %X
   ret i32 %Y
 }
 
 ; Can't fold subtract here because negation it might oveflow.
 ; PR3142
 define i32 @test17(i32 %A) {
 ; CHECK-LABEL: @test17(
 ; CHECK-NEXT:    [[B:%.*]] = sub i32 0, [[A:%.*]]
-; CHECK-NEXT:    [[C:%.*]] = sdiv i32 [[B]], 1234
+; CHECK-NEXT:    [[C:%.*]] = sdiv nof i32 [[B]], 1234
 ; CHECK-NEXT:    ret i32 [[C]]
 ;
   %B = sub i32 0, %A
-  %C = sdiv i32 %B, 1234
+  %C = sdiv nof i32 %B, 1234
   ret i32 %C
 }
 
 define i64 @test18(i64 %Y) {
 ; CHECK-LABEL: @test18(
 ; CHECK-NEXT:    ret i64 0
 ;
   %tmp.4 = shl i64 %Y, 2

 }
 
 define <2 x i32> @test37(<2 x i32> %A) {
 ; CHECK-LABEL: @test37(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <2 x i32> [[A:%.*]], <i32 -2147483648, i32 -2147483648>
 ; CHECK-NEXT:    [[SUB:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[SUB]]
 ;
-  %div = sdiv <2 x i32> %A, <i32 -2147483648, i32 -2147483648>
+  %div = sdiv nof <2 x i32> %A, <i32 -2147483648, i32 -2147483648>
   %sub = sub nsw <2 x i32> zeroinitializer, %div
   ret <2 x i32> %sub
 }
 
 define i32 @test38(i32 %A) {
 ; CHECK-LABEL: @test38(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[A:%.*]], -2147483648
 ; CHECK-NEXT:    [[SUB:%.*]] = sext i1 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[SUB]]
 ;
-  %div = sdiv i32 %A, -2147483648
+  %div = sdiv nof i32 %A, -2147483648
   %sub = sub nsw i32 0, %div
   ret i32 %sub
 }
 
 define i32 @test39(i32 %A, i32 %x) {
 ; CHECK-LABEL: @test39(
 ; CHECK-NEXT:    [[C:%.*]] = add i32 [[X:%.*]], [[A:%.*]]
 ; CHECK-NEXT:    ret i32 [[C]]

test/Transforms/InstCombine/trunc-binop-ext.ll

;
   ret i16 %r
 }
 
 ; Verify that the commuted patterns work. The div is to ensure that complexity-based
 ; canonicalization doesn't swap the binop operands. Use vector types to show those work too.
 
 define <2 x i16> @narrow_sext_and_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_sext_and_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = and <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = sext <2 x i16> %x16 to <2 x i32>
   %b = and <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_zext_and_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_zext_and_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = and <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = zext <2 x i16> %x16 to <2 x i32>
   %b = and <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_sext_or_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_sext_or_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = or <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = sext <2 x i16> %x16 to <2 x i32>
   %b = or <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_zext_or_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_zext_or_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = or <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = zext <2 x i16> %x16 to <2 x i32>
   %b = or <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_sext_xor_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_sext_xor_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = xor <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = sext <2 x i16> %x16 to <2 x i32>
   %b = xor <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_zext_xor_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_zext_xor_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = xor <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = zext <2 x i16> %x16 to <2 x i32>
   %b = xor <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_sext_add_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_sext_add_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = add <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = sext <2 x i16> %x16 to <2 x i32>
   %b = add <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_zext_add_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_zext_add_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = add <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = zext <2 x i16> %x16 to <2 x i32>
   %b = add <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_sext_sub_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_sext_sub_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = sub <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = sext <2 x i16> %x16 to <2 x i32>
   %b = sub <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_zext_sub_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_zext_sub_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = sub <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = zext <2 x i16> %x16 to <2 x i32>
   %b = sub <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_sext_mul_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_sext_mul_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = mul <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = sext <2 x i16> %x16 to <2 x i32>
   %b = mul <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 
 define <2 x i16> @narrow_zext_mul_commute(<2 x i16> %x16, <2 x i32> %y32) {
 ; CHECK-LABEL: @narrow_zext_mul_commute(
-; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+; CHECK-NEXT:    [[Y32OP0:%.*]] = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
 ; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i32> [[Y32OP0]] to <2 x i16>
 ; CHECK-NEXT:    [[R:%.*]] = mul <2 x i16> [[TMP1]], %x16
 ; CHECK-NEXT:    ret <2 x i16> [[R]]
 ;
-  %y32op0 = sdiv <2 x i32> %y32, <i32 7, i32 -17>
+  %y32op0 = sdiv nof <2 x i32> %y32, <i32 7, i32 -17>
   %x32 = zext <2 x i16> %x16 to <2 x i32>
   %b = mul <2 x i32> %y32op0, %x32
   %r = trunc <2 x i32> %b to <2 x i16>
   ret <2 x i16> %r
 }
 

test/Transforms/InstCombine/udiv-simplify.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i64 @test1(i32 %x) nounwind {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    ret i64 0
 ;
   %y = lshr i32 %x, 1
-  %r = udiv i32 %y, -1
+  %r = udiv nof i32 %y, -1
   %z = sext i32 %r to i64
   ret i64 %z
 }
 define i64 @test2(i32 %x) nounwind {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    ret i64 0
 ;
   %y = lshr i32 %x, 31
-  %r = udiv i32 %y, 3
+  %r = udiv nof i32 %y, 3
   %z = sext i32 %r to i64
   ret i64 %z
 }
 
 ; The udiv instructions shouldn't be optimized away, and the
 ; sext instructions should be optimized to zext.
 
 define i64 @test1_PR2274(i32 %x, i32 %g) nounwind {
 ; CHECK-LABEL: @test1_PR2274(
 ; CHECK-NEXT:    [[Y:%.*]] = lshr i32 [[X:%.*]], 30
-; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[Y]], [[G:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = udiv nof i32 [[Y]], [[G:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[R]] to i64
 ; CHECK-NEXT:    ret i64 [[TMP1]]
 ;
   %y = lshr i32 %x, 30
-  %r = udiv i32 %y, %g
+  %r = udiv nof i32 %y, %g
   %z = sext i32 %r to i64
   ret i64 %z
 }
 define i64 @test2_PR2274(i32 %x, i32 %v) nounwind {
 ; CHECK-LABEL: @test2_PR2274(
 ; CHECK-NEXT:    [[Y:%.*]] = lshr i32 [[X:%.*]], 31
-; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[Y]], [[V:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = udiv nof i32 [[Y]], [[V:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[R]] to i64
 ; CHECK-NEXT:    ret i64 [[TMP1]]
 ;
   %y = lshr i32 %x, 31
-  %r = udiv i32 %y, %v
+  %r = udiv nof i32 %y, %v
   %z = sext i32 %r to i64
   ret i64 %z
 }
 
 ; The udiv should be simplified according to the rule:
 ; X udiv (C1 << N), where C1 is `1<<C2` --> X >> (N+C2)
 @b = external global [1 x i16]
 
 define i32 @PR30366(i1 %a) {
 ; CHECK-LABEL: @PR30366(
 ; CHECK-NEXT:    [[Z:%.*]] = zext i1 [[A:%.*]] to i32
 ; CHECK-NEXT:    [[D:%.*]] = lshr i32 [[Z]], zext (i16 ptrtoint ([1 x i16]* @b to i16) to i32)
 ; CHECK-NEXT:    ret i32 [[D]]
 ;
   %z = zext i1 %a to i32
-  %d = udiv i32 %z, zext (i16 shl (i16 1, i16 ptrtoint ([1 x i16]* @b to i16)) to i32)
+  %d = udiv nof i32 %z, zext (i16 shl (i16 1, i16 ptrtoint ([1 x i16]* @b to i16)) to i32)
   ret i32 %d
 }
 
 ; OSS-Fuzz #4857
 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4857
 define i177 @ossfuzz_4857(i177 %X, i177 %Y) {
 ; CHECK-LABEL: @ossfuzz_4857(
 ; CHECK-NEXT:    store i1 false, i1* undef, align 1
 ; CHECK-NEXT:    ret i177 0
 ;
-  %B5 = udiv i177 %Y, -1
+  %B5 = udiv nof i177 %Y, -1
   %B4 = add i177 %B5, -1
   %B2 = add i177 %B4, -1
   %B6 = mul i177 %B5, %B2
   %B3 = add i177 %B2, %B2
   %B9 = xor i177 %B4, %B3
   %B13 = ashr i177 %Y, %B2
   %B22 = add i177 %B9, %B13
-  %B1 = udiv i177 %B5, %B6
+  %B1 = udiv nof i177 %B5, %B6
   %C9 = icmp ult i177 %Y, %B22
   store i1 %C9, i1* undef
   ret i177 %B1
 }

test/Transforms/InstCombine/udivrem-change-width.ll

 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 target datalayout = "n8:32"
 
 ; PR4548
 define i8 @udiv_i8(i8 %a, i8 %b) {
 ; CHECK-LABEL: @udiv_i8(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i8 %a, %b
 ; CHECK-NEXT:    ret i8 [[DIV]]
 ;
   %za = zext i8 %a to i32
   %zb = zext i8 %b to i32
-  %udiv = udiv i32 %za, %zb
+  %udiv = udiv nof i32 %za, %zb
   %conv3 = trunc i32 %udiv to i8
   ret i8 %conv3
 }
 
 define <2 x i8> @udiv_i8_vec(<2 x i8> %a, <2 x i8> %b) {
 ; CHECK-LABEL: @udiv_i8_vec(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i8> %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof <2 x i8> %a, %b
 ; CHECK-NEXT:    ret <2 x i8> [[DIV]]
 ;
   %za = zext <2 x i8> %a to <2 x i32>
   %zb = zext <2 x i8> %b to <2 x i32>
-  %udiv = udiv <2 x i32> %za, %zb
+  %udiv = udiv nof <2 x i32> %za, %zb
   %conv3 = trunc <2 x i32> %udiv to <2 x i8>
   ret <2 x i8> %conv3
 }
 
 define i8 @urem_i8(i8 %a, i8 %b) {
 ; CHECK-LABEL: @urem_i8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, %b
 ; CHECK-NEXT:    ret i8 [[TMP1]]
;
   %zb = zext <2 x i8> %b to <2 x i32>
   %udiv = urem <2 x i32> %za, %zb
   %conv3 = trunc <2 x i32> %udiv to <2 x i8>
   ret <2 x i8> %conv3
 }
 
 define i32 @udiv_i32(i8 %a, i8 %b) {
 ; CHECK-LABEL: @udiv_i32(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i8 %a, %b
 ; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[DIV]] to i32
 ; CHECK-NEXT:    ret i32 [[UDIV]]
 ;
   %za = zext i8 %a to i32
   %zb = zext i8 %b to i32
-  %udiv = udiv i32 %za, %zb
+  %udiv = udiv nof i32 %za, %zb
   ret i32 %udiv
 }
 
 define <2 x i32> @udiv_i32_vec(<2 x i8> %a, <2 x i8> %b) {
 ; CHECK-LABEL: @udiv_i32_vec(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv <2 x i8> %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof <2 x i8> %a, %b
 ; CHECK-NEXT:    [[UDIV:%.*]] = zext <2 x i8> [[DIV]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[UDIV]]
 ;
   %za = zext <2 x i8> %a to <2 x i32>
   %zb = zext <2 x i8> %b to <2 x i32>
-  %udiv = udiv <2 x i32> %za, %zb
+  %udiv = udiv nof <2 x i32> %za, %zb
   ret <2 x i32> %udiv
 }
 
 define i32 @udiv_i32_multiuse(i8 %a, i8 %b) {
 ; CHECK-LABEL: @udiv_i32_multiuse(
 ; CHECK-NEXT:    [[ZA:%.*]] = zext i8 %a to i32
 ; CHECK-NEXT:    [[ZB:%.*]] = zext i8 %b to i32
-; CHECK-NEXT:    [[UDIV:%.*]] = udiv i32 [[ZA]], [[ZB]]
+; CHECK-NEXT:    [[UDIV:%.*]] = udiv nof i32 [[ZA]], [[ZB]]
 ; CHECK-NEXT:    [[EXTRA_USES:%.*]] = add nuw nsw i32 [[ZA]], [[ZB]]
 ; CHECK-NEXT:    [[R:%.*]] = mul nuw nsw i32 [[UDIV]], [[EXTRA_USES]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %za = zext i8 %a to i32
   %zb = zext i8 %b to i32
-  %udiv = udiv i32 %za, %zb
+  %udiv = udiv nof i32 %za, %zb
   %extra_uses = add i32 %za, %zb
   %r = mul i32 %udiv, %extra_uses
   ret i32 %r
 }
 
 define i32 @udiv_illegal_type(i9 %a, i9 %b) {
 ; CHECK-LABEL: @udiv_illegal_type(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i9 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i9 %a, %b
 ; CHECK-NEXT:    [[UDIV:%.*]] = zext i9 [[DIV]] to i32
 ; CHECK-NEXT:    ret i32 [[UDIV]]
 ;
   %za = zext i9 %a to i32
   %zb = zext i9 %b to i32
-  %udiv = udiv i32 %za, %zb
+  %udiv = udiv nof i32 %za, %zb
   ret i32 %udiv
 }
 
 define i32 @urem_i32(i8 %a, i8 %b) {
 ; CHECK-LABEL: @urem_i32(
 ; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, %b
 ; CHECK-NEXT:    [[UREM:%.*]] = zext i8 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[UREM]]
;
   %za = zext i9 %a to i32
   %zb = zext i9 %b to i32
   %urem = urem i32 %za, %zb
   ret i32 %urem
 }
 
 define i32 @udiv_i32_c(i8 %a) {
 ; CHECK-LABEL: @udiv_i32_c(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, 10
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i8 %a, 10
 ; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[DIV]] to i32
 ; CHECK-NEXT:    ret i32 [[UDIV]]
 ;
   %za = zext i8 %a to i32
-  %udiv = udiv i32 %za, 10
+  %udiv = udiv nof i32 %za, 10
   ret i32 %udiv
 }
 
 define <2 x i32> @udiv_i32_c_vec(<2 x i8> %a) {
 ; CHECK-LABEL: @udiv_i32_c_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = udiv <2 x i8> %a, <i8 10, i8 17>
+; CHECK-NEXT:    [[TMP1:%.*]] = udiv nof <2 x i8> %a, <i8 10, i8 17>
 ; CHECK-NEXT:    [[UDIV:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
 ; CHECK-NEXT:    ret <2 x i32> [[UDIV]]
 ;
   %za = zext <2 x i8> %a to <2 x i32>
-  %udiv = udiv <2 x i32> %za, <i32 10, i32 17>
+  %udiv = udiv nof <2 x i32> %za, <i32 10, i32 17>
   ret <2 x i32> %udiv
 }
 
 define i32 @udiv_i32_c_multiuse(i8 %a) {
 ; CHECK-LABEL: @udiv_i32_c_multiuse(
 ; CHECK-NEXT:    [[ZA:%.*]] = zext i8 %a to i32
-; CHECK-NEXT:    [[UDIV:%.*]] = udiv i32 [[ZA]], 10
+; CHECK-NEXT:    [[UDIV:%.*]] = udiv nof i32 [[ZA]], 10
 ; CHECK-NEXT:    [[EXTRA_USE:%.*]] = add nuw nsw i32 [[UDIV]], [[ZA]]
 ; CHECK-NEXT:    ret i32 [[EXTRA_USE]]
 ;
   %za = zext i8 %a to i32
-  %udiv = udiv i32 %za, 10
+  %udiv = udiv nof i32 %za, 10
   %extra_use = add i32 %za, %udiv
   ret i32 %extra_use
 }
 
 define i32 @udiv_illegal_type_c(i9 %a) {
 ; CHECK-LABEL: @udiv_illegal_type_c(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i9 %a, 10
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i9 %a, 10
 ; CHECK-NEXT:    [[UDIV:%.*]] = zext i9 [[DIV]] to i32
 ; CHECK-NEXT:    ret i32 [[UDIV]]
 ;
   %za = zext i9 %a to i32
-  %udiv = udiv i32 %za, 10
+  %udiv = udiv nof i32 %za, 10
   ret i32 %udiv
 }
 
 define i32 @urem_i32_c(i8 %a) {
 ; CHECK-LABEL: @urem_i32_c(
 ; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 %a, 10
 ; CHECK-NEXT:    [[UREM:%.*]] = zext i8 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[UREM]]

 ;
   %za = zext i9 %a to i32
   %urem = urem i32 %za, 10
   ret i32 %urem
 }
 
 define i32 @udiv_c_i32(i8 %a) {
 ; CHECK-LABEL: @udiv_c_i32(
-; CHECK-NEXT:    [[TMP1:%.*]] = udiv i8 10, %a
+; CHECK-NEXT:    [[TMP1:%.*]] = udiv nof i8 10, %a
 ; CHECK-NEXT:    [[UDIV:%.*]] = zext i8 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[UDIV]]
 ;
   %za = zext i8 %a to i32
-  %udiv = udiv i32 10, %za
+  %udiv = udiv nof i32 10, %za
   ret i32 %udiv
 }
 
 define i32 @urem_c_i32(i8 %a) {
 ; CHECK-LABEL: @urem_c_i32(
 ; CHECK-NEXT:    [[TMP1:%.*]] = urem i8 10, %a
 ; CHECK-NEXT:    [[UREM:%.*]] = zext i8 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[UREM]]
 ;
   %za = zext i8 %a to i32
   %urem = urem i32 10, %za
   ret i32 %urem
 }
 
 ; Make sure constexpr is handled.
 
 @b = external global [1 x i8]
 
 define i32 @udiv_constexpr(i8 %a) {
 ; CHECK-LABEL: @udiv_constexpr(
-; CHECK-NEXT:    [[TMP1:%.*]] = udiv i8 %a, ptrtoint ([1 x i8]* @b to i8)
+; CHECK-NEXT:    [[TMP1:%.*]] = udiv nof i8 %a, ptrtoint ([1 x i8]* @b to i8)
 ; CHECK-NEXT:    [[D:%.*]] = zext i8 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[D]]
 ;
   %za = zext i8 %a to i32
-  %d = udiv i32 %za, zext (i8 ptrtoint ([1 x i8]* @b to i8) to i32)
+  %d = udiv nof i32 %za, zext (i8 ptrtoint ([1 x i8]* @b to i8) to i32)
   ret i32 %d
 }
 

test/Transforms/InstSimplify/compare.ll

define i1 @srem3(i16 %X, i32 %Y) {
   %E = icmp slt i32 %D, 0
   ret i1 %E
 }
 
 define i1 @udiv2(i32 %Z) {
 ; CHECK-LABEL: @udiv2(
 ; CHECK-NEXT:    ret i1 true
 ;
-  %A = udiv exact i32 10, %Z
-  %B = udiv exact i32 20, %Z
+  %A = udiv exact nof i32 10, %Z
+  %B = udiv exact nof i32 20, %Z
   %C = icmp ult i32 %A, %B
   ret i1 %C
 }
 
-; Exact sdiv and equality preds can simplify.
+; Exact sdiv nof and equality preds can simplify.
 
 define i1 @sdiv_exact_equality(i32 %Z) {
 ; CHECK-LABEL: @sdiv_exact_equality(
 ; CHECK-NEXT:    ret i1 false
 ;
-  %A = sdiv exact i32 10, %Z
-  %B = sdiv exact i32 20, %Z
+  %A = sdiv exact nof i32 10, %Z
+  %B = sdiv exact nof i32 20, %Z
   %C = icmp eq i32 %A, %B
   ret i1 %C
 }
 
 ; But not other preds: PR32949 - https://bugs.llvm.org/show_bug.cgi?id=32949
 
 define i1 @sdiv_exact_not_equality(i32 %Z) {
 ; CHECK-LABEL: @sdiv_exact_not_equality(
-; CHECK-NEXT:    [[A:%.*]] = sdiv exact i32 10, %Z
-; CHECK-NEXT:    [[B:%.*]] = sdiv exact i32 20, %Z
+; CHECK-NEXT:    [[A:%.*]] = sdiv exact nof i32 10, %Z
+; CHECK-NEXT:    [[B:%.*]] = sdiv exact nof i32 20, %Z
 ; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[A]], [[B]]
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
-  %A = sdiv exact i32 10, %Z
-  %B = sdiv exact i32 20, %Z
+  %A = sdiv exact nof i32 10, %Z
+  %B = sdiv exact nof i32 20, %Z
   %C = icmp ult i32 %A, %B
   ret i1 %C
 }
 
 define i1 @udiv3(i32 %X, i32 %Y) {
 ; CHECK-LABEL: @udiv3(
-  %A = udiv i32 %X, %Y
+  %A = udiv nof i32 %X, %Y
   %C = icmp ugt i32 %A, %X
   ret i1 %C
 ; CHECK: ret i1 false
 }
 
 define i1 @udiv4(i32 %X, i32 %Y) {
 ; CHECK-LABEL: @udiv4(
-  %A = udiv i32 %X, %Y
+  %A = udiv nof i32 %X, %Y
   %C = icmp ule i32 %A, %X
   ret i1 %C
 ; CHECK: ret i1 true
 }
 
 ; PR11340
 define i1 @udiv6(i32 %X) nounwind {
 ; CHECK-LABEL: @udiv6(
-  %A = udiv i32 1, %X
+  %A = udiv nof i32 1, %X
   %C = icmp eq i32 %A, 0
   ret i1 %C
 ; CHECK: ret i1 %C
 }
 
 define i1 @udiv7(i32 %X, i32 %Y) {
 ; CHECK-LABEL: @udiv7(
-  %A = udiv i32 %X, %Y
+  %A = udiv nof i32 %X, %Y
   %C = icmp ult i32 %X, %A
   ret i1 %C
 ; CHECK: ret i1 false
 }
 
 define i1 @udiv8(i32 %X, i32 %Y) {
 ; CHECK-LABEL: @udiv8(
-  %A = udiv i32 %X, %Y
+  %A = udiv nof i32 %X, %Y
   %C = icmp uge i32 %X, %A
   ret i1 %C
 ; CHECK: ret i1 true
 }
 
 define i1 @mul1(i32 %X) {
 ; CHECK-LABEL: @mul1(
 ; Square of a non-zero number is non-zero if there is no overflow.

 ; CHECK-NEXT:    ret <2 x i1> <i1 true, i1 true>
 ;
   %b = mul nsw <2 x i32> %a, <i32 -2, i32 -2>
   %c = icmp ne <2 x i32> %b, <i32 1, i32 1>
   ret <2 x i1> %c
 }
 
 define i1 @icmp_sdiv_int_min(i32 %a) {
-  %div = sdiv i32 -2147483648, %a
+  %div = sdiv nof i32 -2147483648, %a
   %cmp = icmp ne i32 %div, -1073741824
   ret i1 %cmp
 
 ; CHECK-LABEL: @icmp_sdiv_int_min
-; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 -2147483648, %a
+; CHECK-NEXT: [[DIV:%.*]] = sdiv nof i32 -2147483648, %a
 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[DIV]], -1073741824
 ; CHECK-NEXT: ret i1 [[CMP]]
 }
 
 define i1 @icmp_sdiv_pr20288(i64 %a) {
-   %div = sdiv i64 %a, -8589934592
+   %div = sdiv nof i64 %a, -8589934592
    %cmp = icmp ne i64 %div, 1073741824
    ret i1 %cmp
 
 ; CHECK-LABEL: @icmp_sdiv_pr20288
-; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 %a, -8589934592
+; CHECK-NEXT: [[DIV:%.*]] = sdiv nof i64 %a, -8589934592
 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[DIV]], 1073741824
 ; CHECK-NEXT: ret i1 [[CMP]]
 }
 
 define i1 @icmp_sdiv_neg1(i64 %a) {
- %div = sdiv i64 %a, -1
+ %div = sdiv nof i64 %a, -1
  %cmp = icmp ne i64 %div, 1073741824
  ret i1 %cmp
 
 ; CHECK-LABEL: @icmp_sdiv_neg1
-; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 %a, -1
+; CHECK-NEXT: [[DIV:%.*]] = sdiv nof i64 %a, -1
 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[DIV]], 1073741824
 ; CHECK-NEXT: ret i1 [[CMP]]
 }
 
 define i1 @icmp_known_bits(i4 %x, i4 %y) {
   %and1 = and i4 %y, -7
   %and2 = and i4 %x, -7
   %or1 = or i4 %and1, 2

test/Transforms/InstSimplify/div.ll

 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 ; Division-by-zero is undef. UB in any vector lane means the whole op is undef.
 
 define <2 x i8> @sdiv_zero_elt_vec_constfold(<2 x i8> %x) {
 ; CHECK-LABEL: @sdiv_zero_elt_vec_constfold(
 ; CHECK-NEXT:    ret <2 x i8> undef
 ;
-  %div = sdiv <2 x i8> <i8 1, i8 2>, <i8 0, i8 -42>
+  %div = sdiv nof <2 x i8> <i8 1, i8 2>, <i8 0, i8 -42>
   ret <2 x i8> %div
 }
 
 define <2 x i8> @udiv_zero_elt_vec_constfold(<2 x i8> %x) {
 ; CHECK-LABEL: @udiv_zero_elt_vec_constfold(
 ; CHECK-NEXT:    ret <2 x i8> undef
 ;
-  %div = udiv <2 x i8> <i8 1, i8 2>, <i8 42, i8 0>
+  %div = udiv nof <2 x i8> <i8 1, i8 2>, <i8 42, i8 0>
   ret <2 x i8> %div
 }
 
 define <2 x i8> @sdiv_zero_elt_vec(<2 x i8> %x) {
 ; CHECK-LABEL: @sdiv_zero_elt_vec(
 ; CHECK-NEXT:    ret <2 x i8> undef
 ;
-  %div = sdiv <2 x i8> %x, <i8 -42, i8 0>
+  %div = sdiv nof <2 x i8> %x, <i8 -42, i8 0>
   ret <2 x i8> %div
 }
 
 define <2 x i8> @udiv_zero_elt_vec(<2 x i8> %x) {
 ; CHECK-LABEL: @udiv_zero_elt_vec(
 ; CHECK-NEXT:    ret <2 x i8> undef
 ;
-  %div = udiv <2 x i8> %x, <i8 0, i8 42>
+  %div = udiv nof <2 x i8> %x, <i8 0, i8 42>
   ret <2 x i8> %div
 }
 
 define <2 x i8> @sdiv_undef_elt_vec(<2 x i8> %x) {
 ; CHECK-LABEL: @sdiv_undef_elt_vec(
 ; CHECK-NEXT:    ret <2 x i8> undef
 ;
   %div = sdiv <2 x i8> %x, <i8 -42, i8 undef>

 ; Division-by-zero is undef. UB in any vector lane means the whole op is undef.
 ; Thus, we can simplify this: if any element of 'y' is 0, we can do anything.
 ; Therefore, assume that all elements of 'y' must be 1.
 
 define <2 x i1> @sdiv_bool_vec(<2 x i1> %x, <2 x i1> %y) {
 ; CHECK-LABEL: @sdiv_bool_vec(
 ; CHECK-NEXT:    ret <2 x i1> %x
 ;
-  %div = sdiv <2 x i1> %x, %y
+  %div = sdiv nof <2 x i1> %x, %y
   ret <2 x i1> %div
 }
 
 define <2 x i1> @udiv_bool_vec(<2 x i1> %x, <2 x i1> %y) {
 ; CHECK-LABEL: @udiv_bool_vec(
 ; CHECK-NEXT:    ret <2 x i1> %x
 ;
-  %div = udiv <2 x i1> %x, %y
+  %div = udiv nof <2 x i1> %x, %y
   ret <2 x i1> %div
 }
 
 define i32 @udiv_dividend_known_smaller_than_constant_divisor(i32 %x) {
 ; CHECK-LABEL: @udiv_dividend_known_smaller_than_constant_divisor(
 ; CHECK-NEXT:    ret i32 0
 ;
   %and = and i32 %x, 250
-  %div = udiv i32 %and, 251
+  %div = udiv nof i32 %and, 251
   ret i32 %div
 }
 
 define i32 @not_udiv_dividend_known_smaller_than_constant_divisor(i32 %x) {
 ; CHECK-LABEL: @not_udiv_dividend_known_smaller_than_constant_divisor(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %x, 251
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[AND]], 251
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 [[AND]], 251
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %and = and i32 %x, 251
-  %div = udiv i32 %and, 251
+  %div = udiv nof i32 %and, 251
   ret i32 %div
 }
 
 define i32 @udiv_constant_dividend_known_smaller_than_divisor(i32 %x) {
 ; CHECK-LABEL: @udiv_constant_dividend_known_smaller_than_divisor(
 ; CHECK-NEXT:    ret i32 0
 ;
   %or = or i32 %x, 251
-  %div = udiv i32 250, %or
+  %div = udiv nof i32 250, %or
   ret i32 %div
 }
 
 define i32 @not_udiv_constant_dividend_known_smaller_than_divisor(i32 %x) {
 ; CHECK-LABEL: @not_udiv_constant_dividend_known_smaller_than_divisor(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 %x, 251
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 251, [[OR]]
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 251, [[OR]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %or = or i32 %x, 251
-  %div = udiv i32 251, %or
+  %div = udiv nof i32 251, %or
   ret i32 %div
 }
 
 ; This would require computing known bits on both x and y. Is it worth doing?
 
 define i32 @udiv_dividend_known_smaller_than_divisor(i32 %x, i32 %y) {
 ; CHECK-LABEL: @udiv_dividend_known_smaller_than_divisor(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %x, 250
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 %y, 251
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[AND]], [[OR]]
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 [[AND]], [[OR]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %and = and i32 %x, 250
   %or = or i32 %y, 251
-  %div = udiv i32 %and, %or
+  %div = udiv nof i32 %and, %or
   ret i32 %div
 }
 
 define i32 @not_udiv_dividend_known_smaller_than_divisor(i32 %x, i32 %y) {
 ; CHECK-LABEL: @not_udiv_dividend_known_smaller_than_divisor(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %x, 251
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 %y, 251
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[AND]], [[OR]]
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 [[AND]], [[OR]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %and = and i32 %x, 251
   %or = or i32 %y, 251
-  %div = udiv i32 %and, %or
+  %div = udiv nof i32 %and, %or
   ret i32 %div
 }
 
 declare i32 @external()
 
 define i32 @div1() {
 ; CHECK-LABEL: @div1(
 ; CHECK-NEXT:    [[CALL:%.*]] = call i32 @external(), !range !0
 ; CHECK-NEXT:    ret i32 0
 ;
   %call = call i32 @external(), !range !0
-  %urem = udiv i32 %call, 3
+  %urem = udiv nof i32 %call, 3
   ret i32 %urem
 }
 
 !0 = !{i32 0, i32 3}

test/Transforms/InstSimplify/reassociate.ll

 
 ; (no overflow X * Y) / Y -> X
 
 define i32 @mulnsw_sdiv(i32 %x, i32 %y) {
 ; CHECK-LABEL: @mulnsw_sdiv(
 ; CHECK-NEXT:    ret i32 [[X:%.*]]
 ;
   %mul = mul nsw i32 %x, %y
-  %r = sdiv i32 %mul, %y
+  %r = sdiv nof i32 %mul, %y
   ret i32 %r
 }
 
 define <2 x i32> @mulnsw_sdiv_commute(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @mulnsw_sdiv_commute(
 ; CHECK-NEXT:    ret <2 x i32> [[X:%.*]]
 ;
   %mul = mul nsw <2 x i32> %y, %x
-  %r = sdiv <2 x i32> %mul, %y
+  %r = sdiv nof <2 x i32> %mul, %y
   ret <2 x i32> %r
 }
 
 ; (no overflow X * Y) / Y -> X
 
 define <2 x i8> @mulnuw_udiv(<2 x i8> %x, <2 x i8> %y) {
 ; CHECK-LABEL: @mulnuw_udiv(
 ; CHECK-NEXT:    ret <2 x i8> [[X:%.*]]
 ;
   %mul = mul nuw <2 x i8> %x, %y
-  %r = udiv <2 x i8> %mul, %y
+  %r = udiv nof <2 x i8> %mul, %y
   ret <2 x i8> %r
 }
 
 define i32 @mulnuw_udiv_commute(i32 %x, i32 %y) {
 ; CHECK-LABEL: @mulnuw_udiv_commute(
 ; CHECK-NEXT:    ret i32 [[X:%.*]]
 ;
   %mul = mul nuw i32 %y, %x
-  %r = udiv i32 %mul, %y
+  %r = udiv nof i32 %mul, %y
   ret i32 %r
 }
 
 ; (((X / Y) * Y) / Y) -> X / Y
 
 define i32 @sdiv_mul_sdiv(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sdiv_mul_sdiv(
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
-  %div = sdiv i32 %x, %y
+  %div = sdiv nof i32 %x, %y
   %mul = mul i32 %div, %y
-  %r = sdiv i32 %mul, %y
+  %r = sdiv nof i32 %mul, %y
   ret i32 %r
 }
 
 define i32 @sdiv_mul_sdiv_commute(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sdiv_mul_sdiv_commute(
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
-  %div = sdiv i32 %x, %y
+  %div = sdiv nof i32 %x, %y
   %mul = mul i32 %y, %div
-  %r = sdiv i32 %mul, %y
+  %r = sdiv nof i32 %mul, %y
   ret i32 %r
 }
 
 ; (((X / Y) * Y) / Y) -> X / Y
 
 define i32 @udiv_mul_udiv(i32 %x, i32 %y) {
 ; CHECK-LABEL: @udiv_mul_udiv(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
-  %div = udiv i32 %x, %y
+  %div = udiv nof i32 %x, %y
   %mul = mul i32 %div, %y
-  %r = udiv i32 %mul, %y
+  %r = udiv nof i32 %mul, %y
   ret i32 %r
 }
 
 define i32 @udiv_mul_udiv_commute(i32 %x, i32 %y) {
 ; CHECK-LABEL: @udiv_mul_udiv_commute(
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
-  %div = udiv i32 %x, %y
+  %div = udiv nof i32 %x, %y
   %mul = mul i32 %y, %div
-  %r = udiv i32 %mul, %y
+  %r = udiv nof i32 %mul, %y
   ret i32 %r
 }
 
 define i32 @sdiv3(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sdiv3(
 ; CHECK-NEXT:    ret i32 0
 ;
 ; (X rem Y) / Y -> 0
   %rem = srem i32 %x, %y
-  %div = sdiv i32 %rem, %y
+  %div = sdiv nof i32 %rem, %y
   ret i32 %div
 }
 
 define i32 @sdiv4(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sdiv4(
 ; CHECK-NEXT:    ret i32 [[X:%.*]]
 ;
 ; (X / Y) * Y -> X if the division is exact
-  %div = sdiv exact i32 %x, %y
+  %div = sdiv exact nof i32 %x, %y
   %mul = mul i32 %div, %y
   ret i32 %mul
 }
 
 define i32 @sdiv5(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sdiv5(
 ; CHECK-NEXT:    ret i32 [[X:%.*]]
 ;
 ; Y * (X / Y) -> X if the division is exact
-  %div = sdiv exact i32 %x, %y
+  %div = sdiv exact nof i32 %x, %y
   %mul = mul i32 %y, %div
   ret i32 %mul
 }
 
 define i32 @udiv3(i32 %x, i32 %y) {
 ; CHECK-LABEL: @udiv3(
 ; CHECK-NEXT:    ret i32 0
 ;
 ; (X rem Y) / Y -> 0
   %rem = urem i32 %x, %y
-  %div = udiv i32 %rem, %y
+  %div = udiv nof i32 %rem, %y
   ret i32 %div
 }
 
 define i32 @udiv4(i32 %x, i32 %y) {
 ; CHECK-LABEL: @udiv4(
 ; CHECK-NEXT:    ret i32 [[X:%.*]]
 ;
 ; (X / Y) * Y -> X if the division is exact
-  %div = udiv exact i32 %x, %y
+  %div = udiv exact nof i32 %x, %y
   %mul = mul i32 %div, %y
   ret i32 %mul
 }
 
 define i32 @udiv5(i32 %x, i32 %y) {
 ; CHECK-LABEL: @udiv5(
 ; CHECK-NEXT:    ret i32 [[X:%.*]]
 ;
 ; Y * (X / Y) -> X if the division is exact
-  %div = udiv exact i32 %x, %y
+  %div = udiv exact nof i32 %x, %y
   %mul = mul i32 %y, %div
   ret i32 %mul
 }
 
 define i16 @trunc1(i32 %x) {
 ; CHECK-LABEL: @trunc1(
 ; CHECK-NEXT:    ret i16 1
 ;
   %y = add i32 %x, 1
   %tx = trunc i32 %x to i16
   %ty = trunc i32 %y to i16
   %d = sub i16 %ty, %tx
   ret i16 %d
 }

test/Transforms/InstSimplify/signed-div-rem.ll

 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i32 @sdiv_sext_big_divisor(i8 %x) {
 ; CHECK-LABEL: @sdiv_sext_big_divisor(
 ; CHECK-NEXT:    ret i32 0
 ;
   %conv = sext i8 %x to i32
-  %div = sdiv i32 %conv, 129
+  %div = sdiv nof i32 %conv, 129
   ret i32 %div
 }
 
 define i32 @not_sdiv_sext_big_divisor(i8 %x) {
 ; CHECK-LABEL: @not_sdiv_sext_big_divisor(
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i8 %x to i32
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[CONV]], 128
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[CONV]], 128
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %conv = sext i8 %x to i32
-  %div = sdiv i32 %conv, 128
+  %div = sdiv nof i32 %conv, 128
   ret i32 %div
 }
 
 define i32 @sdiv_sext_small_divisor(i8 %x) {
 ; CHECK-LABEL: @sdiv_sext_small_divisor(
 ; CHECK-NEXT:    ret i32 0
 ;
   %conv = sext i8 %x to i32
-  %div = sdiv i32 %conv, -129
+  %div = sdiv nof i32 %conv, -129
   ret i32 %div
 }
 
 define i32 @not_sdiv_sext_small_divisor(i8 %x) {
 ; CHECK-LABEL: @not_sdiv_sext_small_divisor(
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i8 %x to i32
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[CONV]], -128
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[CONV]], -128
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %conv = sext i8 %x to i32
-  %div = sdiv i32 %conv, -128
+  %div = sdiv nof i32 %conv, -128
   ret i32 %div
 }
 
 define i32 @sdiv_zext_big_divisor(i8 %x) {
 ; CHECK-LABEL: @sdiv_zext_big_divisor(
 ; CHECK-NEXT:    ret i32 0
 ;
   %conv = zext i8 %x to i32
-  %div = sdiv i32 %conv, 256
+  %div = sdiv nof i32 %conv, 256
   ret i32 %div
 }
 
 define i32 @not_sdiv_zext_big_divisor(i8 %x) {
 ; CHECK-LABEL: @not_sdiv_zext_big_divisor(
 ; CHECK-NEXT:    [[CONV:%.*]] = zext i8 %x to i32
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[CONV]], 255
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[CONV]], 255
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %conv = zext i8 %x to i32
-  %div = sdiv i32 %conv, 255
+  %div = sdiv nof i32 %conv, 255
   ret i32 %div
 }
 
 define i32 @sdiv_zext_small_divisor(i8 %x) {
 ; CHECK-LABEL: @sdiv_zext_small_divisor(
 ; CHECK-NEXT:    ret i32 0
 ;
   %conv = zext i8 %x to i32
-  %div = sdiv i32 %conv, -256
+  %div = sdiv nof i32 %conv, -256
   ret i32 %div
 }
 
 define i32 @not_sdiv_zext_small_divisor(i8 %x) {
 ; CHECK-LABEL: @not_sdiv_zext_small_divisor(
 ; CHECK-NEXT:    [[CONV:%.*]] = zext i8 %x to i32
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[CONV]], -255
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[CONV]], -255
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %conv = zext i8 %x to i32
-  %div = sdiv i32 %conv, -255
+  %div = sdiv nof i32 %conv, -255
   ret i32 %div
 }
 
 define i32 @sdiv_dividend_known_smaller_than_pos_divisor_clear_bits(i32 %x) {
 ; CHECK-LABEL: @sdiv_dividend_known_smaller_than_pos_divisor_clear_bits(
 ; CHECK-NEXT:    ret i32 0
 ;
   %and = and i32 %x, 253
-  %div = sdiv i32 %and, 254
+  %div = sdiv nof i32 %and, 254
   ret i32 %div
 }
 
 define i32 @not_sdiv_dividend_known_smaller_than_pos_divisor_clear_bits(i32 %x) {
 ; CHECK-LABEL: @not_sdiv_dividend_known_smaller_than_pos_divisor_clear_bits(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %x, 253
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[AND]], 253
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[AND]], 253
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %and = and i32 %x, 253
-  %div = sdiv i32 %and, 253
+  %div = sdiv nof i32 %and, 253
   ret i32 %div
 }
 
 define i32 @sdiv_dividend_known_smaller_than_neg_divisor_clear_bits(i32 %x) {
 ; CHECK-LABEL: @sdiv_dividend_known_smaller_than_neg_divisor_clear_bits(
 ; CHECK-NEXT:    ret i32 0
 ;
   %and = and i32 %x, 253
-  %div = sdiv i32 %and, -254
+  %div = sdiv nof i32 %and, -254
   ret i32 %div
 }
 
 define i32 @not_sdiv_dividend_known_smaller_than_neg_divisor_clear_bits(i32 %x) {
 ; CHECK-LABEL: @not_sdiv_dividend_known_smaller_than_neg_divisor_clear_bits(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %x, 253
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[AND]], -253
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[AND]], -253
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %and = and i32 %x, 253
-  %div = sdiv i32 %and, -253
+  %div = sdiv nof i32 %and, -253
   ret i32 %div
 }
 
 define i32 @sdiv_dividend_known_smaller_than_pos_divisor_set_bits(i32 %x) {
 ; CHECK-LABEL: @sdiv_dividend_known_smaller_than_pos_divisor_set_bits(
 ; CHECK-NEXT:    ret i32 0
 ;
   %or = or i32 %x, -253
-  %div = sdiv i32 %or, 254
+  %div = sdiv nof i32 %or, 254
   ret i32 %div
 }
 
 define i32 @not_sdiv_dividend_known_smaller_than_pos_divisor_set_bits(i32 %x) {
 ; CHECK-LABEL: @not_sdiv_dividend_known_smaller_than_pos_divisor_set_bits(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 %x, -253
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[OR]], 253
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[OR]], 253
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %or = or i32 %x, -253
-  %div = sdiv i32 %or, 253
+  %div = sdiv nof i32 %or, 253
   ret i32 %div
 }
 
 define i32 @sdiv_dividend_known_smaller_than_neg_divisor_set_bits(i32 %x) {
 ; CHECK-LABEL: @sdiv_dividend_known_smaller_than_neg_divisor_set_bits(
 ; CHECK-NEXT:    ret i32 0
 ;
   %or = or i32 %x, -253
-  %div = sdiv i32 %or, -254
+  %div = sdiv nof i32 %or, -254
   ret i32 %div
 }
 
 define i32 @not_sdiv_dividend_known_smaller_than_neg_divisor_set_bits(i32 %x) {
 ; CHECK-LABEL: @not_sdiv_dividend_known_smaller_than_neg_divisor_set_bits(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 %x, -253
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[OR]], -253
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 [[OR]], -253
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %or = or i32 %x, -253
-  %div = sdiv i32 %or, -253
+  %div = sdiv nof i32 %or, -253
   ret i32 %div
 }
 
 define i32 @srem_sext_big_divisor(i8 %x) {
 ; CHECK-LABEL: @srem_sext_big_divisor(
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i8 %x to i32
 ; CHECK-NEXT:    ret i32 [[CONV]]
 ;
;
   ret i32 %rem
 }
 
 ; Make sure that we're handling the minimum signed constant correctly - can't fold this.
 
 define i16 @sdiv_min_dividend(i8 %x) {
 ; CHECK-LABEL: @sdiv_min_dividend(
 ; CHECK-NEXT:    [[Z:%.*]] = zext i8 %x to i16
-; CHECK-NEXT:    [[D:%.*]] = sdiv i16 -32768, [[Z]]
+; CHECK-NEXT:    [[D:%.*]] = sdiv nof i16 -32768, [[Z]]
 ; CHECK-NEXT:    ret i16 [[D]]
 ;
   %z = zext i8 %x to i16
-  %d = sdiv i16 -32768, %z
+  %d = sdiv nof i16 -32768, %z
   ret i16 %d
 }
 
 ; If the quotient is known to not be -32768, then this can fold.
 
 define i16 @sdiv_min_divisor(i8 %x) {
 ; CHECK-LABEL: @sdiv_min_divisor(
 ; CHECK-NEXT:    ret i16 0
 ;
   %z = zext i8 %x to i16
-  %d = sdiv i16 %z, -32768
+  %d = sdiv nof i16 %z, -32768
   ret i16 %d
 }
 

test/Transforms/LICM/hoist-nounwind.ll

 ; Don't hoist division past nounwind call.
 define i32 @test2(i32 %N, i32 %c) nounwind uwtable {
 ; CHECK-LABEL: @test2(
 entry:
   %cmp4 = icmp sgt i32 %N, 0
   br i1 %cmp4, label %for.body, label %for.cond.cleanup
 
 ; CHECK: tail call void @f()
-; CHECK-NEXT: sdiv i32
+; CHECK-NEXT: sdiv nof i32
 for.body:
   %i.05 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
   tail call void @f() nounwind
-  %div = sdiv i32 5, %c
+  %div = sdiv nof i32 5, %c
   %add = add i32 %i.05, 1
   %inc = add i32 %add, %div
   %cmp = icmp slt i32 %inc, %N
   br i1 %cmp, label %for.body, label %for.cond.cleanup
 
 for.cond.cleanup:
   ret i32 0
 }

test/Transforms/LICM/hoisting.ll

; CHECK-LABEL: @test1(
   %A = load i32, i32* @X    ; <i32> [#uses=2]
   br label %Loop
 Loop:   ; preds = %LoopTail, %0
   call void @foo( )
   br i1 %c, label %LoopTail, label %IfUnEqual
         
 IfUnEqual:    ; preds = %Loop
 ; CHECK: IfUnEqual:
-; CHECK-NEXT: sdiv i32 4, %A
-  %B1 = sdiv i32 4, %A    ; <i32> [#uses=1]
+; CHECK-NEXT: sdiv nof i32 4, %A
+  %B1 = sdiv nof i32 4, %A    ; <i32> [#uses=1]
   br label %LoopTail
         
 LoopTail:   ; preds = %IfUnEqual, %Loop
   %B = phi i32 [ 0, %Loop ], [ %B1, %IfUnEqual ]    ; <i32> [#uses=1]
   br i1 %c, label %Loop, label %Out
 Out:    ; preds = %LoopTail
   %C = sub i32 %A, %B   ; <i32> [#uses=1]
   ret i32 %C
 }
 
 
 declare void @foo2(i32) nounwind
 
 
 ;; It is ok and desirable to hoist this potentially trapping instruction.
 define i32 @test2(i1 %c) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT: load i32, i32* @X
-; CHECK-NEXT: %B = sdiv i32 4, %A
+; CHECK-NEXT: %B = sdiv nof i32 4, %A
   %A = load i32, i32* @X
   br label %Loop
 
 Loop:
   ;; Should have hoisted this div!
-  %B = sdiv i32 4, %A
+  %B = sdiv nof i32 4, %A
   br label %loop2
 
 loop2:
   call void @foo2( i32 %B )
   br i1 %c, label %Loop, label %Out
 
 Out:
   %C = sub i32 %A, %B

 define i32 @test4(i32 %x, i32 %y) nounwind uwtable ssp {
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %entry, %for.body
   %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
   %n.01 = phi i32 [ 0, %entry ], [ %add, %for.body ]
   call void @foo_may_call_exit(i32 0)
-  %div = sdiv i32 %x, %y
+  %div = sdiv nof i32 %x, %y
   %add = add nsw i32 %n.01, %div
   %inc = add nsw i32 %i.02, 1
   %cmp = icmp slt i32 %inc, 10000
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:                                          ; preds = %for.body
   %n.0.lcssa = phi i32 [ %add, %for.body ]
   ret i32 %n.0.lcssa

test/Transforms/LICM/preheader-safe.ll

 ; RUN: opt -S -licm < %s | FileCheck %s
 ; RUN: opt -aa-pipeline=basic-aa -passes='require<aa>,require<targetir>,require<scalar-evolution>,require<opt-remark-emit>,loop(licm)' -S %s | FileCheck %s
 
 declare void @use_nothrow(i64 %a) nounwind
 declare void @use(i64 %a)
 
 define void @nothrow(i64 %x, i64 %y, i1* %cond) {
 ; CHECK-LABEL: nothrow
 ; CHECK-LABEL: entry
-; CHECK: %div = udiv i64 %x, %y
+; CHECK: %div = udiv nof i64 %x, %y
 ; CHECK-LABEL: loop
 ; CHECK: call void @use_nothrow(i64 %div)
 entry:
   br label %loop
 
 loop:                                         ; preds = %entry, %for.inc
-  %div = udiv i64 %x, %y
+  %div = udiv nof i64 %x, %y
   br label %loop2
 
 loop2:
   call void @use_nothrow(i64 %div)
   br label %loop
 }
 ; Negative test
 define void @throw_header(i64 %x, i64 %y, i1* %cond) {
 ; CHECK-LABEL: throw_header
 ; CHECK-LABEL: loop
-; CHECK: %div = udiv i64 %x, %y
+; CHECK: %div = udiv nof i64 %x, %y
 ; CHECK: call void @use(i64 %div)
 entry:
   br label %loop
 
 loop:                                         ; preds = %entry, %for.inc
-  %div = udiv i64 %x, %y
+  %div = udiv nof i64 %x, %y
   call void @use(i64 %div)
   br label %loop
 }
 
 ; The header is known no throw, but the loop is not.  We can
 ; still lift out of the header.
 define void @nothrow_header(i64 %x, i64 %y, i1 %cond) {
 ; CHECK-LABEL: nothrow_header
 ; CHECK-LABEL: entry
-; CHECK: %div = udiv i64 %x, %y
+; CHECK: %div = udiv nof i64 %x, %y
 ; CHECK-LABEL: loop
 ; CHECK: call void @use(i64 %div)
 entry:
   br label %loop
 loop:                                         ; preds = %entry, %for.inc
-  %div = udiv i64 %x, %y
+  %div = udiv nof i64 %x, %y
   br i1 %cond, label %loop-if, label %exit
 loop-if:
   call void @use(i64 %div)
   br label %loop
 exit:
   ret void
 }
 ; Negative test - can't move out of throwing block
 define void @nothrow_header_neg(i64 %x, i64 %y, i1 %cond) {
 ; CHECK-LABEL: nothrow_header_neg
 ; CHECK-LABEL: entry
 ; CHECK-LABEL: loop
-; CHECK: %div = udiv i64 %x, %y
+; CHECK: %div = udiv nof i64 %x, %y
 ; CHECK: call void @use(i64 %div)
 entry:
   br label %loop
 loop:                                         ; preds = %entry, %for.inc
   br label %loop-if
 loop-if:
-  %div = udiv i64 %x, %y
+  %div = udiv nof i64 %x, %y
   call void @use(i64 %div)
   br label %loop
 }

test/Transforms/LICM/sinking.ll

 
 ; Potentially trapping instructions may be sunk as long as they are guaranteed
 ; to be executed.
 define i32 @test10(i32 %N) {
 Entry:
   br label %Loop
 Loop:   ; preds = %Loop, %Entry
   %N_addr.0.pn = phi i32 [ %dec, %Loop ], [ %N, %Entry ]    ; <i32> [#uses=3]
-  %tmp.6 = sdiv i32 %N, %N_addr.0.pn    ; <i32> [#uses=1]
+  %tmp.6 = sdiv nof i32 %N, %N_addr.0.pn    ; <i32> [#uses=1]
   %dec = add i32 %N_addr.0.pn, -1   ; <i32> [#uses=1]
   %tmp.1 = icmp ne i32 %N_addr.0.pn, 0    ; <i1> [#uses=1]
   br i1 %tmp.1, label %Loop, label %Out
 Out:    ; preds = %Loop
   ret i32 %tmp.6
         
 ; CHECK-LABEL: @test10(
 ; CHECK: Out: 
 ; CHECK-NEXT:  %[[LCSSAPHI:.*]] = phi i32 [ %N_addr.0.pn
-; CHECK-NEXT:  %tmp.6.le = sdiv i32 %N, %[[LCSSAPHI]]
+; CHECK-NEXT:  %tmp.6.le = sdiv nof i32 %N, %[[LCSSAPHI]]
 ; CHECK-NEXT:  ret i32 %tmp.6.le
 }
 
 ; Should delete, not sink, dead instructions.
 define void @test11() {
   br label %Loop
 Loop:
   %dead = getelementptr %Ty, %Ty* @X2, i64 0, i32 0

test/Transforms/LICM/speculate.ll

 ; RUN: opt -S -licm < %s | FileCheck %s
 ; RUN: opt -passes='require<aa>,require<targetir>,require<scalar-evolution>,require<opt-remark-emit>,loop(licm)' -S %s | FileCheck %s
 
 ; UDiv is safe to speculate if the denominator is known non-zero.
 
 ; CHECK-LABEL: @safe_udiv(
-; CHECK:      %div = udiv i64 %x, 2
+; CHECK:      %div = udiv nof i64 %x, 2
 ; CHECK-NEXT: br label %for.body
 
 define void @safe_udiv(i64 %x, i64 %m, i64 %n, i32* %p, i64* %q) nounwind {
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
   %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
   %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
-  %div = udiv i64 %x, 2
+  %div = udiv nof i64 %x, 2
   %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
 for.inc:                                          ; preds = %if.then, %for.body
   %inc = add i64 %i.02, 1
   %cmp = icmp slt i64 %inc, %n
   br i1 %cmp, label %for.body, label %for.end

 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
   %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
   %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
-  %div = udiv i64 %x, %m
+  %div = udiv nof i64 %x, %m
   %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
 for.inc:                                          ; preds = %if.then, %for.body
   %inc = add i64 %i.02, 1
   %cmp = icmp slt i64 %inc, %n
   br i1 %cmp, label %for.body, label %for.end
 
 for.end:                                          ; preds = %for.inc, %entry
   ret void
 }
 
 ; SDiv is safe to speculate if the denominator is known non-zero and
 ; known to have at least one zero bit.
 
 ; CHECK-LABEL: @safe_sdiv(
-; CHECK:      %div = sdiv i64 %x, 2
+; CHECK:      %div = sdiv nof i64 %x, 2
 ; CHECK-NEXT: br label %for.body
 
 define void @safe_sdiv(i64 %x, i64 %m, i64 %n, i32* %p, i64* %q) nounwind {
 entry:
   %and = and i64 %m, -3
   br label %for.body
 
 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
   %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
   %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
-  %div = sdiv i64 %x, 2
+  %div = sdiv nof i64 %x, 2
   %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
 for.inc:                                          ; preds = %if.then, %for.body
   %inc = add i64 %i.02, 1
   %cmp = icmp slt i64 %inc, %n
   br i1 %cmp, label %for.body, label %for.end

 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
   %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
   %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
-  %div = sdiv i64 %x, %or
+  %div = sdiv nof i64 %x, %or
   %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
 for.inc:                                          ; preds = %if.then, %for.body
   %inc = add i64 %i.02, 1
   %cmp = icmp slt i64 %inc, %n
   br i1 %cmp, label %for.body, label %for.end

 for.body:                                         ; preds = %entry, %for.inc
   %i.02 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
   %arrayidx = getelementptr inbounds i32, i32* %p, i64 %i.02
   %0 = load i32, i32* %arrayidx, align 4
   %tobool = icmp eq i32 %0, 0
   br i1 %tobool, label %for.inc, label %if.then
 
 if.then:                                          ; preds = %for.body
-  %div = sdiv i64 %x, %and
+  %div = sdiv nof i64 %x, %and
   %arrayidx1 = getelementptr inbounds i64, i64* %q, i64 %i.02
   store i64 %div, i64* %arrayidx1, align 8
   br label %for.inc
 
 for.inc:                                          ; preds = %if.then, %for.body
   %inc = add i64 %i.02, 1
   %cmp = icmp slt i64 %inc, %n
   br i1 %cmp, label %for.body, label %for.end

 ; CHECK: br label %for.body
   br label %for.body
 
 for.body:
   %c = icmp eq i64 %b, 0
   br i1 %c, label %backedge, label %if.then
 
 if.then:
-  %d = sdiv i64 %a, %b
+  %d = sdiv nof i64 %a, %b
   store i64 %d, i64* %p
   br label %backedge
 
 backedge:
   br label %for.body
 }

test/Transforms/LoopPredication/basic.ll

 ; CHECK: loop.preheader:
 ; CHECK-NEXT: br label %loop
   br label %loop
 
 loop:
 ; CHECK: loop:
 ; CHECK-NEXT: %loop.acc = phi i32 [ %loop.acc.next, %loop ], [ 0, %loop.preheader ]
 ; CHECK-NEXT: %i = phi i32 [ %i.next, %loop ], [ 0, %loop.preheader ]
-; CHECK-NEXT: %length.udiv = udiv i32 %length, %divider
+; CHECK-NEXT: %length.udiv = udiv nof i32 %length, %divider
 ; CHECK-NEXT: %within.bounds = icmp ult i32 %i, %length.udiv
 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 %within.bounds, i32 9) [ "deopt"() ]
   %loop.acc = phi i32 [ %loop.acc.next, %loop ], [ 0, %loop.preheader ]
   %i = phi i32 [ %i.next, %loop ], [ 0, %loop.preheader ]
-  %length.udiv = udiv i32 %length, %divider
+  %length.udiv = udiv nof i32 %length, %divider
   %within.bounds = icmp ult i32 %i, %length.udiv
   call void (i1, ...) @llvm.experimental.guard(i1 %within.bounds, i32 9) [ "deopt"() ]
 
   %i.i64 = zext i32 %i to i64
   %array.i.ptr = getelementptr inbounds i32, i32* %array, i64 %i.i64
   %array.i = load i32, i32* %array.i.ptr, align 4
   %loop.acc.next = add i32 %loop.acc, %array.i
 
   %i.next = add nuw i32 %i, 1
   %continue = icmp ult i32 %i.next, %n
   br i1 %continue, label %loop, label %exit
 
 exit:
   %result = phi i32 [ 0, %entry ], [ %loop.acc.next, %loop ]
   ret i32 %result
 }

test/Transforms/LoopVectorize/AArch64/aarch64-predication.ll

 ; REQUIRES: asserts
 ; RUN: opt < %s -loop-vectorize -disable-output -debug-only=loop-vectorize 2>&1 | FileCheck %s --check-prefix=COST
 ; RUN: opt < %s -loop-vectorize -force-vector-width=2 -instcombine -simplifycfg -S | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
 
 ; This test checks that we correctly compute the scalarized operands for a
 ; user-specified vectorization factor when interleaving is disabled. We use the
 ; "optsize" attribute to disable all interleaving calculations.  A cost of 4
 ; for %tmp4 indicates that we would scalarize it's operand (%tmp3), giving
 ; %tmp4 a lower scalarization overhead.
 ;
 ; COST-LABEL:  predicated_udiv_scalarized_operand
-; COST:        LV: Found an estimated cost of 4 for VF 2 For instruction: %tmp4 = udiv i64 %tmp2, %tmp3
+; COST:        LV: Found an estimated cost of 4 for VF 2 For instruction: %tmp4 = udiv nof i64 %tmp2, %tmp3
 ;
 ; CHECK-LABEL: @predicated_udiv_scalarized_operand(
 ; CHECK:       vector.body:
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %entry ], [ [[INDEX_NEXT:%.*]], %[[PRED_UDIV_CONTINUE2:.*]] ]
 ; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, %entry ], [ [[TMP17:%.*]], %[[PRED_UDIV_CONTINUE2]] ]
 ; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i64, i64* %a, i64 [[INDEX]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64* [[TMP0]] to <2 x i64>*
 ; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <2 x i64> [[WIDE_LOAD]], zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
 ; CHECK-NEXT:    br i1 [[TMP3]], label %[[PRED_UDIV_IF:.*]], label %[[PRED_UDIV_CONTINUE:.*]]
 ; CHECK:       [[PRED_UDIV_IF]]:
 ; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i32 0
 ; CHECK-NEXT:    [[TMP5:%.*]] = add nsw i64 [[TMP4]], %x
 ; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i32 0
-; CHECK-NEXT:    [[TMP7:%.*]] = udiv i64 [[TMP6]], [[TMP5]]
+; CHECK-NEXT:    [[TMP7:%.*]] = udiv nof i64 [[TMP6]], [[TMP5]]
 ; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x i64> undef, i64 [[TMP7]], i32 0
 ; CHECK-NEXT:    br label %[[PRED_UDIV_CONTINUE]]
 ; CHECK:       [[PRED_UDIV_CONTINUE]]:
 ; CHECK-NEXT:    [[TMP9:%.*]] = phi <2 x i64> [ undef, %vector.body ], [ [[TMP8]], %[[PRED_UDIV_IF]] ]
 ; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
 ; CHECK-NEXT:    br i1 [[TMP10]], label %[[PRED_UDIV_IF1:.*]], label %[[PRED_UDIV_CONTINUE2]]
 ; CHECK:       [[PRED_UDIV_IF1]]:
 ; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i32 1
 ; CHECK-NEXT:    [[TMP12:%.*]] = add nsw i64 [[TMP11]], %x
 ; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <2 x i64> [[WIDE_LOAD]], i32 1
-; CHECK-NEXT:    [[TMP14:%.*]] = udiv i64 [[TMP13]], [[TMP12]]
+; CHECK-NEXT:    [[TMP14:%.*]] = udiv nof i64 [[TMP13]], [[TMP12]]
 ; CHECK-NEXT:    [[TMP15:%.*]] = insertelement <2 x i64> [[TMP9]], i64 [[TMP14]], i32 1
 ; CHECK-NEXT:    br label %[[PRED_UDIV_CONTINUE2]]
 ; CHECK:       [[PRED_UDIV_CONTINUE2]]:
 ; CHECK-NEXT:    [[TMP16:%.*]] = phi <2 x i64> [ [[TMP9]], %[[PRED_UDIV_CONTINUE]] ], [ [[TMP15]], %[[PRED_UDIV_IF1]] ]
 ; CHECK-NEXT:    [[PREDPHI:%.*]] = select <2 x i1> [[TMP2]], <2 x i64> [[TMP16]], <2 x i64> [[WIDE_LOAD]]
 ; CHECK-NEXT:    [[TMP17]] = add <2 x i64> [[VEC_PHI]], [[PREDPHI]]
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 2
 ; CHECK:         br i1 {{.*}}, label %middle.block, label %vector.body
 ;
 define i64 @predicated_udiv_scalarized_operand(i64* %a, i64 %x) optsize {
 entry:
   br label %for.body
 
 for.body:
   %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
   %r = phi i64 [ 0, %entry ], [ %tmp6, %for.inc ]
   %tmp0 = getelementptr inbounds i64, i64* %a, i64 %i
   %tmp2 = load i64, i64* %tmp0, align 4
   %cond0 = icmp sgt i64 %tmp2, 0
   br i1 %cond0, label %if.then, label %for.inc
 
 if.then:
   %tmp3 = add nsw i64 %tmp2, %x
-  %tmp4 = udiv i64 %tmp2, %tmp3
+  %tmp4 = udiv nof i64 %tmp2, %tmp3
   br label %for.inc
 
 for.inc:
   %tmp5 = phi i64 [ %tmp2, %for.body ], [ %tmp4, %if.then]
   %tmp6 = add i64 %r, %tmp5
   %i.next = add nuw nsw i64 %i, 1
   %cond1 = icmp slt i64 %i.next, 100
   br i1 %cond1, label %for.body, label %for.end
 
 for.end:
   %tmp7 = phi i64 [ %tmp6, %for.inc ]
   ret i64 %tmp7
 }

test/Transforms/LoopVectorize/AArch64/predication_costs.ll

 ;
 ; This test checks that we correctly compute the cost of the predicated udiv
 ; instruction. If we assume the block probability is 50%, we compute the cost
 ; as:
 ;
 ; Cost of udiv:
 ;   (udiv(2) + extractelement(6) + insertelement(3)) / 2 = 5
 ;
-; CHECK: Scalarizing and predicating: %tmp4 = udiv i32 %tmp2, %tmp3
-; CHECK: Found an estimated cost of 5 for VF 2 For instruction: %tmp4 = udiv i32 %tmp2, %tmp3
+; CHECK: Scalarizing and predicating: %tmp4 = udiv nof i32 %tmp2, %tmp3
+; CHECK: Found an estimated cost of 5 for VF 2 For instruction: %tmp4 = udiv nof i32 %tmp2, %tmp3
 ;
 define i32 @predicated_udiv(i32* %a, i32* %b, i1 %c, i64 %n) {
 entry:
   br label %for.body
 
 for.body:
   %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
   %r = phi i32 [ 0, %entry ], [ %tmp6, %for.inc ]
   %tmp0 = getelementptr inbounds i32, i32* %a, i64 %i
   %tmp1 = getelementptr inbounds i32, i32* %b, i64 %i
   %tmp2 = load i32, i32* %tmp0, align 4
   %tmp3 = load i32, i32* %tmp1, align 4
   br i1 %c, label %if.then, label %for.inc
 
 if.then:
-  %tmp4 = udiv i32 %tmp2, %tmp3
+  %tmp4 = udiv nof i32 %tmp2, %tmp3
   br label %for.inc
 
 for.inc:
   %tmp5 = phi i32 [ %tmp3, %for.body ], [ %tmp4, %if.then]
   %tmp6 = add i32 %r, %tmp5
   %i.next = add nuw nsw i64 %i, 1
   %cond = icmp slt i64 %i.next, %n
   br i1 %cond, label %for.body, label %for.end

 ; compute the cost as:
 ;
 ; Cost of add:
 ;   (add(2) + extractelement(3)) / 2 = 2
 ; Cost of udiv:
 ;   (udiv(2) + extractelement(3) + insertelement(3)) / 2 = 4
 ;
 ; CHECK: Scalarizing: %tmp3 = add nsw i32 %tmp2, %x
-; CHECK: Scalarizing and predicating: %tmp4 = udiv i32 %tmp2, %tmp3
+; CHECK: Scalarizing and predicating: %tmp4 = udiv nof i32 %tmp2, %tmp3
 ; CHECK: Found an estimated cost of 2 for VF 2 For instruction: %tmp3 = add nsw i32 %tmp2, %x
-; CHECK: Found an estimated cost of 4 for VF 2 For instruction: %tmp4 = udiv i32 %tmp2, %tmp3
+; CHECK: Found an estimated cost of 4 for VF 2 For instruction: %tmp4 = udiv nof i32 %tmp2, %tmp3
 ;
 define i32 @predicated_udiv_scalarized_operand(i32* %a, i1 %c, i32 %x, i64 %n) {
 entry:
   br label %for.body
 
 for.body:
   %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
   %r = phi i32 [ 0, %entry ], [ %tmp6, %for.inc ]
   %tmp0 = getelementptr inbounds i32, i32* %a, i64 %i
   %tmp2 = load i32, i32* %tmp0, align 4
   br i1 %c, label %if.then, label %for.inc
 
 if.then:
   %tmp3 = add nsw i32 %tmp2, %x
-  %tmp4 = udiv i32 %tmp2, %tmp3
+  %tmp4 = udiv nof i32 %tmp2, %tmp3
   br label %for.inc
 
 for.inc:
   %tmp5 = phi i32 [ %tmp2, %for.body ], [ %tmp4, %if.then]
   %tmp6 = add i32 %r, %tmp5
   %i.next = add nuw nsw i64 %i, 1
   %cond = icmp slt i64 %i.next, %n
   br i1 %cond, label %for.body, label %for.end
for.end:
   ret void
 }
 
 ; CHECK-LABEL: predication_multi_context
 ;
 ; This test checks that we correctly compute the cost of multiple predicated
 ; instructions in the same block. The sdiv, udiv, and store must be scalarized
 ; and predicated. The sub feeding the store is scalarized and sunk inside the
-; store's predicated block. However, the add feeding the sdiv and udiv cannot
+; store's predicated block. However, the add feeding the sdiv nof and udiv nof cannot
 ; be sunk and is not scalarized. If we assume the block probability is 50%, we
 ; compute the cost as:
 ;
 ; Cost of add:
 ;   add(1) = 1
 ; Cost of sdiv:
 ;   (sdiv(2) + extractelement(6) + insertelement(3)) / 2 = 5
 ; Cost of udiv:
 ;   (udiv(2) + extractelement(6) + insertelement(3)) / 2 = 5
 ; Cost of sub:
 ;   (sub(2) + extractelement(3)) / 2 = 2
 ; Cost of store:
 ;   store(4) / 2 = 2
 ;
 ; CHECK-NOT: Scalarizing: %tmp2 = add i32 %tmp1, %x
-; CHECK:     Scalarizing and predicating: %tmp3 = sdiv i32 %tmp1, %tmp2
-; CHECK:     Scalarizing and predicating: %tmp4 = udiv i32 %tmp3, %tmp2
+; CHECK:     Scalarizing and predicating: %tmp3 = sdiv nof i32 %tmp1, %tmp2
+; CHECK:     Scalarizing and predicating: %tmp4 = udiv nof i32 %tmp3, %tmp2
 ; CHECK:     Scalarizing: %tmp5 = sub i32 %tmp4, %x
 ; CHECK:     Scalarizing and predicating: store i32 %tmp5, i32* %tmp0, align 4
 ; CHECK:     Found an estimated cost of 1 for VF 2 For instruction: %tmp2 = add i32 %tmp1, %x
-; CHECK:     Found an estimated cost of 5 for VF 2 For instruction: %tmp3 = sdiv i32 %tmp1, %tmp2
-; CHECK:     Found an estimated cost of 5 for VF 2 For instruction: %tmp4 = udiv i32 %tmp3, %tmp2
+; CHECK:     Found an estimated cost of 5 for VF 2 For instruction: %tmp3 = sdiv nof i32 %tmp1, %tmp2
+; CHECK:     Found an estimated cost of 5 for VF 2 For instruction: %tmp4 = udiv nof i32 %tmp3, %tmp2
 ; CHECK:     Found an estimated cost of 2 for VF 2 For instruction: %tmp5 = sub i32 %tmp4, %x
 ; CHECK:     Found an estimated cost of 2 for VF 2 For instruction: store i32 %tmp5, i32* %tmp0, align 4
 ;
 define void @predication_multi_context(i32* %a, i1 %c, i32 %x, i64 %n) {
 entry:
   br label %for.body
 
 for.body:
   %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
   %tmp0 = getelementptr inbounds i32, i32* %a, i64 %i
   %tmp1 = load i32, i32* %tmp0, align 4
   br i1 %c, label %if.then, label %for.inc
 
 if.then:
   %tmp2 = add i32 %tmp1, %x
-  %tmp3 = sdiv i32 %tmp1, %tmp2
-  %tmp4 = udiv i32 %tmp3, %tmp2
+  %tmp3 = sdiv nof i32 %tmp1, %tmp2
+  %tmp4 = udiv nof i32 %tmp3, %tmp2
   %tmp5 = sub i32 %tmp4, %x
   store i32 %tmp5, i32* %tmp0, align 4
   br label %for.inc
 
 for.inc:
   %i.next = add nuw nsw i64 %i, 1
   %cond = icmp slt i64 %i.next, %n
   br i1 %cond, label %for.body, label %for.end
 
 for.end:
   ret void
 }

test/Transforms/LoopVectorize/AArch64/sdiv-pow2.ll

 ; RUN: opt < %s  -loop-vectorize -mtriple=aarch64-unknown-linux-gnu -mcpu=cortex-a57 -S | FileCheck %s
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
 
 %struct.anon = type { [100 x i32], i32, [100 x i32] }
 
 @Foo = common global %struct.anon zeroinitializer, align 4
 
 ; CHECK-LABEL: @foo(
 ; CHECK: load <4 x i32>, <4 x i32>*
-; CHECK: sdiv <4 x i32>
+; CHECK: sdiv nof <4 x i32>
 ; CHECK: store <4 x i32>
 
 define void @foo(){
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %arrayidx = getelementptr inbounds %struct.anon, %struct.anon* @Foo, i64 0, i32 2, i64 %indvars.iv
   %0 = load i32, i32* %arrayidx, align 4
-  %div = sdiv i32 %0, 2
+  %div = sdiv nof i32 %0, 2
   %arrayidx2 = getelementptr inbounds %struct.anon, %struct.anon* @Foo, i64 0, i32 0, i64 %indvars.iv
   store i32 %div, i32* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 100
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body
   ret void
 }

test/Transforms/LoopVectorize/X86/powof2div.ll

 ; RUN: opt < %s  -loop-vectorize -mtriple=x86_64-unknown-linux-gnu -S | FileCheck %s
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 %struct.anon = type { [100 x i32], i32, [100 x i32] }
 
 @Foo = common global %struct.anon zeroinitializer, align 4
 
 ; CHECK-LABEL: @foo(
 ; CHECK: load <4 x i32>, <4 x i32>*
-; CHECK: sdiv <4 x i32>
+; CHECK: sdiv nof <4 x i32>
 ; CHECK: store <4 x i32>
 
 define void @foo(){
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %arrayidx = getelementptr inbounds %struct.anon, %struct.anon* @Foo, i64 0, i32 2, i64 %indvars.iv
   %0 = load i32, i32* %arrayidx, align 4
-  %div = sdiv i32 %0, 2
+  %div = sdiv nof i32 %0, 2
   %arrayidx2 = getelementptr inbounds %struct.anon, %struct.anon* @Foo, i64 0, i32 0, i64 %indvars.iv
   store i32 %div, i32* %arrayidx2, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 100
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body
   ret void
 }
 

test/Transforms/LoopVectorize/X86/x86-predication.ll

 ; can be vectorized with predication, scalarizing it would cause its pointer
 ; operand to become non-uniform.
 ;
 ; CHECK: vector.body:
 ; CHECK:   %wide.masked.load = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32
 ; CHECK:   br i1 {{.*}}, label %[[IF0:.+]], label %[[CONT0:.+]]
 ; CHECK: [[IF0]]:
 ; CHECK:   %[[T0:.+]] = extractelement <2 x i32> %wide.masked.load, i32 0
-; CHECK:   %[[T1:.+]] = sdiv i32 %[[T0]], %x
+; CHECK:   %[[T1:.+]] = sdiv nof i32 %[[T0]], %x
 ; CHECK:   %[[T2:.+]] = insertelement <2 x i32> undef, i32 %[[T1]], i32 0
 ; CHECK:   br label %[[CONT0]]
 ; CHECK: [[CONT0]]:
 ; CHECK:   %[[T3:.+]] = phi <2 x i32> [ undef, %vector.body ], [ %[[T2]], %[[IF0]] ]
 ; CHECK:   br i1 {{.*}}, label %[[IF1:.+]], label %[[CONT1:.+]]
 ; CHECK: [[IF1]]:
 ; CHECK:   %[[T4:.+]] = extractelement <2 x i32> %wide.masked.load, i32 1
-; CHECK:   %[[T5:.+]] = sdiv i32 %[[T4]], %x
+; CHECK:   %[[T5:.+]] = sdiv nof i32 %[[T4]], %x
 ; CHECK:   %[[T6:.+]] = insertelement <2 x i32> %[[T3]], i32 %[[T5]], i32 1
 ; CHECK:   br label %[[CONT1]]
 ; CHECK: [[CONT1]]:
 ; CHECK:   phi <2 x i32> [ %[[T3]], %[[CONT0]] ], [ %[[T6]], %[[IF1]] ]
 ; CHECK:   br i1 {{.*}}, label %middle.block, label %vector.body
 
 define i32 @predicated_sdiv_masked_load(i32* %a, i32* %b, i32 %x, i1 %c) {
 entry:
   br label %for.body
 
 for.body:
   %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
   %r = phi i32 [ 0, %entry ], [ %tmp7, %for.inc ]
   %tmp0 = getelementptr inbounds i32, i32* %a, i64 %i
   %tmp1 = load i32, i32* %tmp0, align 4
   br i1 %c, label %if.then, label %for.inc
 
 if.then:
   %tmp2 = getelementptr inbounds i32, i32* %b, i64 %i
   %tmp3 = load i32, i32* %tmp2, align 4
-  %tmp4 = sdiv i32 %tmp3, %x
+  %tmp4 = sdiv nof i32 %tmp3, %x
   %tmp5 = add nsw i32 %tmp4, %tmp1
   br label %for.inc
 
 for.inc:
   %tmp6 = phi i32 [ %tmp1, %for.body ], [ %tmp5, %if.then]
   %tmp7 = add i32 %r, %tmp6
   %i.next = add nuw nsw i64 %i, 1
   %cond = icmp eq i64 %i.next, 10000
   br i1 %cond, label %for.end, label %for.body
 
 for.end:
   %tmp8 = phi i32 [ %tmp7, %for.inc ]
   ret i32 %tmp8
 }
 
 ; This test ensures that a load, which would have been widened otherwise is
 ; instead scalarized if Cost-Model so decided as part of its
 ; sink-scalar-operands optimization for predicated instructions.
 ;
 ; SINK-GATHER: vector.body:
 ; SINK-GATHER: pred.udiv.if:
 ; SINK-GATHER:   %[[T0:.+]] = load i32, i32* %{{.*}}, align 4
-; SINK-GATHER:   %{{.*}} = udiv i32 %[[T0]], %{{.*}}
+; SINK-GATHER:   %{{.*}} = udiv nof i32 %[[T0]], %{{.*}}
 ; SINK-GATHER: pred.udiv.continue:
 define i32 @scalarize_and_sink_gather(i32* %a, i1 %c, i32 %x, i64 %n) {
 entry:
   br label %for.body
 
 for.body:
   %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
   %r = phi i32 [ 0, %entry ], [ %tmp6, %for.inc ]
   %i7 = mul i64 %i, 777
   br i1 %c, label %if.then, label %for.inc
 
 if.then:
   %tmp0 = getelementptr inbounds i32, i32* %a, i64 %i7
   %tmp2 = load i32, i32* %tmp0, align 4
-  %tmp4 = udiv i32 %tmp2, %x
+  %tmp4 = udiv nof i32 %tmp2, %x
   br label %for.inc
 
 for.inc:
   %tmp5 = phi i32 [ %x, %for.body ], [ %tmp4, %if.then]
   %tmp6 = add i32 %r, %tmp5
   %i.next = add nuw nsw i64 %i, 1
   %cond = icmp slt i64 %i.next, %n
   br i1 %cond, label %for.body, label %for.end
 
 for.end:
   %tmp7 = phi i32 [ %tmp6, %for.inc ]
   ret i32 %tmp7
 }

test/Transforms/LoopVectorize/if-pred-non-void.ll

 
 ; CHECK-LABEL: test
 ; CHECK: vector.body:
 ; CHECK:   %[[SDEE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0
 ; CHECK:   br i1 %[[SDEE]], label %[[CSD:[a-zA-Z0-9.]+]], label %[[ESD:[a-zA-Z0-9.]+]]
 ; CHECK: [[CSD]]:
 ; CHECK:   %[[SDA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
 ; CHECK:   %[[SDA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
-; CHECK:   %[[SD0:[a-zA-Z0-9]+]] = sdiv i32 %[[SDA0]], %[[SDA1]]
+; CHECK:   %[[SD0:[a-zA-Z0-9]+]] = sdiv nof i32 %[[SDA0]], %[[SDA1]]
 ; CHECK:   %[[SD1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[SD0]], i32 0
 ; CHECK:   br label %[[ESD]]
 ; CHECK: [[ESD]]:
 ; CHECK:   %[[SDR:[a-zA-Z0-9]+]] = phi <2 x i32> [ undef, %vector.body ], [ %[[SD1]], %[[CSD]] ]
 ; CHECK:   %[[SDEEH:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 1
 ; CHECK:   br i1 %[[SDEEH]], label %[[CSDH:[a-zA-Z0-9.]+]], label %[[ESDH:[a-zA-Z0-9.]+]]
 ; CHECK: [[CSDH]]:
 ; CHECK:   %[[SDA0H:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 1
 ; CHECK:   %[[SDA1H:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 1
-; CHECK:   %[[SD0H:[a-zA-Z0-9]+]] = sdiv i32 %[[SDA0H]], %[[SDA1H]]
+; CHECK:   %[[SD0H:[a-zA-Z0-9]+]] = sdiv nof i32 %[[SDA0H]], %[[SDA1H]]
 ; CHECK:   %[[SD1H:[a-zA-Z0-9]+]] = insertelement <2 x i32> %[[SDR]], i32 %[[SD0H]], i32 1
 ; CHECK:   br label %[[ESDH]]
 ; CHECK: [[ESDH]]:
 ; CHECK:   %{{.*}} = phi <2 x i32> [ %[[SDR]], %[[ESD]] ], [ %[[SD1H]], %[[CSDH]] ]
 
 ; CHECK:   %[[UDEE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0
 ; CHECK:   br i1 %[[UDEE]], label %[[CUD:[a-zA-Z0-9.]+]], label %[[EUD:[a-zA-Z0-9.]+]]
 ; CHECK: [[CUD]]:
 ; CHECK:   %[[UDA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
 ; CHECK:   %[[UDA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0
-; CHECK:   %[[UD0:[a-zA-Z0-9]+]] = udiv i32 %[[UDA0]], %[[UDA1]]
+; CHECK:   %[[UD0:[a-zA-Z0-9]+]] = udiv nof i32 %[[UDA0]], %[[UDA1]]
 ; CHECK:   %[[UD1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[UD0]], i32 0
 ; CHECK:   br label %[[EUD]]
 ; CHECK: [[EUD]]:
 ; CHECK:   %{{.*}} = phi <2 x i32> [ undef, %{{.*}} ], [ %[[UD1]], %[[CUD]] ]
 
 ; CHECK:   %[[SREE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0
 ; CHECK:   br i1 %[[SREE]], label %[[CSR:[a-zA-Z0-9.]+]], label %[[ESR:[a-zA-Z0-9.]+]]
 ; CHECK: [[CSR]]:
for.body:                                         ; preds = %if.end, %entry
   %psd = add nsw i32 %lsd, 23
   %pud = add nsw i32 %lud, 24
   %psr = add nsw i32 %lsr, 25
   %pur = add nsw i32 %lur, 26
   %cmp1 = icmp slt i32 %lsd, 100
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body
-  %rsd = sdiv i32 %psd, %lsd
-  %rud = udiv i32 %pud, %lud
+  %rsd = sdiv nof i32 %psd, %lsd
+  %rud = udiv nof i32 %pud, %lud
   %rsr = srem i32 %psr, %lsr
   %rur = urem i32 %pur, %lur
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %for.body
   %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ]
   %yud.0 = phi i32 [ %rud, %if.then ], [ %pud, %for.body ]
   %ysr.0 = phi i32 [ %rsr, %if.then ], [ %psr, %for.body ]

 
 for.cond.cleanup:                                 ; preds = %if.end
   ret void
 
 ; CHECK-LABEL: test_scalar2scalar
 ; CHECK: vector.body:
 ; CHECK:   br i1 %{{.*}}, label %[[THEN:[a-zA-Z0-9.]+]], label %[[FI:[a-zA-Z0-9.]+]]
 ; CHECK: [[THEN]]:
-; CHECK:   %[[PD:[a-zA-Z0-9]+]] = sdiv i32 %{{.*}}, %{{.*}}
+; CHECK:   %[[PD:[a-zA-Z0-9]+]] = sdiv nof i32 %{{.*}}, %{{.*}}
 ; CHECK:   br label %[[FI]]
 ; CHECK: [[FI]]:
 ; CHECK:   %{{.*}} = phi i32 [ undef, %vector.body ], [ %[[PD]], %[[THEN]] ]
 
 for.body:                                         ; preds = %if.end, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]
   %isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv
   %lsd = load i32, i32* %isd, align 4
   %isd.b = getelementptr inbounds i32, i32* %bsd, i64 %indvars.iv
   %lsd.b = load i32, i32* %isd.b, align 4
   %psd = add nsw i32 %lsd, 23
   %cmp1 = icmp slt i32 %lsd, 100
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body
-  %sd1 = sdiv i32 %psd, %lsd
-  %rsd = sdiv i32 %lsd.b, %sd1
+  %sd1 = sdiv nof i32 %psd, %lsd
+  %rsd = sdiv nof i32 %lsd.b, %sd1
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %for.body
   %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ]
   store i32 %ysd.0, i32* %isd, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 128
   br i1 %exitcond, label %for.cond.cleanup, label %for.body

 ; CHECK: %[[CMP1:.+]] = icmp slt <2 x i32> %[[VAL:.+]], <i32 100, i32 100>
 ; CHECK: %[[CMP2:.+]] = icmp sge <2 x i32> %[[VAL]], <i32 200, i32 200>
 ; CHECK: %[[NOT:.+]] = xor <2 x i1> %[[CMP1]], <i1 true, i1 true>
 ; CHECK: %[[AND:.+]] = and <2 x i1> %[[CMP2]], %[[NOT]]
 ; CHECK: %[[OR:.+]] = or <2 x i1> %[[AND]], %[[CMP1]]
 ; CHECK: %[[EXTRACT:.+]] = extractelement <2 x i1> %[[OR]], i32 0
 ; CHECK: br i1 %[[EXTRACT]], label %[[THEN:[a-zA-Z0-9.]+]], label %[[FI:[a-zA-Z0-9.]+]]
 ; CHECK: [[THEN]]:
-; CHECK:   %[[PD:[a-zA-Z0-9]+]] = sdiv i32 %{{.*}}, %{{.*}}
+; CHECK:   %[[PD:[a-zA-Z0-9]+]] = sdiv nof i32 %{{.*}}, %{{.*}}
 ; CHECK:   br label %[[FI]]
 ; CHECK: [[FI]]:
 ; CHECK:   %{{.*}} = phi i32 [ undef, %vector.body ], [ %[[PD]], %[[THEN]] ]
 
 
 for.body:                                         ; preds = %if.end, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]
   %isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv
   %lsd = load i32, i32* %isd, align 4
   %isd.b = getelementptr inbounds i32, i32* %bsd, i64 %indvars.iv
   %lsd.b = load i32, i32* %isd.b, align 4
   %psd = add nsw i32 %lsd, 23
   %cmp1 = icmp slt i32 %lsd, 100
   br i1 %cmp1, label %if.then, label %check
 
 check:                                            ; preds = %for.body
   %cmp2 = icmp sge i32 %lsd, 200
   br i1 %cmp2, label %if.then, label %if.end
 
 if.then:                                          ; preds = %check, %for.body
-  %sd1 = sdiv i32 %psd, %lsd
-  %rsd = sdiv i32 %lsd.b, %sd1
+  %sd1 = sdiv nof i32 %psd, %lsd
+  %rsd = sdiv nof i32 %lsd.b, %sd1
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %check
   %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %check ] 
   store i32 %ysd.0, i32* %isd, align 4
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
   %exitcond = icmp eq i64 %indvars.iv.next, 128
   br i1 %exitcond, label %for.cond.cleanup, label %for.body
 }
 
 
 define i32 @predicated_udiv_scalarized_operand(i32* %a, i1 %c, i32 %x, i64 %n) {
 entry:
   br label %for.body
 
 ; CHECK-LABEL: predicated_udiv_scalarized_operand
 ; CHECK: vector.body:
 ; CHECK:   %wide.load = load <2 x i32>, <2 x i32>* {{.*}}, align 4
 ; CHECK:   br i1 {{.*}}, label %[[IF0:.+]], label %[[CONT0:.+]]
 ; CHECK: [[IF0]]:
 ; CHECK:   %[[T00:.+]] = extractelement <2 x i32> %wide.load, i32 0
 ; CHECK:   %[[T01:.+]] = add nsw i32 %[[T00]], %x
 ; CHECK:   %[[T02:.+]] = extractelement <2 x i32> %wide.load, i32 0
-; CHECK:   %[[T03:.+]] = udiv i32 %[[T02]], %[[T01]]
+; CHECK:   %[[T03:.+]] = udiv nof i32 %[[T02]], %[[T01]]
 ; CHECK:   %[[T04:.+]] = insertelement <2 x i32> undef, i32 %[[T03]], i32 0
 ; CHECK:   br label %[[CONT0]]
 ; CHECK: [[CONT0]]:
 ; CHECK:   %[[T05:.+]] = phi <2 x i32> [ undef, %vector.body ], [ %[[T04]], %[[IF0]] ]
 ; CHECK:   br i1 {{.*}}, label %[[IF1:.+]], label %[[CONT1:.+]]
 ; CHECK: [[IF1]]:
 ; CHECK:   %[[T06:.+]] = extractelement <2 x i32> %wide.load, i32 1
 ; CHECK:   %[[T07:.+]] = add nsw i32 %[[T06]], %x
 ; CHECK:   %[[T08:.+]] = extractelement <2 x i32> %wide.load, i32 1
-; CHECK:   %[[T09:.+]] = udiv i32 %[[T08]], %[[T07]]
+; CHECK:   %[[T09:.+]] = udiv nof i32 %[[T08]], %[[T07]]
 ; CHECK:   %[[T10:.+]] = insertelement <2 x i32> %[[T05]], i32 %[[T09]], i32 1
 ; CHECK:   br label %[[CONT1]]
 ; CHECK: [[CONT1]]:
 ; CHECK:   phi <2 x i32> [ %[[T05]], %[[CONT0]] ], [ %[[T10]], %[[IF1]] ]
 ; CHECK:   br i1 {{.*}}, label %middle.block, label %vector.body
 
 ; Test predicating an instruction that feeds a vectorizable use, when unrolled
 ; but not vectorized. Derived from pr34248 reproducer.
 ;
 ; UNROLL-NO-VF-LABEL: predicated_udiv_scalarized_operand
 ; UNROLL-NO-VF: vector.body:
 ; UNROLL-NO-VF:   %[[LOAD0:.+]] = load i32, i32*
 ; UNROLL-NO-VF:   %[[LOAD1:.+]] = load i32, i32*
 ; UNROLL-NO-VF:   br i1 {{.*}}, label %[[IF0:.+]], label %[[CONT0:.+]]
 ; UNROLL-NO-VF: [[IF0]]:
 ; UNROLL-NO-VF:   %[[ADD0:.+]] = add nsw i32 %[[LOAD0]], %x
-; UNROLL-NO-VF:   %[[DIV0:.+]] = udiv i32 %[[LOAD0]], %[[ADD0]]
+; UNROLL-NO-VF:   %[[DIV0:.+]] = udiv nof i32 %[[LOAD0]], %[[ADD0]]
 ; UNROLL-NO-VF:   br label %[[CONT0]]
 ; UNROLL-NO-VF: [[CONT0]]:
 ; UNROLL-NO-VF:   phi i32 [ undef, %vector.body ], [ %[[DIV0]], %[[IF0]] ]
 ; UNROLL-NO-VF:   br i1 {{.*}}, label %[[IF1:.+]], label %[[CONT1:.+]]
 ; UNROLL-NO-VF: [[IF1]]:
 ; UNROLL-NO-VF:   %[[ADD1:.+]] = add nsw i32 %[[LOAD1]], %x
-; UNROLL-NO-VF:   %[[DIV1:.+]] = udiv i32 %[[LOAD1]], %[[ADD1]]
+; UNROLL-NO-VF:   %[[DIV1:.+]] = udiv nof i32 %[[LOAD1]], %[[ADD1]]
 ; UNROLL-NO-VF:   br label %[[CONT1]]
 ; UNROLL-NO-VF: [[CONT1]]:
 ; UNROLL-NO-VF:   phi i32 [ undef, %[[CONT0]] ], [ %[[DIV1]], %[[IF1]] ]
 ; UNROLL-NO-VF:   br i1 {{.*}}, label %middle.block, label %vector.body
 ;
 for.body:
   %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ]
   %r = phi i32 [ 0, %entry ], [ %tmp6, %for.inc ]
   %tmp0 = getelementptr inbounds i32, i32* %a, i64 %i
   %tmp2 = load i32, i32* %tmp0, align 4
   br i1 %c, label %if.then, label %for.inc
 
 if.then:
   %tmp3 = add nsw i32 %tmp2, %x
-  %tmp4 = udiv i32 %tmp2, %tmp3
+  %tmp4 = udiv nof i32 %tmp2, %tmp3
   br label %for.inc
 
 for.inc:
   %tmp5 = phi i32 [ %tmp2, %for.body ], [ %tmp4, %if.then]
   %tmp6 = add i32 %r, %tmp5
   %i.next = add nuw nsw i64 %i, 1
   %cond = icmp slt i64 %i.next, %n
   br i1 %cond, label %for.body, label %for.end
 
 for.end:
   %tmp7 = phi i32 [ %tmp6, %for.inc ]
   ret i32 %tmp7
 }

test/Transforms/LoopVectorize/if-pred-not-when-safe.ll

 entry:
   br label %for.body
 
 for.cond.cleanup:                                 ; preds = %if.end
   ret void
 
 ; CHECK-LABEL: test
 ; CHECK: vector.body:
-; CHECK: %{{.*}} = sdiv <2 x i32> %{{.*}}, <i32 11, i32 11>
-; CHECK: %{{.*}} = udiv <2 x i32> %{{.*}}, <i32 13, i32 13>
+; CHECK: %{{.*}} = sdiv nof <2 x i32> %{{.*}}, <i32 11, i32 11>
+; CHECK: %{{.*}} = udiv nof <2 x i32> %{{.*}}, <i32 13, i32 13>
 ; CHECK: %{{.*}} = srem <2 x i32> %{{.*}}, <i32 17, i32 17>
 ; CHECK: %{{.*}} = urem <2 x i32> %{{.*}}, <i32 19, i32 19>
-; CHECK-NOT: %{{.*}} = sdiv <2 x i32> %{{.*}}, <i32 0, i32 0>
-; CHECK-NOT: %{{.*}} = udiv <2 x i32> %{{.*}}, <i32 0, i32 0>
+; CHECK-NOT: %{{.*}} = sdiv nof <2 x i32> %{{.*}}, <i32 0, i32 0>
+; CHECK-NOT: %{{.*}} = udiv nof <2 x i32> %{{.*}}, <i32 0, i32 0>
 ; CHECK-NOT: %{{.*}} = srem <2 x i32> %{{.*}}, <i32 0, i32 0>
 ; CHECK-NOT: %{{.*}} = urem <2 x i32> %{{.*}}, <i32 0, i32 0>
 
 for.body:                                         ; preds = %if.end, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ]
   %isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv
   %iud = getelementptr inbounds i32, i32* %aud, i64 %indvars.iv
   %isr = getelementptr inbounds i32, i32* %asr, i64 %indvars.iv
for.body:                                         ; preds = %if.end, %entry
   %psd0 = add nsw i32 %lsd, 27
   %pud0 = add nsw i32 %lud, 28
   %psr0 = add nsw i32 %lsr, 29
   %pur0 = add nsw i32 %lur, 30
   %cmp1 = icmp slt i32 %lsd, 100
   br i1 %cmp1, label %if.then, label %if.end
 
 if.then:                                          ; preds = %for.body
-  %rsd = sdiv i32 %psd, 11
-  %rud = udiv i32 %pud, 13
+  %rsd = sdiv nof i32 %psd, 11
+  %rud = udiv nof i32 %pud, 13
   %rsr = srem i32 %psr, 17
   %rur = urem i32 %pur, 19
-  %rsd0 = sdiv i32 %psd0, 0
-  %rud0 = udiv i32 %pud0, 0
+  %rsd0 = sdiv nof i32 %psd0, 0
+  %rud0 = udiv nof i32 %pud0, 0
   %rsr0 = srem i32 %psr0, 0
   %rur0 = urem i32 %pur0, 0
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %for.body
   %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ]
   %yud.0 = phi i32 [ %rud, %if.then ], [ %pud, %for.body ]
   %ysr.0 = phi i32 [ %rsr, %if.then ], [ %psr, %for.body ]

test/Transforms/LoopVectorize/induction.ll

for.body:
   br i1 %cond, label %for.end, label %for.body
 
 for.end:
   ret void
 }
 
 ; PR30542. Ensure we generate all the scalar steps for the induction variable.
 ; The scalar induction variable is used by a getelementptr instruction
-; (uniform), and a udiv (non-uniform).
+; (uniform), and a udiv nof (non-uniform).
 ;
 ; int sum = 0;
 ; for (int i = 0; i < n; ++i) {
 ;   int x = a[i];
 ;   if (c)
 ;     x /= i;
 ;   sum += x;
 ; }
 ;
 ; CHECK-LABEL: @scalarize_induction_variable_05(
 ; CHECK: vector.body:
 ; CHECK:   %index = phi i32 [ 0, %vector.ph ], [ %index.next, %pred.udiv.continue{{[0-9]+}} ]
 ; CHECK:   %[[I0:.+]] = add i32 %index, 0
 ; CHECK:   getelementptr inbounds i32, i32* %a, i32 %[[I0]]
 ; CHECK: pred.udiv.if:
-; CHECK:   udiv i32 {{.*}}, %[[I0]]
+; CHECK:   udiv nof i32 {{.*}}, %[[I0]]
 ; CHECK: pred.udiv.if{{[0-9]+}}:
 ; CHECK:   %[[I1:.+]] = add i32 %index, 1
-; CHECK:   udiv i32 {{.*}}, %[[I1]]
+; CHECK:   udiv nof i32 {{.*}}, %[[I1]]
 ;
 ; UNROLL-NO_IC-LABEL: @scalarize_induction_variable_05(
 ; UNROLL-NO-IC: vector.body:
 ; UNROLL-NO-IC:   %index = phi i32 [ 0, %vector.ph ], [ %index.next, %pred.udiv.continue{{[0-9]+}} ]
 ; UNROLL-NO-IC:   %[[I0:.+]] = add i32 %index, 0
 ; UNROLL-NO-IC:   %[[I2:.+]] = add i32 %index, 2
 ; UNROLL-NO-IC:   getelementptr inbounds i32, i32* %a, i32 %[[I0]]
 ; UNROLL-NO-IC:   getelementptr inbounds i32, i32* %a, i32 %[[I2]]
 ; UNROLL-NO-IC: pred.udiv.if:
-; UNROLL-NO-IC:   udiv i32 {{.*}}, %[[I0]]
+; UNROLL-NO-IC:   udiv nof i32 {{.*}}, %[[I0]]
 ; UNROLL-NO-IC: pred.udiv.if{{[0-9]+}}:
 ; UNROLL-NO-IC:   %[[I1:.+]] = add i32 %index, 1
-; UNROLL-NO-IC:   udiv i32 {{.*}}, %[[I1]]
+; UNROLL-NO-IC:   udiv nof i32 {{.*}}, %[[I1]]
 ; UNROLL-NO-IC: pred.udiv.if{{[0-9]+}}:
-; UNROLL-NO-IC:   udiv i32 {{.*}}, %[[I2]]
+; UNROLL-NO-IC:   udiv nof i32 {{.*}}, %[[I2]]
 ; UNROLL-NO-IC: pred.udiv.if{{[0-9]+}}:
 ; UNROLL-NO-IC:   %[[I3:.+]] = add i32 %index, 3
-; UNROLL-NO-IC:   udiv i32 {{.*}}, %[[I3]]
+; UNROLL-NO-IC:   udiv nof i32 {{.*}}, %[[I3]]
 ;
 ; IND-LABEL: @scalarize_induction_variable_05(
 ; IND: vector.body:
 ; IND:   %index = phi i32 [ 0, %vector.ph ], [ %index.next, %pred.udiv.continue{{[0-9]+}} ]
 ; IND:   %[[E0:.+]] = sext i32 %index to i64
 ; IND:   getelementptr inbounds i32, i32* %a, i64 %[[E0]]
 ; IND: pred.udiv.if:
-; IND:   udiv i32 {{.*}}, %index
+; IND:   udiv nof i32 {{.*}}, %index
 ; IND: pred.udiv.if{{[0-9]+}}:
 ; IND:   %[[I1:.+]] = or i32 %index, 1
-; IND:   udiv i32 {{.*}}, %[[I1]]
+; IND:   udiv nof i32 {{.*}}, %[[I1]]
 ;
 ; UNROLL-LABEL: @scalarize_induction_variable_05(
 ; UNROLL: vector.body:
 ; UNROLL:   %index = phi i32 [ 0, %vector.ph ], [ %index.next, %pred.udiv.continue{{[0-9]+}} ]
 ; UNROLL:   %[[I2:.+]] = or i32 %index, 2
 ; UNROLL:   %[[E0:.+]] = sext i32 %index to i64
 ; UNROLL:   %[[G0:.+]] = getelementptr inbounds i32, i32* %a, i64 %[[E0]]
 ; UNROLL:   getelementptr i32, i32* %[[G0]], i64 2
 ; UNROLL: pred.udiv.if:
-; UNROLL:   udiv i32 {{.*}}, %index
+; UNROLL:   udiv nof i32 {{.*}}, %index
 ; UNROLL: pred.udiv.if{{[0-9]+}}:
 ; UNROLL:   %[[I1:.+]] = or i32 %index, 1
-; UNROLL:   udiv i32 {{.*}}, %[[I1]]
+; UNROLL:   udiv nof i32 {{.*}}, %[[I1]]
 ; UNROLL: pred.udiv.if{{[0-9]+}}:
-; UNROLL:   udiv i32 {{.*}}, %[[I2]]
+; UNROLL:   udiv nof i32 {{.*}}, %[[I2]]
 ; UNROLL: pred.udiv.if{{[0-9]+}}:
 ; UNROLL:   %[[I3:.+]] = or i32 %index, 3
-; UNROLL:   udiv i32 {{.*}}, %[[I3]]
+; UNROLL:   udiv nof i32 {{.*}}, %[[I3]]
 
 define i32 @scalarize_induction_variable_05(i32* %a, i32 %x, i1 %c, i32 %n) {
 entry:
   br label %for.body
 
 for.body:
   %i = phi i32 [ 0, %entry ], [ %i.next, %if.end ]
   %sum = phi i32 [ 0, %entry ], [ %tmp4, %if.end ]
   %tmp0 = getelementptr inbounds i32, i32* %a, i32 %i
   %tmp1 = load i32, i32* %tmp0, align 4
   br i1 %c, label %if.then, label %if.end
 
 if.then:
-  %tmp2 = udiv i32 %tmp1, %i
+  %tmp2 = udiv nof i32 %tmp1, %i
   br label %if.end
 
 if.end:
   %tmp3 = phi i32 [ %tmp2, %if.then ], [ %tmp1, %for.body ]
   %tmp4 = add i32 %tmp3, %sum
   %i.next = add nuw nsw i32 %i, 1
   %cond = icmp slt i32 %i.next, %n
   br i1 %cond, label %for.body, label %for.end

test/Transforms/NewGVN/calls-readonly.ll

 ; RUN: opt < %s -basicaa -newgvn -S | FileCheck %s
 ; Should delete the second call to strlen even though the intervening strchr call exists.
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin7"
 
 define i8* @test(i8* %P, i8* %Q, i32 %x, i32 %y) nounwind readonly {
 entry:
   %0 = tail call i32 @strlen(i8* %P)              ; <i32> [#uses=2]
   %1 = icmp eq i32 %0, 0                          ; <i1> [#uses=1]
   br i1 %1, label %bb, label %bb1
 
 bb:                                               ; preds = %entry
-  %2 = sdiv i32 %x, %y                            ; <i32> [#uses=1]
+  %2 = sdiv nof i32 %x, %y                            ; <i32> [#uses=1]
   br label %bb1
 
 bb1:                                              ; preds = %bb, %entry
   %x_addr.0 = phi i32 [ %2, %bb ], [ %x, %entry ] ; <i32> [#uses=1]
   %3 = tail call i8* @strchr(i8* %Q, i32 97)      ; <i8*> [#uses=1]
   %4 = tail call i32 @strlen(i8* %P)              ; <i32> [#uses=1]
   %5 = add i32 %x_addr.0, %0                      ; <i32> [#uses=1]
   %.sum = sub i32 %5, %4                          ; <i32> [#uses=1]
   %6 = getelementptr i8, i8* %3, i32 %.sum            ; <i8*> [#uses=1]
   ret i8* %6
 }
 
 ; CHECK: define i8* @test(i8* %P, i8* %Q, i32 %x, i32 %y) #0 {
 ; CHECK: entry:
 ; CHECK-NEXT:   %0 = tail call i32 @strlen(i8* %P)
 ; CHECK-NEXT:   %1 = icmp eq i32 %0, 0
 ; CHECK-NEXT:   br i1 %1, label %bb, label %bb1
 ; CHECK: bb:
-; CHECK-NEXT:   %2 = sdiv i32 %x, %y
+; CHECK-NEXT:   %2 = sdiv nof i32 %x, %y
 ; CHECK-NEXT:   br label %bb1
 ; CHECK: bb1:
 ; CHECK-NEXT:   %x_addr.0 = phi i32 [ %2, %bb ], [ %x, %entry ]
 ; CHECK-NEXT:   %3 = tail call i8* @strchr(i8* %Q, i32 97)
 ; CHECK-NEXT:   %4 = add i32 %x_addr.0, %0
 ; CHECK-NEXT:   %5 = getelementptr i8, i8* %3, i32 %x_addr.0
 ; CHECK-NEXT:   ret i8* %5
 ; CHECK: }
 
 declare i32 @strlen(i8*) nounwind readonly
 
 declare i8* @strchr(i8*, i32) nounwind readonly

test/Transforms/NewGVN/pr32838.ll

 ; CHECK-NEXT:    [[SECONDPHI:%.*]] = phi i64 [ [[THIRDPHI:%.*]], [[THIRDPHIBLOCK:%.*]] ], [ undef, [[FIRSTPHIBLOCK]] ]
 ; CHECK-NEXT:    br i1 undef, label [[FIRSTPHIBLOCK]], label [[THIRDPHIBLOCK]]
 ; CHECK:       thirdphiblock:
 ; CHECK-NEXT:    [[THIRDPHI]] = phi i64 [ [[SECONDPHI]], [[SECONDPHIBLOCK]] ], [ [[DIV:%.*]], [[COND_TRUE]] ]
 ; CHECK-NEXT:    br label [[SECONDPHIBLOCK]]
 ; CHECK:       for.cond17thread-pre-split:
 ; CHECK-NEXT:    br label [[COND_TRUE]]
 ; CHECK:       cond.true:
-; CHECK-NEXT:    [[DIV]] = sdiv i64 [[ARG:%.*]], 4
+; CHECK-NEXT:    [[DIV]] = sdiv nof i64 [[ARG:%.*]], 4
 ; CHECK-NEXT:    br label [[THIRDPHIBLOCK]]
 ; CHECK:       temp:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br i1 undef, label %if.then, label %cond.true
 if.then:
   br i1 false, label %firstphiblock, label %temp
 firstphiblock:
   %firstphi = phi i64 [ %arg, %if.then ], [ undef, %secondphiblock ]
   br i1 undef, label %for.cond17thread-pre-split, label %secondphiblock
 secondphiblock:
   %secondphi = phi i64 [ %thirdphi, %thirdphiblock ], [ %firstphi, %firstphiblock ]
   br i1 undef, label %firstphiblock, label %thirdphiblock
 thirdphiblock:
   %thirdphi = phi i64 [ %secondphi, %secondphiblock ], [ %div, %cond.true ]
   br label %secondphiblock
 for.cond17thread-pre-split:
   br label %cond.true
 cond.true:
   %fourthphi = phi i64 [ %arg, %entry ], [ %firstphi, %for.cond17thread-pre-split ]
-  %div = sdiv i64 %fourthphi, 4
+  %div = sdiv nof i64 %fourthphi, 4
   br label %thirdphiblock
 temp:
   ret void
 }
 define void @fn2(i64 %arg) {
 ; CHECK-LABEL: @fn2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 undef, label [[IF_THEN:%.*]], label [[COND_TRUE:%.*]]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    br i1 false, label [[FIRSTPHIBLOCK:%.*]], label [[TEMP:%.*]]
 ; CHECK:       firstphiblock:
 ; CHECK-NEXT:    [[FIRSTPHI:%.*]] = phi i64 [ undef, [[IF_THEN]] ], [ [[SECONDPHI:%.*]], [[SECONDPHIBLOCK:%.*]] ]
 ; CHECK-NEXT:    br i1 undef, label %for.cond17thread-pre-split, label [[SECONDPHIBLOCK]]
 ; CHECK:       secondphiblock:
 ; CHECK-NEXT:    [[SECONDPHI]] = phi i64 [ [[THIRDPHI:%.*]], [[THIRDPHIBLOCK:%.*]] ], [ [[FIRSTPHI]], [[FIRSTPHIBLOCK]] ]
 ; CHECK-NEXT:    br i1 undef, label [[FIRSTPHIBLOCK]], label [[THIRDPHIBLOCK]]
 ; CHECK:       thirdphiblock:
 ; CHECK-NEXT:    [[THIRDPHI]] = phi i64 [ [[SECONDPHI]], [[SECONDPHIBLOCK]] ], [ [[DIV:%.*]], [[COND_TRUE]] ]
 ; CHECK-NEXT:    br label [[SECONDPHIBLOCK]]
 ; CHECK:       for.cond17thread-pre-split:
 ; CHECK-NEXT:    br label [[COND_TRUE]]
 ; CHECK:       cond.true:
 ; CHECK-NEXT:    [[FOURTHPHI:%.*]] = phi i64 [ [[ARG:%.*]], [[ENTRY:%.*]] ], [ [[FIRSTPHI]], %for.cond17thread-pre-split ]
-; CHECK-NEXT:    [[DIV]] = sdiv i64 [[FOURTHPHI]], 4
+; CHECK-NEXT:    [[DIV]] = sdiv nof i64 [[FOURTHPHI]], 4
 ; CHECK-NEXT:    br label [[THIRDPHIBLOCK]]
 ; CHECK:       temp:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br i1 undef, label %if.then, label %cond.true
 if.then:
   br i1 false, label %firstphiblock, label %temp
 firstphiblock:
   %firstphi = phi i64 [ %arg, %if.then ], [ %secondphi, %secondphiblock ]
   br i1 undef, label %for.cond17thread-pre-split, label %secondphiblock
 secondphiblock:
   %secondphi = phi i64 [ %thirdphi, %thirdphiblock ], [ %firstphi, %firstphiblock ]
   br i1 undef, label %firstphiblock, label %thirdphiblock
 thirdphiblock:
   %thirdphi = phi i64 [ %secondphi, %secondphiblock ], [ %div, %cond.true ]
   br label %secondphiblock
 for.cond17thread-pre-split:
   br label %cond.true
 cond.true:
   %fourthphi = phi i64 [ %arg, %entry ], [ %firstphi, %for.cond17thread-pre-split ]
-  %div = sdiv i64 %fourthphi, 4
+  %div = sdiv nof i64 %fourthphi, 4
   br label %thirdphiblock
 temp:
   ret void
 }
 @b = external global i32, align 4
 @a = external global i32, align 4
 define void @fn3() {
 ; CHECK-LABEL: @fn3(

test/Transforms/NewGVN/pr33185.ll

 ; CHECK-NEXT:    [[CMP1_I:%.*]] = icmp ne i32 [[TMP]], 0
 ; CHECK-NEXT:    br label [[FOR_BODY_I:%.*]]
 ; CHECK:       for.body.i:
 ; CHECK-NEXT:    [[TMP1:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[COND_END_I:%.*]] ]
 ; CHECK-NEXT:    [[F_08_I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[COND_END_I]] ]
 ; CHECK-NEXT:    [[MUL_I:%.*]] = select i1 [[CMP1_I]], i32 [[F_08_I]], i32 0
 ; CHECK-NEXT:    br i1 [[TMP1]], label [[COND_END_I]], label [[COND_TRUE_I:%.*]]
 ; CHECK:       cond.true.i:
-; CHECK-NEXT:    [[DIV_I:%.*]] = udiv i32 [[MUL_I]], [[F_08_I]]
+; CHECK-NEXT:    [[DIV_I:%.*]] = udiv nof i32 [[MUL_I]], [[F_08_I]]
 ; CHECK-NEXT:    br label [[COND_END_I]]
 ; CHECK:       cond.end.i:
 ; CHECK-NEXT:    [[COND_I:%.*]] = phi i32 [ [[DIV_I]], [[COND_TRUE_I]] ], [ 0, [[FOR_BODY_I]] ]
 ; CHECK-NEXT:    [[INC_I]] = add nuw nsw i32 [[F_08_I]], 1
 ; CHECK-NEXT:    [[EXITCOND_I:%.*]] = icmp eq i32 [[INC_I]], 4
 ; CHECK-NEXT:    br i1 [[EXITCOND_I]], label [[FN1_EXIT:%.*]], label [[FOR_BODY_I]]
 ; CHECK:       fn1.exit:
 ; CHECK-NEXT:    [[CALL4:%.*]] = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), i32 [[COND_I]])
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   %tmp = load i32, i32* @a, align 4
   %cmp1.i = icmp ne i32 %tmp, 0
   br label %for.body.i
 
 for.body.i:
   %tmp1 = phi i1 [ true, %entry ], [ false, %cond.end.i ]
   %f.08.i = phi i32 [ 0, %entry ], [ %inc.i, %cond.end.i ]
   %mul.i = select i1 %cmp1.i, i32 %f.08.i, i32 0
   br i1 %tmp1, label %cond.end.i, label %cond.true.i
 
 cond.true.i:
   ;; Ensure we don't replace this divide with a phi of ops that merges the wrong loop iteration value
-  %div.i = udiv i32 %mul.i, %f.08.i
+  %div.i = udiv nof i32 %mul.i, %f.08.i
   br label %cond.end.i
 
 cond.end.i:
   %cond.i = phi i32 [ %div.i, %cond.true.i ], [ 0, %for.body.i ]
   %inc.i = add nuw nsw i32 %f.08.i, 1
   %exitcond.i = icmp eq i32 %inc.i, 4
   br i1 %exitcond.i, label %fn1.exit, label %for.body.i
 
 fn1.exit:
   %cond.i.lcssa = phi i32 [ %cond.i, %cond.end.i ]
   %call4= tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), i32 %cond.i.lcssa)
   ret i32 0
 }
 
 declare i32 @printf(i8* nocapture readonly, ...)
 
-;; Variant of the above where we have made the udiv available in each predecessor with the wrong values.
+;; Variant of the above where we have made the udiv nof available in each predecessor with the wrong values.
 ;; In the entry block, it is always 0, so we don't try to create a leader there, only in %cond.end.i.
 ;; We should not create a phi of ops for it using these leaders.
-;; A correct phi of ops for this udiv would be phi(0, 1), which we are not smart enough to figure out.
+;; A correct phi of ops for this udiv nof would be phi(0, 1), which we are not smart enough to figure out.
 ;; If we reuse the incorrect leaders, we will get phi(0, 0).
 define i32 @test2() local_unnamed_addr {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP:%.*]] = load i32, i32* @a, align 4
 ; CHECK-NEXT:    [[CMP1_I:%.*]] = icmp ne i32 [[TMP]], 0
 ; CHECK-NEXT:    br label [[FOR_BODY_I:%.*]]
 ; CHECK:       for.body.i:
 ; CHECK-NEXT:    [[TMP1:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[COND_END_I:%.*]] ]
 ; CHECK-NEXT:    [[F_08_I:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC_I:%.*]], [[COND_END_I]] ]
 ; CHECK-NEXT:    [[MUL_I:%.*]] = select i1 [[CMP1_I]], i32 [[F_08_I]], i32 0
 ; CHECK-NEXT:    br i1 [[TMP1]], label [[COND_END_I]], label [[COND_TRUE_I:%.*]]
 ; CHECK:       cond.true.i:
-; CHECK-NEXT:    [[DIV_I:%.*]] = udiv i32 [[MUL_I]], [[F_08_I]]
+; CHECK-NEXT:    [[DIV_I:%.*]] = udiv nof i32 [[MUL_I]], [[F_08_I]]
 ; CHECK-NEXT:    br label [[COND_END_I]]
 ; CHECK:       cond.end.i:
 ; CHECK-NEXT:    [[COND_I:%.*]] = phi i32 [ [[DIV_I]], [[COND_TRUE_I]] ], [ 0, [[FOR_BODY_I]] ]
 ; CHECK-NEXT:    [[INC_I]] = add nuw nsw i32 [[F_08_I]], 1
 ; CHECK-NEXT:    [[CALL5:%.*]] = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), i32 0)
 ; CHECK-NEXT:    [[EXITCOND_I:%.*]] = icmp eq i32 [[INC_I]], 4
 ; CHECK-NEXT:    br i1 [[EXITCOND_I]], label [[FN1_EXIT:%.*]], label [[FOR_BODY_I]]
 ; CHECK:       fn1.exit:
 ; CHECK-NEXT:    [[CALL4:%.*]] = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), i32 [[COND_I]])
 ; CHECK-NEXT:    ret i32 0
 ;
 entry:
   %tmp = load i32, i32* @a, align 4
   %cmp1.i = icmp ne i32 %tmp, 0
   br label %for.body.i
 
 for.body.i:
   %tmp1 = phi i1 [ true, %entry ], [ false, %cond.end.i ]
   %f.08.i = phi i32 [ 0, %entry ], [ %inc.i, %cond.end.i ]
   %mul.i = select i1 %cmp1.i, i32 %f.08.i, i32 0
   br i1 %tmp1, label %cond.end.i, label %cond.true.i
 
 cond.true.i:
   ;; Ensure we don't replace this divide with a phi of ops that merges the wrong loop iteration value
-  %div.i = udiv i32 %mul.i, %f.08.i
+  %div.i = udiv nof i32 %mul.i, %f.08.i
   br label %cond.end.i
 
 cond.end.i:
   %cond.i = phi i32 [ %div.i, %cond.true.i ], [ 0, %for.body.i ]
   %inc.i = add nuw nsw i32 %f.08.i, 1
-  %test = udiv i32 %mul.i, %inc.i
+  %test = udiv nof i32 %mul.i, %inc.i
   %call5= tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), i32 %test)
   %exitcond.i = icmp eq i32 %inc.i, 4
   br i1 %exitcond.i, label %fn1.exit, label %for.body.i
 
 fn1.exit:
   %cond.i.lcssa = phi i32 [ %cond.i, %cond.end.i ]
   %call4= tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str4, i64 0, i64 0), i32 %cond.i.lcssa)
   ret i32 0
 }
 
 

test/Transforms/SLPVectorizer/AArch64/sdiv-pow2.ll

 ; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=aarch64-unknown-linux-gnu -mcpu=cortex-a57 | FileCheck %s
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
 
 ; CHECK-LABEL: @test1
 ; CHECK: load <4 x i32>
 ; CHECK: add nsw <4 x i32>
-; CHECK: sdiv <4 x i32>
+; CHECK: sdiv nof <4 x i32>
 
 define void @test1(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* noalias nocapture readonly %c) {
 entry:
   %0 = load i32, i32* %b, align 4
   %1 = load i32, i32* %c, align 4
   %add = add nsw i32 %1, %0
-  %div = sdiv i32 %add, 2
+  %div = sdiv nof i32 %add, 2
   store i32 %div, i32* %a, align 4
   %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 1
   %2 = load i32, i32* %arrayidx3, align 4
   %arrayidx4 = getelementptr inbounds i32, i32* %c, i64 1
   %3 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %3, %2
-  %div6 = sdiv i32 %add5, 2
+  %div6 = sdiv nof i32 %add5, 2
   %arrayidx7 = getelementptr inbounds i32, i32* %a, i64 1
   store i32 %div6, i32* %arrayidx7, align 4
   %arrayidx8 = getelementptr inbounds i32, i32* %b, i64 2
   %4 = load i32, i32* %arrayidx8, align 4
   %arrayidx9 = getelementptr inbounds i32, i32* %c, i64 2
   %5 = load i32, i32* %arrayidx9, align 4
   %add10 = add nsw i32 %5, %4
-  %div11 = sdiv i32 %add10, 2
+  %div11 = sdiv nof i32 %add10, 2
   %arrayidx12 = getelementptr inbounds i32, i32* %a, i64 2
   store i32 %div11, i32* %arrayidx12, align 4
   %arrayidx13 = getelementptr inbounds i32, i32* %b, i64 3
   %6 = load i32, i32* %arrayidx13, align 4
   %arrayidx14 = getelementptr inbounds i32, i32* %c, i64 3
   %7 = load i32, i32* %arrayidx14, align 4
   %add15 = add nsw i32 %7, %6
-  %div16 = sdiv i32 %add15, 2
+  %div16 = sdiv nof i32 %add15, 2
   %arrayidx17 = getelementptr inbounds i32, i32* %a, i64 3
   store i32 %div16, i32* %arrayidx17, align 4
   ret void
 }

test/Transforms/SLPVectorizer/X86/blending-shuffle.ll

 ; CHECK-LABEL: @j(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]], <2 x i32> <i32 0, i32 5>
 ; CHECK-NEXT:    [[TMP2:%.*]] = mul <2 x i8> [[TMP1]], [[TMP1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[Y]], <2 x i32> <i32 3, i32 6>
 ; CHECK-NEXT:    [[TMP4:%.*]] = mul <2 x i8> [[TMP3]], [[TMP3]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = add <2 x i8> [[TMP2]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i8> [[TMP5]], i32 0
 ; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i8> [[TMP5]], i32 1
-; CHECK-NEXT:    [[TMP8:%.*]] = sdiv i8 [[TMP6]], [[TMP7]]
+; CHECK-NEXT:    [[TMP8:%.*]] = sdiv nof i8 [[TMP6]], [[TMP7]]
 ; CHECK-NEXT:    ret i8 [[TMP8]]
 ;
   %x0 = extractelement <4 x i8> %x, i32 0
   %x3 = extractelement <4 x i8> %x, i32 3
   %y1 = extractelement <4 x i8> %y, i32 1
   %y2 = extractelement <4 x i8> %y, i32 2
   %x0x0 = mul i8 %x0, %x0
   %x3x3 = mul i8 %x3, %x3
   %y1y1 = mul i8 %y1, %y1
   %y2y2 = mul i8 %y2, %y2
   %1 = add i8 %x0x0, %x3x3
   %2 = add i8 %y1y1, %y2y2
-  %3 = sdiv i8 %1, %2
+  %3 = sdiv nof i8 %1, %2
   ret i8 %3
 }
 
 define i8 @k(<4 x i8> %x) {
 ; CHECK-LABEL: @k(
 ; CHECK-NEXT:    [[TMP1:%.*]] = mul <4 x i8> [[X:%.*]], [[X]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> undef, <2 x i32> <i32 0, i32 1>
 ; CHECK-NEXT:    [[TMP3:%.*]] = mul <4 x i8> [[X]], [[X]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> undef, <2 x i32> <i32 3, i32 2>
 ; CHECK-NEXT:    [[TMP5:%.*]] = add <2 x i8> [[TMP2]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i8> [[TMP5]], i32 0
 ; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i8> [[TMP5]], i32 1
-; CHECK-NEXT:    [[TMP8:%.*]] = sdiv i8 [[TMP6]], [[TMP7]]
+; CHECK-NEXT:    [[TMP8:%.*]] = sdiv nof i8 [[TMP6]], [[TMP7]]
 ; CHECK-NEXT:    ret i8 [[TMP8]]
 ;
   %x0 = extractelement <4 x i8> %x, i32 0
   %x3 = extractelement <4 x i8> %x, i32 3
   %x1 = extractelement <4 x i8> %x, i32 1
   %x2 = extractelement <4 x i8> %x, i32 2
   %x0x0 = mul i8 %x0, %x0
   %x3x3 = mul i8 %x3, %x3
   %x1x1 = mul i8 %x1, %x1
   %x2x2 = mul i8 %x2, %x2
   %1 = add i8 %x0x0, %x3x3
   %2 = add i8 %x1x1, %x2x2
-  %3 = sdiv i8 %1, %2
+  %3 = sdiv nof i8 %1, %2
   ret i8 %3
 }
 
 define i8 @k_bb(<4 x i8> %x) {
 ; CHECK-LABEL: @k_bb(
 ; CHECK-NEXT:    [[X0:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 0
 ; CHECK-NEXT:    br label [[BB1:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[X3:%.*]] = extractelement <4 x i8> [[X]], i32 3
 ; CHECK-NEXT:    [[X0X0:%.*]] = mul i8 [[X0]], [[X0]]
 ; CHECK-NEXT:    [[X3X3:%.*]] = mul i8 [[X3]], [[X3]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = mul <4 x i8> [[X]], [[X]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[X0X0]], [[X3X3]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
 ; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
 ; CHECK-NEXT:    [[TMP5:%.*]] = add i8 [[TMP3]], [[TMP4]]
-; CHECK-NEXT:    [[TMP6:%.*]] = sdiv i8 [[TMP2]], [[TMP5]]
+; CHECK-NEXT:    [[TMP6:%.*]] = sdiv nof i8 [[TMP2]], [[TMP5]]
 ; CHECK-NEXT:    ret i8 [[TMP6]]
 ;
   %x0 = extractelement <4 x i8> %x, i32 0
   br label %bb1
 bb1:
   %x3 = extractelement <4 x i8> %x, i32 3
   %x1 = extractelement <4 x i8> %x, i32 1
   %x2 = extractelement <4 x i8> %x, i32 2
   %x0x0 = mul i8 %x0, %x0
   %x3x3 = mul i8 %x3, %x3
   %x1x1 = mul i8 %x1, %x1
   %x2x2 = mul i8 %x2, %x2
   %1 = add i8 %x0x0, %x3x3
   %2 = add i8 %x1x1, %x2x2
-  %3 = sdiv i8 %1, %2
+  %3 = sdiv nof i8 %1, %2
   ret i8 %3
 }

test/Transforms/SLPVectorizer/X86/powof2div.ll

 ; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ;CHECK-LABEL: @powof2div(
 ;CHECK: load <4 x i32>, <4 x i32>*
 ;CHECK: add nsw <4 x i32>
-;CHECK: sdiv <4 x i32>
+;CHECK: sdiv nof <4 x i32>
 define void @powof2div(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* noalias nocapture readonly %c){
 entry:
   %0 = load i32, i32* %b, align 4
   %1 = load i32, i32* %c, align 4
   %add = add nsw i32 %1, %0
-  %div = sdiv i32 %add, 2
+  %div = sdiv nof i32 %add, 2
   store i32 %div, i32* %a, align 4
   %arrayidx3 = getelementptr inbounds i32, i32* %b, i64 1
   %2 = load i32, i32* %arrayidx3, align 4
   %arrayidx4 = getelementptr inbounds i32, i32* %c, i64 1
   %3 = load i32, i32* %arrayidx4, align 4
   %add5 = add nsw i32 %3, %2
-  %div6 = sdiv i32 %add5, 2
+  %div6 = sdiv nof i32 %add5, 2
   %arrayidx7 = getelementptr inbounds i32, i32* %a, i64 1
   store i32 %div6, i32* %arrayidx7, align 4
   %arrayidx8 = getelementptr inbounds i32, i32* %b, i64 2
   %4 = load i32, i32* %arrayidx8, align 4
   %arrayidx9 = getelementptr inbounds i32, i32* %c, i64 2
   %5 = load i32, i32* %arrayidx9, align 4
   %add10 = add nsw i32 %5, %4
-  %div11 = sdiv i32 %add10, 2
+  %div11 = sdiv nof i32 %add10, 2
   %arrayidx12 = getelementptr inbounds i32, i32* %a, i64 2
   store i32 %div11, i32* %arrayidx12, align 4
   %arrayidx13 = getelementptr inbounds i32, i32* %b, i64 3
   %6 = load i32, i32* %arrayidx13, align 4
   %arrayidx14 = getelementptr inbounds i32, i32* %c, i64 3
   %7 = load i32, i32* %arrayidx14, align 4
   %add15 = add nsw i32 %7, %6
-  %div16 = sdiv i32 %add15, 2
+  %div16 = sdiv nof i32 %add15, 2
   %arrayidx17 = getelementptr inbounds i32, i32* %a, i64 3
   store i32 %div16, i32* %arrayidx17, align 4
   ret void
 }
 

test/Transforms/ScalarizeMayOverflowDiv/scalarize-may-overflow-div.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -mcpu=atom -scalarize-may-overflow-div -S -o - | FileCheck %s --check-prefix=ATOM
+; RUN: opt %s -mcpu=core-avx2 -scalarize-may-overflow-div -S -o - | FileCheck %s --check-prefix=AVX2
+target triple = "x86_64-unknown-unknown"
+
+define i32 @udiv_scalarize_i32(i32 %op1, i32 %op2) {
+; ATOM-LABEL: @udiv_scalarize_i32(
+; ATOM-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[OP2:%.*]], 0
+; ATOM-NEXT:    br i1 [[TMP1]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; ATOM:       cond.div:
+; ATOM-NEXT:    [[TMP2:%.*]] = udiv nof i32 [[OP1:%.*]], [[OP2]]
+; ATOM-NEXT:    br label [[ELSE]]
+; ATOM:       else:
+; ATOM-NEXT:    [[RES_PHI_SELECT:%.*]] = phi i32 [ [[TMP2]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; ATOM-NEXT:    ret i32 [[RES_PHI_SELECT]]
+;
+; AVX2-LABEL: @udiv_scalarize_i32(
+; AVX2-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[OP2:%.*]], 0
+; AVX2-NEXT:    br i1 [[TMP1]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; AVX2:       cond.div:
+; AVX2-NEXT:    [[TMP2:%.*]] = udiv nof i32 [[OP1:%.*]], [[OP2]]
+; AVX2-NEXT:    br label [[ELSE]]
+; AVX2:       else:
+; AVX2-NEXT:    [[RES_PHI_SELECT:%.*]] = phi i32 [ [[TMP2]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; AVX2-NEXT:    ret i32 [[RES_PHI_SELECT]]
+;
+  %res = udiv mof i32 %op1, %op2
+  ret i32 %res;
+}
+
+define <1 x i32> @udiv_scalarize_v1i32(<1 x i32> %op1, <1 x i32> %op2) {
+; ATOM-LABEL: @udiv_scalarize_v1i32(
+; ATOM-NEXT:    [[TMP1:%.*]] = icmp ne <1 x i32> [[OP2:%.*]], zeroinitializer
+; ATOM-NEXT:    [[TMP2:%.*]] = extractelement <1 x i1> [[TMP1]], i64 0
+; ATOM-NEXT:    br i1 [[TMP2]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; ATOM:       cond.div:
+; ATOM-NEXT:    [[TMP3:%.*]] = extractelement <1 x i32> [[OP1:%.*]], i64 0
+; ATOM-NEXT:    [[TMP4:%.*]] = extractelement <1 x i32> [[OP2]], i64 0
+; ATOM-NEXT:    [[TMP5:%.*]] = udiv nof i32 [[TMP3]], [[TMP4]]
+; ATOM-NEXT:    [[TMP6:%.*]] = insertelement <1 x i32> undef, i32 [[TMP5]], i64 0
+; ATOM-NEXT:    br label [[ELSE]]
+; ATOM:       else:
+; ATOM-NEXT:    [[RES_PHI_SELECT:%.*]] = phi <1 x i32> [ [[TMP6]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; ATOM-NEXT:    ret <1 x i32> [[RES_PHI_SELECT]]
+;
+; AVX2-LABEL: @udiv_scalarize_v1i32(
+; AVX2-NEXT:    [[TMP1:%.*]] = icmp ne <1 x i32> [[OP2:%.*]], zeroinitializer
+; AVX2-NEXT:    [[TMP2:%.*]] = extractelement <1 x i1> [[TMP1]], i64 0
+; AVX2-NEXT:    br i1 [[TMP2]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; AVX2:       cond.div:
+; AVX2-NEXT:    [[TMP3:%.*]] = extractelement <1 x i32> [[OP1:%.*]], i64 0
+; AVX2-NEXT:    [[TMP4:%.*]] = extractelement <1 x i32> [[OP2]], i64 0
+; AVX2-NEXT:    [[TMP5:%.*]] = udiv nof i32 [[TMP3]], [[TMP4]]
+; AVX2-NEXT:    [[TMP6:%.*]] = insertelement <1 x i32> undef, i32 [[TMP5]], i64 0
+; AVX2-NEXT:    br label [[ELSE]]
+; AVX2:       else:
+; AVX2-NEXT:    [[RES_PHI_SELECT:%.*]] = phi <1 x i32> [ [[TMP6]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; AVX2-NEXT:    ret <1 x i32> [[RES_PHI_SELECT]]
+;
+  %res = udiv mof <1 x i32> %op1, %op2
+  ret <1 x i32> %res;
+}
+
+define i32 @sdiv_scalarize_i32(i32 %op1, i32 %op2) {
+; ATOM-LABEL: @sdiv_scalarize_i32(
+; ATOM-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[OP2:%.*]], 0
+; ATOM-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[OP2]], -1
+; ATOM-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[OP1:%.*]], -2147483648
+; ATOM-NEXT:    [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]]
+; ATOM-NEXT:    [[TMP5:%.*]] = and i1 [[TMP4]], [[TMP1]]
+; ATOM-NEXT:    br i1 [[TMP5]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; ATOM:       cond.div:
+; ATOM-NEXT:    [[TMP6:%.*]] = sdiv nof i32 [[OP1]], [[OP2]]
+; ATOM-NEXT:    br label [[ELSE]]
+; ATOM:       else:
+; ATOM-NEXT:    [[RES_PHI_SELECT:%.*]] = phi i32 [ [[TMP6]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; ATOM-NEXT:    ret i32 [[RES_PHI_SELECT]]
+;
+; AVX2-LABEL: @sdiv_scalarize_i32(
+; AVX2-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[OP2:%.*]], 0
+; AVX2-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[OP2]], -1
+; AVX2-NEXT:    [[TMP3:%.*]] = icmp ne i32 [[OP1:%.*]], -2147483648
+; AVX2-NEXT:    [[TMP4:%.*]] = or i1 [[TMP2]], [[TMP3]]
+; AVX2-NEXT:    [[TMP5:%.*]] = and i1 [[TMP4]], [[TMP1]]
+; AVX2-NEXT:    br i1 [[TMP5]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; AVX2:       cond.div:
+; AVX2-NEXT:    [[TMP6:%.*]] = sdiv nof i32 [[OP1]], [[OP2]]
+; AVX2-NEXT:    br label [[ELSE]]
+; AVX2:       else:
+; AVX2-NEXT:    [[RES_PHI_SELECT:%.*]] = phi i32 [ [[TMP6]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; AVX2-NEXT:    ret i32 [[RES_PHI_SELECT]]
+;
+  %res = sdiv mof i32 %op1, %op2
+  ret i32 %res;
+}
+
+define <1 x i32> @sdiv_scalarize_v1i32(<1 x i32> %op1, <1 x i32> %op2) {
+; ATOM-LABEL: @sdiv_scalarize_v1i32(
+; ATOM-NEXT:    [[TMP1:%.*]] = icmp ne <1 x i32> [[OP2:%.*]], zeroinitializer
+; ATOM-NEXT:    [[TMP2:%.*]] = icmp ne <1 x i32> [[OP2]], <i32 -1>
+; ATOM-NEXT:    [[TMP3:%.*]] = icmp ne <1 x i32> [[OP1:%.*]], <i32 -2147483648>
+; ATOM-NEXT:    [[TMP4:%.*]] = or <1 x i1> [[TMP2]], [[TMP3]]
+; ATOM-NEXT:    [[TMP5:%.*]] = and <1 x i1> [[TMP4]], [[TMP1]]
+; ATOM-NEXT:    [[TMP6:%.*]] = extractelement <1 x i1> [[TMP5]], i64 0
+; ATOM-NEXT:    br i1 [[TMP6]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; ATOM:       cond.div:
+; ATOM-NEXT:    [[TMP7:%.*]] = extractelement <1 x i32> [[OP1]], i64 0
+; ATOM-NEXT:    [[TMP8:%.*]] = extractelement <1 x i32> [[OP2]], i64 0
+; ATOM-NEXT:    [[TMP9:%.*]] = sdiv nof i32 [[TMP7]], [[TMP8]]
+; ATOM-NEXT:    [[TMP10:%.*]] = insertelement <1 x i32> undef, i32 [[TMP9]], i64 0
+; ATOM-NEXT:    br label [[ELSE]]
+; ATOM:       else:
+; ATOM-NEXT:    [[RES_PHI_SELECT:%.*]] = phi <1 x i32> [ [[TMP10]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; ATOM-NEXT:    ret <1 x i32> [[RES_PHI_SELECT]]
+;
+; AVX2-LABEL: @sdiv_scalarize_v1i32(
+; AVX2-NEXT:    [[TMP1:%.*]] = icmp ne <1 x i32> [[OP2:%.*]], zeroinitializer
+; AVX2-NEXT:    [[TMP2:%.*]] = icmp ne <1 x i32> [[OP2]], <i32 -1>
+; AVX2-NEXT:    [[TMP3:%.*]] = icmp ne <1 x i32> [[OP1:%.*]], <i32 -2147483648>
+; AVX2-NEXT:    [[TMP4:%.*]] = or <1 x i1> [[TMP2]], [[TMP3]]
+; AVX2-NEXT:    [[TMP5:%.*]] = and <1 x i1> [[TMP4]], [[TMP1]]
+; AVX2-NEXT:    [[TMP6:%.*]] = extractelement <1 x i1> [[TMP5]], i64 0
+; AVX2-NEXT:    br i1 [[TMP6]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; AVX2:       cond.div:
+; AVX2-NEXT:    [[TMP7:%.*]] = extractelement <1 x i32> [[OP1]], i64 0
+; AVX2-NEXT:    [[TMP8:%.*]] = extractelement <1 x i32> [[OP2]], i64 0
+; AVX2-NEXT:    [[TMP9:%.*]] = sdiv nof i32 [[TMP7]], [[TMP8]]
+; AVX2-NEXT:    [[TMP10:%.*]] = insertelement <1 x i32> undef, i32 [[TMP9]], i64 0
+; AVX2-NEXT:    br label [[ELSE]]
+; AVX2:       else:
+; AVX2-NEXT:    [[RES_PHI_SELECT:%.*]] = phi <1 x i32> [ [[TMP10]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; AVX2-NEXT:    ret <1 x i32> [[RES_PHI_SELECT]]
+;
+  %res = sdiv mof <1 x i32> %op1, %op2
+  ret <1 x i32> %res;
+}
+
+define <4 x i32> @udiv_scalarize(<4 x i32> %op1, <4 x i32> %op2) {
+; ATOM-LABEL: @udiv_scalarize(
+; ATOM-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[OP2:%.*]], zeroinitializer
+; ATOM-NEXT:    [[TMP2:%.*]] = extractelement <4 x i1> [[TMP1]], i64 0
+; ATOM-NEXT:    br i1 [[TMP2]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; ATOM:       cond.div:
+; ATOM-NEXT:    [[TMP3:%.*]] = extractelement <4 x i32> [[OP1:%.*]], i64 0
+; ATOM-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[OP2]], i64 0
+; ATOM-NEXT:    [[TMP5:%.*]] = udiv nof i32 [[TMP3]], [[TMP4]]
+; ATOM-NEXT:    [[TMP6:%.*]] = insertelement <4 x i32> undef, i32 [[TMP5]], i64 0
+; ATOM-NEXT:    br label [[ELSE]]
+; ATOM:       else:
+; ATOM-NEXT:    [[RES_PHI_ELSE:%.*]] = phi <4 x i32> [ [[TMP6]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; ATOM-NEXT:    [[TMP7:%.*]] = extractelement <4 x i1> [[TMP1]], i64 1
+; ATOM-NEXT:    br i1 [[TMP7]], label [[COND_DIV1:%.*]], label [[ELSE2:%.*]]
+; ATOM:       cond.div1:
+; ATOM-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[OP1]], i64 1
+; ATOM-NEXT:    [[TMP9:%.*]] = extractelement <4 x i32> [[OP2]], i64 1
+; ATOM-NEXT:    [[TMP10:%.*]] = udiv nof i32 [[TMP8]], [[TMP9]]
+; ATOM-NEXT:    [[TMP11:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE]], i32 [[TMP10]], i64 1
+; ATOM-NEXT:    br label [[ELSE2]]
+; ATOM:       else2:
+; ATOM-NEXT:    [[RES_PHI_ELSE3:%.*]] = phi <4 x i32> [ [[TMP11]], [[COND_DIV1]] ], [ [[RES_PHI_ELSE]], [[ELSE]] ]
+; ATOM-NEXT:    [[TMP12:%.*]] = extractelement <4 x i1> [[TMP1]], i64 2
+; ATOM-NEXT:    br i1 [[TMP12]], label [[COND_DIV4:%.*]], label [[ELSE5:%.*]]
+; ATOM:       cond.div4:
+; ATOM-NEXT:    [[TMP13:%.*]] = extractelement <4 x i32> [[OP1]], i64 2
+; ATOM-NEXT:    [[TMP14:%.*]] = extractelement <4 x i32> [[OP2]], i64 2
+; ATOM-NEXT:    [[TMP15:%.*]] = udiv nof i32 [[TMP13]], [[TMP14]]
+; ATOM-NEXT:    [[TMP16:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE3]], i32 [[TMP15]], i64 2
+; ATOM-NEXT:    br label [[ELSE5]]
+; ATOM:       else5:
+; ATOM-NEXT:    [[RES_PHI_ELSE6:%.*]] = phi <4 x i32> [ [[TMP16]], [[COND_DIV4]] ], [ [[RES_PHI_ELSE3]], [[ELSE2]] ]
+; ATOM-NEXT:    [[TMP17:%.*]] = extractelement <4 x i1> [[TMP1]], i64 3
+; ATOM-NEXT:    br i1 [[TMP17]], label [[COND_DIV7:%.*]], label [[ELSE8:%.*]]
+; ATOM:       cond.div7:
+; ATOM-NEXT:    [[TMP18:%.*]] = extractelement <4 x i32> [[OP1]], i64 3
+; ATOM-NEXT:    [[TMP19:%.*]] = extractelement <4 x i32> [[OP2]], i64 3
+; ATOM-NEXT:    [[TMP20:%.*]] = udiv nof i32 [[TMP18]], [[TMP19]]
+; ATOM-NEXT:    [[TMP21:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE6]], i32 [[TMP20]], i64 3
+; ATOM-NEXT:    br label [[ELSE8]]
+; ATOM:       else8:
+; ATOM-NEXT:    [[RES_PHI_SELECT:%.*]] = phi <4 x i32> [ [[TMP21]], [[COND_DIV7]] ], [ [[RES_PHI_ELSE6]], [[ELSE5]] ]
+; ATOM-NEXT:    ret <4 x i32> [[RES_PHI_SELECT]]
+;
+; AVX2-LABEL: @udiv_scalarize(
+; AVX2-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[OP2:%.*]], zeroinitializer
+; AVX2-NEXT:    [[TMP2:%.*]] = extractelement <4 x i1> [[TMP1]], i64 0
+; AVX2-NEXT:    br i1 [[TMP2]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; AVX2:       cond.div:
+; AVX2-NEXT:    [[TMP3:%.*]] = extractelement <4 x i32> [[OP1:%.*]], i64 0
+; AVX2-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[OP2]], i64 0
+; AVX2-NEXT:    [[TMP5:%.*]] = udiv nof i32 [[TMP3]], [[TMP4]]
+; AVX2-NEXT:    [[TMP6:%.*]] = insertelement <4 x i32> undef, i32 [[TMP5]], i64 0
+; AVX2-NEXT:    br label [[ELSE]]
+; AVX2:       else:
+; AVX2-NEXT:    [[RES_PHI_ELSE:%.*]] = phi <4 x i32> [ [[TMP6]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; AVX2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i1> [[TMP1]], i64 1
+; AVX2-NEXT:    br i1 [[TMP7]], label [[COND_DIV1:%.*]], label [[ELSE2:%.*]]
+; AVX2:       cond.div1:
+; AVX2-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[OP1]], i64 1
+; AVX2-NEXT:    [[TMP9:%.*]] = extractelement <4 x i32> [[OP2]], i64 1
+; AVX2-NEXT:    [[TMP10:%.*]] = udiv nof i32 [[TMP8]], [[TMP9]]
+; AVX2-NEXT:    [[TMP11:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE]], i32 [[TMP10]], i64 1
+; AVX2-NEXT:    br label [[ELSE2]]
+; AVX2:       else2:
+; AVX2-NEXT:    [[RES_PHI_ELSE3:%.*]] = phi <4 x i32> [ [[TMP11]], [[COND_DIV1]] ], [ [[RES_PHI_ELSE]], [[ELSE]] ]
+; AVX2-NEXT:    [[TMP12:%.*]] = extractelement <4 x i1> [[TMP1]], i64 2
+; AVX2-NEXT:    br i1 [[TMP12]], label [[COND_DIV4:%.*]], label [[ELSE5:%.*]]
+; AVX2:       cond.div4:
+; AVX2-NEXT:    [[TMP13:%.*]] = extractelement <4 x i32> [[OP1]], i64 2
+; AVX2-NEXT:    [[TMP14:%.*]] = extractelement <4 x i32> [[OP2]], i64 2
+; AVX2-NEXT:    [[TMP15:%.*]] = udiv nof i32 [[TMP13]], [[TMP14]]
+; AVX2-NEXT:    [[TMP16:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE3]], i32 [[TMP15]], i64 2
+; AVX2-NEXT:    br label [[ELSE5]]
+; AVX2:       else5:
+; AVX2-NEXT:    [[RES_PHI_ELSE6:%.*]] = phi <4 x i32> [ [[TMP16]], [[COND_DIV4]] ], [ [[RES_PHI_ELSE3]], [[ELSE2]] ]
+; AVX2-NEXT:    [[TMP17:%.*]] = extractelement <4 x i1> [[TMP1]], i64 3
+; AVX2-NEXT:    br i1 [[TMP17]], label [[COND_DIV7:%.*]], label [[ELSE8:%.*]]
+; AVX2:       cond.div7:
+; AVX2-NEXT:    [[TMP18:%.*]] = extractelement <4 x i32> [[OP1]], i64 3
+; AVX2-NEXT:    [[TMP19:%.*]] = extractelement <4 x i32> [[OP2]], i64 3
+; AVX2-NEXT:    [[TMP20:%.*]] = udiv nof i32 [[TMP18]], [[TMP19]]
+; AVX2-NEXT:    [[TMP21:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE6]], i32 [[TMP20]], i64 3
+; AVX2-NEXT:    br label [[ELSE8]]
+; AVX2:       else8:
+; AVX2-NEXT:    [[RES_PHI_SELECT:%.*]] = phi <4 x i32> [ [[TMP21]], [[COND_DIV7]] ], [ [[RES_PHI_ELSE6]], [[ELSE5]] ]
+; AVX2-NEXT:    ret <4 x i32> [[RES_PHI_SELECT]]
+;
+  %res = udiv mof <4 x i32> %op1, %op2
+  ret <4 x i32> %res;
+}
+
+define <4 x i32> @sdiv_scalarize(<4 x i32> %op1, <4 x i32> %op2) {
+; ATOM-LABEL: @sdiv_scalarize(
+; ATOM-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[OP2:%.*]], zeroinitializer
+; ATOM-NEXT:    [[TMP2:%.*]] = icmp ne <4 x i32> [[OP2]], <i32 -1, i32 -1, i32 -1, i32 -1>
+; ATOM-NEXT:    [[TMP3:%.*]] = icmp ne <4 x i32> [[OP1:%.*]], <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
+; ATOM-NEXT:    [[TMP4:%.*]] = or <4 x i1> [[TMP2]], [[TMP3]]
+; ATOM-NEXT:    [[TMP5:%.*]] = and <4 x i1> [[TMP4]], [[TMP1]]
+; ATOM-NEXT:    [[TMP6:%.*]] = extractelement <4 x i1> [[TMP5]], i64 0
+; ATOM-NEXT:    br i1 [[TMP6]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; ATOM:       cond.div:
+; ATOM-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[OP1]], i64 0
+; ATOM-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[OP2]], i64 0
+; ATOM-NEXT:    [[TMP9:%.*]] = sdiv nof i32 [[TMP7]], [[TMP8]]
+; ATOM-NEXT:    [[TMP10:%.*]] = insertelement <4 x i32> undef, i32 [[TMP9]], i64 0
+; ATOM-NEXT:    br label [[ELSE]]
+; ATOM:       else:
+; ATOM-NEXT:    [[RES_PHI_ELSE:%.*]] = phi <4 x i32> [ [[TMP10]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; ATOM-NEXT:    [[TMP11:%.*]] = extractelement <4 x i1> [[TMP5]], i64 1
+; ATOM-NEXT:    br i1 [[TMP11]], label [[COND_DIV1:%.*]], label [[ELSE2:%.*]]
+; ATOM:       cond.div1:
+; ATOM-NEXT:    [[TMP12:%.*]] = extractelement <4 x i32> [[OP1]], i64 1
+; ATOM-NEXT:    [[TMP13:%.*]] = extractelement <4 x i32> [[OP2]], i64 1
+; ATOM-NEXT:    [[TMP14:%.*]] = sdiv nof i32 [[TMP12]], [[TMP13]]
+; ATOM-NEXT:    [[TMP15:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE]], i32 [[TMP14]], i64 1
+; ATOM-NEXT:    br label [[ELSE2]]
+; ATOM:       else2:
+; ATOM-NEXT:    [[RES_PHI_ELSE3:%.*]] = phi <4 x i32> [ [[TMP15]], [[COND_DIV1]] ], [ [[RES_PHI_ELSE]], [[ELSE]] ]
+; ATOM-NEXT:    [[TMP16:%.*]] = extractelement <4 x i1> [[TMP5]], i64 2
+; ATOM-NEXT:    br i1 [[TMP16]], label [[COND_DIV4:%.*]], label [[ELSE5:%.*]]
+; ATOM:       cond.div4:
+; ATOM-NEXT:    [[TMP17:%.*]] = extractelement <4 x i32> [[OP1]], i64 2
+; ATOM-NEXT:    [[TMP18:%.*]] = extractelement <4 x i32> [[OP2]], i64 2
+; ATOM-NEXT:    [[TMP19:%.*]] = sdiv nof i32 [[TMP17]], [[TMP18]]
+; ATOM-NEXT:    [[TMP20:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE3]], i32 [[TMP19]], i64 2
+; ATOM-NEXT:    br label [[ELSE5]]
+; ATOM:       else5:
+; ATOM-NEXT:    [[RES_PHI_ELSE6:%.*]] = phi <4 x i32> [ [[TMP20]], [[COND_DIV4]] ], [ [[RES_PHI_ELSE3]], [[ELSE2]] ]
+; ATOM-NEXT:    [[TMP21:%.*]] = extractelement <4 x i1> [[TMP5]], i64 3
+; ATOM-NEXT:    br i1 [[TMP21]], label [[COND_DIV7:%.*]], label [[ELSE8:%.*]]
+; ATOM:       cond.div7:
+; ATOM-NEXT:    [[TMP22:%.*]] = extractelement <4 x i32> [[OP1]], i64 3
+; ATOM-NEXT:    [[TMP23:%.*]] = extractelement <4 x i32> [[OP2]], i64 3
+; ATOM-NEXT:    [[TMP24:%.*]] = sdiv nof i32 [[TMP22]], [[TMP23]]
+; ATOM-NEXT:    [[TMP25:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE6]], i32 [[TMP24]], i64 3
+; ATOM-NEXT:    br label [[ELSE8]]
+; ATOM:       else8:
+; ATOM-NEXT:    [[RES_PHI_SELECT:%.*]] = phi <4 x i32> [ [[TMP25]], [[COND_DIV7]] ], [ [[RES_PHI_ELSE6]], [[ELSE5]] ]
+; ATOM-NEXT:    ret <4 x i32> [[RES_PHI_SELECT]]
+;
+; AVX2-LABEL: @sdiv_scalarize(
+; AVX2-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[OP2:%.*]], zeroinitializer
+; AVX2-NEXT:    [[TMP2:%.*]] = icmp ne <4 x i32> [[OP2]], <i32 -1, i32 -1, i32 -1, i32 -1>
+; AVX2-NEXT:    [[TMP3:%.*]] = icmp ne <4 x i32> [[OP1:%.*]], <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
+; AVX2-NEXT:    [[TMP4:%.*]] = or <4 x i1> [[TMP2]], [[TMP3]]
+; AVX2-NEXT:    [[TMP5:%.*]] = and <4 x i1> [[TMP4]], [[TMP1]]
+; AVX2-NEXT:    [[TMP6:%.*]] = extractelement <4 x i1> [[TMP5]], i64 0
+; AVX2-NEXT:    br i1 [[TMP6]], label [[COND_DIV:%.*]], label [[ELSE:%.*]]
+; AVX2:       cond.div:
+; AVX2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[OP1]], i64 0
+; AVX2-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[OP2]], i64 0
+; AVX2-NEXT:    [[TMP9:%.*]] = sdiv nof i32 [[TMP7]], [[TMP8]]
+; AVX2-NEXT:    [[TMP10:%.*]] = insertelement <4 x i32> undef, i32 [[TMP9]], i64 0
+; AVX2-NEXT:    br label [[ELSE]]
+; AVX2:       else:
+; AVX2-NEXT:    [[RES_PHI_ELSE:%.*]] = phi <4 x i32> [ [[TMP10]], [[COND_DIV]] ], [ undef, [[TMP0:%.*]] ]
+; AVX2-NEXT:    [[TMP11:%.*]] = extractelement <4 x i1> [[TMP5]], i64 1
+; AVX2-NEXT:    br i1 [[TMP11]], label [[COND_DIV1:%.*]], label [[ELSE2:%.*]]
+; AVX2:       cond.div1:
+; AVX2-NEXT:    [[TMP12:%.*]] = extractelement <4 x i32> [[OP1]], i64 1
+; AVX2-NEXT:    [[TMP13:%.*]] = extractelement <4 x i32> [[OP2]], i64 1
+; AVX2-NEXT:    [[TMP14:%.*]] = sdiv nof i32 [[TMP12]], [[TMP13]]
+; AVX2-NEXT:    [[TMP15:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE]], i32 [[TMP14]], i64 1
+; AVX2-NEXT:    br label [[ELSE2]]
+; AVX2:       else2:
+; AVX2-NEXT:    [[RES_PHI_ELSE3:%.*]] = phi <4 x i32> [ [[TMP15]], [[COND_DIV1]] ], [ [[RES_PHI_ELSE]], [[ELSE]] ]
+; AVX2-NEXT:    [[TMP16:%.*]] = extractelement <4 x i1> [[TMP5]], i64 2
+; AVX2-NEXT:    br i1 [[TMP16]], label [[COND_DIV4:%.*]], label [[ELSE5:%.*]]
+; AVX2:       cond.div4:
+; AVX2-NEXT:    [[TMP17:%.*]] = extractelement <4 x i32> [[OP1]], i64 2
+; AVX2-NEXT:    [[TMP18:%.*]] = extractelement <4 x i32> [[OP2]], i64 2
+; AVX2-NEXT:    [[TMP19:%.*]] = sdiv nof i32 [[TMP17]], [[TMP18]]
+; AVX2-NEXT:    [[TMP20:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE3]], i32 [[TMP19]], i64 2
+; AVX2-NEXT:    br label [[ELSE5]]
+; AVX2:       else5:
+; AVX2-NEXT:    [[RES_PHI_ELSE6:%.*]] = phi <4 x i32> [ [[TMP20]], [[COND_DIV4]] ], [ [[RES_PHI_ELSE3]], [[ELSE2]] ]
+; AVX2-NEXT:    [[TMP21:%.*]] = extractelement <4 x i1> [[TMP5]], i64 3
+; AVX2-NEXT:    br i1 [[TMP21]], label [[COND_DIV7:%.*]], label [[ELSE8:%.*]]
+; AVX2:       cond.div7:
+; AVX2-NEXT:    [[TMP22:%.*]] = extractelement <4 x i32> [[OP1]], i64 3
+; AVX2-NEXT:    [[TMP23:%.*]] = extractelement <4 x i32> [[OP2]], i64 3
+; AVX2-NEXT:    [[TMP24:%.*]] = sdiv nof i32 [[TMP22]], [[TMP23]]
+; AVX2-NEXT:    [[TMP25:%.*]] = insertelement <4 x i32> [[RES_PHI_ELSE6]], i32 [[TMP24]], i64 3
+; AVX2-NEXT:    br label [[ELSE8]]
+; AVX2:       else8:
+; AVX2-NEXT:    [[RES_PHI_SELECT:%.*]] = phi <4 x i32> [ [[TMP25]], [[COND_DIV7]] ], [ [[RES_PHI_ELSE6]], [[ELSE5]] ]
+; AVX2-NEXT:    ret <4 x i32> [[RES_PHI_SELECT]]
+;
+  %res = sdiv mof <4 x i32> %op1, %op2
+  ret <4 x i32> %res;
+}

test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -S | FileCheck %s
 
 @G = extern_weak global i32
 
 ; PR3354
 ; Do not merge bb1 into the entry block, it might trap.
 
 define i32 @admiral(i32 %a, i32 %b) {
 ; CHECK-LABEL: @admiral(
 ; CHECK-NEXT:    [[C:%.*]] = icmp sle i32 %a, %b
 ; CHECK-NEXT:    br i1 [[C]], label %bb2, label %bb1
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[D:%.*]] = icmp sgt i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
+; CHECK-NEXT:    [[D:%.*]] = icmp sgt i32 sdiv nof (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
 ; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[D]], i32 927, i32 42
 ; CHECK-NEXT:    br label %bb2
 ; CHECK:       bb2:
 ; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 42, %0 ], [ [[DOT]], %bb1 ]
 ; CHECK-NEXT:    ret i32 [[MERGE]]
 ;
   %c = icmp sle i32 %a, %b
   br i1 %c, label %bb2, label %bb1
 bb1:
-  %d = icmp sgt i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
+  %d = icmp sgt i32 sdiv nof (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
   br i1 %d, label %bb6, label %bb2
 bb2:
   ret i32 42
 bb6:
   ret i32 927
 }
 
 define i32 @ackbar(i1 %c) {
 ; CHECK-LABEL: @ackbar(
 ; CHECK-NEXT:    br i1 %c, label %bb5, label %bb6
 ; CHECK:       bb5:
-; CHECK-NEXT:    [[DOT:%.*]] = select i1 icmp sgt (i32 sdiv (i32 32767, i32 ptrtoint (i32* @G to i32)), i32 0), i32 42, i32 927
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 icmp sgt (i32 sdiv nof (i32 32767, i32 ptrtoint (i32* @G to i32)), i32 0), i32 42, i32 927
 ; CHECK-NEXT:    br label %bb6
 ; CHECK:       bb6:
 ; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 42, %0 ], [ [[DOT]], %bb5 ]
 ; CHECK-NEXT:    ret i32 [[MERGE]]
 ;
   br i1 %c, label %bb5, label %bb6
 bb5:
-  br i1 icmp sgt (i32 sdiv (i32 32767, i32 ptrtoint (i32* @G to i32)), i32 0), label %bb6, label %bb7
+  br i1 icmp sgt (i32 sdiv nof (i32 32767, i32 ptrtoint (i32* @G to i32)), i32 0), label %bb6, label %bb7
 bb6:
   ret i32 42
 bb7:
   ret i32 927
 }
 
 ; FP ops don't trap by default, so this is safe to hoist.
 

test/Transforms/SimplifyCFG/div-rem-pairs.ll

 ; RUN: opt -simplifycfg -S < %s | FileCheck %s
 
 ; We could hoist the div/rem in these tests because it's safe to do so.
 ; PR31028 - https://bugs.llvm.org/show_bug.cgi?id=31028
 ; ...but since there's a separate pass for that, don't bother.
 
 define i32 @hoist_sdiv(i32 %a, i32 %b) {
 ; CHECK-LABEL: @hoist_sdiv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i32 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[REM]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i32 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i32 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
 entry:
   %rem = srem i32 %a, %b
   %cmp = icmp eq i32 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = sdiv i32 %a, %b
+  %div = sdiv nof i32 %a, %b
   br label %end
 
 end:
   %ret = phi i32 [ %div, %if ], [ 3, %entry ]
   ret i32 %ret
 }
 
 define i64 @hoist_udiv(i64 %a, i64 %b) {
 ; CHECK-LABEL: @hoist_udiv(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[REM:%.*]] = urem i64 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i64 [[REM]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i64 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i64 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i64 [ [[DIV]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i64 [[RET]]
 ;
 entry:
   %rem = urem i64 %a, %b
   %cmp = icmp eq i64 %rem, 42
   br i1 %cmp, label %if, label %end
 
 if:
-  %div = udiv i64 %a, %b
+  %div = udiv nof i64 %a, %b
   br label %end
 
 end:
   %ret = phi i64 [ %div, %if ], [ 3, %entry ]
   ret i64 %ret
 }
 
 define i16 @hoist_srem(i16 %a, i16 %b) {
 ; CHECK-LABEL: @hoist_srem(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = sdiv i16 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv nof i16 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i16 [[DIV]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    [[REM:%.*]] = srem i16 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i16 [ [[REM]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i16 [[RET]]
 ;
 entry:
-  %div = sdiv i16 %a, %b
+  %div = sdiv nof i16 %a, %b
   %cmp = icmp eq i16 %div, 42
   br i1 %cmp, label %if, label %end
 
 if:
   %rem = srem i16 %a, %b
   br label %end
 
 end:
   %ret = phi i16 [ %rem, %if ], [ 3, %entry ]
   ret i16 %ret
 }
 
 define i8 @hoist_urem(i8 %a, i8 %b) {
 ; CHECK-LABEL: @hoist_urem(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i8 %a, %b
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i8 %a, %b
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[DIV]], 42
 ; CHECK-NEXT:    br i1 [[CMP]], label %if, label %end
 ; CHECK:       if:
 ; CHECK-NEXT:    [[REM:%.*]] = urem i8 %a, %b
 ; CHECK-NEXT:    br label %end
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i8 [ [[REM]], %if ], [ 3, %entry ]
 ; CHECK-NEXT:    ret i8 [[RET]]
 ;
 entry:
-  %div = udiv i8 %a, %b
+  %div = udiv nof i8 %a, %b
   %cmp = icmp eq i8 %div, 42
   br i1 %cmp, label %if, label %end
 
 if:
   %rem = urem i8 %a, %b
   br label %end
 
 end:
   %ret = phi i8 [ %rem, %if ], [ 3, %entry ]
   ret i8 %ret
 }
 

test/Transforms/SimplifyCFG/multiple-phis.ll

 ; CHECK-NEXT:    br label [[WHILE_COND:%.*]]
 ; CHECK:       while.cond:
 ; CHECK-NEXT:    [[HIGH_ADDR_0:%.*]] = phi i32 [ [[HIGH:%.*]], [[ENTRY:%.*]] ], [ [[DIV_HIGH_ADDR_0:%.*]], [[WHILE_BODY:%.*]] ]
 ; CHECK-NEXT:    [[LOW_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[LOW_0_ADD2:%.*]], [[WHILE_BODY]] ]
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[LOW_0]], [[HIGH_ADDR_0]]
 ; CHECK-NEXT:    br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END:%.*]]
 ; CHECK:       while.body:
 ; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[LOW_0]], [[HIGH_ADDR_0]]
-; CHECK-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 2
+; CHECK-NEXT:    [[DIV:%.*]] = udiv nof i32 [[ADD]], 2
 ; CHECK-NEXT:    [[IDXPROM:%.*]] = zext i32 [[DIV]] to i64
 ; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[R:%.*]], i64 [[IDXPROM]]
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]]
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp ult i32 [[K:%.*]], [[TMP0]]
 ; CHECK-NEXT:    [[ADD2:%.*]] = add i32 [[DIV]], 1
 ; CHECK-NEXT:    [[DIV_HIGH_ADDR_0]] = select i1 [[CMP1]], i32 [[DIV]], i32 [[HIGH_ADDR_0]]
 ; CHECK-NEXT:    [[LOW_0_ADD2]] = select i1 [[CMP1]], i32 [[LOW_0]], i32 [[ADD2]]
 ; CHECK-NEXT:    br label [[WHILE_COND]]
 ; CHECK:       while.end:
 ; CHECK-NEXT:    ret i32 [[LOW_0]]
 ;
 entry:
   br label %while.cond
 
 while.cond:                                       ; preds = %if.then, %if.else, %entry
   %high.addr.0 = phi i32 [ %high, %entry ], [ %div, %if.then ], [ %high.addr.0, %if.else ]
   %low.0 = phi i32 [ 0, %entry ], [ %low.0, %if.then ], [ %add2, %if.else ]
   %cmp = icmp ult i32 %low.0, %high.addr.0
   br i1 %cmp, label %while.body, label %while.end
 
 while.body:                                       ; preds = %while.cond
   %add = add i32 %low.0, %high.addr.0
-  %div = udiv i32 %add, 2
+  %div = udiv nof i32 %add, 2
   %idxprom = zext i32 %div to i64
   %arrayidx = getelementptr inbounds i32, i32* %r, i64 %idxprom
   %0 = load i32, i32* %arrayidx
   %cmp1 = icmp ult i32 %k, %0
   br i1 %cmp1, label %if.then, label %if.else
 
 if.then:                                          ; preds = %while.body
   br label %while.cond
 
 if.else:                                          ; preds = %while.body
   %add2 = add i32 %div, 1
   br label %while.cond
 
 while.end:                                        ; preds = %while.cond
   ret i32 %low.0
 }

test/Transforms/Util/PredicateInfo/pr33456.ll

 ; CHECK:         [[TMP4:%.*]] = load i32, i32* @a, align 4
 ; CHECK-NEXT:    [[TMP5:%.*]] = load i32, i32* @c, align 4
 ; CHECK-NEXT:    [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 1
 ; CHECK-NEXT:    br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP9:%.*]]
 ; CHECK:         [[TMP8:%.*]] = icmp eq i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[TMP8]], label [[TMP9]], label [[TMP9]]
 ; CHECK:         [[DOT0:%.*]] = phi i32 [ [[TMP4]], [[TMP7]] ], [ [[TMP4]], [[TMP7]] ], [ [[DOT1:%.*]], [[TMP13]] ], [ [[TMP4]], [[TMP3]] ]
 ; CHECK-NEXT:    [[TMP10:%.*]] = load i32, i32* @b, align 4
-; CHECK-NEXT:    [[TMP11:%.*]] = sdiv i32 [[TMP10]], [[DOT0]]
+; CHECK-NEXT:    [[TMP11:%.*]] = sdiv nof i32 [[TMP10]], [[DOT0]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[TMP11]], 0
 ; CHECK-NEXT:    br i1 [[TMP12]], label [[TMP13]], label [[TMP13]]
 ; CHECK:         [[DOT1]] = phi i32 [ [[DOT0]], [[TMP9]] ], [ [[DOT0]], [[TMP9]] ], [ undef, [[TMP0:%.*]] ]
 ; CHECK-NEXT:    [[TMP14:%.*]] = load i32, i32* @e, align 4
 ; CHECK-NEXT:    [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0
 ; CHECK-NEXT:    br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP9]]
 ; CHECK:         ret i32 0
 ;

tools/llc/llc.cpp

int main(int argc, char **argv) {
   initializeLowerIntrinsicsPass(*Registry);
   initializeEntryExitInstrumenterPass(*Registry);
   initializePostInlineEntryExitInstrumenterPass(*Registry);
   initializeUnreachableBlockElimLegacyPassPass(*Registry);
   initializeConstantHoistingLegacyPassPass(*Registry);
   initializeScalarOpts(*Registry);
   initializeVectorization(*Registry);
   initializeScalarizeMaskedMemIntrinPass(*Registry);
+  initializeScalarizeMayOverflowDivPass(*Registry);
   initializeExpandReductionsPass(*Registry);
 
   // Initialize debugging passes.
   initializeScavengerTestPass(*Registry);
 
   // Register the target printer for --version.
   cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion);
 

tools/opt/opt.cpp

int main(int argc, char **argv) {
   initializeInstCombine(Registry);
   initializeAggressiveInstCombinerLegacyPassPass(Registry);
   initializeInstrumentation(Registry);
   initializeTarget(Registry);
   // For codegen passes, only passes that do IR to IR transformation are
   // supported.
   initializeExpandMemCmpPassPass(Registry);
   initializeScalarizeMaskedMemIntrinPass(Registry);
+  initializeScalarizeMayOverflowDivPass(Registry);
   initializeCodeGenPreparePass(Registry);
   initializeAtomicExpandPass(Registry);
   initializeRewriteSymbolsLegacyPassPass(Registry);
   initializeWinEHPreparePass(Registry);
   initializeDwarfEHPreparePass(Registry);
   initializeSafeStackLegacyPassPass(Registry);
   initializeSjLjEHPreparePass(Registry);
   initializePreISelIntrinsicLoweringLegacyPassPass(Registry);

unittests/IR/ConstantsTest.cpp

CHECK(ConstantExpr::getAdd(P0, P0, false, true), "add nsw i32 " P0STR ", "
         P0STR);
   CHECK(ConstantExpr::getAdd(P0, P0, true, true), "add nuw nsw i32 " P0STR ", "
         P0STR);
   CHECK(ConstantExpr::getFAdd(P1, P1), "fadd float " P1STR ", " P1STR);
   CHECK(ConstantExpr::getSub(P0, P0), "sub i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getFSub(P1, P1), "fsub float " P1STR ", " P1STR);
   CHECK(ConstantExpr::getMul(P0, P0), "mul i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getFMul(P1, P1), "fmul float " P1STR ", " P1STR);
-  CHECK(ConstantExpr::getUDiv(P0, P0), "udiv i32 " P0STR ", " P0STR);
-  CHECK(ConstantExpr::getSDiv(P0, P0), "sdiv i32 " P0STR ", " P0STR);
+  CHECK(ConstantExpr::getUDiv(P0, P0), "udiv nof i32 " P0STR ", " P0STR);
+  CHECK(ConstantExpr::getSDiv(P0, P0), "sdiv nof i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getFDiv(P1, P1), "fdiv float " P1STR ", " P1STR);
   CHECK(ConstantExpr::getURem(P0, P0), "urem i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getSRem(P0, P0), "srem i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getFRem(P1, P1), "frem float " P1STR ", " P1STR);
   CHECK(ConstantExpr::getAnd(P0, P0), "and i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getOr(P0, P0), "or i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getXor(P0, P0), "xor i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getShl(P0, P0), "shl i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getShl(P0, P0, true), "shl nuw i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getShl(P0, P0, false, true), "shl nsw i32 " P0STR ", "
         P0STR);
   CHECK(ConstantExpr::getLShr(P0, P0, false), "lshr i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getLShr(P0, P0, true), "lshr exact i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getAShr(P0, P0, false), "ashr i32 " P0STR ", " P0STR);
   CHECK(ConstantExpr::getAShr(P0, P0, true), "ashr exact i32 " P0STR ", " P0STR);
 
   CHECK(ConstantExpr::getSExt(P0, Int64Ty), "sext i32 " P0STR " to i64");
   CHECK(ConstantExpr::getZExt(P0, Int64Ty), "zext i32 " P0STR " to i64");
   CHECK(ConstantExpr::getFPTrunc(P2, FloatTy), "fptrunc double " P2STR
         " to float");
   CHECK(ConstantExpr::getFPExtend(P1, DoubleTy), "fpext float " P1STR
         " to double");
 
-  CHECK(ConstantExpr::getExactUDiv(P0, P0), "udiv exact i32 " P0STR ", " P0STR);
+  CHECK(ConstantExpr::getExactUDiv(P0, P0),
+        "udiv exact nof i32 " P0STR ", " P0STR);
 
   CHECK(ConstantExpr::getSelect(P3, P0, P4), "select i1 " P3STR ", i32 " P0STR
         ", i32 " P4STR);
   CHECK(ConstantExpr::getICmp(CmpInst::ICMP_EQ, P0, P4), "icmp eq i32 " P0STR
         ", " P4STR);
   CHECK(ConstantExpr::getFCmp(CmpInst::FCMP_ULT, P1, P5), "fcmp ult float "
         P1STR ", " P5STR);