sabuasal (Sameer AbuAsal)
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Oct 18 2016, 6:44 PM (83 w, 3 d)

Recent Activity

Yesterday

sabuasal updated the diff for D45748: [RISCV] Add peepholes for Global Address lowering patterns.
  • Added a test case that shows this patch inability to deal with global address nodes spanning multiple blocks.
Thu, May 24, 2:20 PM
sabuasal added a comment to D45748: [RISCV] Add peepholes for Global Address lowering patterns.
In D45748#1111477, @asb wrote:
In D45748#1110644, @asb wrote:

I'm happy to land this patch as-is. It generates good code in a wide variety of cases (more so than many other backends). But please add the above example to your test file with a note about the missed optimisation opportunity.

The example is actually already added to the test (define dso_local i32 @load_half() nounwind).

Sorry, I was focusing on the diff and had forgotten you already added this in the previous patch. Thanks!

On the other hand, after some chat with @efriedma I am starting to think that this whole thing could be better handled with a machine function Pass that runs after MachineCSE. Your point in your original longer example (and the example I have in the test case called control_flow) shows that we are getting different notes for the lowered global address (just run llc with --stop-before=machine--cse), hasUseOnce always considers the uses within the basic block you are on, not the whole function (which makes sense). The reason these two examples worked (and by worked I mean NOT having the offset merged back into the global address lowering) is because the ADDI generated for the offset was folded into the Load\STore and my peephole found no Tail to kick in. If we add a MachineFunctionPasss we we will have:

I agree with your analysis. It's conceivable you could have an IR pass that tries to improve codegen, but it would have to operate based on assumption about how global lowering would work. I think as you suggest, a machine function pass is promising.

So would the plan be to always generate offset separate from the global (as is current upstream behaviour after your recent patch), and to opportunistically merge the offset in the case the the global base only has a single reference, or (optionally, probably less common) every reference using that base has the same offset.

Thu, May 24, 2:02 PM
sabuasal updated subscribers of D45748: [RISCV] Add peepholes for Global Address lowering patterns.
In D45748#1110644, @asb wrote:

The point I was trying to make is that even with these peepholes, there are trivial cases that aren't caught, such as the example I shared:

@foo = global [6 x i16] [i16 1, i16 2, i16 3, i16 4, i16 5, i16 0], align 2                                     
                                                                                                                
define i32 @main() nounwind {                                                                                   
entry:                                                                                                          
  %0 = load i16, i16* getelementptr inbounds ([6 x i16], [6 x i16]* @foo, i32 0, i32 4), align 2                
  %cmp = icmp eq i16 %0, 140                                                                                    
  br i1 %cmp, label %if.end, label %if.then                                                                     
                                                                                                                
if.then:                                                                                                        
  tail call void @abort()                                                                                       
  unreachable                                                                                                   
                                                                                                                
if.end:                                                                                                         
  ret i32 0                                                                                                     
}                                                                                                               
                                                                                                                
declare void @abort()

This generates 3 instructions for the global access when you'd obviously prefer to use two:

lui     a0, %hi(foo)
addi    a0, a0, %lo(foo)
lhu     a0, 8(a0)

I proposed one way of adding a peephole, but don't see a way of differentiating between the case above and more complex cases where the peephole is counter-productive (such as in the longer IR sample I shared). Possible the solution would be to have an IR pass perform common subexpression elimination on the getelementptr calculations - possibly such a pass already exists.

Hi alex,

Thu, May 24, 12:46 AM

Wed, May 23

sabuasal committed rL333132: [RISCV] Set CostPerUse for registers.
[RISCV] Set CostPerUse for registers
Wed, May 23, 2:38 PM
sabuasal closed D47039: [RISCV] Set CostPerUse for registers.
Wed, May 23, 2:38 PM
sabuasal updated the diff for D47039: [RISCV] Set CostPerUse for registers.

Updated the comment.

Wed, May 23, 2:31 PM
sabuasal added a comment to D45748: [RISCV] Add peepholes for Global Address lowering patterns.

Ping?

Wed, May 23, 12:06 PM
sabuasal added a comment to D47039: [RISCV] Set CostPerUse for registers.

Ping?
is this good to merge?

Wed, May 23, 12:03 PM

Fri, May 18

sabuasal added a comment to D46630: [RISCV] Insert NOPs and R_RISCV_ALIGN relocation type for .align directive when linker relaxation enabled.

Hi Shiva,

Fri, May 18, 4:13 PM
sabuasal updated the diff for D47039: [RISCV] Set CostPerUse for registers.
Fri, May 18, 2:29 PM
sabuasal updated the diff for D47039: [RISCV] Set CostPerUse for registers.

Added descriptive comments for rationale behind setting the CostPerUse property.

Fri, May 18, 2:28 PM

Thu, May 17

sabuasal created D47039: [RISCV] Set CostPerUse for registers.
Thu, May 17, 4:40 PM
sabuasal updated the summary of D45748: [RISCV] Add peepholes for Global Address lowering patterns.
Thu, May 17, 12:51 PM
sabuasal updated the summary of D45748: [RISCV] Add peepholes for Global Address lowering patterns.
Thu, May 17, 12:51 PM
sabuasal updated the summary of D45748: [RISCV] Add peepholes for Global Address lowering patterns.
Thu, May 17, 12:51 PM
sabuasal updated the summary of D45748: [RISCV] Add peepholes for Global Address lowering patterns.
Thu, May 17, 12:44 PM
sabuasal updated the summary of D45748: [RISCV] Add peepholes for Global Address lowering patterns.
Thu, May 17, 12:25 PM
sabuasal added a dependent revision for D46989: [RISCV] Separate base from offset in lowerGlobalAddress: D45748: [RISCV] Add peepholes for Global Address lowering patterns.
Thu, May 17, 12:20 PM
sabuasal added a dependency for D45748: [RISCV] Add peepholes for Global Address lowering patterns: D46989: [RISCV] Separate base from offset in lowerGlobalAddress.
Thu, May 17, 12:20 PM
sabuasal updated the diff for D45748: [RISCV] Add peepholes for Global Address lowering patterns.

Updated the patch to only show the peephole optimizations.

Thu, May 17, 12:18 PM
sabuasal committed rL332641: [RISCV] Separate base from offset in lowerGlobalAddress.
[RISCV] Separate base from offset in lowerGlobalAddress
Thu, May 17, 11:18 AM
sabuasal closed D46989: [RISCV] Separate base from offset in lowerGlobalAddress.
Thu, May 17, 11:18 AM
sabuasal updated the diff for D46989: [RISCV] Separate base from offset in lowerGlobalAddress.
Thu, May 17, 11:13 AM

Wed, May 16

sabuasal retitled D46989: [RISCV] Separate base from offset in lowerGlobalAddress from [RISCV] Separate base from offset in lowerGlobalAddress to [RISCV] Separate base from offset in lowerGlobalAddress (no peephole).
Wed, May 16, 5:05 PM
sabuasal added a comment to D45748: [RISCV] Add peepholes for Global Address lowering patterns.
In D45748#1100940, @asb wrote:

I think we've all spent enough time looking at this to see that separating the base from offset in lowerGlobalAddress is a better starting point, even though there are a range of examples where it results in more instructions. I think we'll soon arrive at a solution that fixes the most common of those cases, but it's obviously not quite as straight-forward as originally hoped. If you'd like to land the change to lowerGlobalAddress quickly, I'd happily now review that as a standalone change. If you like, you could create a new review thread that includes that change as well as test cases that demonstrates where it helps, and cases where it's worse marked with TODO.

Wed, May 16, 4:20 PM
sabuasal updated the summary of D46989: [RISCV] Separate base from offset in lowerGlobalAddress.
Wed, May 16, 4:18 PM
sabuasal updated the summary of D46989: [RISCV] Separate base from offset in lowerGlobalAddress.
Wed, May 16, 4:18 PM
sabuasal added reviewers for D46989: [RISCV] Separate base from offset in lowerGlobalAddress: asb, apazos.
Wed, May 16, 4:17 PM
sabuasal created D46989: [RISCV] Separate base from offset in lowerGlobalAddress.
Wed, May 16, 4:16 PM
sabuasal added a comment to D45748: [RISCV] Add peepholes for Global Address lowering patterns.
In D45748#1100874, @asb wrote:

I've started a discussion on GlobalAddress lowering strategy on llvm-dev here: http://lists.llvm.org/pipermail/llvm-dev/2018-May/123359.html

Your peephole code seems well written and really solid, but I'd like to discuss the dagcombiner approach some more. The sort of approach taken in rL330630 seems to catch the cases discussed in this thread and has a simpler implementation.

Wed, May 16, 10:49 AM
sabuasal added a comment to D45748: [RISCV] Add peepholes for Global Address lowering patterns.
In D45748#1100079, @asb wrote:

I looked at this in some more detail. I have a few very rough statistics on the effect of the various peepholes on the GCC torture suite. I don't claim this is representative of real code, but of course global accesses are highly codebase dependent anyway. Stats are just on the total static instruction count, i.e. it doesn't take into account if instructions are moved from hot to cold basic blocks or vice versa.

Improvement of your proposed peephole over your patch with the peephole disabled:

  • 26 files have reduced number of instructions
  • 10 have an increased number of instructions
  • 6 have changed output but the same static instruction count

    If you then add my proposed peephole on top of that, then you see the following changes (baseline = this patch including your peephole)
  • 23 files have reduced number of instructions
  • 11 have increased number of instructions
  • 2 have changed output but the same static instruction count

So you are saying your addition hurts size, right?

If it were doable, the ideal starting point would be the following:

  • If the global base has only a single reference across the whole function, or every reference has the same offset then combine the global with offset
  • If the global base has multiple references with different offsets, then never combine the global with the offset

This is exactly what I am doing in my peephole:

  • Catch a tail node (RISCV::ADD or RISCV::ADD)
  • Look at the operands of the node t detect a global address lowering sequence (LUI %hifollowed by and ADDI %lo)
  • Look at the other operands of the tail node to catch the and reconstruct the offset. (it can be just an operand if the tail is an ADDI, or you might have to reconstruct from an LUI + ADDI pair if the offset is big or just an LUI)
  • Merge the offset back into the GlobalAddress if the global address only had one use. We can trust that at this point because ALL the blocks have RISCV target nodes.

I think the above two rules would be sensible regardless of whether you are linking statically or e.g. dynamic linking with PIC. Unfortunately we don't have access to that information at the point we'd like to make a decision about combining an offset. A particular lui+addi of a global may have only a single use, but that global may be referenced many times in the function. New TargetGlobalAddress nodes are introduced each time rather than reusing them. In these cases, MachineCSE can remove redundant instructions as long as different offsets aren't folded into the global. Unless we can force the reuse of identical TargetGlobalAddress nodes we can't easily write a peephole pass that respects the two rules proposed above. This input shows the problem well:

@a = internal unnamed_addr global [4 x i32] zeroinitializer, align 4

; Function Attrs: noreturn nounwind
define dso_local i32 @main() local_unnamed_addr #0 {
entry:
  %0 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i32 0), align 4
  %cmp = icmp eq i32 %0, 0
  br i1 %cmp, label %if.end, label %if.then

if.then:                                          ; preds = %entry
  tail call void @abort() #3
  unreachable

if.end:                                           ; preds = %entry
  %1 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i32 1), align 4
  %cmp1 = icmp eq i32 %1, 3
  br i1 %cmp1, label %if.end3, label %if.then2

if.then2:                                         ; preds = %if.end
  tail call void @abort() #3
  unreachable

if.end3:                                          ; preds = %if.end
  %2 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i32 2), align 4
  %cmp4 = icmp eq i32 %2, 2
  br i1 %cmp4, label %if.end6, label %if.then5

if.then5:                                         ; preds = %if.end3
  tail call void @abort() #3
  unreachable

if.end6:                                          ; preds = %if.end3
  %3 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @a, i32 0, i32 3), align 4
  %cmp7 = icmp eq i32 %3, 1
  br i1 %cmp7, label %if.end9, label %if.then8

if.then8:                                         ; preds = %if.end6
  tail call void @abort() #3
  unreachable

if.end9:                                          ; preds = %if.end6
  tail call void @exit(i32 0) #3
  unreachable
}

declare void @abort()

declare void @exit(i32)

So, what is the path forwards here? It feels like we should try to do something sensible without adding too much complex logic. Without a whole-function view we're not going to be better in all cases. Having the combines discussed in this thread feels like a reasonable starting point, but it is possible to imaging pathological inputs with uses spread across many basic blocks. Maybe these combines should be enabled only for a static relocation model?

I'd welcome further thoughts.

Wed, May 16, 10:31 AM
sabuasal added a comment to D45748: [RISCV] Add peepholes for Global Address lowering patterns.
In D45748#1099689, @asb wrote:

Thanks for the update Sameer. I've been evaluating this patch today. I was curious about the decision to perform a peephole rather than a DAG combine. You mention that the DAG combiner doesn't work for uses spanning multiple basic blocks, but doesn't the SelectionDAG (and hence RISCVISelDAGToDAG) also work on a per-basic-block granularity?

Yes. Here is the problem with DAG combine:

  • In our optimization we lower the Global address in a target global address and an ISD::ADD (a generic node, not target specific node)
  • We create a DAG combine that does a call back for ISD::ADD.
  • Right after the lowerGlobalAddress is done you hit the DAG combiner function. Now at this point other blocks are yet to be processed and the global address there is still not lowered into a TargetGlobalAddress, in other blocks (as listed in the the IR test I added called "control_flow") so the Target node we created only has one use only. Our combiner check will go back and put the offset back in the target lowering because it simply doesn't know.
Wed, May 16, 10:26 AM

Wed, May 9

sabuasal updated the diff for D45748: [RISCV] Add peepholes for Global Address lowering patterns.
  • Updated tests and formatting.
  • Added peepholes to handle corner cases, handling these cases with dag combiner doesn't work for uses spanning multiple basic blocks (dag combiner works on BB level),
Wed, May 9, 6:51 PM

Apr 22 2018

sabuasal added a reviewer for D45864: [RISCV] Support .option rvc and norvc: sabuasal.
Apr 22 2018, 3:17 PM
sabuasal added inline comments to D45864: [RISCV] Support .option rvc and norvc.
Apr 22 2018, 3:16 PM
sabuasal added inline comments to D45864: [RISCV] Support .option rvc and norvc.
Apr 22 2018, 2:52 PM

Apr 17 2018

sabuasal added a comment to D41949: [RISCV] implement li pseudo instruction.

This patch causes repeated LUI generation for the following test case :

Apr 17 2018, 6:20 PM
sabuasal created D45748: [RISCV] Add peepholes for Global Address lowering patterns.
Apr 17 2018, 4:13 PM

Apr 16 2018

sabuasal added a comment to D44887: [RISCV] Add shouldForceRelocationWithApplyFixup MC AsmBackend Target Hook.

Hi Alex ,

In D44887#1068861, @asb wrote:

Could you please expand rv32-relaxation.s and rv64-relaxation.s so the test includes the behaviour for branches to an unresolved symbol?

Apr 16 2018, 11:00 AM

Apr 15 2018

sabuasal added inline comments to D44887: [RISCV] Add shouldForceRelocationWithApplyFixup MC AsmBackend Target Hook.
Apr 15 2018, 9:52 PM
sabuasal added inline comments to D44971: [RISCV] Override fixupNeedsRelaxationAdvanced to avoid MC relaxation always promote to 32-bit form when -mrelax enabled.
Apr 15 2018, 9:51 PM

Apr 13 2018

sabuasal added inline comments to D41949: [RISCV] implement li pseudo instruction.
Apr 13 2018, 6:58 PM
sabuasal added inline comments to D41949: [RISCV] implement li pseudo instruction.
Apr 13 2018, 6:52 PM
sabuasal added inline comments to D44971: [RISCV] Override fixupNeedsRelaxationAdvanced to avoid MC relaxation always promote to 32-bit form when -mrelax enabled.
Apr 13 2018, 10:13 AM
sabuasal added inline comments to D44971: [RISCV] Override fixupNeedsRelaxationAdvanced to avoid MC relaxation always promote to 32-bit form when -mrelax enabled.
Apr 13 2018, 9:32 AM

Apr 12 2018

sabuasal committed rL329939: [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0.
[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0
Apr 12 2018, 12:27 PM
sabuasal closed D45583: [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0.
Apr 12 2018, 12:27 PM
sabuasal updated the summary of D45583: [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0.
Apr 12 2018, 11:36 AM
sabuasal created D45583: [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0.
Apr 12 2018, 11:28 AM
sabuasal added inline comments to D44971: [RISCV] Override fixupNeedsRelaxationAdvanced to avoid MC relaxation always promote to 32-bit form when -mrelax enabled.
Apr 12 2018, 9:17 AM
sabuasal added inline comments to D44971: [RISCV] Override fixupNeedsRelaxationAdvanced to avoid MC relaxation always promote to 32-bit form when -mrelax enabled.
Apr 12 2018, 9:17 AM

Apr 6 2018

sabuasal closed D41932: [RISCV] Hooks for enabling instruction compression.

Committed with: https://reviews.llvm.org/D45385

Apr 6 2018, 2:20 PM
sabuasal closed D42780: [RISCV] CompressPat Tablegen-driven Instruction Compression.

Committed with: https://reviews.llvm.org/D45385

Apr 6 2018, 2:18 PM
sabuasal closed D45119: [RISCV] Override EmitToStreamer in RISCVAsmPrinter to handle missed compression opportunities.

Committed with: https://reviews.llvm.org/D45385

Apr 6 2018, 2:17 PM
sabuasal committed rL329455: [RISCV] Tablegen-driven Instruction Compression..
[RISCV] Tablegen-driven Instruction Compression.
Apr 6 2018, 2:11 PM
sabuasal closed D45385: [RISCV] Tablegen-driven Instruction Compression..
Apr 6 2018, 2:11 PM
sabuasal updated the diff for D45385: [RISCV] Tablegen-driven Instruction Compression..
Apr 6 2018, 12:16 PM
sabuasal added reviewers for D45385: [RISCV] Tablegen-driven Instruction Compression.: asb, efriedma, apazos, llvm-commits.
Apr 6 2018, 12:13 PM
sabuasal accepted D45385: [RISCV] Tablegen-driven Instruction Compression..

Patch was reviewed in D45119 , D42780 and D41932.

Apr 6 2018, 12:13 PM
sabuasal created D45385: [RISCV] Tablegen-driven Instruction Compression..
Apr 6 2018, 12:11 PM
sabuasal committed rL329441: [RISCV] Update MC compression tests.
[RISCV] Update MC compression tests
Apr 6 2018, 11:30 AM
sabuasal closed D43328: [RISCV] Update MC compression tests.
Apr 6 2018, 11:30 AM

Apr 5 2018

sabuasal updated the diff for D42780: [RISCV] CompressPat Tablegen-driven Instruction Compression.
  • Renamed evaluateSymbolRef to isBaresymbolRef
  • Updated compress-inline test case.
  • Looked over the assert and unreachable statements and converted needed to PrintFatalError.
Apr 5 2018, 5:27 PM
sabuasal updated the summary of D45119: [RISCV] Override EmitToStreamer in RISCVAsmPrinter to handle missed compression opportunities.
Apr 5 2018, 5:24 PM
sabuasal updated the diff for D45119: [RISCV] Override EmitToStreamer in RISCVAsmPrinter to handle missed compression opportunities.

Shadow instead of override.

Apr 5 2018, 5:23 PM

Apr 4 2018

sabuasal updated the diff for D42780: [RISCV] CompressPat Tablegen-driven Instruction Compression.
  • Removed the function "AreEqualOpernds"
  • ----added sanity test cases--- compression run lines to tests:
Apr 4 2018, 8:40 PM

Apr 3 2018

sabuasal added a reviewer for D45119: [RISCV] Override EmitToStreamer in RISCVAsmPrinter to handle missed compression opportunities: efriedma.
Apr 3 2018, 4:44 PM

Mar 30 2018

sabuasal added a dependency for D45119: [RISCV] Override EmitToStreamer in RISCVAsmPrinter to handle missed compression opportunities: D41932: [RISCV] Hooks for enabling instruction compression.
Mar 30 2018, 7:36 PM
sabuasal created D45119: [RISCV] Override EmitToStreamer in RISCVAsmPrinter to handle missed compression opportunities.
Mar 30 2018, 7:36 PM
sabuasal added a dependent revision for D41932: [RISCV] Hooks for enabling instruction compression: D45119: [RISCV] Override EmitToStreamer in RISCVAsmPrinter to handle missed compression opportunities.
Mar 30 2018, 7:36 PM

Mar 29 2018

sabuasal added a comment to D41932: [RISCV] Hooks for enabling instruction compression.

Hi Alex,

Mar 29 2018, 8:36 AM

Mar 28 2018

sabuasal edited reviewers for D44971: [RISCV] Override fixupNeedsRelaxationAdvanced to avoid MC relaxation always promote to 32-bit form when -mrelax enabled, added: sabuasal; removed: sameer.abuasal.
Mar 28 2018, 11:35 AM
sabuasal added inline comments to D44971: [RISCV] Override fixupNeedsRelaxationAdvanced to avoid MC relaxation always promote to 32-bit form when -mrelax enabled.
Mar 28 2018, 11:34 AM
sabuasal added a reviewer for D43328: [RISCV] Update MC compression tests: apazos.
Mar 28 2018, 11:03 AM
sabuasal added a reviewer for D42780: [RISCV] CompressPat Tablegen-driven Instruction Compression: apazos.
Mar 28 2018, 11:02 AM

Mar 27 2018

sabuasal updated the diff for D42780: [RISCV] CompressPat Tablegen-driven Instruction Compression.
  • addressed comments by @asb
Mar 27 2018, 8:27 PM
sabuasal added a comment to D42780: [RISCV] CompressPat Tablegen-driven Instruction Compression.
In D42780#1039073, @asb wrote:
In D42780#1038674, @asb wrote:

By the way, I'm getting the following error while trying to build this:

CMake Error: The inter-target dependency graph contains the following strongly connected component (cycle):
  "LLVMRISCVAsmPrinter" of type SHARED_LIBRARY
    depends on "LLVMRISCVDesc" (weak)
  "LLVMRISCVDesc" of type SHARED_LIBRARY
    depends on "LLVMRISCVAsmPrinter" (weak)
At least one of these targets is not a STATIC_LIBRARY.  Cyclic dependencies are allowed only among static libraries.

If you're not seeing this, it may be because I build with -DBUILD_SHARED_LIBS=true during development.

I think the best solution is to avoid the layering issue altogether and move evaluateMCOpAsConstantImm and evaluateMCOpAsSymbolRef to MCInst.cpp as methods of MCOperand. I got this compiling after making that adjustment, renaming to evaluateAsConstantImm and evaluateAsSymbolRef. However I note that evaluateAsSymbolRef isn't really an accurate name, is this seems to be a simple predicate that doesn't return any data.

fixed.

Mar 27 2018, 8:18 PM

Mar 26 2018

sabuasal added a comment to D42780: [RISCV] CompressPat Tablegen-driven Instruction Compression.
In D42780#1023507, @asb wrote:

Hi Sameer. Some notes primarily from reviewing the patterns and testing so far:

  • In the RISCV backend we order tablegen instruction definitions to match the ordering in the instruction set manual (which allows easy cross-reference, makes it harder to miss one) and typically order codegen patterns grouped by function. For the case of the CompressPat, I'd probably keep them ordered by the instruction set manual (page 82 in the spec, like the instruction definitions) as each pattern is so mechanical. This makes it easier at a glance to see that every compressed instruction has a matching transformation. The basic MC tests should be ordered to reflect this too. I know this is probably a tedious change to make, but I do think a little effort in the formatting here has an impact on maintainability.

Thank you for the comment, Alex.

Mar 26 2018, 3:15 PM
sabuasal added a comment to D44887: [RISCV] Add shouldForceRelocationWithApplyFixup MC AsmBackend Target Hook.

Hi Shiva,

Mar 26 2018, 1:33 PM

Mar 23 2018

sabuasal added a comment to D41932: [RISCV] Hooks for enabling instruction compression.

Removed the call to EmitInstr in ELFStream.
Updated test cases.

Mar 23 2018, 5:49 PM
sabuasal updated the diff for D41932: [RISCV] Hooks for enabling instruction compression.
Mar 23 2018, 5:48 PM

Mar 21 2018

sabuasal added inline comments to D41932: [RISCV] Hooks for enabling instruction compression.
Mar 21 2018, 1:24 PM
sabuasal commandeered D41932: [RISCV] Hooks for enabling instruction compression.
Mar 21 2018, 12:02 PM

Mar 19 2018

sabuasal updated the summary of D41932: [RISCV] Hooks for enabling instruction compression.
Mar 19 2018, 5:59 PM
sabuasal updated the summary of D41932: [RISCV] Hooks for enabling instruction compression.
Mar 19 2018, 5:58 PM

Mar 9 2018

sabuasal added a comment to rL327079: Propagate flags to SDValue in SplitVecOp_VECREDUCE.

Thank you for the note and apologies for the trouble. I actually had the patch reviewed here (https://reviews.llvm.org/D44245) before I submitted, I guess we all missed it.

Mar 9 2018, 10:35 AM

Mar 8 2018

sabuasal closed D44245: Propagate flags to SDValue in SplitVecOp_VECREDUCE.

committed in @327079

Mar 8 2018, 3:47 PM
sabuasal committed rL327079: Propagate flags to SDValue in SplitVecOp_VECREDUCE.
Propagate flags to SDValue in SplitVecOp_VECREDUCE
Mar 8 2018, 3:45 PM
sabuasal updated the diff for D44245: Propagate flags to SDValue in SplitVecOp_VECREDUCE.

updated test name.

Mar 8 2018, 1:02 PM
sabuasal updated the diff for D44245: Propagate flags to SDValue in SplitVecOp_VECREDUCE.

Test case added.

Mar 8 2018, 12:33 PM
sabuasal added a comment to D44245: Propagate flags to SDValue in SplitVecOp_VECREDUCE.

Thanks for the review. I tried to apply the patch on tip, it applies cleanly but it doesn't compile, I think it is out of date.

Mar 8 2018, 12:32 PM

Mar 7 2018

sabuasal created D44245: Propagate flags to SDValue in SplitVecOp_VECREDUCE.
Mar 7 2018, 7:57 PM

Mar 6 2018

sabuasal added inline comments to D27846: [SLP] Support for horizontal min/max reduction.
Mar 6 2018, 6:47 PM

Mar 2 2018

sabuasal added a comment to D43055: [RISCV] Implement MC relaxations for compressed instructions..

Thanks for the timely review, Alex!

Mar 2 2018, 2:14 PM
sabuasal committed rL326626: [RISCV] Implement MC relaxations for compressed instructions..
[RISCV] Implement MC relaxations for compressed instructions.
Mar 2 2018, 2:07 PM
sabuasal closed D43055: [RISCV] Implement MC relaxations for compressed instructions..
Mar 2 2018, 2:07 PM

Mar 1 2018

sabuasal removed a dependent revision for D43328: [RISCV] Update MC compression tests: D43055: [RISCV] Implement MC relaxations for compressed instructions..
Mar 1 2018, 7:55 PM
sabuasal removed a dependency for D43055: [RISCV] Implement MC relaxations for compressed instructions.: D43328: [RISCV] Update MC compression tests.
Mar 1 2018, 7:55 PM
sabuasal updated the diff for D43328: [RISCV] Update MC compression tests.

address comments from @asb

Mar 1 2018, 7:53 PM
sabuasal added inline comments to D43328: [RISCV] Update MC compression tests.
Mar 1 2018, 7:37 PM