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niosHD (Mario Werner)
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User Since
Sep 9 2016, 12:55 AM (157 w, 5 d)

Recent Activity

Oct 11 2018

niosHD added a comment to D52961: [RISCV] Introduce the RISCVMatInt::generateInstSeq helper.

For me the patch looks good, thank you for working on it Alex!

Oct 11 2018, 7:43 AM

Jun 7 2018

niosHD added a comment to D46118: [RISCV] AsmParser support for the li pseudo instruction.

@asb I just missed my opportunity in the call to ping you regarding this patch. ;) Are there any remaining issues with it that I missed?

Jun 7 2018, 8:24 AM

May 30 2018

niosHD updated the diff for D46118: [RISCV] AsmParser support for the li pseudo instruction.

Updated the patch to emit ADDIW again and rebased it.

May 30 2018, 5:01 AM
niosHD added inline comments to D46118: [RISCV] AsmParser support for the li pseudo instruction.
May 30 2018, 12:23 AM

May 29 2018

niosHD added a comment to D46118: [RISCV] AsmParser support for the li pseudo instruction.

Thank you for finding the flaw in my thinking. I obviously missed that everything falls apart due to the sign extension of the LUI instruction...

May 29 2018, 9:38 AM

May 24 2018

niosHD added a comment to D46118: [RISCV] AsmParser support for the li pseudo instruction.

In case it helps, my reasoning is as follows. There are basically two situations which can occur:

May 24 2018, 6:02 AM

May 23 2018

niosHD updated the diff for D46118: [RISCV] AsmParser support for the li pseudo instruction.

Rebased the patch. Luckily, it was not as bad as I anticipated. :)

May 23 2018, 2:30 AM

May 22 2018

niosHD added a comment to D46118: [RISCV] AsmParser support for the li pseudo instruction.

Ping! Some feedback would be nice before I rebase this patch (which is less fun as it should be due to the recent improvements on the ASM parser)...

May 22 2018, 2:42 AM

May 11 2018

niosHD updated the diff for D46118: [RISCV] AsmParser support for the li pseudo instruction.

I finally found the time to work on this patch, sorry for the delay.

May 11 2018, 8:44 AM

Apr 26 2018

niosHD created D46118: [RISCV] AsmParser support for the li pseudo instruction.
Apr 26 2018, 6:20 AM

Apr 18 2018

niosHD added a comment to D41949: [RISCV] implement li pseudo instruction.

Hi Sameer,

Apr 18 2018, 2:17 AM

Apr 17 2018

niosHD added a comment to D41949: [RISCV] implement li pseudo instruction.
In D41949#1069751, @asb wrote:

I'll think more about compression handling. If you already have something that works, it might be worth just posting that so we have something concrete to discuss.

Apr 17 2018, 7:33 AM
niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

Updated patch to fix variable names.

Apr 17 2018, 7:30 AM
niosHD added a comment to D41949: [RISCV] implement li pseudo instruction.
In D41949#1067297, @asb wrote:

I'd do the compressed changes in a different patch. Thanks for updating the peephole RISCVISelDAGToDAG, I'll review that bit ASAP and then commit. At a first look, it seems to handle this exactly as I would expect.

Apr 17 2018, 12:45 AM

Apr 13 2018

niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

Extended peephole optimisation to fix introduced codegen regression.

Apr 13 2018, 9:15 AM
niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

Rebased on master as Mandeep requested via email .

Apr 13 2018, 6:03 AM

Mar 23 2018

niosHD added a comment to D41949: [RISCV] implement li pseudo instruction.
In D41949#1045516, @asb wrote:

Thanks Mario. I think this is looking good to land now.

Mar 23 2018, 7:24 AM

Mar 15 2018

niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

I rebased the patch and addressed all comments. Thank you again for the feedback.

Mar 15 2018, 5:27 AM

Mar 7 2018

niosHD added a comment to D41949: [RISCV] implement li pseudo instruction.

Hi Alex, thank you very much for your comments!

Mar 7 2018, 8:27 AM

Feb 26 2018

niosHD added inline comments to D41949: [RISCV] implement li pseudo instruction.
Feb 26 2018, 2:32 AM
niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

Thank you for your comments Eli!

Feb 26 2018, 2:31 AM

Feb 23 2018

niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

Addressed the discovered defect regarding the immediate of the li instruction. In RV32 mode we now accept either a signed or an unsigned 32-bit value. In RV64 mode we accept basically everything that fits into 64-bit.

Feb 23 2018, 9:33 AM

Feb 16 2018

niosHD added a comment to D41949: [RISCV] implement li pseudo instruction.

I just stumbled across a difference between the binutils assembler and my current li implementation regarding accepted immediate values.

Feb 16 2018, 2:35 AM

Feb 6 2018

niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

Fixed some typos in the comments.

Feb 6 2018, 9:15 AM
niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

Added support for handling 64-bit immediate values.

Feb 6 2018, 9:09 AM

Feb 2 2018

niosHD added a comment to D41949: [RISCV] implement li pseudo instruction.

Thank you Ana for your comments!

Feb 2 2018, 7:33 AM

Jan 31 2018

niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

Moved the shared emitLoadImm methods to a free function into the RISCVDesc library. Additionally, the Size of the pseudo instruction has been set to 8 (worst case for RV32) to ensure proper branch relaxation. Finally, the pattern for 32-bit immediate integers has been updated to generate PseudoLI and the tests have been updated accordingly.

Jan 31 2018, 4:39 AM

Jan 18 2018

niosHD updated the diff for D41949: [RISCV] implement li pseudo instruction.

Addresses all of Alex's comments (thank you) and integrates PseudoLI emission into CodeGen.

Jan 18 2018, 10:11 AM

Jan 12 2018

niosHD added a comment to D41949: [RISCV] implement li pseudo instruction.

Hi Alex, thank you for your comments!

Jan 12 2018, 4:46 AM

Jan 11 2018

niosHD accepted D41503: [RISCV] Pass MCSubtargetInfo to print methods..

Great, thank you Ana for confirming that this patch fixes the problem.

Jan 11 2018, 8:30 AM
niosHD created D41949: [RISCV] implement li pseudo instruction.
Jan 11 2018, 6:52 AM

Jan 4 2018

niosHD added a comment to D41503: [RISCV] Pass MCSubtargetInfo to print methods..

Ignoring the predicates currently leads to the problem that aliases get printed although the corresponding extension is not enabled.

Jan 4 2018, 9:59 AM

Dec 14 2017

niosHD created D41225: [RISCV] enable emission of alias instructions by default.
Dec 14 2017, 12:40 AM

Dec 13 2017

niosHD added a comment to D41071: [RISCV] implemented assembler pseudo floating point instructions.

Great. I am going to work on the patch which enables aliases by default and updates the tests next. Is it preferred that only the RUN lines are updated to disable aliases in the already existing tests or should the actual content of the tests be updated with aliases?

Dec 13 2017, 4:31 AM

Dec 11 2017

niosHD created D41071: [RISCV] implemented assembler pseudo floating point instructions.
Dec 11 2017, 8:24 AM
niosHD updated the diff for D40902: [RISCV] implemented assembler pseudo instructions for RV32I and RV64I.

Addressed all comments for this patch. I already used riscv-no-aliases as command line flag but defaulted it to true instead of adding riscv-aliases which would be removed soon anyway.

Dec 11 2017, 8:15 AM
niosHD added a comment to D40902: [RISCV] implemented assembler pseudo instructions for RV32I and RV64I.

Thank you for the review Alex. I will incorporate your comments in an updated patch today.

Dec 11 2017, 12:46 AM

Dec 7 2017

niosHD updated the diff for D40902: [RISCV] implemented assembler pseudo instructions for RV32I and RV64I.

Rebased as requested.

Dec 7 2017, 7:16 AM

Dec 6 2017

niosHD created D40902: [RISCV] implemented assembler pseudo instructions for RV32I and RV64I.
Dec 6 2017, 8:19 AM