[Codegen] support of 'nof' flag lowering on X86 target

[magabari]

Summary

This patch contains a support of lowering 'nof' flag in https://reviews.llvm.org/D41944
Currently this support is for X86 target and other target may provide their own implementation.

[craig.topper]

CodeGen/SelectionDAG/LegalizeVectorOps.cpp

755

What guarantees HalfVT is a legal type for the target?

CodeGen/X86/combine-sdiv.ll

265

FIXME and TODO are the common prefixes for comments like this. No one is ever going to look for "FIX IT"

Target/X86/X86ISelLowering.cpp

38113

hasAVX2 implies hasAVX512. But what's special about AVX2 here?

[magabari]

fixed craig notes

CodeGen/SelectionDAG/LegalizeVectorOps.cpp

755

In fact I did this only because as you may notice that i use wider FP types (i32 goes to f64), I assume that when we get to this function the original integer vector type is legal, so if I enlarge the FP type it may be not legal anymore. because of that i did the split.
but in any case i think that Type legalizer should take care of that if HalfVT still not legal.

Target/X86/X86ISelLowering.cpp

38113

fixed.
We have measured this optimization in AVX2 and AVX512 and it gives good speedups but in SSE that may not be the optimized way to do that so we return false.

[craig.topper]

CodeGen/SelectionDAG/LegalizeVectorOps.cpp

755

There is another type legalizer run after vector ops legalization, but it shouldn't be legalizing vector types. It's intended to legalize scalar types created by unrolling.

CodeGen/SelectionDAG/LegalizeVectorOps.cpp

class VectorLegalizer {
   SDValue ExpandSELECT(SDValue Op);
   SDValue ExpandLoad(SDValue Op);
   SDValue ExpandStore(SDValue Op);
   SDValue ExpandFNEG(SDValue Op);
   SDValue ExpandFSUB(SDValue Op);
   SDValue ExpandBITREVERSE(SDValue Op);
   SDValue ExpandCTLZ(SDValue Op);
   SDValue ExpandCTTZ_ZERO_UNDEF(SDValue Op);
+  SDValue ExpandIDIV(SDValue Op);
+
+  /// Helper Function for expanding idiv using fp div
+  SDValue ExpandIDivUsingFPDiv(bool isSigned, SDLoc dl,
+            EVT FPVT, EVT IVT, SDValue A, SDValue B);
 
   /// \brief Implements vector promotion.
   ///
   /// This is essentially just bitcasting the operands to a different type and
   /// bitcasting the result back to the original type.
   SDValue Promote(SDValue Op);
 
   /// \brief Implements [SU]INT_TO_FP vector promotion.
case ISD::SETCC:
     return UnrollVSETCC(Op);
   case ISD::BITREVERSE:
     return ExpandBITREVERSE(Op);
   case ISD::CTLZ:
   case ISD::CTLZ_ZERO_UNDEF:
     return ExpandCTLZ(Op);
   case ISD::CTTZ_ZERO_UNDEF:
     return ExpandCTTZ_ZERO_UNDEF(Op);
+  case ISD::SDIV:
+  case ISD::UDIV:
+    return ExpandIDIV(Op);
   default:
     return DAG.UnrollVectorOp(Op.getNode());
   }
 }
 
+SDValue VectorLegalizer::ExpandIDivUsingFPDiv(bool isSigned, SDLoc dl, 
+          EVT FPVT, EVT IVT, SDValue A, SDValue B) {
+  unsigned Opcode = isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;   
+  SDValue LHS = DAG.getNode(Opcode, dl, FPVT, A);
+  SDValue RHS = DAG.getNode(Opcode, dl, FPVT, B);
+
+  SDValue Res = DAG.getNode(ISD::FDIV, dl, FPVT, LHS, RHS);
+  Opcode = isSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
+  return DAG.getNode(Opcode, dl, IVT, Res);
+}
+
+SDValue VectorLegalizer::ExpandIDIV(SDValue Op) {
+  SDLoc dl(Op);
+  EVT VT = Op.getValueType();
+
+  assert(VT.isVector() && "unexpected type");
+  unsigned int NumElts = VT.getVectorNumElements();
+  EVT EltVT = VT.getVectorElementType();
+
+  if (NumElts == 1)
+    return DAG.UnrollVectorOp(Op.getNode());
+
+  if (!TLI.isDesirableToExpandIDivWithFPDiv(VT))
+    return DAG.UnrollVectorOp(Op.getNode());
+
+  EVT FloatVT;
+  if (EltVT == MVT::i32)
+    FloatVT = MVT::f64;
+  else if (EltVT == MVT::i16)
+    FloatVT = MVT::f32;
+  else  
+    // in any other case go ahead and unroll
+    return DAG.UnrollVectorOp(Op.getNode());
+
+  SDValue LHS = Op.getOperand(0);
+  SDValue RHS = Op.getOperand(1);
+  EVT DstVT = EVT::getVectorVT(*DAG.getContext(), FloatVT, NumElts);
+
+  bool isSigned = (Op.getOpcode() == ISD::SDIV);
+
+  if (!TLI.isOperationLegalOrCustom(ISD::FDIV, DstVT)) {
+    EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts / 2);
+    DstVT = EVT::getVectorVT(*DAG.getContext(), FloatVT, NumElts);
+
+    SDValue Lo = DAG.getIntPtrConstant(0, dl);
+    SDValue Hi = DAG.getIntPtrConstant(NumElts / 2, dl);
+    SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, LHS, Lo);
+    SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, RHS, Lo);
+    SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, LHS, Hi);
+    SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, RHS, Hi);
+
+    SDValue ResLo = ExpandIDivUsingFPDiv(isSigned, dl, DstVT, HalfVT, ALo, BLo); 
+    SDValue ResHi = ExpandIDivUsingFPDiv(isSigned, dl, DstVT, HalfVT, AHi, BHi);
+
+    return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, ResLo, ResHi);
+  }
+  return ExpandIDivUsingFPDiv(isSigned, dl, DstVT, VT, LHS, RHS); 
+}
+
 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
   // Lower a select instruction where the condition is a scalar and the
   // operands are vectors. Lower this select to VSELECT and implement it
   // using XOR AND OR. The selector bit is broadcasted.
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
 
   SDValue Mask = Op.getOperand(0);

CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 
 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
   SDValue Op1 = getValue(I.getOperand(0));
   SDValue Op2 = getValue(I.getOperand(1));
 
   bool nuw = false;
   bool nsw = false;
   bool exact = false;
+  bool nof = false;
   bool vec_redux = false;
   FastMathFlags FMF;
 
   if (const OverflowingBinaryOperator *OFBinOp =
           dyn_cast<const OverflowingBinaryOperator>(&I)) {
     nuw = OFBinOp->hasNoUnsignedWrap();
     nsw = OFBinOp->hasNoSignedWrap();
   }
   if (const PossiblyExactOperator *ExactOp =
           dyn_cast<const PossiblyExactOperator>(&I))
     exact = ExactOp->isExact();
+  if (const PossiblyOverflowOperator *OverflowOp = 
+          dyn_cast<const PossiblyOverflowOperator>(&I))
+    nof = OverflowOp->isNoOverflow();
   if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
     FMF = FPOp->getFastMathFlags();
 
   if (isVectorReductionOp(&I)) {
     vec_redux = true;
     DEBUG(dbgs() << "Detected a reduction operation:" << I << "\n");
   }
 
   SDNodeFlags Flags;
   Flags.setExact(exact);
+  Flags.setNOF(nof);
   Flags.setNoSignedWrap(nsw);
   Flags.setNoUnsignedWrap(nuw);
   Flags.setVectorReduction(vec_redux);
   Flags.setAllowReciprocal(FMF.allowReciprocal());
   Flags.setAllowContract(FMF.allowContract());
   Flags.setNoInfs(FMF.noInfs());
   Flags.setNoNaNs(FMF.noNaNs());
   Flags.setNoSignedZeros(FMF.noSignedZeros());

 
 void SelectionDAGBuilder::visitSDiv(const User &I) {
   SDValue Op1 = getValue(I.getOperand(0));
   SDValue Op2 = getValue(I.getOperand(1));
 
   SDNodeFlags Flags;
   Flags.setExact(isa<PossiblyExactOperator>(&I) &&
                  cast<PossiblyExactOperator>(&I)->isExact());
+  Flags.setNOF(isa<PossiblyOverflowOperator>(&I) &&
+               cast<PossiblyOverflowOperator>(&I)->isNoOverflow()); 
   setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
                            Op2, Flags));
 }
 
 void SelectionDAGBuilder::visitICmp(const User &I) {
   ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
   if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
     predicate = IC->getPredicate();

CodeGen/X86/combine-sdiv.ll

 ; SSE-NEXT:    pextrd $3, %xmm0, %ecx
 ; SSE-NEXT:    movl %ecx, %eax
 ; SSE-NEXT:    cltd
 ; SSE-NEXT:    idivl %ecx
 ; SSE-NEXT:    pinsrd $3, %eax, %xmm1
 ; SSE-NEXT:    movdqa %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX-LABEL: combine_vec_sdiv_dupe:
-; AVX:       # %bb.0:
-; AVX-NEXT:    vpextrd $1, %xmm0, %ecx
-; AVX-NEXT:    movl %ecx, %eax
-; AVX-NEXT:    cltd
-; AVX-NEXT:    idivl %ecx
-; AVX-NEXT:    movl %eax, %ecx
-; AVX-NEXT:    vmovd %xmm0, %esi
-; AVX-NEXT:    movl %esi, %eax
-; AVX-NEXT:    cltd
-; AVX-NEXT:    idivl %esi
-; AVX-NEXT:    vmovd %eax, %xmm1
-; AVX-NEXT:    vpinsrd $1, %ecx, %xmm1, %xmm1
-; AVX-NEXT:    vpextrd $2, %xmm0, %ecx
-; AVX-NEXT:    movl %ecx, %eax
-; AVX-NEXT:    cltd
-; AVX-NEXT:    idivl %ecx
-; AVX-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
-; AVX-NEXT:    vpextrd $3, %xmm0, %ecx
-; AVX-NEXT:    movl %ecx, %eax
-; AVX-NEXT:    cltd
-; AVX-NEXT:    idivl %ecx
-; AVX-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
-; AVX-NEXT:    retq
+; AVX1-LABEL: combine_vec_sdiv_dupe:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpextrd $1, %xmm0, %ecx
+; AVX1-NEXT:    movl %ecx, %eax
+; AVX1-NEXT:    cltd
+; AVX1-NEXT:    idivl %ecx
+; AVX1-NEXT:    movl %eax, %ecx
+; AVX1-NEXT:    vmovd %xmm0, %esi
+; AVX1-NEXT:    movl %esi, %eax
+; AVX1-NEXT:    cltd
+; AVX1-NEXT:    idivl %esi
+; AVX1-NEXT:    vmovd %eax, %xmm1
+; AVX1-NEXT:    vpinsrd $1, %ecx, %xmm1, %xmm1
+; AVX1-NEXT:    vpextrd $2, %xmm0, %ecx
+; AVX1-NEXT:    movl %ecx, %eax
+; AVX1-NEXT:    cltd
+; AVX1-NEXT:    idivl %ecx
+; AVX1-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
+; AVX1-NEXT:    vpextrd $3, %xmm0, %ecx
+; AVX1-NEXT:    movl %ecx, %eax
+; AVX1-NEXT:    cltd
+; AVX1-NEXT:    idivl %ecx
+; AVX1-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_vec_sdiv_dupe:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vcvtdq2pd   %xmm0, %ymm0
+; AVX2-NEXT:    vdivpd  %ymm0, %ymm0, %ymm0
+; AVX2-NEXT:    vcvttpd2dq  %ymm0, %xmm0
+; AVX2-NEXT:    vzeroupper
+; AVX2-NEXT:    retq
   %1 = sdiv nof <4 x i32> %x, %x
   ret <4 x i32> %1
 }
 
 ; fold (sdiv nof x, y) -> (udiv nof x, y) iff x and y are positive
 define <4 x i32> @combine_vec_sdiv_by_pos0(<4 x i32> %x) {
 ; SSE-LABEL: combine_vec_sdiv_by_pos0:
 ; SSE:       # %bb.0:

 ; SSE-NEXT:    movl %edx, %eax
 ; SSE-NEXT:    sarl $31, %eax
 ; SSE-NEXT:    shrl $28, %eax
 ; SSE-NEXT:    addl %edx, %eax
 ; SSE-NEXT:    sarl $4, %eax
 ; SSE-NEXT:    pinsrd $3, %eax, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX-LABEL: combine_vec_sdiv_by_pow2b:
-; AVX:       # %bb.0:
-; AVX-NEXT:    vpextrd $1, %xmm0, %eax
-; AVX-NEXT:    movl %eax, %ecx
-; AVX-NEXT:    sarl $31, %ecx
-; AVX-NEXT:    shrl $30, %ecx
-; AVX-NEXT:    addl %eax, %ecx
-; AVX-NEXT:    sarl $2, %ecx
-; AVX-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm1
-; AVX-NEXT:    vpextrd $2, %xmm0, %eax
-; AVX-NEXT:    movl %eax, %ecx
-; AVX-NEXT:    sarl $31, %ecx
-; AVX-NEXT:    shrl $29, %ecx
-; AVX-NEXT:    addl %eax, %ecx
-; AVX-NEXT:    sarl $3, %ecx
-; AVX-NEXT:    vpinsrd $2, %ecx, %xmm1, %xmm1
-; AVX-NEXT:    vpextrd $3, %xmm0, %eax
-; AVX-NEXT:    movl %eax, %ecx
-; AVX-NEXT:    sarl $31, %ecx
-; AVX-NEXT:    shrl $28, %ecx
-; AVX-NEXT:    addl %eax, %ecx
-; AVX-NEXT:    sarl $4, %ecx
-; AVX-NEXT:    vpinsrd $3, %ecx, %xmm1, %xmm0
-; AVX-NEXT:    retq
+; FIX IT: X86 support variable shift of vectors need to catch this
+;   in DAGCombine
+;
+; AVX1-LABEL: combine_vec_sdiv_by_pow2b:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpextrd $1, %xmm0, %eax
+; AVX1-NEXT:    movl %eax, %ecx
+; AVX1-NEXT:    sarl $31, %ecx
+; AVX1-NEXT:    shrl $30, %ecx
+; AVX1-NEXT:    addl %eax, %ecx
+; AVX1-NEXT:    sarl $2, %ecx
+; AVX1-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm1
+; AVX1-NEXT:    vpextrd $2, %xmm0, %eax
+; AVX1-NEXT:    movl %eax, %ecx
+; AVX1-NEXT:    sarl $31, %ecx
+; AVX1-NEXT:    shrl $29, %ecx
+; AVX1-NEXT:    addl %eax, %ecx
+; AVX1-NEXT:    sarl $3, %ecx
+; AVX1-NEXT:    vpinsrd $2, %ecx, %xmm1, %xmm1
+; AVX1-NEXT:    vpextrd $3, %xmm0, %eax
+; AVX1-NEXT:    movl %eax, %ecx
+; AVX1-NEXT:    sarl $31, %ecx
+; AVX1-NEXT:    shrl $28, %ecx
+; AVX1-NEXT:    addl %eax, %ecx
+; AVX1-NEXT:    sarl $4, %ecx
+; AVX1-NEXT:    vpinsrd $3, %ecx, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: combine_vec_sdiv_by_pow2b:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vcvtdq2pd   %xmm0, %ymm0
+; AVX2-NEXT:    vdivpd  .LCPI13_0(%rip), %ymm0, %ymm0
+; AVX2-NEXT:    vcvttpd2dq  %ymm0, %xmm0
+; AVX2-NEXT:    vzeroupper
+; AVX2-NEXT:    retq
   %1 = sdiv nof <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
   ret <4 x i32> %1
 }

CodeGen/X86/combine-udiv.ll

 ; SSE-NEXT:    pinsrd $2, %eax, %xmm1
 ; SSE-NEXT:    pextrd $3, %xmm0, %eax
 ; SSE-NEXT:    xorl %edx, %edx
 ; SSE-NEXT:    divl %eax
 ; SSE-NEXT:    pinsrd $3, %eax, %xmm1
 ; SSE-NEXT:    movdqa %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX-LABEL: combine_vec_udiv_dupe:
-; AVX:       # %bb.0:
-; AVX-NEXT:    vpextrd $1, %xmm0, %eax
-; AVX-NEXT:    xorl %edx, %edx
-; AVX-NEXT:    divl %eax
-; AVX-NEXT:    movl %eax, %ecx
-; AVX-NEXT:    vmovd %xmm0, %eax
-; AVX-NEXT:    xorl %edx, %edx
-; AVX-NEXT:    divl %eax
-; AVX-NEXT:    vmovd %eax, %xmm1
-; AVX-NEXT:    vpinsrd $1, %ecx, %xmm1, %xmm1
-; AVX-NEXT:    vpextrd $2, %xmm0, %eax
-; AVX-NEXT:    xorl %edx, %edx
-; AVX-NEXT:    divl %eax
-; AVX-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
-; AVX-NEXT:    vpextrd $3, %xmm0, %eax
-; AVX-NEXT:    xorl %edx, %edx
-; AVX-NEXT:    divl %eax
-; AVX-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
-; AVX-NEXT:    retq
+; AVX1-LABEL: combine_vec_udiv_dupe:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpextrd $1, %xmm0, %eax
+; AVX1-NEXT:    xorl %edx, %edx
+; AVX1-NEXT:    divl %eax
+; AVX1-NEXT:    movl %eax, %ecx
+; AVX1-NEXT:    vmovd %xmm0, %eax
+; AVX1-NEXT:    xorl %edx, %edx
+; AVX1-NEXT:    divl %eax
+; AVX1-NEXT:    vmovd %eax, %xmm1
+; AVX1-NEXT:    vpinsrd $1, %ecx, %xmm1, %xmm1
+; AVX1-NEXT:    vpextrd $2, %xmm0, %eax
+; AVX1-NEXT:    xorl %edx, %edx
+; AVX1-NEXT:    divl %eax
+; AVX1-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
+; AVX1-NEXT:    vpextrd $3, %xmm0, %eax
+; AVX1-NEXT:    xorl %edx, %edx
+; AVX1-NEXT:    divl %eax
+; AVX1-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
+; AVX1-NEXT:    retq
+;
+; FIXME: uint to double conversion is not effecient GCC has better sequence
+;
+; AVX2-LABEL: combine_vec_udiv_dupe:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vpsrld  $16, %xmm0, %xmm1
+; AVX2-NEXT:    vcvtdq2pd   %xmm1, %ymm1
+; AVX2-NEXT:    vbroadcastsd    .LCPI7_0(%rip), %ymm2 # ymm2 = [65536,65536,65536,65536]
+; AVX2-NEXT:    vmulpd  %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vxorpd  %xmm2, %xmm2, %xmm2
+; AVX2-NEXT:    vpblendw    $170, %xmm2, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
+; AVX2-NEXT:    vcvtdq2pd   %xmm0, %ymm0
+; AVX2-NEXT:    vaddpd  %ymm0, %ymm1, %ymm0
+; AVX2-NEXT:    vdivpd  %ymm0, %ymm0, %ymm0
+; AVX2-NEXT:    vpermilpd   $1, %xmm0, %xmm1 # xmm1 = xmm0[1,0]
+; AVX2-NEXT:    vcvttsd2si  %xmm1, %rax
+; AVX2-NEXT:    vcvttsd2si  %xmm0, %rcx
+; AVX2-NEXT:    vmovd   %ecx, %xmm1
+; AVX2-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
+; AVX2-NEXT:    vextractf128    $1, %ymm0, %xmm0
+; AVX2-NEXT:    vcvttsd2si  %xmm0, %rax
+; AVX2-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
+; AVX2-NEXT:    vpermilpd   $1, %xmm0, %xmm0 # xmm0 = xmm0[1,0]
+; AVX2-NEXT:    vcvttsd2si  %xmm0, %rax
+; AVX2-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
+; AVX2-NEXT:    vzeroupper
+; AVX2-NEXT:    retq
   %1 = udiv nof <4 x i32> %x, %x
   ret <4 x i32> %1
 }
 
 ; fold (udiv nof x, (1 << c)) -> x >>u c
 define <4 x i32> @combine_vec_udiv_by_pow2a(<4 x i32> %x) {
 ; SSE-LABEL: combine_vec_udiv_by_pow2a:
 ; SSE:       # %bb.0:

Target/X86/X86ISelLowering.h

public:
     /// Replace the results of node with an illegal result
     /// type with new values built out of custom code.
     ///
     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
                             SelectionDAG &DAG) const override;
 
     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
+    /// Return true if it is profitable to expand integer division using
+    /// floating point division instruction
+    bool isDesirableToExpandIDivWithFPDiv(EVT VT) const override;
+
     // Return true if it is profitable to combine a BUILD_VECTOR with a
     // stride-pattern to a shuffle and a truncate.
     // Example of such a combine:
     // v4i32 build_vector((extract_elt V, 1),
     //                    (extract_elt V, 3),
     //                    (extract_elt V, 5),
     //                    (extract_elt V, 7))
     //  -->

Target/X86/X86ISelLowering.cpp

if (!Subtarget.useSoftFloat() && Subtarget.hasFp256()) {
     }
 
     for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
                      MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
       setOperationAction(ISD::MLOAD,  VT, Legal);
       setOperationAction(ISD::MSTORE, VT, Legal);
     }
 
+    if (Subtarget.hasAVX2()) {
+      for (auto VT: {MVT::v8i32, MVT::v16i16}) {
+        setOperationAction(ISD::SDIV, VT, Expand);
+        setOperationAction(ISD::UDIV, VT, Expand);
+      }
+      for (auto VT: {MVT::v4i32, MVT::v8i16}) {
+        setOperationAction(ISD::SDIV, VT, Expand);
+        setOperationAction(ISD::UDIV, VT, Expand);
+      }
+    }  
+
     // Extract subvector is special because the value type
     // (result) is 128-bit but the source is 256-bit wide.
     for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
                      MVT::v4f32, MVT::v2f64 }) {
       setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
     }
 
     // Custom lower several nodes for 256-bit types.
if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v8i1,  Custom);
     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v4i1,  Custom);
     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v4i1,  Custom);
     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v8i1,  Custom);
     setOperationAction(ISD::INSERT_SUBVECTOR,   MVT::v16i1, Custom);
     for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
       setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
 
+    if (Subtarget.hasAVX512()) {
+      for (auto VT: {MVT::v8i32, MVT::v16i16}) {
+        setOperationAction(ISD::SDIV, VT, Expand);
+        setOperationAction(ISD::UDIV, VT, Expand);
+      }
+      for (auto VT: {MVT::v16i32, MVT::v32i16}) {
+        setOperationAction(ISD::SDIV, VT, Expand);
+        setOperationAction(ISD::UDIV, VT, Expand);
+      }
+    }  
+
     for (MVT VT : MVT::fp_vector_valuetypes())
       setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
 
     for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
       setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8,  Legal);
       setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal);
       setLoadExtAction(ExtType, MVT::v8i64,  MVT::v8i8,   Legal);
       setLoadExtAction(ExtType, MVT::v8i64,  MVT::v8i16,  Legal);
case ISD::SUB: {
     Promote = true;
   }
   }
 
   PVT = MVT::i32;
   return Promote;
 }
 
+bool X86TargetLowering::isDesirableToExpandIDivWithFPDiv(EVT VT) 
+    const {
+  // not profitable to convert scalar idiv to fpdiv  
+  if (!VT.isVector())
+    return false;
+
+  unsigned NumElements = VT.getVectorNumElements();
+
+  // in case of small vector still not worthy to do that
+  if (NumElements <= 2)
+    return false;
+
+  // we prefer this only in case of AVX2\AVX512 
+  return (Subtarget.hasAVX2() || Subtarget.hasAVX512());
+}    
+
 bool X86TargetLowering::
     isDesirableToCombineBuildVectorToShuffleTruncate(
         ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
 
   assert(SrcVT.getVectorNumElements() == ShuffleMask.size() &&
          "Element count mismatch");
   assert(
       Subtarget.getTargetLowering()->isShuffleMaskLegal(ShuffleMask, SrcVT) &&

Target/X86/X86TargetTransformInfo.cpp

 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) {
   // AVX2 doesn't support scatter
   if (!ST->hasAVX512())
     return false;
   return isLegalMaskedGather(DataType);
 }
 
 bool X86TTIImpl::isLegalMayOverflowUDiv(Type *DataType) {
+  assert(DataType && "datatype is null");
+  if (ST->hasAVX512() || ST->hasAVX2()) {
+    if (DataType->isVectorTy()) {
+      Type *ElmType = DataType->getVectorElementType();
+      unsigned BW   = ElmType->getIntegerBitWidth();
+      return ElmType->isIntegerTy() && (BW == 16 || BW == 32);
+    }
+  }  
   return false;
 }
 
 bool X86TTIImpl::isLegalMayOverflowSDiv(Type *DataType) {
   return isLegalMayOverflowUDiv(DataType);
 }
 
 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {

llvm/CodeGen/SelectionDAGNodes.h

private:
   bool Exact : 1;
   bool UnsafeAlgebra : 1;
   bool NoNaNs : 1;
   bool NoInfs : 1;
   bool NoSignedZeros : 1;
   bool AllowReciprocal : 1;
   bool VectorReduction : 1;
   bool AllowContract : 1;
+  bool IsNOF : 1;
 
 public:
   /// Default constructor turns off all optimization flags.
   SDNodeFlags()
       : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
         Exact(false), UnsafeAlgebra(false), NoNaNs(false), NoInfs(false),
         NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
-        AllowContract(false) {}
+        AllowContract(false), IsNOF(false) {}
 
   /// Sets the state of the flags to the defined state.
   void setDefined() { AnyDefined = true; }
   /// Returns true if the flags are in a defined state.
   bool isDefined() const { return AnyDefined; }
 
   // These are mutators for each flag.
   void setNoUnsignedWrap(bool b) {
public:
   void setVectorReduction(bool b) {
     setDefined();
     VectorReduction = b;
   }
   void setAllowContract(bool b) {
     setDefined();
     AllowContract = b;
   }
+  void setNOF(bool b) {
+    setDefined();
+    IsNOF = b;
+  }  
 
   // These are accessors for each flag.
   bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
   bool hasNoSignedWrap() const { return NoSignedWrap; }
   bool hasExact() const { return Exact; }
   bool hasUnsafeAlgebra() const { return UnsafeAlgebra; }
   bool hasNoNaNs() const { return NoNaNs; }
   bool hasNoInfs() const { return NoInfs; }
   bool hasNoSignedZeros() const { return NoSignedZeros; }
   bool hasAllowReciprocal() const { return AllowReciprocal; }
   bool hasVectorReduction() const { return VectorReduction; }
   bool hasAllowContract() const { return AllowContract; }
+  bool hasNOF() const { return IsNOF; }
 
   /// Clear any flags in this flag set that aren't also set in Flags.
   /// If the given Flags are undefined then don't do anything.
   void intersectWith(const SDNodeFlags Flags) {
     if (!Flags.isDefined())
       return;
     NoUnsignedWrap &= Flags.NoUnsignedWrap;
     NoSignedWrap &= Flags.NoSignedWrap;
     Exact &= Flags.Exact;
     UnsafeAlgebra &= Flags.UnsafeAlgebra;
     NoNaNs &= Flags.NoNaNs;
     NoInfs &= Flags.NoInfs;
     NoSignedZeros &= Flags.NoSignedZeros;
     AllowReciprocal &= Flags.AllowReciprocal;
     VectorReduction &= Flags.VectorReduction;
     AllowContract &= Flags.AllowContract;
+    IsNOF &= Flags.IsNOF;
   }
 };
 
 /// Represents one node in the SelectionDAG.
 ///
 class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
 private:
   /// The operation that this node performs.

llvm/CodeGen/TargetLowering.h

public:
   ///   SDValue.Val == N   - N was replaced, is dead, and is already handled.
   ///   otherwise          - N should be replaced by the returned Operand.
   ///
   /// In addition, methods provided by DAGCombinerInfo may be used to perform
   /// more complex transformations.
   ///
   virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 
+  /// Return true if it is profitable to expand integer division using 
+  /// floating point division instruction
+  virtual bool isDesirableToExpandIDivWithFPDiv(EVT VT) const {
+    return false;
+  }  
+
   /// Return true if it is profitable to move a following shift through this
   //  node, adjusting any immediate operands as necessary to preserve semantics.
   //  This transformation may not be desirable if it disrupts a particularly
   //  auspicious target-specific tree (e.g. bitfield extraction in AArch64).
   //  By default, it returns true.
   virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
     return true;
   }