[lld] Support RISC-V

[PkmX]

Summary

This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications.

The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd.

The patch should be pretty straightforward. Some highlights:

• A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses
• LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump.
• We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld.

[ruiu]

As you said this looks like a pretty straightforward port to RISC-V. Thank you for doing this!

IIRC, last time when we discussed RISC-V support in lld, I had a concern that linker relaxation (moving code inside a section to make it compact) is virtually mandatory to link RISC-V object files. What is the situation of it? If you can link a small static executable with this patch, then it is probably no longer mandatory, but I want to make sure that that's the case.

ELF/Arch/RISCV.cpp

39–40 ↗

(On Diff #120366)

We usually do not enclose an entire cpp file in namespaces. Please take a look at X86.cpp and do the same thing.

45 ↗

(On Diff #120366)

This is redundant, I would remove this line.

46 ↗

(On Diff #120366)

Please use RelType instead of uint32_t if a variable represents a relocation type, even though RelType is just a typedef for uint32_t.

55 ↗

(On Diff #120366)

& 0xFFFF is not needed as it is automatically trimmed.

68 ↗

(On Diff #120366)

We do not indent cases. Maybe you want to just use clang-format-diff.

87 ↗

(On Diff #120366)

I don't like this comment -- could you describe the function?

90 ↗

(On Diff #120366)

I think

return (V >> End) & ((1 << Begin) - 1);

is more straightforward (if I understand this expression correctly.) You can do shift the result to the left after returning from this function.

I'd make the range half-open (e.g. pass (8, 9) instead of (8, 8)) because it feels more C++-ish.

Function names usually should be verb. Something like extract is a better name.

109 ↗

(On Diff #120366)

I don't think you need a cast because you are using the least signifcant 8 bits anyway.

111–116 ↗

(On Diff #120366)

They are obviously not mutated, and in that case, we don't usually add const.

218 ↗

(On Diff #120366)

+=

258–268 ↗

(On Diff #120366)

Move these cases to the end of this switch (just before default), to remove gotos.

293–296 ↗

(On Diff #120366)

Is big-endian RISCV actually a thing? I know it is technically defined, but I wonder if there exists a real user.

ELF/Driver.cpp

118–132 ↗

(On Diff #120366)

Sort

ELF/InputSection.cpp

569–571 ↗

(On Diff #120366)

Move this comment inside the following case

575 ↗

(On Diff #120366)

If Body is an absolute symbol, Section is a nullptr. Are you sure that this shouldn't happen?

(And basically, please remove const from local variables as our functions are usually small and their scopes are pretty small.)

ELF/Symbols.cpp

31–42 ↗

(On Diff #120366)

Sort

ELF/Symbols.h

346–353 ↗

(On Diff #120366)

Sort

353 ↗

(On Diff #120366)

Please add a comment.

[ruiu]

ELF/Target.cpp

76–93 ↗

(On Diff #120366)

Sort

82–89 ↗

(On Diff #120366)

Big-endian RISC-Vs seems unreachable. I'd remove them if it is not needed now.

ELF/Target.h

123–131 ↗

(On Diff #120366)

Sort

(Basically, we want to add new code to the place where it would have been if it had existed from beginning. This makes our code look less patch-y.)

ELF/Writer.cpp

782–783 ↗

(On Diff #120366)

Needs comment.

954–960 ↗

(On Diff #120366)

Format

[PkmX]

In D39322#908393, @ruiu wrote:

As you said this looks like a pretty straightforward port to RISC-V. Thank you for doing this!

IIRC, last time when we discussed RISC-V support in lld, I had a concern that linker relaxation (moving code inside a section to make it compact) is virtually mandatory to link RISC-V object files. What is the situation of it? If you can link a small static executable with this patch, then it is probably no longer mandatory, but I want to make sure that that's the case.

Yes, linker relaxation is no longer mandatory, after these followup discussion here:
https://github.com/riscv/riscv-binutils-gdb/pull/88
https://github.com/riscv/riscv-tools/issues/132

ELF/Arch/RISCV.cpp

90 ↗

(On Diff #120366)

Yes, basically it extracts the bits from [Begin, End] and shifts the result so the LSB is at LShift bit.

Making the range half-open does make it work more like C++ iterators, but it does make cross-referencing with the ISA spec more difficult as ranges are often given in closed forms, e.g. Inst[5:0] means the lowest 6 bits.

I agree we can move the left shift out of the function, and I will also rename the function to extractBits.

293–296 ↗

(On Diff #120366)

I don't think there are any big-endian implementations (and the toolchain/libraries are most likely not intensively tested for BE), so yeah I'm going to remove these.

ELF/Symbols.h

346–353 ↗

(On Diff #120366)

RISCVGlobalPointer should be the last one in alphabetical order, no?

ELF/Target.cpp

76–93 ↗

(On Diff #120366)

It is already in alphabetical order.

[ruiu]

ELF/Arch/RISCV.cpp

90 ↗

(On Diff #120366)

If it is consistent with the specification, I'm fine with open interval.

[ruiu]

ELF/Arch/RISCV.cpp

44 ↗

(On Diff #120541)

This is where you should use RelType too.

86 ↗

(On Diff #120541)

I'd replace static_cast<uint64_t>(1) with 1u, as we assume int is at least 32 bits.

293–296 ↗

(On Diff #120366)

Thanks!

Then maybe it makes more sense if you provide two functions, getRISCV32TargetInfo and getRISCV64TargetInfo, I guess?

[PkmX]

• Renamed uint32_t to RelType.
• Detemplate the RISCV class.

[ruiu]

Generally looking pretty good except lo12 relocations.

ELF/Arch/RISCV.cpp

49–54 ↗

(On Diff #120794)

Please remove this function and directly use write32le (I believe instead of calling write16le twice, you can use write32le.).

56–58 ↗

(On Diff #120794)

Ditto -- please use read32le directly.

84 ↗

(On Diff #120794)

static_cast<uint64_t>(1) -> (uint64_t)1 or 1ULL

as it is obvious that it is a static cast.

ELF/InputSection.cpp

575–582 ↗

(On Diff #120794)

It is O(n^2), isn't it? It doesn't seems good.

Fundamentally I think I don't understand why R_RISCV_PCREL_LO12{I,S} were designed that way. IIUC, they are relocations to load a PC-relative symbol address and used in combination with PC_RISCV_PCREL_HI20. A pair of HI and LO relocations are associated via label locations. That seems unnecessarily tricky to me.

The spec says that they are computed this way:

hi20 = ((symbol_address - hi20_reloc_offset + 0x800) >> 12);
lo12 = symbol_address - hi20_reloc_offset - hi20;

but why can't we define lo12 as a more regular relocation like this:

hi20 = ((symbol_address - hi20_reloc_offset + 0x800) >> 12);
lo12 = symbol_address - lo20_reloc_offset - ((symbol_address - lo20_reloc_offset + 0x800 + Addend) >> 12) + Addend;

and set a relocation addend to a distance between a lo12 relocation and a hi12 relocation? This way, you don't really have to associate two relocation, but you can just compute their values separately. What am I missing?

[PkmX]

• Use {read,write}32le to read/write insturctions.
• Make __global_pointer$ non-absolute.

[asb]

I'm not an LLD expert, but the RISC-V bits seem correct as far as I can see. I've just added a couple of minor comments.

ELF/Arch/RISCV.cpp

71 ↗

(On Diff #120939)

A comment that clarifies the semantics would be useful. Perhaps "Begin and End are inclusive, e.g. extractBits(V, 0, 5) will return the lower 6 bits."

165 ↗

(On Diff #120939)

It would seem consistent with the other cases do define Imm* local variables to help piece together the final instruction. It's slightly more verbose, but enforcing uniformity across the cases might make this slightly easier to read?

[ruiu]

What do you think of lo20 relocations? If there's a better place to ask about the design of the RISC-V ABI, please let me know so that I can start a thread.

[PkmX]

I believe the best place would be either the issue tracker on the psABI doc, or RISC-V's sw-dev mailing list.

ELF/Arch/RISCV.cpp

86 ↗

(On Diff #120541)

On common systems where int is 32-bit (x86_64) and with Begin == 31, 1u << 32 would invoke undefined behavior.

With that said, this will still break if Begin == 63, so I think it is more correct to right-shift from UINT64_MAX.

109 ↗

(On Diff #120366)

The cast is needed: consider uint64_t Val = -1, right-shifting an unsigned integer in C performs zero-extension in the MSB and produces a large positive number if interpreted as signed later.

I've removed redundant casts in other checkInt where no shifting is performed.

293–296 ↗

(On Diff #120366)

I think it should actually be possible to de-template the class and just use Config->Wordsize and Config->Endianness, then we can just provide a single instance.

71 ↗

(On Diff #120939)

Will do.

165 ↗

(On Diff #120939)

That sounds reasonable. The other cases are more complicated as the Imm needs to be split up and shifted into the correct bit position and or'ed together. With auipc (U-Type) and jalr (I-Type), the imm fields in the instruction are already packed in the right order, so we only need a simple mask and shift.

Actually, for R_RISCV_CALL, I think I should just recursively call relocateOne with R_RISCV_PCREL_HI20 at Buf and R_RISCV_PCREL_LO12_I at Buf + 4 to remove redundant code. This should be okay since we aren't doing relaxation for now.

ELF/Driver.cpp

118–132 ↗

(On Diff #120366)

Sorting this alphabetically will put elf32lriscv awkwardly between elf32btsmip and elf32ltsmip, so I think it's better to put it after these two?

.Cases("elf32btsmip", "elf32btsmipn32", {ELF32BEKind, EM_MIPS})                                                                                                                      
.Cases("elf32ltsmip", "elf32ltsmipn32", {ELF32LEKind, EM_MIPS})        
.Case("elf32lriscv", {ELF32LEKind, EM_RISCV})                          
.Case("elf32ppc", {ELF32BEKind, EM_PPC})                               
.Case("elf64btsmip", {ELF64BEKind, EM_MIPS})                           
.Case("elf64ltsmip", {ELF64LEKind, EM_MIPS})                           
.Case("elf64lriscv", {ELF64LEKind, EM_RISCV})

ELF/InputSection.cpp

575 ↗

(On Diff #120366)

I don't think that should ever happen since the symbol should point to an auipc instruction somewhere in a text section.

575–582 ↗

(On Diff #120794)

RISC-V expects linker relaxation so the distance between a pair of HI20 and LO12 relocation isn't static. If some code is removed then you need to update the addend of the LO12 of all HI/LO pairs surrounding that change.

It should be possible to pre-compute a mapping from symbols to relocations to reduce the search time complexity, but I think that could go in another patch?

[ruiu]

ELF/InputSection.cpp

575–582 ↗

(On Diff #120794)

Yeah, I guessed that that might be reason. But, if the linker relaxes and repacks instructions, it naturally knows how many bytes have been removed between any two locations, so it can easily compute how many bytes need to be adjusted for lo20 addends, right? I'd think computing the same value using labels is unnecessarily complicated, and it seems like a residue of when the code shrinking relaxation was mandatory for RISC-V.

[PkmX]

Make R_RISCV_CALL reuse R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I.

[PkmX]

• Rebase onto latest master
• Clean up #includes

[ruiu]

ELF/InputSection.cpp

575–582 ↗

(On Diff #120794)

I still have a concern on HI20 and LO20 relocations. Could you start a thread to discuss whether it can be fixed in the ABI?

[asb]

For what it's worth, this is the thread @PkmX started on the sw-dev mailing list: https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CACSh3m3pwKZrqhfZ_LWwkHOLVUx%3Dadamrf-yiMCH468a5%3DrtGw%40mail.gmail.com

[PkmX]

Oops. It looks like I actually didn't submit some of these draft comments.

ELF/Arch/RISCV.cpp

10–27 ↗

(On Diff #121106)

I think some #includes here are only needed in the subsequent patches and some are simply unnecessary. Noting in case I forget to revise this.

ELF/InputSection.cpp

575–582 ↗

(On Diff #120794)

Yeah, that sounds workable. This does mean that the linker needs scan the whole section for LO12 to update the addend during relaxation, as the HI20/LO12 pair may be far apart (it is also perfectly fine for many PCREL_LO12 relocations to refer to the same PCREL_HI20). I'm not sure how this compares performance-wise with storing a label since you only pay for the penalty when you want the value or to find the linked PCREL_HI20.

With that said, I think it may be too late to change the ABI, especially when it comes to a fundamental change like this.

575–582 ↗

(On Diff #120794)

BTW, those are called LO12, not LO20.

575–582 ↗

(On Diff #120794)

FYI, I've opened a follow-up thread on RISC-V's mailing list:

https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/IqYjXvl4o4Q

575–582 ↗

(On Diff #120794)

FYI, I've opened a follow-up thread on RISC-V's mailing list:

https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/IqYjXvl4o4Q

575–582 ↗

(On Diff #120794)

It's been a while and I don't think they are willing to change the ABI at this point. Do you have further comments and is there still anything that needs to be done with this patch?

[xiangzhai]

Hi Chen,

I believe the best place would be either the issue tracker on the psABI doc, or RISC-V's sw-dev mailing list.

It is a good news that RISCV's ABI document is open! it doesn't like AVR target, I have to borrow code from bintuils because it is difficult to guess ELF Relocation Records Calculation Formula, take AMDGPU for an instance http://llvm.org/docs/AMDGPUUsage.html#relocation-records it is Magic Number to me without ABI document.
I need to learn RISCV ISA and ABI documents, and Chen's great work for LLD and bintuils, because RISCV is more complex than AVR, it needs to implement GOT, PLT, TLS, Trunks, I haven't experienced.

Rui is a nice teacher who reviewed my patch carefully and patiently, it took up his rest time:

朝の8時半から試験っていうのは慌ただしい。昼の会社のソファーでちょっと寝てしまった。やや寝不足。

I experienced a lack of sleep discomfort, it feels really bad! so my sincere thanks will goto LLD leader - Rui ありがとうございました！

Regards,
Leslie Zhai

[PkmX]

Rebase onto latest master.

Rui, is there anything else that is still blocking this patch?

[Razer6]

Is there anything missing to land in upstream?

[PkmX]

Rebase onto master.

Is there still anything that needs to be done before this patch can be accepted?

[Razer6]

ELF/Arch/RISCV.cpp

141 ↗

(On Diff #133979)

This check should be treated as unsigned (checkUInt<32>) since it is an absolute address.

149 ↗

(On Diff #133979)

checkUInt<32> as above

156 ↗

(On Diff #133979)

checkUInt<32> as above

164 ↗

(On Diff #133979)

checkUInt<32> as above

[PkmX]

ELF/Arch/RISCV.cpp

141 ↗

(On Diff #133979)

The range of R_RISCV_CALL is signed 32-bit (± 2GiB), so checkInt<32> is indeed correct here.

149 ↗

(On Diff #133979)

R_RISCV_HI20 can also address the negative 2 GiB (0xffffffff80000000 to 0xffffffffffffffff) in RV64, so the use checkInt<32> is still correct here.

156 ↗

(On Diff #133979)

See above.

164 ↗

(On Diff #133979)

See above.

[PkmX]

Hello,

I've rebased the diff to latest trunk again. Some notable differences from last revision:

• For RISC-V, relocations are sorted by offset target after they have been inserted in scanRelocs, and we use std::equal_range to binary search for R_RISCV_PCREL_HI20. I did some profiling using lld to link RISC-V's Linux kernel and it only spends less than 2% of time in getRISCVPCRelHi20, so it should be fast enough without changing the ABI.

• RISCV::calcEFlags() is now implemented (docs). The RVC flag is set if any of the object has it set, and the float ABI and RVE flags must be the same across all inputs.

• __global_pointer$ is now set to .sdata + 0x800 only if it is not already defined by --defsym or from the linker script.

[emaste]

@ruiu what do you suggest as the next step here?

[ruiu]

Apologies for my belated response. I think this patch is generally looking good. One thing I'd fix before submitting is to rewrite a test using assembly. We do not usually use YAML file for testing. Is there any reason you needed to write them in YAML?

ELF/Relocations.h

132 ↗

(On Diff #158925)

Do you really need this abstraction? I'd write a lambda in-place rather than defining a new struct for three two different types of comparisons.

ELF/Symbols.h

335 ↗

(On Diff #158925)

nit: add a blank line.

[PkmX]

In D39322#1190218, @ruiu wrote:

Apologies for my belated response. I think this patch is generally looking good. One thing I'd fix before submitting is to rewrite a test using assembly. We do not usually use YAML file for testing. Is there any reason you needed to write them in YAML?

These tests were written in ObjectYAML format since LLVM MC support was very incomplete for RISC-V, and the latest llvm-mc from trunk still cannot assemble these tests correctly due to lack of addend handling. I did include the original assembly text in the tests so once the LLVM port is upstreamed we can just swap it to run assembler proper.

ELF/Relocations.h

132 ↗

(On Diff #158925)

You need all these overloads to do heterogeneous comparison in C++ (call std::equal_range on a Relocation vector to find the range equal to an uint64_t offset). You can't use lambdas in-place since they can't be overloaded without some hackery.

ELF/Symbols.h

335 ↗

(On Diff #158925)

Will do.

[ruiu]

LGTM

These tests were written in ObjectYAML format since LLVM MC support was very incomplete for RISC-V, and the latest llvm-mc from trunk still cannot assemble these tests correctly due to lack of addend handling. I did include the original assembly text in the tests so once the LLVM port is upstreamed we can just swap it to run assembler proper.

Yeah, we might have discussed this earlier. Sorry for bringing it up again.

[PkmX]

@ruiu I've uploaded a new patch that adds the blank line to RISCVGlobalPointer as requested. As I do not have commit rights to the LLD repository, could you commit the patch if there are no last-minute issues.

Thanks to all for the review and comments.

lld/trunk/ELF/Arch/RISCV.cpp

+//===- RISCV.cpp ----------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "InputFiles.h"
+#include "Target.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+
+class RISCV final : public TargetInfo {
+public:
+  virtual uint32_t calcEFlags() const override;
+  RelExpr getRelExpr(RelType Type, const Symbol &S,
+                     const uint8_t *Loc) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+};
+
+} // end anonymous namespace
+
+static uint32_t getEFlags(InputFile *F) {
+  if (Config->Is64)
+    return cast<ObjFile<ELF64LE>>(F)->getObj().getHeader()->e_flags;
+  else
+    return cast<ObjFile<ELF32LE>>(F)->getObj().getHeader()->e_flags;
+}
+
+uint32_t RISCV::calcEFlags() const {
+  assert(!ObjectFiles.empty());
+
+  uint32_t Target = getEFlags(ObjectFiles.front());
+
+  for (InputFile *F : ObjectFiles) {
+    uint32_t EFlags = getEFlags(F);
+    if (EFlags & EF_RISCV_RVC)
+      Target |= EF_RISCV_RVC;
+
+    if ((EFlags & EF_RISCV_FLOAT_ABI) != (Target & EF_RISCV_FLOAT_ABI))
+      error(toString(F) +
+            ": cannot link object files with different floating-point ABI");
+
+    if ((EFlags & EF_RISCV_RVE) != (Target & EF_RISCV_RVE))
+      error(toString(F) +
+            ": cannot link object files with different EF_RISCV_RVE");
+  }
+
+  return Target;
+}
+
+RelExpr RISCV::getRelExpr(const RelType Type, const Symbol &S,
+                          const uint8_t *Loc) const {
+  switch (Type) {
+  case R_RISCV_JAL:
+  case R_RISCV_BRANCH:
+  case R_RISCV_CALL:
+  case R_RISCV_PCREL_HI20:
+  case R_RISCV_RVC_BRANCH:
+  case R_RISCV_RVC_JUMP:
+  case R_RISCV_32_PCREL:
+    return R_PC;
+  case R_RISCV_PCREL_LO12_I:
+  case R_RISCV_PCREL_LO12_S:
+    return R_RISCV_PC_INDIRECT;
+  case R_RISCV_RELAX:
+  case R_RISCV_ALIGN:
+    return R_HINT;
+  default:
+    return R_ABS;
+  }
+}
+
+// Extract bits V[Begin:End], where range is inclusive, and Begin must be < 63.
+static uint32_t extractBits(uint64_t V, uint32_t Begin, uint32_t End) {
+  return (V & ((1ULL << (Begin + 1)) - 1)) >> End;
+}
+
+void RISCV::relocateOne(uint8_t *Loc, const RelType Type,
+                        const uint64_t Val) const {
+  switch (Type) {
+  case R_RISCV_32:
+    write32le(Loc, Val);
+    return;
+  case R_RISCV_64:
+    write64le(Loc, Val);
+    return;
+
+  case R_RISCV_RVC_BRANCH: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 8, Type);
+    checkAlignment(Loc, Val, 2, Type);
+    uint16_t Insn = read16le(Loc) & 0xE383;
+    uint16_t Imm8 = extractBits(Val, 8, 8) << 12;
+    uint16_t Imm4_3 = extractBits(Val, 4, 3) << 10;
+    uint16_t Imm7_6 = extractBits(Val, 7, 6) << 5;
+    uint16_t Imm2_1 = extractBits(Val, 2, 1) << 3;
+    uint16_t Imm5 = extractBits(Val, 5, 5) << 2;
+    Insn |= Imm8 | Imm4_3 | Imm7_6 | Imm2_1 | Imm5;
+
+    write16le(Loc, Insn);
+    return;
+  }
+
+  case R_RISCV_RVC_JUMP: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 11, Type);
+    checkAlignment(Loc, Val, 2, Type);
+    uint16_t Insn = read16le(Loc) & 0xE003;
+    uint16_t Imm11 = extractBits(Val, 11, 11) << 12;
+    uint16_t Imm4 = extractBits(Val, 4, 4) << 11;
+    uint16_t Imm9_8 = extractBits(Val, 9, 8) << 9;
+    uint16_t Imm10 = extractBits(Val, 10, 10) << 8;
+    uint16_t Imm6 = extractBits(Val, 6, 6) << 7;
+    uint16_t Imm7 = extractBits(Val, 7, 7) << 6;
+    uint16_t Imm3_1 = extractBits(Val, 3, 1) << 3;
+    uint16_t Imm5 = extractBits(Val, 5, 5) << 2;
+    Insn |= Imm11 | Imm4 | Imm9_8 | Imm10 | Imm6 | Imm7 | Imm3_1 | Imm5;
+
+    write16le(Loc, Insn);
+    return;
+  }
+
+  case R_RISCV_RVC_LUI: {
+    int32_t Imm = ((Val + 0x800) >> 12);
+    checkUInt(Loc, Imm, 6, Type);
+    if (Imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0`
+      write16le(Loc, (read16le(Loc) & 0x0F83) | 0x4000);
+    } else {
+      uint16_t Imm17 = extractBits(Val + 0x800, 17, 17) << 12;
+      uint16_t Imm16_12 = extractBits(Val + 0x800, 16, 12) << 2;
+      write16le(Loc, (read16le(Loc) & 0xEF83) | Imm17 | Imm16_12);
+    }
+    return;
+  }
+
+  case R_RISCV_JAL: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 20, Type);
+    checkAlignment(Loc, Val, 2, Type);
+
+    uint32_t Insn = read32le(Loc) & 0xFFF;
+    uint32_t Imm20 = extractBits(Val, 20, 20) << 31;
+    uint32_t Imm10_1 = extractBits(Val, 10, 1) << 21;
+    uint32_t Imm11 = extractBits(Val, 11, 11) << 20;
+    uint32_t Imm19_12 = extractBits(Val, 19, 12) << 12;
+    Insn |= Imm20 | Imm10_1 | Imm11 | Imm19_12;
+
+    write32le(Loc, Insn);
+    return;
+  }
+
+  case R_RISCV_BRANCH: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 12, Type);
+    checkAlignment(Loc, Val, 2, Type);
+
+    uint32_t Insn = read32le(Loc) & 0x1FFF07F;
+    uint32_t Imm12 = extractBits(Val, 12, 12) << 31;
+    uint32_t Imm10_5 = extractBits(Val, 10, 5) << 25;
+    uint32_t Imm4_1 = extractBits(Val, 4, 1) << 8;
+    uint32_t Imm11 = extractBits(Val, 11, 11) << 7;
+    Insn |= Imm12 | Imm10_5 | Imm4_1 | Imm11;
+
+    write32le(Loc, Insn);
+    return;
+  }
+
+  // auipc + jalr pair
+  case R_RISCV_CALL: {
+    checkInt(Loc, Val, 32, Type);
+    if (isInt<32>(Val)) {
+      relocateOne(Loc, R_RISCV_PCREL_HI20, Val);
+      relocateOne(Loc + 4, R_RISCV_PCREL_LO12_I, Val);
+    }
+    return;
+  }
+
+  case R_RISCV_PCREL_HI20:
+  case R_RISCV_HI20: {
+    checkInt(Loc, Val, 32, Type);
+    uint32_t Hi = Val + 0x800;
+    write32le(Loc, (read32le(Loc) & 0xFFF) | (Hi & 0xFFFFF000));
+    return;
+  }
+
+  case R_RISCV_PCREL_LO12_I:
+  case R_RISCV_LO12_I: {
+    checkInt(Loc, Val, 32, Type);
+    uint32_t Hi = Val + 0x800;
+    uint32_t Lo = Val - (Hi & 0xFFFFF000);
+    write32le(Loc, (read32le(Loc) & 0xFFFFF) | ((Lo & 0xFFF) << 20));
+    return;
+  }
+
+  case R_RISCV_PCREL_LO12_S:
+  case R_RISCV_LO12_S: {
+    checkInt(Loc, Val, 32, Type);
+    uint32_t Hi = Val + 0x800;
+    uint32_t Lo = Val - (Hi & 0xFFFFF000);
+    uint32_t Imm11_5 = extractBits(Lo, 11, 5) << 25;
+    uint32_t Imm4_0 = extractBits(Lo, 4, 0) << 7;
+    write32le(Loc, (read32le(Loc) & 0x1FFF07F) | Imm11_5 | Imm4_0);
+    return;
+  }
+
+  case R_RISCV_ADD8:
+    *Loc += Val;
+    return;
+  case R_RISCV_ADD16:
+    write16le(Loc, read16le(Loc) + Val);
+    return;
+  case R_RISCV_ADD32:
+    write32le(Loc, read32le(Loc) + Val);
+    return;
+  case R_RISCV_ADD64:
+    write64le(Loc, read64le(Loc) + Val);
+    return;
+  case R_RISCV_SUB6:
+    *Loc = (*Loc & 0xc0) | (((*Loc & 0x3f) - Val) & 0x3f);
+    return;
+  case R_RISCV_SUB8:
+    *Loc -= Val;
+    return;
+  case R_RISCV_SUB16:
+    write16le(Loc, read16le(Loc) - Val);
+    return;
+  case R_RISCV_SUB32:
+    write32le(Loc, read32le(Loc) - Val);
+    return;
+  case R_RISCV_SUB64:
+    write64le(Loc, read64le(Loc) - Val);
+    return;
+  case R_RISCV_SET6:
+    *Loc = (*Loc & 0xc0) | (Val & 0x3f);
+    return;
+  case R_RISCV_SET8:
+    *Loc = Val;
+    return;
+  case R_RISCV_SET16:
+    write16le(Loc, Val);
+    return;
+  case R_RISCV_SET32:
+  case R_RISCV_32_PCREL:
+    write32le(Loc, Val);
+    return;
+
+  case R_RISCV_ALIGN:
+  case R_RISCV_RELAX:
+    return; // Ignored (for now)
+  case R_RISCV_NONE:
+    return; // Do nothing
+
+  // These are handled by the dynamic linker
+  case R_RISCV_RELATIVE:
+  case R_RISCV_COPY:
+  case R_RISCV_JUMP_SLOT:
+  // GP-relative relocations are only produced after relaxation, which
+  // we don't support for now
+  case R_RISCV_GPREL_I:
+  case R_RISCV_GPREL_S:
+  default:
+    error(getErrorLocation(Loc) +
+          "unimplemented relocation: " + toString(Type));
+    return;
+  }
+}
+
+TargetInfo *elf::getRISCVTargetInfo() {
+  static RISCV Target;
+  return &Target;
+}

lld/trunk/ELF/CMakeLists.txt

add_lld_library(lldELF
   Arch/AMDGPU.cpp
   Arch/ARM.cpp
   Arch/AVR.cpp
   Arch/Hexagon.cpp
   Arch/Mips.cpp
   Arch/MipsArchTree.cpp
   Arch/PPC.cpp
   Arch/PPC64.cpp
+  Arch/RISCV.cpp
   Arch/SPARCV9.cpp
   Arch/X86.cpp
   Arch/X86_64.cpp
   CallGraphSort.cpp
   Driver.cpp
   DriverUtils.cpp
   EhFrame.cpp
   Filesystem.cpp

lld/trunk/ELF/Driver.cpp

static std::tuple<ELFKind, uint16_t, uint8_t> parseEmulation(StringRef Emul) {
   std::pair<ELFKind, uint16_t> Ret =
       StringSwitch<std::pair<ELFKind, uint16_t>>(S)
           .Cases("aarch64elf", "aarch64linux", "aarch64_elf64_le_vec",
                  {ELF64LEKind, EM_AARCH64})
           .Cases("armelf", "armelf_linux_eabi", {ELF32LEKind, EM_ARM})
           .Case("elf32_x86_64", {ELF32LEKind, EM_X86_64})
           .Cases("elf32btsmip", "elf32btsmipn32", {ELF32BEKind, EM_MIPS})
           .Cases("elf32ltsmip", "elf32ltsmipn32", {ELF32LEKind, EM_MIPS})
+          .Case("elf32lriscv", {ELF32LEKind, EM_RISCV})
           .Case("elf32ppc", {ELF32BEKind, EM_PPC})
           .Case("elf64btsmip", {ELF64BEKind, EM_MIPS})
           .Case("elf64ltsmip", {ELF64LEKind, EM_MIPS})
+          .Case("elf64lriscv", {ELF64LEKind, EM_RISCV})
           .Case("elf64ppc", {ELF64BEKind, EM_PPC64})
           .Case("elf64lppc", {ELF64LEKind, EM_PPC64})
           .Cases("elf_amd64", "elf_x86_64", {ELF64LEKind, EM_X86_64})
           .Case("elf_i386", {ELF32LEKind, EM_386})
           .Case("elf_iamcu", {ELF32LEKind, EM_IAMCU})
           .Default({ELFNoneKind, EM_NONE});
 
   if (Ret.first == ELFNoneKind)
static void setConfigs(opt::InputArgList &Args) {
   // 4 or 8 byte for each relocation entry. We don't know why ELF defined two
   // different mechanisms in the first place, but this is how the spec is
   // defined.
   //
   // You cannot choose which one, Rel or Rela, you want to use. Instead each
   // ABI defines which one you need to use. The following expression expresses
   // that.
   Config->IsRela =
-      (Config->Is64 || IsX32 || Machine == EM_PPC) && Machine != EM_MIPS;
+      (Config->Is64 || IsX32 || Machine == EM_PPC || Machine == EM_RISCV) &&
+      Machine != EM_MIPS;
 
   // If the output uses REL relocations we must store the dynamic relocation
   // addends to the output sections. We also store addends for RELA relocations
   // if --apply-dynamic-relocs is used.
   // We default to not writing the addends when using RELA relocations since
   // any standard conforming tool can find it in r_addend.
   Config->WriteAddends = Args.hasFlag(OPT_apply_dynamic_relocs,
                                       OPT_no_apply_dynamic_relocs, false) ||

lld/trunk/ELF/InputSection.h

private:
   template <class ELFT, class RelTy>
   void copyRelocations(uint8_t *Buf, llvm::ArrayRef<RelTy> Rels);
 
   template <class ELFT> void copyShtGroup(uint8_t *Buf);
 };
 
 // The list of all input sections.
 extern std::vector<InputSectionBase *> InputSections;
+
+Relocation *getRISCVPCRelHi20(const Symbol *Sym, const uint64_t Addend);
 } // namespace elf
 
 std::string toString(const elf::InputSectionBase *);
 } // namespace lld
 
 #endif

lld/trunk/ELF/InputSection.cpp

 // of the RW segment.
 static uint64_t getARMStaticBase(const Symbol &Sym) {
   OutputSection *OS = Sym.getOutputSection();
   if (!OS || !OS->PtLoad || !OS->PtLoad->FirstSec)
     fatal("SBREL relocation to " + Sym.getName() + " without static base");
   return OS->PtLoad->FirstSec->Addr;
 }
 
+// For R_RISCV_PC_INDIRECT (R_RISCV_PCREL_LO12_{I,S}), the symbol actually
+// points the corresponding R_RISCV_PCREL_HI20 relocation, and the target VA
+// is calculated using PCREL_HI20's symbol.
+//
+// This function returns the R_RISCV_PCREL_HI20 relocation from
+// R_RISCV_PCREL_LO12's symbol and addend.
+Relocation *lld::elf::getRISCVPCRelHi20(const Symbol *Sym, uint64_t Addend) {
+  const Defined *D = cast<Defined>(Sym);
+  InputSection *IS = cast<InputSection>(D->Section);
+
+  if (Addend != 0)
+    warn("Non-zero addend in R_RISCV_PCREL_LO12 relocation to " +
+         IS->getObjMsg(D->Value) + " is ignored");
+
+  // Relocations are sorted by offset, so we can use std::equal_range to do
+  // binary search.
+  auto Range = std::equal_range(IS->Relocations.begin(), IS->Relocations.end(),
+                                D->Value, RelocationOffsetComparator{});
+  for (auto It = std::get<0>(Range); It != std::get<1>(Range); ++It)
+    if (isRelExprOneOf<R_PC>(It->Expr))
+      return &*It;
+
+  error("R_RISCV_PCREL_LO12 relocation points to " + IS->getObjMsg(D->Value) +
+        " without an associated R_RISCV_PCREL_HI20 relocation");
+  return nullptr;
+}
+
 static uint64_t getRelocTargetVA(const InputFile *File, RelType Type, int64_t A,
                                  uint64_t P, const Symbol &Sym, RelExpr Expr) {
   switch (Expr) {
   case R_INVALID:
     return 0;
   case R_ABS:
   case R_RELAX_TLS_LD_TO_LE_ABS:
   case R_RELAX_GOT_PC_NOPIC:
static uint64_t getRelocTargetVA(const InputFile *File, RelType Type, int64_t A,
   case R_PLT_PAGE_PC: {
     uint64_t Dest;
     if (Sym.isUndefWeak())
       Dest = getAArch64Page(A);
     else
       Dest = getAArch64Page(Sym.getVA(A));
     return Dest - getAArch64Page(P);
   }
+  case R_RISCV_PC_INDIRECT: {
+    const Relocation *HiRel = getRISCVPCRelHi20(&Sym, A);
+    if (!HiRel)
+      return 0;
+    return getRelocTargetVA(File, HiRel->Type, HiRel->Addend, Sym.getVA(),
+                            *HiRel->Sym, HiRel->Expr);
+  }
   case R_PC: {
     uint64_t Dest;
     if (Sym.isUndefWeak()) {
       // On ARM and AArch64 a branch to an undefined weak resolves to the
       // next instruction, otherwise the place.
       if (Config->EMachine == EM_ARM)
         Dest = getARMUndefinedRelativeWeakVA(Type, A, P);
       else if (Config->EMachine == EM_AARCH64)

lld/trunk/ELF/Relocations.h

enum RelExpr {
   R_RELAX_TLS_GD_TO_IE_END,
   R_RELAX_TLS_GD_TO_IE_GOT_OFF,
   R_RELAX_TLS_GD_TO_IE_PAGE_PC,
   R_RELAX_TLS_GD_TO_LE,
   R_RELAX_TLS_GD_TO_LE_NEG,
   R_RELAX_TLS_IE_TO_LE,
   R_RELAX_TLS_LD_TO_LE,
   R_RELAX_TLS_LD_TO_LE_ABS,
+  R_RISCV_PC_INDIRECT,
   R_SIZE,
   R_TLS,
   R_TLSDESC,
   R_TLSDESC_CALL,
   R_TLSDESC_PAGE,
   R_TLSGD_GOT,
   R_TLSGD_GOT_FROM_END,
   R_TLSGD_PC,

 struct Relocation {
   RelExpr Expr;
   RelType Type;
   uint64_t Offset;
   int64_t Addend;
   Symbol *Sym;
 };
 
+struct RelocationOffsetComparator {
+  bool operator()(const Relocation &Lhs, const Relocation &Rhs) {
+    return Lhs.Offset < Rhs.Offset;
+  }
+
+  // For std::lower_bound, std::upper_bound, std::equal_range.
+  bool operator()(const Relocation &Rel, uint64_t Val) {
+    return Rel.Offset < Val;
+  }
+
+  bool operator()(uint64_t Val, const Relocation &Rel) {
+    return Val < Rel.Offset;
+  }
+};
+
 template <class ELFT> void scanRelocations(InputSectionBase &);
 
 class ThunkSection;
 class Thunk;
 struct InputSectionDescription;
 
 class ThunkCreator {
 public:

lld/trunk/ELF/Relocations.cpp

 static void scanRelocs(InputSectionBase &Sec, ArrayRef<RelTy> Rels) {
   OffsetGetter GetOffset(Sec);
 
   // Not all relocations end up in Sec.Relocations, but a lot do.
   Sec.Relocations.reserve(Rels.size());
 
   for (auto I = Rels.begin(), End = Rels.end(); I != End;)
     scanReloc<ELFT>(Sec, GetOffset, I, End);
+
+  // Sort relocations by offset to binary search for R_RISCV_PCREL_HI20
+  if (Config->EMachine == EM_RISCV)
+    std::stable_sort(Sec.Relocations.begin(), Sec.Relocations.end(),
+                     RelocationOffsetComparator{});
 }
 
 template <class ELFT> void elf::scanRelocations(InputSectionBase &S) {
   if (S.AreRelocsRela)
     scanRelocs<ELFT>(S, S.relas<ELFT>());
   else
     scanRelocs<ELFT>(S, S.rels<ELFT>());
 }

lld/trunk/ELF/Symbols.h

struct ElfSym {
 
   // _gp, _gp_disp and __gnu_local_gp symbols. Only for MIPS.
   static Defined *MipsGp;
   static Defined *MipsGpDisp;
   static Defined *MipsLocalGp;
 
   // __rela_iplt_end or __rel_iplt_end
   static Defined *RelaIpltEnd;
+
+  // __global_pointer$ in RISC-V.
+  static Defined *RISCVGlobalPointer;
 };
 
 // A buffer class that is large enough to hold any Symbol-derived
 // object. We allocate memory using this class and instantiate a symbol
 // using the placement new.
 union SymbolUnion {
   alignas(Defined) char A[sizeof(Defined)];
   alignas(Undefined) char C[sizeof(Undefined)];

lld/trunk/ELF/Symbols.cpp

 Defined *ElfSym::Edata2;
 Defined *ElfSym::End1;
 Defined *ElfSym::End2;
 Defined *ElfSym::GlobalOffsetTable;
 Defined *ElfSym::MipsGp;
 Defined *ElfSym::MipsGpDisp;
 Defined *ElfSym::MipsLocalGp;
 Defined *ElfSym::RelaIpltEnd;
+Defined *ElfSym::RISCVGlobalPointer;
 
 static uint64_t getSymVA(const Symbol &Sym, int64_t &Addend) {
   switch (Sym.kind()) {
   case Symbol::DefinedKind: {
     auto &D = cast<Defined>(Sym);
     SectionBase *IS = D.Section;
 
     // According to the ELF spec reference to a local symbol from outside

lld/trunk/ELF/Target.h

 
 TargetInfo *getAArch64TargetInfo();
 TargetInfo *getAMDGPUTargetInfo();
 TargetInfo *getARMTargetInfo();
 TargetInfo *getAVRTargetInfo();
 TargetInfo *getHexagonTargetInfo();
 TargetInfo *getPPC64TargetInfo();
 TargetInfo *getPPCTargetInfo();
+TargetInfo *getRISCVTargetInfo();
 TargetInfo *getSPARCV9TargetInfo();
 TargetInfo *getX32TargetInfo();
 TargetInfo *getX86TargetInfo();
 TargetInfo *getX86_64TargetInfo();
 template <class ELFT> TargetInfo *getMipsTargetInfo();
 
 struct ErrorPlace {
   InputSectionBase *IS;

lld/trunk/ELF/Target.cpp

case ELF64BEKind:
       return getMipsTargetInfo<ELF64BE>();
     default:
       fatal("unsupported MIPS target");
     }
   case EM_PPC:
     return getPPCTargetInfo();
   case EM_PPC64:
     return getPPC64TargetInfo();
+  case EM_RISCV:
+    return getRISCVTargetInfo();
   case EM_SPARCV9:
     return getSPARCV9TargetInfo();
   case EM_X86_64:
     if (Config->EKind == ELF32LEKind)
       return getX32TargetInfo();
     return getX86_64TargetInfo();
   }
   fatal("unknown target machine");

lld/trunk/ELF/Writer.cpp

template <class ELFT> void Writer<ELFT>::finalizeSections() {
   if (InX::DynSymTab)
     Symtab->addRegular("_DYNAMIC", STV_HIDDEN, STT_NOTYPE, 0 /*Value*/,
                        /*Size=*/0, STB_WEAK, InX::Dynamic,
                        /*File=*/nullptr);
 
   // Define __rel[a]_iplt_{start,end} symbols if needed.
   addRelIpltSymbols();
 
+  // RISC-V's gp can address +/- 2 KiB, set it to .sdata + 0x800 if not defined.
+  if (Config->EMachine == EM_RISCV) {
+    ElfSym::RISCVGlobalPointer =
+        dyn_cast_or_null<Defined>(Symtab->find("__global_pointer$"));
+    if (!ElfSym::RISCVGlobalPointer)
+      ElfSym::RISCVGlobalPointer =
+          addOptionalRegular("__global_pointer$", findSection(".sdata"), 0x800);
+  }
+
   // This responsible for splitting up .eh_frame section into
   // pieces. The relocation scan uses those pieces, so this has to be
   // earlier.
   applySynthetic({InX::EhFrame},
                  [](SyntheticSection *SS) { SS->finalizeContents(); });
 
   for (Symbol *S : Symtab->getSymbols())
     S->IsPreemptible |= computeIsPreemptible(*S);

lld/trunk/test/ELF/riscv-branch.test

+# .option norelax
+# .global _start
+# _start:
+#     beq x0, x0, _start
+#
+# .section .reloc_max, "ax", @progbits
+# L1:
+#     beq x0, x0, L1 + 0xffe
+#
+# .section .reloc_min, "ax", @progbits
+# L2:
+#     beq x0, x0, L2 - 0x1000
+#
+# REQUIRES: riscv
+# RUN: yaml2obj %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: obj2yaml %t | FileCheck %s
+#
+# CHECK: - Name:            .text
+# CHECK:   Content:         '63000000'
+# 11000:       00000063                beqz    zero,11000 <_start>
+#
+# CHECK: - Name:            .reloc_max
+# CHECK:   Content:         E30F007E
+# 11004:       7e000fe3                beqz    zero,12002
+#
+# CHECK: - Name:            .reloc_min
+# CHECK:   Content:         '63000080'
+# 11008:       80000063                beqz    zero,10008
+
+--- !ELF
+FileHeader:
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_RISCV
+  Flags:           [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_SOFT ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000002
+    Content:         '63000000'
+  - Name:            .rela.text
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .text
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          _start
+        Type:            R_RISCV_BRANCH
+  - Name:            .data
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+    Content:         ''
+  - Name:            .bss
+    Type:            SHT_NOBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+  - Name:            .reloc_max
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000001
+    Content:         E30F007E
+  - Name:            .rela.reloc_max
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .reloc_max
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          L1
+        Type:            R_RISCV_BRANCH
+        Addend:          4094
+  - Name:            .reloc_min
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000001
+    Content:         '63000080'
+  - Name:            .rela.reloc_min
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .reloc_min
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          L2
+        Type:            R_RISCV_BRANCH
+        Addend:          -4096
+Symbols:
+  Local:
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+    - Name:            .data
+      Type:            STT_SECTION
+      Section:         .data
+    - Name:            .bss
+      Type:            STT_SECTION
+      Section:         .bss
+    - Name:            .reloc_max
+      Type:            STT_SECTION
+      Section:         .reloc_max
+    - Name:            L1
+      Section:         .reloc_max
+    - Name:            .reloc_min
+      Type:            STT_SECTION
+      Section:         .reloc_min
+    - Name:            L2
+      Section:         .reloc_min
+  Global:
+    - Name:            _start
+      Section:         .text
+...

lld/trunk/test/ELF/riscv-call.test

+# .option norelax
+# .global _start
+# _start:
+#     call    _start + 4
+#
+# .section .reloc_neg, "ax", @progbits
+# L1:
+#     call    L1 - 4
+#
+# REQUIRES: riscv
+# RUN: yaml2obj %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: obj2yaml %t | FileCheck %s
+#
+# CHECK:  - Name:            .text
+# CHECK:    Content:         '97000000E7804000'
+#
+# 11000:       00000097                auipc   ra,0x0
+# 11004:       004080e7                jalr    4(ra)
+#
+# CHECK:  - Name:            .reloc_neg
+# CHECK:    Content:         97000000E780C0FF
+#
+# 11008:       00000097                auipc   ra,0x0
+# 1100c:       ffc080e7                jalr    -4(ra)
+
+--- !ELF
+FileHeader:
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_RISCV
+  Flags:           [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_SOFT ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000002
+    Content:         '97000000E7800000'
+  - Name:            .rela.text
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .text
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          _start
+        Type:            R_RISCV_CALL
+        Addend:          4
+  - Name:            .data
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+    Content:         ''
+  - Name:            .bss
+    Type:            SHT_NOBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+  - Name:            .reloc_neg
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000001
+    Content:         '97000000E7800000'
+  - Name:            .rela.reloc_neg
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .reloc_neg
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          L1
+        Type:            R_RISCV_CALL
+        Addend:          -4
+Symbols:
+  Local:
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+    - Name:            .data
+      Type:            STT_SECTION
+      Section:         .data
+    - Name:            .bss
+      Type:            STT_SECTION
+      Section:         .bss
+    - Name:            .reloc_neg
+      Type:            STT_SECTION
+      Section:         .reloc_neg
+    - Name:            L1
+      Section:         .reloc_neg
+  Global:
+    - Name:            _start
+      Section:         .text
+...

lld/trunk/test/ELF/riscv-hi20-lo12.test

+# .option norelax
+# .global _start
+#
+# .section .reloc_12345678, "ax", @progbits
+# _start:
+# foo = 0x12345678
+#     lui     a0, %hi(foo)
+#     addi    a0, a0, %lo(foo)
+#     lw      a0, %lo(foo)(a0)
+#
+# .section .reloc_fedcba98, "ax", @progbits
+# foo = 0xfedcba98
+#     lui     a0, %hi(foo)
+#     addi    a0, a0, %lo(foo)
+#
+# REQUIRES: riscv
+# RUN: yaml2obj %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: obj2yaml %t | FileCheck %s
+#
+# CHECK: - Name:            .reloc_12345678
+# CHECK:   Content:         '375534121305856703258567'
+# 11000:       12345537                lui     a0,0x12345
+# 11004:       67850513                addi    a0,a0,1656 # 12345678 <__global_pointer$+0x12332e78>
+# 11008:       67852503                lw      a0,1656(a0)
+#
+# CHECK: - Name:            .reloc_fedcba98
+# CHECK:   Content:         37C5DCFE130585A9
+# 1100c:       fedcc537                lui     a0,0xfedcc
+# 11010:       a9850513                addi    a0,a0,-1384 # fedcba98 <__global_pointer$+0xfedb9298>
+
+--- !ELF
+FileHeader:
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_RISCV
+  Flags:           [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_SOFT ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000002
+    Content:         ''
+  - Name:            .data
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+    Content:         ''
+  - Name:            .bss
+    Type:            SHT_NOBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+  - Name:            .reloc_12345678
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000001
+    Content:         '375534121305856703258567'
+  - Name:            .reloc_fedcba98
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000001
+    Content:         37C5DCFE130585A9
+Symbols:
+  Local:
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+    - Name:            .data
+      Type:            STT_SECTION
+      Section:         .data
+    - Name:            .bss
+      Type:            STT_SECTION
+      Section:         .bss
+    - Name:            .reloc_12345678
+      Type:            STT_SECTION
+      Section:         .reloc_12345678
+    - Name:            foo
+      Value:           0x00000000FEDCBA98
+    - Name:            .reloc_fedcba98
+      Type:            STT_SECTION
+      Section:         .reloc_fedcba98
+  Global:
+    - Name:            _start
+      Section:         .reloc_12345678
+...

lld/trunk/test/ELF/riscv-jal-error.test

+# .option norelax
+# .global _start
+#
+# _start:
+# L1:
+#     jal x0, L1 + 0x100000
+# L2:
+#     jal x0, L2 - 0x100002
+# L3:
+#     jal x0, L3 + 1
+# L4:
+#     c.jal L4 + 1
+#
+# REQUIRES: riscv
+# RUN: yaml2obj %s -o %t.o
+# RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
+#
+# CHECK: {{.*}}(.text+0x0): relocation R_RISCV_JAL out of range
+# CHECK: {{.*}}(.text+0x4): relocation R_RISCV_JAL out of range
+# CHECK: {{.*}}(.text+0x8): improper alignment for relocation R_RISCV_JAL
+# CHECK: {{.*}}(.text+0xC): improper alignment for relocation R_RISCV_RVC_JUMP
+
+--- !ELF
+FileHeader:
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_RISCV
+  Flags:           [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_SOFT ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000002
+    Content:         6F0000806FF0FF7F6F0000000120
+  - Name:            .rela.text
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .text
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          L1
+        Type:            R_RISCV_JAL
+        Addend:          1048576
+      - Offset:          0x0000000000000004
+        Symbol:          L2
+        Type:            R_RISCV_JAL
+        Addend:          -1048578
+      - Offset:          0x0000000000000008
+        Symbol:          L3
+        Type:            R_RISCV_JAL
+        Addend:          1
+      - Offset:          0x000000000000000C
+        Symbol:          L4
+        Type:            R_RISCV_RVC_JUMP
+        Addend:          1
+  - Name:            .data
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+    Content:         ''
+  - Name:            .bss
+    Type:            SHT_NOBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+Symbols:
+  Local:
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+    - Name:            .data
+      Type:            STT_SECTION
+      Section:         .data
+    - Name:            .bss
+      Type:            STT_SECTION
+      Section:         .bss
+    - Name:            L1
+      Section:         .text
+    - Name:            L2
+      Section:         .text
+      Value:           0x0000000000000004
+    - Name:            L3
+      Section:         .text
+      Value:           0x0000000000000008
+    - Name:            L4
+      Section:         .text
+      Value:           0x000000000000000C
+  Global:
+    - Name:            _start
+      Section:         .text
+...

lld/trunk/test/ELF/riscv-jal.test

+# .option norelax
+# .global _start
+#
+# .section .reloc_zero, "ax", @progbits
+# _start:
+# L1:
+#     jal x0, L1
+# L2:
+#     c.jal L2
+#
+# .section .reloc_max, "ax", @progbits
+# L3:
+#     jal x0, L3 + 0xffffe
+# L4:
+#     c.jal L4 + 0x7fe
+#
+# .section .reloc_min, "ax", @progbits
+# L5:
+#     jal x0, L5 - 0x100000
+# L6:
+#     c.jal L6 - 0x800
+#
+# REQUIRES: riscv
+# RUN: yaml2obj %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: obj2yaml %t | FileCheck %s
+#
+# CHECK: - Name:            .reloc_zero
+# CHECK:   Content:         6F0000000120
+# 11000:       0000006f                j       11000
+# 11004:       2001                    jal     11004
+#
+# CHECK: - Name:            .reloc_max
+# CHECK:   Content:         6FF0FF7FFD2F
+# 11006:       7ffff06f                j       111004
+# 1100a:       2ffd                    jal     11808
+#
+# CHECK: - Name:            .reloc_min
+# CHECK:   Content:         6F0000800130
+# 1100c:       8000006f                j       fff1100c
+# 11010:       3001                    jal     10810
+
+--- !ELF
+FileHeader:
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_RISCV
+  Flags:           [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_SOFT ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000002
+    Content:         ''
+  - Name:            .data
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+    Content:         ''
+  - Name:            .bss
+    Type:            SHT_NOBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+  - Name:            .reloc_zero
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000001
+    Content:         6F0000000120
+  - Name:            .rela.reloc_zero
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .reloc_zero
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          L1
+        Type:            R_RISCV_JAL
+      - Offset:          0x0000000000000004
+        Symbol:          L2
+        Type:            R_RISCV_RVC_JUMP
+  - Name:            .reloc_max
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000001
+    Content:         6FF0FF7FFD2F
+  - Name:            .rela.reloc_max
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .reloc_max
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          L3
+        Type:            R_RISCV_JAL
+        Addend:          1048574
+      - Offset:          0x0000000000000004
+        Symbol:          L4
+        Type:            R_RISCV_RVC_JUMP
+        Addend:          2046
+  - Name:            .reloc_min
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000001
+    Content:         6F0000800130
+  - Name:            .rela.reloc_min
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .reloc_min
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          L5
+        Type:            R_RISCV_JAL
+        Addend:          -1048576
+      - Offset:          0x0000000000000004
+        Symbol:          L6
+        Type:            R_RISCV_RVC_JUMP
+        Addend:          -2048
+Symbols:
+  Local:
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+    - Name:            .data
+      Type:            STT_SECTION
+      Section:         .data
+    - Name:            .bss
+      Type:            STT_SECTION
+      Section:         .bss
+    - Name:            .reloc_zero
+      Type:            STT_SECTION
+      Section:         .reloc_zero
+    - Name:            L1
+      Section:         .reloc_zero
+    - Name:            L2
+      Section:         .reloc_zero
+      Value:           0x0000000000000004
+    - Name:            .reloc_max
+      Type:            STT_SECTION
+      Section:         .reloc_max
+    - Name:            L3
+      Section:         .reloc_max
+    - Name:            L4
+      Section:         .reloc_max
+      Value:           0x0000000000000004
+    - Name:            .reloc_min
+      Type:            STT_SECTION
+      Section:         .reloc_min
+    - Name:            L5
+      Section:         .reloc_min
+    - Name:            L6
+      Section:         .reloc_min
+      Value:           0x0000000000000004
+  Global:
+    - Name:            _start
+      Section:         .reloc_zero
+...

lld/trunk/test/ELF/riscv-pcrel-hilo.test

+# .option norelax
+# .global _start
+#
+# _start:
+#     auipc   a0, %pcrel_hi(_start + 4)
+#     addi    a0, a0, %pcrel_lo(_start)
+#
+# .section .reloc_neg, "ax", @progbits
+# L1:
+#     auipc   a0, %pcrel_hi(L1 - 2)
+#     addi    a0, a0, %pcrel_lo(L1)
+#
+#
+# REQUIRES: riscv
+# RUN: yaml2obj %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: obj2yaml %t | FileCheck %s
+#
+# CHECK: - Name:            .text
+# CHECK:   Content:         '1705000013054500'
+# 11000:       00000517                auipc   a0,0x0
+# 11004:       00450513                addi    a0,a0,4 # 11004 <_start+0x4>
+#
+# CHECK: - Name:            .reloc_neg
+# CHECK:   Content:         170500001305E5FF
+# 11008:       00000517                auipc   a0,0x0
+# 1100c:       ffe50513                addi    a0,a0,-2 # 11006 <_start+0x6>
+
+--- !ELF
+FileHeader:
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_RISCV
+  Flags:           [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_SOFT ]
+Sections:
+  - Name:            .text
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000002
+    Content:         '1705000013050500'
+  - Name:            .rela.text
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .text
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          _start
+        Type:            R_RISCV_PCREL_HI20
+        Addend:          4
+      - Offset:          0x0000000000000004
+        Symbol:          _start
+        Type:            R_RISCV_PCREL_LO12_I
+  - Name:            .data
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+    Content:         ''
+  - Name:            .bss
+    Type:            SHT_NOBITS
+    Flags:           [ SHF_WRITE, SHF_ALLOC ]
+    AddressAlign:    0x0000000000000001
+  - Name:            .reloc_neg
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x0000000000000001
+    Content:         '1705000013050500'
+  - Name:            .rela.reloc_neg
+    Type:            SHT_RELA
+    Flags:           [ SHF_INFO_LINK ]
+    Link:            .symtab
+    AddressAlign:    0x0000000000000004
+    Info:            .reloc_neg
+    Relocations:
+      - Offset:          0x0000000000000000
+        Symbol:          L1
+        Type:            R_RISCV_PCREL_HI20
+        Addend:          -2
+      - Offset:          0x0000000000000004
+        Symbol:          L1
+        Type:            R_RISCV_PCREL_LO12_I
+Symbols:
+  Local:
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+    - Name:            .data
+      Type:            STT_SECTION
+      Section:         .data
+    - Name:            .bss
+      Type:            STT_SECTION
+      Section:         .bss
+    - Name:            .reloc_neg
+      Type:            STT_SECTION
+      Section:         .reloc_neg
+    - Name:            L1
+      Section:         .reloc_neg
+  Global:
+    - Name:            _start
+      Section:         .text
+...

lld/trunk/test/lit.cfg.py

llvm_config.feature_config(
      ('--assertion-mode', {'ON': 'asserts'}),
      ('--targets-built', {'AArch64': 'aarch64',
                           'AMDGPU': 'amdgpu',
                           'ARM': 'arm',
                           'AVR': 'avr',
                           'Hexagon': 'hexagon',
                           'Mips': 'mips',
                           'PowerPC': 'ppc',
+                          'RISCV': 'riscv',
                           'Sparc': 'sparc',
                           'WebAssembly': 'wasm',
                           'X86': 'x86'})
      ])
 
 # Set a fake constant version so that we get consistent output.
 config.environment['LLD_VERSION'] = 'LLD 1.0'
 config.environment['LLD_IN_TEST'] = '1'