- User Since
- Jan 31 2017, 5:57 AM (207 w, 1 d)
Apr 20 2020
LGTM. Tested the patch for RISC-V.
Apr 17 2020
Apr 16 2020
It seems that this change breaks the RISCV backend. RISCVAsmBackend::relaxInstruction assumes that the Relaxed parameter is a fresh uninitialized MCInst. With this change, invalid instructions with too many operands are generated. A similar problem probably happens for the Hexagon and for the AMDGPU backend.
Feb 23 2018
Jan 19 2018
Is there anything missing to land in upstream?