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Razer6 (Robert Schilling)


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User Since
Jan 31 2017, 5:57 AM (295 w, 1 d)

Recent Activity

Apr 20 2020

Razer6 accepted D78364: [MC][Bugfix] Remove redundant parameter for relaxInstruction.

LGTM. Tested the patch for RISC-V.

Apr 20 2020, 6:59 AM · Restricted Project

Apr 17 2020

Razer6 added a comment to D77851: [X86][MC] Make -x86-pad-max-prefix-size compatible with --mc-relax-all.

Which way do you think is better? Personally, I prefer the second one, since getAssembler().getBackend().relaxInstruction(Relaxed, STI, Relaxed) is called in a loop, the assumption that third argument of relaxInstruction is a fresh uninitialized MCInst is very strange.

Special casing RISC-V looks good to me.

Apr 17 2020, 1:02 AM · Restricted Project

Apr 16 2020

Razer6 updated subscribers of D77851: [X86][MC] Make -x86-pad-max-prefix-size compatible with --mc-relax-all.

It seems that this change breaks the RISCV backend. RISCVAsmBackend::relaxInstruction assumes that the Relaxed parameter is a fresh uninitialized MCInst. With this change, invalid instructions with too many operands are generated. A similar problem probably happens for the Hexagon and for the AMDGPU backend.

Apr 16 2020, 5:36 AM · Restricted Project

Feb 23 2018

Razer6 added inline comments to D39322: [lld] Support RISC-V.
Feb 23 2018, 8:18 AM · lld

Jan 19 2018

Razer6 added a comment to D39322: [lld] Support RISC-V.

Is there anything missing to land in upstream?

Jan 19 2018, 9:32 AM · lld

Feb 1 2017

Razer6 added a comment to D23568: [RISCV 10/10] Add common fixups and relocations.

@theraven @jyknight What's the state of this change?

Feb 1 2017, 5:13 AM