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- User Since
- Jan 31 2017, 5:57 AM (207 w, 1 d)
Apr 20 2020
Apr 20 2020
LGTM. Tested the patch for RISC-V.
Apr 20 2020, 6:59 AM · Restricted Project
Apr 17 2020
Apr 17 2020
Razer6 added a comment to D77851: [X86][MC] Make -x86-pad-max-prefix-size compatible with --mc-relax-all.
Apr 17 2020, 1:02 AM · Restricted Project
Apr 16 2020
Apr 16 2020
Razer6 updated subscribers of D77851: [X86][MC] Make -x86-pad-max-prefix-size compatible with --mc-relax-all.
It seems that this change breaks the RISCV backend. RISCVAsmBackend::relaxInstruction assumes that the Relaxed parameter is a fresh uninitialized MCInst. With this change, invalid instructions with too many operands are generated. A similar problem probably happens for the Hexagon and for the AMDGPU backend.
Apr 16 2020, 5:36 AM · Restricted Project
Feb 23 2018
Feb 23 2018
Razer6 added inline comments to D39322: [lld] Support RISC-V.
Jan 19 2018
Jan 19 2018
Razer6 added a comment to D39322: [lld] Support RISC-V.
Is there anything missing to land in upstream?
Feb 1 2017
Feb 1 2017
Razer6 added a comment to D23568: [RISCV 10/10] Add common fixups and relocations.