[RISCV] Teach MatInt to use (ADD_UW X, (SLLI X, 32)) to materialize some constants.

[craig.topper]

Summary

If the high and low 32 bits are the same, we try to use
(ADD X, (SLLI X, 32)) but that only works if bit 31 is clear since
the low 32 bits will be sign extended.

If we have Zba we can use add.uw to zero the sign extended bits.

[craig.topper]

clang-format

[wangpc]

It seems reasonable to me.
LGTM.

[reames]

LGTM.

Mostly for completeness sake, here's how I convinced myself this is correct.

• If we could generate a unsigned 32 constant in the 64 bit register, we could do OR((shl C, 32), C). The ADD and OR are equivalent in this case due to no common set bits.
• Generating a zext(i32) is hard, but we can generate a sext(i32) and then truncate. We then have to put the zext/trunc somewhere.
• add.uw applies a trunc/zext operation to one input.

A couple of thoughts off that.

• It would be super handy to have a sh32add.uw. To bad we don't.
• shl.uw allows us to produce a 32 bit contiguous constant at any point in the i64.
• sh3add.uw allows us to produce a 35 bit constant or a sign extended 35 bit constant in at most four instructions.

[craig.topper]

In D159253#4631902, @reames wrote:

LGTM.

Mostly for completeness sake, here's how I convinced myself this is correct.

• If we could generate a unsigned 32 constant in the 64 bit register, we could do OR((shl C, 32), C). The ADD and OR are equivalent in this case due to no common set bits.
• Generating a zext(i32) is hard, but we can generate a sext(i32) and then truncate. We then have to put the zext/trunc somewhere.
• add.uw applies a trunc/zext operation to one input.

A couple of thoughts off that.

• It would be super handy to have a sh32add.uw. To bad we don't.
• shl.uw allows us to produce a 32 bit contiguous constant at any point in the i64.
• sh3add.uw allows us to produce a 35 bit constant or a sign extended 35 bit constant in at most four instructions.

I think sh32add.uw is equivalent to the PACK instruction from the old Zbp spec which took the lower 32 bits from two registers and concatenated them.
Did you mean slli.uw instead of shl.uw?

[reames]

In D159253#4631914, @craig.topper wrote:

In D159253#4631902, @reames wrote:

LGTM.

Mostly for completeness sake, here's how I convinced myself this is correct.

• If we could generate a unsigned 32 constant in the 64 bit register, we could do OR((shl C, 32), C). The ADD and OR are equivalent in this case due to no common set bits.
• Generating a zext(i32) is hard, but we can generate a sext(i32) and then truncate. We then have to put the zext/trunc somewhere.
• add.uw applies a trunc/zext operation to one input.

A couple of thoughts off that.

• It would be super handy to have a sh32add.uw. To bad we don't.
• shl.uw allows us to produce a 32 bit contiguous constant at any point in the i64.
• sh3add.uw allows us to produce a 35 bit constant or a sign extended 35 bit constant in at most four instructions.

I think sh32add.uw is equivalent to the PACK instruction from the old Zbp spec which took the lower 32 bits from two registers and concatenated them.

Agreed. I wish we had that instruction, but unfortunately we don't.

Did you mean slli.uw instead of shl.uw?

Yeah. I swapped the llvm IR name and the instruction name.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 static SDValue selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
                          int64_t Imm, const RISCVSubtarget &Subtarget) {
   RISCVMatInt::InstSeq Seq =
       RISCVMatInt::generateInstSeq(Imm, Subtarget.getFeatureBits());
 
   // See if we can create this constant as (ADD (SLLI X, 32), X) where X is at
   // worst an LUI+ADDIW. This will require an extra register, but avoids a
   // constant pool.
+  // If we have Zba we can use (ADD_UW X, (SLLI X, 32)) to handle cases where
+  // low and high 32 bits are the same and bit 31 and 63 are set.
   if (Seq.size() > 3) {
     int64_t LoVal = SignExtend64<32>(Imm);
     int64_t HiVal = SignExtend64<32>(((uint64_t)Imm - (uint64_t)LoVal) >> 32);
-    if (LoVal == HiVal) {
+    if (LoVal == HiVal ||
+        (Subtarget.hasStdExtZba() && Lo_32(Imm) == Hi_32(Imm))) {
       RISCVMatInt::InstSeq SeqLo =
           RISCVMatInt::generateInstSeq(LoVal, Subtarget.getFeatureBits());
       if ((SeqLo.size() + 2) < Seq.size()) {
         SDValue Lo = selectImmSeq(CurDAG, DL, VT, SeqLo);
 
         SDValue SLLI = SDValue(
             CurDAG->getMachineNode(RISCV::SLLI, DL, VT, Lo,
                                    CurDAG->getTargetConstant(32, DL, VT)),
             0);
-        return SDValue(CurDAG->getMachineNode(RISCV::ADD, DL, VT, Lo, SLLI),
-                       0);
+        // Prefer ADD when possible.
+        unsigned AddOpc = (LoVal == HiVal) ? RISCV::ADD : RISCV::ADD_UW;
+        return SDValue(CurDAG->getMachineNode(AddOpc, DL, VT, Lo, SLLI), 0);
       }
     }
   }
 
   // Otherwise, use the original sequence.
   return selectImmSeq(CurDAG, DL, VT, Seq);
 }
 

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static SDValue lowerConstant(SDValue Op, SelectionDAG &DAG,
   RISCVMatInt::InstSeq Seq =
       RISCVMatInt::generateInstSeq(Imm, Subtarget.getFeatureBits());
   if (Seq.size() <= Subtarget.getMaxBuildIntsCost())
     return Op;
 
   // Special case. See if we can build the constant as (ADD (SLLI X, 32), X) do
   // that if it will avoid a constant pool.
   // It will require an extra temporary register though.
+  // If we have Zba we can use (ADD_UW X, (SLLI X, 32)) to handle cases where
+  // low and high 32 bits are the same and bit 31 and 63 are set.
   if (!DAG.shouldOptForSize()) {
     int64_t LoVal = SignExtend64<32>(Imm);
     int64_t HiVal = SignExtend64<32>(((uint64_t)Imm - (uint64_t)LoVal) >> 32);
-    if (LoVal == HiVal) {
+    if (LoVal == HiVal ||
+        (Subtarget.hasStdExtZba() && Lo_32(Imm) == Hi_32(Imm))) {
       RISCVMatInt::InstSeq SeqLo =
           RISCVMatInt::generateInstSeq(LoVal, Subtarget.getFeatureBits());
       if ((SeqLo.size() + 2) <= Subtarget.getMaxBuildIntsCost())
         return Op;
     }
   }
 
   // Expand to a constant pool using the default expansion code.

llvm/test/CodeGen/RISCV/imm.ll

 ; RV64IXTHEADBB:       # %bb.0:
 ; RV64IXTHEADBB-NEXT:    lui a0, 65793
 ; RV64IXTHEADBB-NEXT:    addiw a0, a0, 16
 ; RV64IXTHEADBB-NEXT:    slli a1, a0, 32
 ; RV64IXTHEADBB-NEXT:    add a0, a0, a1
 ; RV64IXTHEADBB-NEXT:    ret
   ret i64 1157442765409226768 ; 0x0101010101010101
 }
+
+; Hi and lo are the same and also negative.
+define i64 @imm64_same_lo_hi_negative() nounwind {
+; RV32I-LABEL: imm64_same_lo_hi_negative:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 526344
+; RV32I-NEXT:    addi a0, a0, 128
+; RV32I-NEXT:    mv a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64-NOPOOL-LABEL: imm64_same_lo_hi_negative:
+; RV64-NOPOOL:       # %bb.0:
+; RV64-NOPOOL-NEXT:    lui a0, 983297
+; RV64-NOPOOL-NEXT:    slli a0, a0, 4
+; RV64-NOPOOL-NEXT:    addi a0, a0, 257
+; RV64-NOPOOL-NEXT:    slli a0, a0, 16
+; RV64-NOPOOL-NEXT:    addi a0, a0, 257
+; RV64-NOPOOL-NEXT:    slli a0, a0, 15
+; RV64-NOPOOL-NEXT:    addi a0, a0, 128
+; RV64-NOPOOL-NEXT:    ret
+;
+; RV64I-POOL-LABEL: imm64_same_lo_hi_negative:
+; RV64I-POOL:       # %bb.0:
+; RV64I-POOL-NEXT:    lui a0, %hi(.LCPI65_0)
+; RV64I-POOL-NEXT:    ld a0, %lo(.LCPI65_0)(a0)
+; RV64I-POOL-NEXT:    ret
+;
+; RV64IZBA-LABEL: imm64_same_lo_hi_negative:
+; RV64IZBA:       # %bb.0:
+; RV64IZBA-NEXT:    lui a0, 526344
+; RV64IZBA-NEXT:    addiw a0, a0, 128
+; RV64IZBA-NEXT:    slli a1, a0, 32
+; RV64IZBA-NEXT:    add.uw a0, a0, a1
+; RV64IZBA-NEXT:    ret
+;
+; RV64IZBB-LABEL: imm64_same_lo_hi_negative:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 983297
+; RV64IZBB-NEXT:    slli a0, a0, 4
+; RV64IZBB-NEXT:    addi a0, a0, 257
+; RV64IZBB-NEXT:    slli a0, a0, 16
+; RV64IZBB-NEXT:    addi a0, a0, 257
+; RV64IZBB-NEXT:    slli a0, a0, 15
+; RV64IZBB-NEXT:    addi a0, a0, 128
+; RV64IZBB-NEXT:    ret
+;
+; RV64IZBS-LABEL: imm64_same_lo_hi_negative:
+; RV64IZBS:       # %bb.0:
+; RV64IZBS-NEXT:    lui a0, 983297
+; RV64IZBS-NEXT:    slli a0, a0, 4
+; RV64IZBS-NEXT:    addi a0, a0, 257
+; RV64IZBS-NEXT:    slli a0, a0, 16
+; RV64IZBS-NEXT:    addi a0, a0, 257
+; RV64IZBS-NEXT:    slli a0, a0, 15
+; RV64IZBS-NEXT:    addi a0, a0, 128
+; RV64IZBS-NEXT:    ret
+;
+; RV64IXTHEADBB-LABEL: imm64_same_lo_hi_negative:
+; RV64IXTHEADBB:       # %bb.0:
+; RV64IXTHEADBB-NEXT:    lui a0, 983297
+; RV64IXTHEADBB-NEXT:    slli a0, a0, 4
+; RV64IXTHEADBB-NEXT:    addi a0, a0, 257
+; RV64IXTHEADBB-NEXT:    slli a0, a0, 16
+; RV64IXTHEADBB-NEXT:    addi a0, a0, 257
+; RV64IXTHEADBB-NEXT:    slli a0, a0, 15
+; RV64IXTHEADBB-NEXT:    addi a0, a0, 128
+; RV64IXTHEADBB-NEXT:    ret
+  ret i64 9259542123273814144 ; 0x8080808080808080
+}