[llvm][aarch64] Add support for the MS qualifiers __ptr32, __ptr64, __sptr, __uptr

[a_vorobev]

Summary

This is backend patch for D158857 .
This patch is implementing backend support of zero and sign extension for the ptr32, ptr64, sptr, uptr pointers.
We inject at the time of creating read , write , and cast addressspace nodes and add sign or zero extension or truncation operations to the emitted DAG nodes, depending on the type of cast. The extension itself goes like this: first we perform the same operations that we would perform when doing ptrtoint, and then we attach the required node to the resulting node as a result of this operation. This is necessary due to the fact that in the arm64 architecture there is no such thing as a 32-bit pointer, and therefore we have to ... emulate it. Additionally, instrinfo.td has been modified to have a true zero extension instead of ORRWrs, and instrinfo.cpp to provide copy operations between a 32 bit pointer register and a 64 bit output register. Also changes made to DagCombiner to handle zero extensionsion and truncation

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
 
   // zext(undef) = 0
   if (N0.isUndef())
     return DAG.getConstant(0, DL, VT);
 
   if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
     return Res;
 
+  if (TLI.getTargetMachine().getTargetTriple().getArch() ==
+      llvm::Triple::aarch64) {
+    if (N0.getOpcode() == ISD::TRUNCATE) {
+
+      if (SDValue lowerLoad = reduceLoadWidth(N0.getNode())) {
+        SDNode *load = N0.getOperand(0).getNode();
+
+        if (lowerLoad.getNode() != N0.getNode()) {
+          CombineTo(N0.getNode(), lowerLoad);
+          AddToWorklist(load);
+        }
+      }
+      if (SDValue ExtLoad = CombineExtLoad(N))
+        return ExtLoad;
+      return SDValue(N, 0);
+    }
+  }
+  
+
   // fold (zext (zext x)) -> (zext x)
   // fold (zext (aext x)) -> (zext x)
   if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
     return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
 
   // fold (zext (aext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x)
   // fold (zext (zext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x)
   if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

else
     setValue(&I, N);            // noop cast.
 }
 
 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   const Value *SV = I.getOperand(0);
   SDValue N = getValue(SV);
   EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
+  SDLoc Dl = getCurSDLoc();
 
   unsigned SrcAS = SV->getType()->getPointerAddressSpace();
   unsigned DestAS = I.getType()->getPointerAddressSpace();
 
   if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS))
-    N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
+    N = DAG.getAddrSpaceCast(Dl, DestVT, N, SrcAS, DestAS);
 
   setValue(&I, N);
 }
 
 void SelectionDAGBuilder::visitInsertElement(const User &I) {
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   SDValue InVec = getValue(I.getOperand(0));
   SDValue InVal = getValue(I.getOperand(1));
void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
 
   SDLoc dl = getCurSDLoc();
 
   if (isVolatile)
     Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
 
   SmallVector<SDValue, 4> Values(NumValues);
   SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
+  EVT PtrVT = Ptr.getValueType();
+
+
+  if (TLI.getTargetMachine().getTargetTriple().getArch() ==
+      llvm::Triple::aarch64) {
+    unsigned SrcAS = SV->getType()->getPointerAddressSpace();
+    if ((SrcAS == 270) || (SrcAS == 271)) {
+      MVT DVT = MVT::i32;
+      MVT DestVT = MVT::i64;
+
+      Ptr = DAG.getPtrExtOrTrunc(Ptr, dl, DVT);
+      Ptr = DAG.getZExtOrTrunc(Ptr, dl, DVT);
+      if (SrcAS == 270) {
+        Ptr = DAG.getNode(ISD::SIGN_EXTEND, dl, DestVT, Ptr,
+                          DAG.getTargetConstant(0, dl, DestVT));
+      } else if (SrcAS == 271) {
+        Ptr = DAG.getNode(ISD::ZERO_EXTEND, dl, DestVT, Ptr,
+                          DAG.getTargetConstant(0, dl, DestVT));
+      }
+    }
+  }
+
 
   unsigned ChainI = 0;
   for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
     // Serializing loads here may result in excessive register pressure, and
     // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
     // could recover a bit by hoisting nodes upward in the chain by recognizing
     // they are side-effect free or do not alias. The optimizer should really
     // avoid this case by converting large object/array copies to llvm.memcpy
if (NumValues == 0)
     return;
 
   // Get the lowered operands. Note that we do this after
   // checking if NumResults is zero, because with zero results
   // the operands won't have values in the map.
   SDValue Src = getValue(SrcV);
   SDValue Ptr = getValue(PtrV);
 
+  SDLoc dl = getCurSDLoc();
+  if (TLI.getTargetMachine().getTargetTriple().getArch() ==
+      llvm::Triple::aarch64) {
+    unsigned SrcAS = PtrV->getType()->getPointerAddressSpace();
+    if ((SrcAS == 270) || (SrcAS == 271)) {
+      MVT DVT = MVT::i32;
+      MVT DestVT = MVT::i64;
+
+      Ptr = DAG.getPtrExtOrTrunc(Ptr, dl, DVT);
+      Ptr = DAG.getZExtOrTrunc(Ptr, dl, DVT);
+      if (SrcAS == 270) {
+        Ptr = DAG.getNode(ISD::SIGN_EXTEND, dl, DestVT, Ptr,
+                          DAG.getTargetConstant(0, dl, DestVT));
+      } else if (SrcAS == 271) {
+        Ptr = DAG.getNode(ISD::ZERO_EXTEND, dl, DestVT, Ptr,
+                          DAG.getTargetConstant(0, dl, DestVT));
+      }
+    }
+  }
+
+
   SDValue Root = I.isVolatile() ? getRoot() : getMemoryRoot();
   SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
-  SDLoc dl = getCurSDLoc();
   Align Alignment = I.getAlign();
   AAMDNodes AAInfo = I.getAAMetadata();
 
   auto MMOFlags = TLI.getStoreMemOperandFlags(I, DAG.getDataLayout());
 
   unsigned ChainI = 0;
   for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
     // See visitLoad comments.

llvm/lib/Target/AArch64/AArch64.h

 void initializeAArch64StackTaggingPass(PassRegistry &);
 void initializeAArch64StackTaggingPreRAPass(PassRegistry &);
 void initializeAArch64StorePairSuppressPass(PassRegistry&);
 void initializeFalkorHWPFFixPass(PassRegistry&);
 void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry&);
 void initializeLDTLSCleanupPass(PassRegistry&);
 void initializeSMEABIPass(PassRegistry &);
 void initializeSVEIntrinsicOptsPass(PassRegistry &);
+namespace ARM64AS {
+enum : unsigned { PTR32_SPTR = 270, PTR32_UPTR = 271, PTR64 = 272 };
+}
+
 } // end namespace llvm
 
 #endif

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
 
   setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
 
   // Custom lowering hooks are needed for XOR
   // to fold it into CSINC/CSINV.
   setOperationAction(ISD::XOR, MVT::i32, Custom);
   setOperationAction(ISD::XOR, MVT::i64, Custom);
 
+  setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
+  setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
+
   // Virtually no operation on f128 is legal, but LLVM can't expand them when
   // there's a valid register class, so we need custom operations in most cases.
   setOperationAction(ISD::FABS, MVT::f128, Expand);
   setOperationAction(ISD::FADD, MVT::f128, LibCall);
   setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
   setOperationAction(ISD::FCOS, MVT::f128, Expand);
   setOperationAction(ISD::FDIV, MVT::f128, LibCall);
   setOperationAction(ISD::FMA, MVT::f128, Expand);
static SDValue LowerTruncateVectorStore(SDLoc DL, StoreSDNode *ST,
   Trunc = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Trunc);
   SDValue ExtractTrunc = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
                                      Trunc, DAG.getConstant(0, DL, MVT::i64));
 
   return DAG.getStore(ST->getChain(), DL, ExtractTrunc,
                       ST->getBasePtr(), ST->getMemOperand());
 }
 
+static SDValue LowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) {
+  SDLoc dl(Op);
+  SDValue Src = Op.getOperand(0);
+  MVT DestVT = Op.getSimpleValueType();
+  AddrSpaceCastSDNode *N = cast<AddrSpaceCastSDNode>(Op.getNode());
+  unsigned SrcAS = N->getSrcAddressSpace();
+  unsigned DestAS = N->getDestAddressSpace();
+
+  assert(SrcAS != DestAS &&
+         "addrspacecast must be between different address spaces");
+
+  EVT LowerVT = MVT::i32;
+
+  if ((SrcAS == ARM64AS::PTR32_SPTR || SrcAS == ARM64AS::PTR32_UPTR) ||
+      (DestAS == ARM64AS::PTR32_SPTR || DestAS == ARM64AS::PTR32_UPTR)) {
+    Src = DAG.getPtrExtOrTrunc(Src, dl, LowerVT);
+    Src = DAG.getZExtOrTrunc(Src, dl, LowerVT);
+
+    if (SrcAS == ARM64AS::PTR32_SPTR) {
+      return DAG.getNode(ISD::SIGN_EXTEND, dl, DestVT, Src,
+                         DAG.getTargetConstant(0, dl, DestVT));
+    } else if (SrcAS == ARM64AS::PTR32_UPTR) {
+      return DAG.getNode(ISD::ZERO_EXTEND, dl, DestVT, Src, DAG.getTargetConstant(0, dl, DestVT));
+    } else if ((DestAS == ARM64AS::PTR32_SPTR) ||
+               (DestAS == ARM64AS::PTR32_UPTR)) {         
+       SDValue Ext = DAG.getAnyExtOrTrunc(Src.getOperand(0), dl, DestVT);
+       SDValue Trunc = DAG.getZeroExtendInReg(Ext, dl, LowerVT);
+       return Trunc;
+
+    }
+  }
+  return Op;
+}
+
+
 // Custom lowering for any store, vector or scalar and/or default or with
 // a truncate operations.  Currently only custom lower truncate operation
 // from vector v4i16 to v4i8 or volatile stores of i128.
 SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
                                           SelectionDAG &DAG) const {
   SDLoc Dl(Op);
   StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
   assert (StoreNode && "Can only custom lower store nodes");
SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
   case ISD::DYNAMIC_STACKALLOC:
     return LowerDYNAMIC_STACKALLOC(Op, DAG);
   case ISD::VSCALE:
     return LowerVSCALE(Op, DAG);
   case ISD::ANY_EXTEND:
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND:
     return LowerFixedLengthVectorIntExtendToSVE(Op, DAG);
+  case ISD::ADDRSPACECAST:
+    return LowerADDRSPACECAST(Op, DAG);  
   case ISD::SIGN_EXTEND_INREG: {
     // Only custom lower when ExtraVT has a legal byte based element type.
     EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
     EVT ExtraEltVT = ExtraVT.getVectorElementType();
     if ((ExtraEltVT != MVT::i8) && (ExtraEltVT != MVT::i16) &&
         (ExtraEltVT != MVT::i32) && (ExtraEltVT != MVT::i64))
       return SDValue();
 
void AArch64TargetLowering::ReplaceNodeResults(
   case ISD::ATOMIC_LOAD_OR:
   case ISD::ATOMIC_SWAP: {
     assert(cast<AtomicSDNode>(N)->getVal().getValueType() == MVT::i128 &&
            "Expected 128-bit atomicrmw.");
     // These need custom type legalisation so we go directly to instruction.
     ReplaceATOMIC_LOAD_128Results(N, Results, DAG, Subtarget);
     return;
   }
+  case ISD::ADDRSPACECAST: {
+    SDValue V = LowerADDRSPACECAST(SDValue(N,0), DAG);
+    Results.push_back(V);
+    return;
+  }
   case ISD::ATOMIC_LOAD:
   case ISD::LOAD: {
     MemSDNode *LoadNode = cast<MemSDNode>(N);
     EVT MemVT = LoadNode->getMemoryVT();
     // Handle lowering 256 bit non temporal loads into LDNP for little-endian
     // targets.
     if (LoadNode->isNonTemporal() && Subtarget->isLittleEndian() &&
         MemVT.getSizeInBits() == 256u &&

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   if (SrcReg == AArch64::NZCV) {
     assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
     BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg)
         .addImm(AArch64SysReg::NZCV)
         .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
     return;
   }
 
+  if (AArch64::GPR32RegClass.contains(DestReg) &&
+      AArch64::GPR64RegClass.contains(SrcReg)) {
+    const TargetRegisterInfo *TRI = &getRegisterInfo();
+    MCRegister DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
+                                                   &AArch64::GPR64spRegClass);
+    BuildMI(MBB, I, DL, get(AArch64::UBFMXri), DestRegX)
+        .addReg(SrcReg, getKillRegState(KillSrc))
+        .addImm(0)
+        .addImm(31);
+    return;
+  }
+
 #ifndef NDEBUG
   const TargetRegisterInfo &TRI = getRegisterInfo();
   errs() << TRI.getRegAsmName(DestReg) << " = COPY "
          << TRI.getRegAsmName(SrcReg) << "\n";
 #endif
   llvm_unreachable("unimplemented reg-to-reg copy");
 }
 

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 //----------------------------------------------------------------------------
 // FIXME: Like for X86, these should go in their own separate .td file.
 
 // For an anyext, we don't care what the high bits are, so we can perform an
 // INSERT_SUBREF into an IMPLICIT_DEF.
 def : Pat<(i64 (anyext GPR32:$src)),
           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
 
-// When we need to explicitly zero-extend, we use a 32-bit MOV instruction and
-// then assert the extension has happened.
+// When we need to explicitly zero-extend, we use an unsigned bitfield move
+// instruction (UBFM) on the enclosing super-reg.
 def : Pat<(i64 (zext GPR32:$src)),
-          (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>;
+   (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
 
 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
 // containing super-reg.
 def : Pat<(i64 (sext GPR32:$src)),
    (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
 def : Pat<(i64 (sext_inreg GPR64:$src, i8)),  (SBFMXri GPR64:$src, 0, 7)>;

llvm/lib/Target/AArch64/AArch64TargetMachine.h

public:
   convertFuncInfoToYAML(const MachineFunction &MF) const override;
   bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
                                 PerFunctionMIParsingState &PFS,
                                 SMDiagnostic &Error,
                                 SMRange &SourceRange) const override;
 
   /// Returns true if a cast between SrcAS and DestAS is a noop.
   bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
-    // Addrspacecasts are always noops.
+    if (getPointerSize(SrcAS) != getPointerSize(DestAS))
+      return false;
     return true;
   }
 
 private:
   bool isLittle;
 };
 
 // AArch64 little endian target machine.

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
       case 15:
         if (IsSigned)
           AsmMnemonic = "sxth";
         else if (!Is64Bit)
           AsmMnemonic = "uxth";
         break;
       case 31:
         // *xtw is only valid for signed 64-bit operations.
-        if (Is64Bit && IsSigned)
+        if (Is64Bit) {
+          if (IsSigned) {
             AsmMnemonic = "sxtw";
+          } else {
+            AsmMnemonic = "uxtw";
+          }
+        }
         break;
       }
 
       if (AsmMnemonic) {
         O << '\t' << AsmMnemonic << '\t';
         printRegName(O, Op0.getReg());
         O << ", ";
         printRegName(O, getWRegFromXReg(Op1.getReg()));

llvm/test/CodeGen/AArch64/aarch64-mixed-ptr-sizes.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s --check-prefixes=ALL,CHECK
+
+; Source to regenerate:
+; struct Foo {
+;   int * __ptr32 p32;
+;   int * __ptr64 p64;
+;   __attribute__((address_space(9))) int *p_other;
+; };
+; void use_foo(Foo *f);
+; void test_sign_ext(Foo *f, int * __ptr32 __sptr i) {
+;   f->p64 = i;
+;   use_foo(f);
+; }
+; void test_zero_ext(Foo *f, int * __ptr32 __uptr i) {
+;   f->p64 = i;
+;   use_foo(f);
+; }
+; void test_trunc(Foo *f, int * __ptr64 i) {
+;   f->p32 = i;
+;   use_foo(f);
+; }
+; void test_noop1(Foo *f, int * __ptr32 i) {
+;   f->p32 = i;
+;   use_foo(f);
+; }
+; void test_noop2(Foo *f, int * __ptr64 i) {
+;   f->p64 = i;
+;   use_foo(f);
+; }
+; void test_null_arg(Foo *f, int * __ptr32 i) {
+;   test_noop1(f, 0);
+; }
+; void test_unrecognized(Foo *f, __attribute__((address_space(14))) int *i) {
+;   f->p32 = (int * __ptr32)i;
+;   use_foo(f);
+; }
+;
+; $ clang -cc1 -triple x86_64-windows-msvc -fms-extensions -O2 -S t.cpp
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+%struct.Foo = type { ptr addrspace(270), ptr, ptr addrspace(9) }
+declare dso_local void @use_foo(ptr)
+
+define dso_local void @test_sign_ext(ptr %f, ptr addrspace(270) %i) {
+; ALL-LABEL: test_sign_ext:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    sxtw x8, w1
+; ALL-NEXT:    str  x8, [x0, #8]
+; ALL-NEXT:    b  use_foo # TAILCALL
+entry:
+  %0 = addrspacecast ptr addrspace(270) %i to ptr
+  %p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
+  store ptr %0, ptr %p64, align 8
+  tail call void @use_foo(ptr %f)
+  ret void
+}
+
+define dso_local void @test_zero_ext(ptr %f, ptr addrspace(271) %i) {
+; CHECK-LABEL: test_zero_ext:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    uxtw x8, w1
+; CHECK-NEXT:    str  x8, [x0, #8]
+; CHECK-NEXT:    b  use_foo # TAILCALL
+entry:
+  %0 = addrspacecast ptr addrspace(271) %i to ptr
+  %p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
+  store ptr %0, ptr %p64, align 8
+  tail call void @use_foo(ptr %f)
+  ret void
+}
+
+define dso_local void @test_trunc(ptr %f, ptr %i) {
+; CHECK-LABEL: test_trunc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    str  w1, [x0]
+; CHECK-NEXT:    b  use_foo # TAILCALL
+entry:
+  %0 = addrspacecast ptr %i to ptr addrspace(270)
+  store ptr addrspace(270) %0, ptr %f, align 8
+  tail call void @use_foo(ptr %f)
+  ret void
+}
+
+define dso_local void @test_noop1(ptr %f, ptr addrspace(270) %i) {
+; ALL-LABEL: test_noop1:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    str  w1, [x0]
+; ALL-NEXT:    b  use_foo # TAILCALL
+entry:
+  store ptr addrspace(270) %i, ptr %f, align 8
+  tail call void @use_foo(ptr %f)
+  ret void
+}
+
+define dso_local void @test_noop2(ptr %f, ptr %i) {
+; ALL-LABEL: test_noop2:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    str  x1, [x0, #8]
+; ALL-NEXT:    b  use_foo # TAILCALL
+entry:
+  %p64 = getelementptr inbounds %struct.Foo, ptr %f, i64 0, i32 1
+  store ptr %i, ptr %p64, align 8
+  tail call void @use_foo(ptr %f)
+  ret void
+}
+
+; Test that null can be passed as a 32-bit pointer.
+define dso_local void @test_null_arg(ptr %f) {
+; ALL-LABEL: test_null_arg:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    str  wzr, [x0]
+; ALL-NEXT:    b  use_foo
+entry:
+  call void @test_noop1(ptr %f, ptr addrspace(270) null)
+  ret void
+}
+
+; Test casts between unrecognized address spaces.
+define void @test_unrecognized(ptr %f, ptr addrspace(14) %i) {
+; CHECK-LABEL: test_unrecognized:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    str   w1, [x0]
+; CHECK-NEXT:    b  use_foo # TAILCALL
+entry:
+  %0 = addrspacecast ptr addrspace(14) %i to ptr addrspace(270)
+  store ptr addrspace(270) %0, ptr %f, align 8
+  tail call void @use_foo(ptr %f)
+  ret void
+}
+