This is the first full integration with the mainline LLVM Repo. This will be (shortly) broken into smaller commits which focus on individual parts for review. The components roughly break down as:
- Deltas to Target library code: ~1000
- Deltas to CodeGen and MC libraries: ~2800
- New utilities: ~20000
- Documentation: ~5000
The MDL language provides an alternate way (from TableGen) to describe a target micro-architecture (ie an alternative to Schedules and Itineraries) to the CodeGen and MC libraries. It provides all the capability of Tablegen Schedules and Itineraries, but can efficiently describe much more complex processors.
You can find the RFC with more detailed descriptions of this work at discourse.llvm.org/t/rfc-mdl-a-micro-architecture-description-language-for-llvm (from Nov 2022). Detailed documentation about the design and the MDL language (and the RFC) can be found in
the repo at llvm/docs/Mdl/.
This is the first integration of work that we plan to expand going forward, and we'd like to land this to avoid bitrot and make the work
available to others. This integration is fully integrated - it can extract microarchitecture information from TableGen, create equivalent
MDL descriptions, and compile and use that information in CodeGen and MC libraries. This works for any target that has Schedules or Itineraries (AArch64, AMDGPU, AMDGPU/R600, ARM, Hexagon, Lanai, Mips, PowerPC, RISCV,
Sparc, SystemZ, and X86).
MDL support is enabled using the LLVM_ENABLE_MDL cmake parameter. When enabled, we build the MDL compiler and a tool to scrape necessary information from tablegen files, then use this information in backend libraries instead of using TableGen generated information. When not enabled (the default), all the MDL-specific code is guarded by runtime flags that disable it.
We welcome comments and suggestions, and look forward to your feedback.