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Differential D158625

[RISCV] Use vmv.v.x if Hi bits are undef when lowering splat_vector_parts
ClosedPublic

Authored by luke on Aug 23 2023, 8:22 AM.

Details

Reviewers
craig.topper
reames
frasercrmck
Commits
rGe772c0ecd814: [RISCV] Use vmv.v.x if Hi bits are undef when lowering splat_vector_parts
Summary

When lowering a splat_vector_parts, if the hi bits are undefined then we can
splat the lo bits without having to check if it's going to be sign extended or
not, because those bits will be undefined anyway.

I've handled it for both fixed and scalable vectors, but there's no diff
on the scalable vror tests, since the hi bits aren't combined away to
undef in SimplifyDemanded for scalable vectors. I'm not sure why that is.

Diff Detail

Event Timeline

luke created this revision.Aug 23 2023, 8:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2023, 8:22 AM
Herald added subscribers: jobnoorman, asb, sunshaoce and 28 others. · View Herald Transcript
luke requested review of this revision.Aug 23 2023, 8:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2023, 8:22 AM
Herald added subscribers: llvm-commits, wangpc, alextsao1999 and 2 others. · View Herald Transcript
Harbormaster completed remote builds in B254352: Diff 552724.Aug 23 2023, 9:24 AM
luke mentioned this in D158634: [RISCV] Fix wrong operand being used for VL in shift combine.Aug 23 2023, 9:34 AM
craig.topper accepted this revision.Aug 23 2023, 9:55 AM
This revision is now accepted and ready to land.Aug 23 2023, 9:55 AM
Closed by commit rGe772c0ecd814: [RISCV] Use vmv.v.x if Hi bits are undef when lowering splat_vector_parts (authored by luke). · Explain WhyAug 24 2023, 4:19 AM
This revision was automatically updated to reflect the committed changes.
luke added a commit: rGe772c0ecd814: [RISCV] Use vmv.v.x if Hi bits are undef when lowering splat_vector_parts.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
10 lines
test/
CodeGen/
RISCV/
rvv/
191 lines
191 lines

Diff 552724

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,498 Lines • ▼ Show 20 Lines if (LoC == HiC && isAllOnesConstant(VL)) {
// TODO: if vl <= min(VLMAX), we can also do this. But we could not // TODO: if vl <= min(VLMAX), we can also do this. But we could not
// access the subtarget here now. // access the subtarget here now.
auto InterVec = DAG.getNode( auto InterVec = DAG.getNode(
RISCVISD::VMV_V_X_VL, DL, InterVT, DAG.getUNDEF(InterVT), Lo, RISCVISD::VMV_V_X_VL, DL, InterVT, DAG.getUNDEF(InterVT), Lo,
DAG.getRegister(RISCV::X0, MVT::i32)); DAG.getRegister(RISCV::X0, MVT::i32));
return DAG.getNode(ISD::BITCAST, DL, VT, InterVec); return DAG.getNode(ISD::BITCAST, DL, VT, InterVec);
} }
} }
// If the hi bits of the splat are undefined, then it's fine to just splat Lo
// even if it might be sign extended.
if (Hi.isUndef())
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Lo, VL);
// Fall back to a stack store and stride x0 vector load. // Fall back to a stack store and stride x0 vector load.
return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VT, Passthru, Lo, return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VT, Passthru, Lo,
Hi, VL); Hi, VL);
} }
// Called by type legalization to handle splat of i64 on RV32. // Called by type legalization to handle splat of i64 on RV32.
// FIXME: We can optimize this when the type has sign or zero bits in one // FIXME: We can optimize this when the type has sign or zero bits in one
▲ Show 20 Lines • Show All 3,170 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op,
// Detect cases where Hi is (SRA Lo, 31) which means Hi is Lo sign extended. // Detect cases where Hi is (SRA Lo, 31) which means Hi is Lo sign extended.
if (Hi.getOpcode() == ISD::SRA && Hi.getOperand(0) == Lo && if (Hi.getOpcode() == ISD::SRA && Hi.getOperand(0) == Lo &&
isa<ConstantSDNode>(Hi.getOperand(1)) && isa<ConstantSDNode>(Hi.getOperand(1)) &&
Hi.getConstantOperandVal(1) == 31) Hi.getConstantOperandVal(1) == 31)
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT), Lo, return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT), Lo,
DAG.getRegister(RISCV::X0, MVT::i32)); DAG.getRegister(RISCV::X0, MVT::i32));
// If the hi bits of the splat are undefined, then it's fine to just splat Lo
// even if it might be sign extended.
if (Hi.isUndef())
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VecVT, DAG.getUNDEF(VecVT), Lo,
DAG.getRegister(RISCV::X0, MVT::i32));
// Fall back to use a stack store and stride x0 vector load. Use X0 as VL. // Fall back to use a stack store and stride x0 vector load. Use X0 as VL.
return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VecVT, return DAG.getNode(RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, DL, VecVT,
DAG.getUNDEF(VecVT), Lo, Hi, DAG.getUNDEF(VecVT), Lo, Hi,
DAG.getRegister(RISCV::X0, MVT::i32)); DAG.getRegister(RISCV::X0, MVT::i32));
} }
// Custom-lower extensions from mask vectors by using a vselect either with 1 // Custom-lower extensions from mask vectors by using a vselect either with 1
// for zero/any-extension or -1 for sign-extension: // for zero/any-extension or -1 for sign-extension:
▲ Show 20 Lines • Show All 11,235 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll

Show First 20 Lines • Show All 910 Lines • ▼ Show 20 Lines
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b) %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b)
ret <1 x i64> %x ret <1 x i64> %x
} }
define <1 x i64> @vrol_vx_v1i64(<1 x i64> %a, i64 %b) { define <1 x i64> @vrol_vx_v1i64(<1 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vrol_vx_v1i64: ; CHECK-RV32-LABEL: vrol_vx_v1i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a0, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero
; CHECK-RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v10, 0 ; CHECK-RV32-NEXT: vmv.v.i v9, 0
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsub.vv v11, v10, v9 ; CHECK-RV32-NEXT: vsub.vx v10, v9, a0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a1, 63
; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, ma ; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, ma
; CHECK-RV32-NEXT: vmv.s.x v10, a0 ; CHECK-RV32-NEXT: vmv.s.x v9, a1
; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-RV32-NEXT: vand.vv v11, v11, v10 ; CHECK-RV32-NEXT: vand.vv v10, v10, v9
; CHECK-RV32-NEXT: vsrl.vv v11, v8, v11 ; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10
; CHECK-RV32-NEXT: vand.vv v9, v9, v10 ; CHECK-RV32-NEXT: vand.vx v9, v9, a0
; CHECK-RV32-NEXT: vsll.vv v8, v8, v9 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v9
; CHECK-RV32-NEXT: vor.vv v8, v8, v11 ; CHECK-RV32-NEXT: vor.vv v8, v8, v10
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vrol_vx_v1i64: ; CHECK-RV64-LABEL: vrol_vx_v1i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v9, a0 ; CHECK-RV64-NEXT: vmv.v.x v9, a0
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vand.vx v10, v9, a0 ; CHECK-RV64-NEXT: vand.vx v10, v9, a0
; CHECK-RV64-NEXT: vsll.vv v10, v8, v10 ; CHECK-RV64-NEXT: vsll.vv v10, v8, v10
; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0 ; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0
; CHECK-RV64-NEXT: vand.vx v9, v9, a0 ; CHECK-RV64-NEXT: vand.vx v9, v9, a0
; CHECK-RV64-NEXT: vsrl.vv v8, v8, v9 ; CHECK-RV64-NEXT: vsrl.vv v8, v8, v9
; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: vor.vv v8, v10, v8
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vrol_vx_v1i64: ; CHECK-ZVBB-LABEL: vrol_vx_v1i64:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB32-NEXT: sw a0, 12(sp) ; CHECK-ZVBB-NEXT: ret
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v9, (a0), zero
; CHECK-ZVBB32-NEXT: vrol.vv v8, v8, v9
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vrol_vx_v1i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-ZVBB64-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
%b.head = insertelement <1 x i64> poison, i64 %b, i32 0 %b.head = insertelement <1 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer
%x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat) %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat)
ret <1 x i64> %x ret <1 x i64> %x
} }
declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
Show All 32 Lines
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b) %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i64> @vrol_vx_v2i64(<2 x i64> %a, i64 %b) { define <2 x i64> @vrol_vx_v2i64(<2 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vrol_vx_v2i64: ; CHECK-RV32-LABEL: vrol_vx_v2i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a0, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero ; CHECK-RV32-NEXT: vmv.v.x v9, a0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a1, 63
; CHECK-RV32-NEXT: vand.vx v10, v9, a0 ; CHECK-RV32-NEXT: vand.vx v9, v9, a1
; CHECK-RV32-NEXT: vsll.vv v10, v8, v10 ; CHECK-RV32-NEXT: vsll.vv v9, v8, v9
; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v11, 0 ; CHECK-RV32-NEXT: vmv.v.i v10, 0
; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsub.vv v9, v11, v9 ; CHECK-RV32-NEXT: vsub.vx v10, v10, a0
; CHECK-RV32-NEXT: vand.vx v9, v9, a0 ; CHECK-RV32-NEXT: vand.vx v10, v10, a1
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v9 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
; CHECK-RV32-NEXT: vor.vv v8, v10, v8 ; CHECK-RV32-NEXT: vor.vv v8, v9, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vrol_vx_v2i64: ; CHECK-RV64-LABEL: vrol_vx_v2i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v9, a0 ; CHECK-RV64-NEXT: vmv.v.x v9, a0
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vand.vx v10, v9, a0 ; CHECK-RV64-NEXT: vand.vx v10, v9, a0
; CHECK-RV64-NEXT: vsll.vv v10, v8, v10 ; CHECK-RV64-NEXT: vsll.vv v10, v8, v10
; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0 ; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0
; CHECK-RV64-NEXT: vand.vx v9, v9, a0 ; CHECK-RV64-NEXT: vand.vx v9, v9, a0
; CHECK-RV64-NEXT: vsrl.vv v8, v8, v9 ; CHECK-RV64-NEXT: vsrl.vv v8, v8, v9
; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: vor.vv v8, v10, v8
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vrol_vx_v2i64: ; CHECK-ZVBB-LABEL: vrol_vx_v2i64:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB32-NEXT: sw a0, 12(sp) ; CHECK-ZVBB-NEXT: ret
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v9, (a0), zero
; CHECK-ZVBB32-NEXT: vrol.vv v8, v8, v9
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vrol_vx_v2i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-ZVBB64-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
%b.head = insertelement <2 x i64> poison, i64 %b, i32 0 %b.head = insertelement <2 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer %b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer
%x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat) %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat)
ret <2 x i64> %x ret <2 x i64> %x
} }
declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>) declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
Show All 32 Lines
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b) %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %x ret <4 x i64> %x
} }
define <4 x i64> @vrol_vx_v4i64(<4 x i64> %a, i64 %b) { define <4 x i64> @vrol_vx_v4i64(<4 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vrol_vx_v4i64: ; CHECK-RV32-LABEL: vrol_vx_v4i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a0, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero ; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a1, 63
; CHECK-RV32-NEXT: vand.vx v12, v10, a0 ; CHECK-RV32-NEXT: vand.vx v10, v10, a1
; CHECK-RV32-NEXT: vsll.vv v12, v8, v12 ; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v14, 0 ; CHECK-RV32-NEXT: vmv.v.i v12, 0
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vsub.vv v10, v14, v10 ; CHECK-RV32-NEXT: vsub.vx v12, v12, a0
; CHECK-RV32-NEXT: vand.vx v10, v10, a0 ; CHECK-RV32-NEXT: vand.vx v12, v12, a1
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12
; CHECK-RV32-NEXT: vor.vv v8, v12, v8 ; CHECK-RV32-NEXT: vor.vv v8, v10, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vrol_vx_v4i64: ; CHECK-RV64-LABEL: vrol_vx_v4i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v10, a0 ; CHECK-RV64-NEXT: vmv.v.x v10, a0
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vand.vx v12, v10, a0 ; CHECK-RV64-NEXT: vand.vx v12, v10, a0
; CHECK-RV64-NEXT: vsll.vv v12, v8, v12 ; CHECK-RV64-NEXT: vsll.vv v12, v8, v12
; CHECK-RV64-NEXT: vrsub.vi v10, v10, 0 ; CHECK-RV64-NEXT: vrsub.vi v10, v10, 0
; CHECK-RV64-NEXT: vand.vx v10, v10, a0 ; CHECK-RV64-NEXT: vand.vx v10, v10, a0
; CHECK-RV64-NEXT: vsrl.vv v8, v8, v10 ; CHECK-RV64-NEXT: vsrl.vv v8, v8, v10
; CHECK-RV64-NEXT: vor.vv v8, v12, v8 ; CHECK-RV64-NEXT: vor.vv v8, v12, v8
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vrol_vx_v4i64: ; CHECK-ZVBB-LABEL: vrol_vx_v4i64:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB32-NEXT: sw a0, 12(sp) ; CHECK-ZVBB-NEXT: ret
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v10, (a0), zero
; CHECK-ZVBB32-NEXT: vrol.vv v8, v8, v10
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vrol_vx_v4i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB64-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
%b.head = insertelement <4 x i64> poison, i64 %b, i32 0 %b.head = insertelement <4 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer %b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer
%x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat) %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat)
ret <4 x i64> %x ret <4 x i64> %x
} }
declare <8 x i64> @llvm.fshl.v8i64(<8 x i64>, <8 x i64>, <8 x i64>) declare <8 x i64> @llvm.fshl.v8i64(<8 x i64>, <8 x i64>, <8 x i64>)
Show All 32 Lines
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b) %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b)
ret <8 x i64> %x ret <8 x i64> %x
} }
define <8 x i64> @vrol_vx_v8i64(<8 x i64> %a, i64 %b) { define <8 x i64> @vrol_vx_v8i64(<8 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vrol_vx_v8i64: ; CHECK-RV32-LABEL: vrol_vx_v8i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a0, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero ; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a1, 63
; CHECK-RV32-NEXT: vand.vx v16, v12, a0 ; CHECK-RV32-NEXT: vand.vx v12, v12, a1
; CHECK-RV32-NEXT: vsll.vv v16, v8, v16 ; CHECK-RV32-NEXT: vsll.vv v12, v8, v12
; CHECK-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v20, 0 ; CHECK-RV32-NEXT: vmv.v.i v16, 0
; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vsub.vv v12, v20, v12 ; CHECK-RV32-NEXT: vsub.vx v16, v16, a0
; CHECK-RV32-NEXT: vand.vx v12, v12, a0 ; CHECK-RV32-NEXT: vand.vx v16, v16, a1
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v16
; CHECK-RV32-NEXT: vor.vv v8, v16, v8 ; CHECK-RV32-NEXT: vor.vv v8, v12, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vrol_vx_v8i64: ; CHECK-RV64-LABEL: vrol_vx_v8i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v12, a0 ; CHECK-RV64-NEXT: vmv.v.x v12, a0
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vand.vx v16, v12, a0 ; CHECK-RV64-NEXT: vand.vx v16, v12, a0
; CHECK-RV64-NEXT: vsll.vv v16, v8, v16 ; CHECK-RV64-NEXT: vsll.vv v16, v8, v16
; CHECK-RV64-NEXT: vrsub.vi v12, v12, 0 ; CHECK-RV64-NEXT: vrsub.vi v12, v12, 0
; CHECK-RV64-NEXT: vand.vx v12, v12, a0 ; CHECK-RV64-NEXT: vand.vx v12, v12, a0
; CHECK-RV64-NEXT: vsrl.vv v8, v8, v12 ; CHECK-RV64-NEXT: vsrl.vv v8, v8, v12
; CHECK-RV64-NEXT: vor.vv v8, v16, v8 ; CHECK-RV64-NEXT: vor.vv v8, v16, v8
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vrol_vx_v8i64: ; CHECK-ZVBB-LABEL: vrol_vx_v8i64:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB32-NEXT: sw a0, 12(sp) ; CHECK-ZVBB-NEXT: ret
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v12, (a0), zero
; CHECK-ZVBB32-NEXT: vrol.vv v8, v8, v12
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vrol_vx_v8i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-ZVBB64-NEXT: vrol.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
%b.head = insertelement <8 x i64> poison, i64 %b, i32 0 %b.head = insertelement <8 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer
%x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat) %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat)
ret <8 x i64> %x ret <8 x i64> %x
} }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-ZVBB32: {{.*}}
; CHECK-ZVBB64: {{.*}}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll

Show First 20 Lines • Show All 1,589 Lines • ▼ Show 20 Lines
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b) %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b)
ret <1 x i64> %x ret <1 x i64> %x
} }
define <1 x i64> @vror_vx_v1i64(<1 x i64> %a, i64 %b) { define <1 x i64> @vror_vx_v1i64(<1 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vror_vx_v1i64: ; CHECK-RV32-LABEL: vror_vx_v1i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a0, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero
; CHECK-RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v10, 0 ; CHECK-RV32-NEXT: vmv.v.i v9, 0
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsub.vv v11, v10, v9 ; CHECK-RV32-NEXT: vsub.vx v10, v9, a0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a1, 63
; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, ma ; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, ma
; CHECK-RV32-NEXT: vmv.s.x v10, a0 ; CHECK-RV32-NEXT: vmv.s.x v9, a1
; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-RV32-NEXT: vand.vv v11, v11, v10 ; CHECK-RV32-NEXT: vand.vv v10, v10, v9
; CHECK-RV32-NEXT: vsll.vv v11, v8, v11 ; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
; CHECK-RV32-NEXT: vand.vv v9, v9, v10 ; CHECK-RV32-NEXT: vand.vx v9, v9, a0
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v9 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v9
; CHECK-RV32-NEXT: vor.vv v8, v8, v11 ; CHECK-RV32-NEXT: vor.vv v8, v8, v10
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vx_v1i64: ; CHECK-RV64-LABEL: vror_vx_v1i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v9, a0 ; CHECK-RV64-NEXT: vmv.v.x v9, a0
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vand.vx v10, v9, a0 ; CHECK-RV64-NEXT: vand.vx v10, v9, a0
; CHECK-RV64-NEXT: vsrl.vv v10, v8, v10 ; CHECK-RV64-NEXT: vsrl.vv v10, v8, v10
; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0 ; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0
; CHECK-RV64-NEXT: vand.vx v9, v9, a0 ; CHECK-RV64-NEXT: vand.vx v9, v9, a0
; CHECK-RV64-NEXT: vsll.vv v8, v8, v9 ; CHECK-RV64-NEXT: vsll.vv v8, v8, v9
; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: vor.vv v8, v10, v8
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vror_vx_v1i64: ; CHECK-ZVBB-LABEL: vror_vx_v1i64:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0
; CHECK-ZVBB32-NEXT: sw a0, 12(sp) ; CHECK-ZVBB-NEXT: ret
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v9, (a0), zero
; CHECK-ZVBB32-NEXT: vror.vv v8, v8, v9
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vror_vx_v1i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-ZVBB64-NEXT: vror.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
%b.head = insertelement <1 x i64> poison, i64 %b, i32 0 %b.head = insertelement <1 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer
%x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat) %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat)
ret <1 x i64> %x ret <1 x i64> %x
} }
define <1 x i64> @vror_vi_v1i64(<1 x i64> %a) { define <1 x i64> @vror_vi_v1i64(<1 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v1i64: ; CHECK-RV32-LABEL: vror_vi_v1i64:
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; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b) %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i64> @vror_vx_v2i64(<2 x i64> %a, i64 %b) { define <2 x i64> @vror_vx_v2i64(<2 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vror_vx_v2i64: ; CHECK-RV32-LABEL: vror_vx_v2i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a0, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero ; CHECK-RV32-NEXT: vmv.v.x v9, a0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a1, 63
; CHECK-RV32-NEXT: vand.vx v10, v9, a0 ; CHECK-RV32-NEXT: vand.vx v9, v9, a1
; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10 ; CHECK-RV32-NEXT: vsrl.vv v9, v8, v9
; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v11, 0 ; CHECK-RV32-NEXT: vmv.v.i v10, 0
; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsub.vv v9, v11, v9 ; CHECK-RV32-NEXT: vsub.vx v10, v10, a0
; CHECK-RV32-NEXT: vand.vx v9, v9, a0 ; CHECK-RV32-NEXT: vand.vx v10, v10, a1
; CHECK-RV32-NEXT: vsll.vv v8, v8, v9 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v10
; CHECK-RV32-NEXT: vor.vv v8, v10, v8 ; CHECK-RV32-NEXT: vor.vv v8, v9, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vx_v2i64: ; CHECK-RV64-LABEL: vror_vx_v2i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v9, a0 ; CHECK-RV64-NEXT: vmv.v.x v9, a0
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vand.vx v10, v9, a0 ; CHECK-RV64-NEXT: vand.vx v10, v9, a0
; CHECK-RV64-NEXT: vsrl.vv v10, v8, v10 ; CHECK-RV64-NEXT: vsrl.vv v10, v8, v10
; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0 ; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0
; CHECK-RV64-NEXT: vand.vx v9, v9, a0 ; CHECK-RV64-NEXT: vand.vx v9, v9, a0
; CHECK-RV64-NEXT: vsll.vv v8, v8, v9 ; CHECK-RV64-NEXT: vsll.vv v8, v8, v9
; CHECK-RV64-NEXT: vor.vv v8, v10, v8 ; CHECK-RV64-NEXT: vor.vv v8, v10, v8
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vror_vx_v2i64: ; CHECK-ZVBB-LABEL: vror_vx_v2i64:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0
; CHECK-ZVBB32-NEXT: sw a0, 12(sp) ; CHECK-ZVBB-NEXT: ret
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v9, (a0), zero
; CHECK-ZVBB32-NEXT: vror.vv v8, v8, v9
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vror_vx_v2i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-ZVBB64-NEXT: vror.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
%b.head = insertelement <2 x i64> poison, i64 %b, i32 0 %b.head = insertelement <2 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer %b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer
%x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat) %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat)
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) { define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v2i64: ; CHECK-RV32-LABEL: vror_vi_v2i64:
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; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b) %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %x ret <4 x i64> %x
} }
define <4 x i64> @vror_vx_v4i64(<4 x i64> %a, i64 %b) { define <4 x i64> @vror_vx_v4i64(<4 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vror_vx_v4i64: ; CHECK-RV32-LABEL: vror_vx_v4i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a0, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero ; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a1, 63
; CHECK-RV32-NEXT: vand.vx v12, v10, a0 ; CHECK-RV32-NEXT: vand.vx v10, v10, a1
; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12 ; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10
; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v14, 0 ; CHECK-RV32-NEXT: vmv.v.i v12, 0
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vsub.vv v10, v14, v10 ; CHECK-RV32-NEXT: vsub.vx v12, v12, a0
; CHECK-RV32-NEXT: vand.vx v10, v10, a0 ; CHECK-RV32-NEXT: vand.vx v12, v12, a1
; CHECK-RV32-NEXT: vsll.vv v8, v8, v10 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v12
; CHECK-RV32-NEXT: vor.vv v8, v12, v8 ; CHECK-RV32-NEXT: vor.vv v8, v10, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vx_v4i64: ; CHECK-RV64-LABEL: vror_vx_v4i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v10, a0 ; CHECK-RV64-NEXT: vmv.v.x v10, a0
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vand.vx v12, v10, a0 ; CHECK-RV64-NEXT: vand.vx v12, v10, a0
; CHECK-RV64-NEXT: vsrl.vv v12, v8, v12 ; CHECK-RV64-NEXT: vsrl.vv v12, v8, v12
; CHECK-RV64-NEXT: vrsub.vi v10, v10, 0 ; CHECK-RV64-NEXT: vrsub.vi v10, v10, 0
; CHECK-RV64-NEXT: vand.vx v10, v10, a0 ; CHECK-RV64-NEXT: vand.vx v10, v10, a0
; CHECK-RV64-NEXT: vsll.vv v8, v8, v10 ; CHECK-RV64-NEXT: vsll.vv v8, v8, v10
; CHECK-RV64-NEXT: vor.vv v8, v12, v8 ; CHECK-RV64-NEXT: vor.vv v8, v12, v8
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vror_vx_v4i64: ; CHECK-ZVBB-LABEL: vror_vx_v4i64:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0
; CHECK-ZVBB32-NEXT: sw a0, 12(sp) ; CHECK-ZVBB-NEXT: ret
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v10, (a0), zero
; CHECK-ZVBB32-NEXT: vror.vv v8, v8, v10
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vror_vx_v4i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB64-NEXT: vror.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
%b.head = insertelement <4 x i64> poison, i64 %b, i32 0 %b.head = insertelement <4 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer %b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer
%x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat) %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat)
ret <4 x i64> %x ret <4 x i64> %x
} }
define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) { define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v4i64: ; CHECK-RV32-LABEL: vror_vi_v4i64:
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; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b) %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b)
ret <8 x i64> %x ret <8 x i64> %x
} }
define <8 x i64> @vror_vx_v8i64(<8 x i64> %a, i64 %b) { define <8 x i64> @vror_vx_v8i64(<8 x i64> %a, i64 %b) {
; CHECK-RV32-LABEL: vror_vx_v8i64: ; CHECK-RV32-LABEL: vror_vx_v8i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a0, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero ; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a1, 63
; CHECK-RV32-NEXT: vand.vx v16, v12, a0 ; CHECK-RV32-NEXT: vand.vx v12, v12, a1
; CHECK-RV32-NEXT: vsrl.vv v16, v8, v16 ; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12
; CHECK-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v20, 0 ; CHECK-RV32-NEXT: vmv.v.i v16, 0
; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vsub.vv v12, v20, v12 ; CHECK-RV32-NEXT: vsub.vx v16, v16, a0
; CHECK-RV32-NEXT: vand.vx v12, v12, a0 ; CHECK-RV32-NEXT: vand.vx v16, v16, a1
; CHECK-RV32-NEXT: vsll.vv v8, v8, v12 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v16
; CHECK-RV32-NEXT: vor.vv v8, v16, v8 ; CHECK-RV32-NEXT: vor.vv v8, v12, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vx_v8i64: ; CHECK-RV64-LABEL: vror_vx_v8i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v12, a0 ; CHECK-RV64-NEXT: vmv.v.x v12, a0
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vand.vx v16, v12, a0 ; CHECK-RV64-NEXT: vand.vx v16, v12, a0
; CHECK-RV64-NEXT: vsrl.vv v16, v8, v16 ; CHECK-RV64-NEXT: vsrl.vv v16, v8, v16
; CHECK-RV64-NEXT: vrsub.vi v12, v12, 0 ; CHECK-RV64-NEXT: vrsub.vi v12, v12, 0
; CHECK-RV64-NEXT: vand.vx v12, v12, a0 ; CHECK-RV64-NEXT: vand.vx v12, v12, a0
; CHECK-RV64-NEXT: vsll.vv v8, v8, v12 ; CHECK-RV64-NEXT: vsll.vv v8, v8, v12
; CHECK-RV64-NEXT: vor.vv v8, v16, v8 ; CHECK-RV64-NEXT: vor.vv v8, v16, v8
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vror_vx_v8i64: ; CHECK-ZVBB-LABEL: vror_vx_v8i64:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB-NEXT: vror.vx v8, v8, a0
; CHECK-ZVBB32-NEXT: sw a0, 12(sp) ; CHECK-ZVBB-NEXT: ret
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v12, (a0), zero
; CHECK-ZVBB32-NEXT: vror.vv v8, v8, v12
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vror_vx_v8i64:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-ZVBB64-NEXT: vror.vx v8, v8, a0
; CHECK-ZVBB64-NEXT: ret
%b.head = insertelement <8 x i64> poison, i64 %b, i32 0 %b.head = insertelement <8 x i64> poison, i64 %b, i32 0
%b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer
%x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat) %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat)
ret <8 x i64> %x ret <8 x i64> %x
} }
define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) { define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v8i64: ; CHECK-RV32-LABEL: vror_vi_v8i64:
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; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63 ; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> shufflevector(<8 x i64> insertelement(<8 x i64> poison, i64 1, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer)) %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> shufflevector(<8 x i64> insertelement(<8 x i64> poison, i64 1, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer))
ret <8 x i64> %x ret <8 x i64> %x
} }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-ZVBB32: {{.*}}
; CHECK-ZVBB64: {{.*}}