[RISCV] Add CSR RegisterClass and save/restore fcsr in interrupt

[wangpc]

Summary

We add a new RegisterClass to represent CSRs and modify
storeRegToStackSlot/loadRegFromStackSlot so that we can
save/restore these CSRs.

This is an alternative of D158396

[wangpc]

Fix wrong restore dst reg.

[wangpc]

Fix paste error.

[wangpc]

CSR restore should be ahead.

[Jim]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

379–380

If we put FCSR at first in CSR_XLEN_F32_Interrupt/CSR_XLEN_F64_Interrupt, is it still need to depend on save or restore to determinate the order of CSR inserted.

577

Typo. IsRestore.

[wangpc]

Fix typo.

[wangpc]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

379–380

Yes. We should save FCSR after saving t0 and restore it before restoring t0 since we are using t0 as a temporary register.

[wangpc]

Gentle ping. :-)

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

549

This seems tricky to me to hardcode a GPR in here. This makes the code only work in certain scenarios. Do other targets do anything like this?

[wangpc]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

549

This seems tricky to me to hardcode a GPR in here.

We just need a GPR to store the value of CSRs.

This makes the code only work in certain scenarios.

I don't get it. This code is only for saving CSRs.

Do other targets do anything like this?

No, I haven't find any target doing this.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

549

This seems tricky to me to hardcode a GPR in here.

We just need a GPR to store the value of CSRs.

This makes the code only work in certain scenarios.

I don't get it. This code is only for saving CSRs.

It only works in the prolog and epilogue where that GPR is available. loadRegFromStackSlot and storeRegToStackSlot are normally also used for spills and reloads, but that wouldn’t work if we ever needed that for CSRs.

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

600

This overlaps with FRM and FFLAGS. Probably at least deserves a comment about why they aren’t subregs.

[asb]

Left a trivial comment. Not sure on this vs D158396 - the logic of the other patch does seem a bit easier to follow as you suggested in your comment there.

llvm/lib/Target/RISCV/RISCVCallingConv.td

34

We should probably mention fcsr in this comment (and the one for f64 below).