[RISCV] Teach store merging to honor NoImplicitFloat.

[craig.topper]

Summary

NoImplicitFloat means we shouldn't use float or vector operations
that weren't present in the original source.

Similar code can be found on AArch64 and X86.

[craig.topper]

Tests pass without this change...

llvm/lib/Target/RISCV/RISCVISelLowering.h

 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
   int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
   bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
                                unsigned Index) const override;
 
   bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
 
+  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
+                        const MachineFunction &MF) const override;
+
   bool preferScalarizeSplat(SDNode *N) const override;
 
   bool softPromoteHalfType() const override { return true; }
 
   /// Return the register type for a given MVT, ensuring vectors are treated
   /// as a series of gpr sized integers.
   MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
                                     EVT VT) const override;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation  -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 bool RISCVTargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
   // When aggressively optimizing for code size, we prefer to use a div
   // instruction, as it is usually smaller than the alternative sequence.
   // TODO: Add vector division?
   bool OptSize = Attr.hasFnAttr(Attribute::MinSize);
   return OptSize && !VT.isVector();
 }
 
+bool RISCVTargetLowering::canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
+                                           const MachineFunction &MF) const {
+  // Do not merge to greater than XLen  if no implicit float attribute is set.
+
+  bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat);
+
+  if (NoFloat)
+    return (MemVT.getSizeInBits() <= Subtarget.getXLen());
+  return true;
+}
+
 bool RISCVTargetLowering::preferScalarizeSplat(SDNode *N) const {
   // Scalarize zero_ext and sign_ext might stop match to widening instruction in
   // some situation.
   unsigned Opc = N->getOpcode();
   if (Opc == ISD::ZERO_EXTEND || Opc == ISD::SIGN_EXTEND)
     return false;
   return true;
 }

llvm/test/CodeGen/RISCV/rvv/combine-store.ll

; CHECK-NEXT:    ret
   store i8 zeroinitializer, ptr %gep1
   %gep2 = getelementptr i8, ptr %p, i64 2
   store i8 zeroinitializer, ptr %gep2
   %gep3 = getelementptr i8, ptr %p, i64 3
   store i8 zeroinitializer, ptr %gep3
   ret void
 }
 
+define void @combine_zero_stores_4xi8_noimplicitfloat(ptr %p) noimplicitfloat {
+; CHECK-LABEL: combine_zero_stores_4xi8_noimplicitfloat:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sw zero, 0(a0)
+; CHECK-NEXT:    ret
+  store i8 zeroinitializer, ptr %p, align 4
+  %gep1 = getelementptr i8, ptr %p, i64 1
+  store i8 zeroinitializer, ptr %gep1
+  %gep2 = getelementptr i8, ptr %p, i64 2
+  store i8 zeroinitializer, ptr %gep2
+  %gep3 = getelementptr i8, ptr %p, i64 3
+  store i8 zeroinitializer, ptr %gep3
+  ret void
+}
+
 define void @combine_zero_stores_8xi8(ptr %p) {
 ; RV32-LABEL: combine_zero_stores_8xi8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    sw zero, 0(a0)
 ; RV32-NEXT:    sw zero, 4(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: combine_zero_stores_8xi8:

 ; CHECK-NEXT:    sw zero, 0(a0)
 ; CHECK-NEXT:    ret
   store i16 zeroinitializer, ptr %p, align 4
   %gep = getelementptr i8, ptr %p, i64 2
   store i16 zeroinitializer, ptr %gep
   ret void
 }
 
+define void @combine_zero_stores_8xi8_noimplicitfloat(ptr %p) noimplicitfloat {
+; RV32-LABEL: combine_zero_stores_8xi8_noimplicitfloat:
+; RV32:       # %bb.0:
+; RV32-NEXT:    sw zero, 0(a0)
+; RV32-NEXT:    sw zero, 4(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: combine_zero_stores_8xi8_noimplicitfloat:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sd zero, 0(a0)
+; RV64-NEXT:    ret
+  store i8 zeroinitializer, ptr %p, align 8
+  %gep1 = getelementptr i8, ptr %p, i64 1
+  store i8 zeroinitializer, ptr %gep1
+  %gep2 = getelementptr i8, ptr %p, i64 2
+  store i8 zeroinitializer, ptr %gep2
+  %gep3 = getelementptr i8, ptr %p, i64 3
+  store i8 zeroinitializer, ptr %gep3
+  %gep4 = getelementptr i8, ptr %p, i64 4
+  store i8 zeroinitializer, ptr %gep4, align 8
+  %gep5 = getelementptr i8, ptr %p, i64 5
+  store i8 zeroinitializer, ptr %gep5
+  %gep6 = getelementptr i8, ptr %p, i64 6
+  store i8 zeroinitializer, ptr %gep6
+  %gep7 = getelementptr i8, ptr %p, i64 7
+  store i8 zeroinitializer, ptr %gep7
+  ret void
+}
+
 define void @combine_zero_stores_4xi16(ptr %p) {
 ; RV32-LABEL: combine_zero_stores_4xi16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    sw zero, 0(a0)
 ; RV32-NEXT:    sw zero, 4(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: combine_zero_stores_4xi16:
; RV64-NEXT:    ret
   store i32 zeroinitializer, ptr %gep1
   %gep2 = getelementptr i32, ptr %p, i64 2
   store i32 zeroinitializer, ptr %gep2, align 8
   %gep3 = getelementptr i32, ptr %p, i64 3
   store i32 zeroinitializer, ptr %gep3
   ret void
 }
 
+define void @combine_zero_stores_4xi32_noimplicitfloat(ptr %p) noimplicitfloat {
+; RV32-LABEL: combine_zero_stores_4xi32_noimplicitfloat:
+; RV32:       # %bb.0:
+; RV32-NEXT:    sw zero, 0(a0)
+; RV32-NEXT:    sw zero, 4(a0)
+; RV32-NEXT:    sw zero, 8(a0)
+; RV32-NEXT:    sw zero, 12(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: combine_zero_stores_4xi32_noimplicitfloat:
+; RV64:       # %bb.0:
+; RV64-NEXT:    sd zero, 0(a0)
+; RV64-NEXT:    sd zero, 8(a0)
+; RV64-NEXT:    ret
+  store i32 zeroinitializer, ptr %p, align 16
+  %gep1 = getelementptr i32, ptr %p, i64 1
+  store i32 zeroinitializer, ptr %gep1
+  %gep2 = getelementptr i32, ptr %p, i64 2
+  store i32 zeroinitializer, ptr %gep2, align 8
+  %gep3 = getelementptr i32, ptr %p, i64 3
+  store i32 zeroinitializer, ptr %gep3
+  ret void
+}
+
 define void @combine_zero_stores_8xi32(ptr %p) {
 ; RV32-LABEL: combine_zero_stores_8xi32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    vse32.v v8, (a0)
 ; RV32-NEXT:    ret
 ;