[RISCV] Call combineSelectToBinOp before generic select expansion for Zicond.

[craig.topper]

Summary

This handles logical ops of setccs and optimizes when the true or
false value is -1.

[wangpc]

LGTM

llvm/test/CodeGen/RISCV/select-binop-identity.ll

45

nit: These CHECKs are the same as RV32I/RV64I, add prefixes to RUN lines of zicond/xventanacondops?

[asb]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation  -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (TrueV.getOpcode() == ISD::AND &&
           DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, CondV));
     // (select c, t, (and t, x)) -> (or (czero_eqz t, c), (and t, x))
     if (FalseV.getOpcode() == ISD::AND &&
         (FalseV.getOperand(0) == TrueV || FalseV.getOperand(1) == TrueV))
       return DAG.getNode(
           ISD::OR, DL, VT, FalseV,
           DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV));
 
+    // Try some other optimizations before falling back to generic lowering.
+    if (SDValue V = combineSelectToBinOp(Op.getNode(), DAG, Subtarget))
+      return V;
+
     // (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c))
     return DAG.getNode(ISD::OR, DL, VT,
                        DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV),
                        DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, CondV));
   }
 
   if (SDValue V = combineSelectToBinOp(Op.getNode(), DAG, Subtarget))
     return V;

llvm/test/CodeGen/RISCV/select-binop-identity.ll

 ; SFB64:       # %bb.0:
 ; SFB64-NEXT:    beqz a0, .LBB0_2
 ; SFB64-NEXT:  # %bb.1:
 ; SFB64-NEXT:    and a2, a2, a1
 ; SFB64-NEXT:  .LBB0_2:
 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: and_select_all_ones_i32:
 ; VTCONDOPS64:       # %bb.0:
-; VTCONDOPS64-NEXT:    li a3, -1
-; VTCONDOPS64-NEXT:    vt.maskcn a3, a3, a0
-; VTCONDOPS64-NEXT:    vt.maskc a0, a1, a0
-; VTCONDOPS64-NEXT:    or a0, a0, a3
+; VTCONDOPS64-NEXT:    addi a0, a0, -1
+; VTCONDOPS64-NEXT:    or a0, a0, a1
 ; VTCONDOPS64-NEXT:    and a0, a0, a2
 ; VTCONDOPS64-NEXT:    ret
 ;
 ; ZICOND-LABEL: and_select_all_ones_i32:
 ; ZICOND:       # %bb.0:
-; ZICOND-NEXT:    li a3, -1
-; ZICOND-NEXT:    czero.nez a3, a3, a0
-; ZICOND-NEXT:    czero.eqz a0, a1, a0
-; ZICOND-NEXT:    or a0, a0, a3
+; ZICOND-NEXT:    addi a0, a0, -1
+; ZICOND-NEXT:    or a0, a0, a1
 ; ZICOND-NEXT:    and a0, a0, a2
 ; ZICOND-NEXT:    ret
   %a = select i1 %c, i32 %x, i32 -1
   %b = and i32 %a, %y
   ret i32 %b
 }
 
 define i64 @and_select_all_ones_i64(i1 zeroext %c, i64 %x, i64 %y) {

 ; SFB64-NEXT:  # %bb.1:
 ; SFB64-NEXT:    and a2, a2, a1
 ; SFB64-NEXT:  .LBB1_2:
 ; SFB64-NEXT:    mv a0, a2
 ; SFB64-NEXT:    ret
 ;
 ; VTCONDOPS64-LABEL: and_select_all_ones_i64:
 ; VTCONDOPS64:       # %bb.0:
-; VTCONDOPS64-NEXT:    vt.maskcn a1, a1, a0
-; VTCONDOPS64-NEXT:    li a3, -1
-; VTCONDOPS64-NEXT:    vt.maskc a0, a3, a0
+; VTCONDOPS64-NEXT:    neg a0, a0
 ; VTCONDOPS64-NEXT:    or a0, a0, a1
 ; VTCONDOPS64-NEXT:    and a0, a2, a0
 ; VTCONDOPS64-NEXT:    ret
 ;
 ; ZICOND32-LABEL: and_select_all_ones_i64:
 ; ZICOND32:       # %bb.0:
-; ZICOND32-NEXT:    czero.nez a2, a2, a0
-; ZICOND32-NEXT:    li a5, -1
-; ZICOND32-NEXT:    czero.eqz a5, a5, a0
-; ZICOND32-NEXT:    or a2, a5, a2
-; ZICOND32-NEXT:    czero.nez a0, a1, a0
-; ZICOND32-NEXT:    or a0, a5, a0
+; ZICOND32-NEXT:    neg a0, a0
+; ZICOND32-NEXT:    or a2, a0, a2
+; ZICOND32-NEXT:    or a0, a0, a1
 ; ZICOND32-NEXT:    and a0, a3, a0
 ; ZICOND32-NEXT:    and a1, a4, a2
 ; ZICOND32-NEXT:    ret
 ;
 ; ZICOND64-LABEL: and_select_all_ones_i64:
 ; ZICOND64:       # %bb.0:
-; ZICOND64-NEXT:    czero.nez a1, a1, a0
-; ZICOND64-NEXT:    li a3, -1
-; ZICOND64-NEXT:    czero.eqz a0, a3, a0
+; ZICOND64-NEXT:    neg a0, a0
 ; ZICOND64-NEXT:    or a0, a0, a1
 ; ZICOND64-NEXT:    and a0, a2, a0
 ; ZICOND64-NEXT:    ret
   %a = select i1 %c, i64 -1, i64 %x
   %b = and i64 %y, %a
   ret i64 %b
 }
 

llvm/test/CodeGen/RISCV/xaluo.ll

 ; RV64ZBA-NEXT:    ret
 ;
 ; RV32ZICOND-LABEL: uaddo.i64.constant:
 ; RV32ZICOND:       # %bb.0: # %entry
 ; RV32ZICOND-NEXT:    addi a3, a0, 2
 ; RV32ZICOND-NEXT:    sltu a0, a3, a0
 ; RV32ZICOND-NEXT:    add a4, a1, a0
 ; RV32ZICOND-NEXT:    sltu a1, a4, a1
-; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
-; RV32ZICOND-NEXT:    czero.nez a0, a0, a0
-; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    and a0, a0, a1
 ; RV32ZICOND-NEXT:    sw a3, 0(a2)
 ; RV32ZICOND-NEXT:    sw a4, 4(a2)
 ; RV32ZICOND-NEXT:    ret
 ;
 ; RV64ZICOND-LABEL: uaddo.i64.constant:
 ; RV64ZICOND:       # %bb.0: # %entry
 ; RV64ZICOND-NEXT:    addi a2, a0, 2
 ; RV64ZICOND-NEXT:    sltu a0, a2, a0

 ;
 ; RV32ZICOND-LABEL: uaddo.i64.constant_2048:
 ; RV32ZICOND:       # %bb.0: # %entry
 ; RV32ZICOND-NEXT:    addi a3, a0, 2047
 ; RV32ZICOND-NEXT:    addi a3, a3, 1
 ; RV32ZICOND-NEXT:    sltu a0, a3, a0
 ; RV32ZICOND-NEXT:    add a4, a1, a0
 ; RV32ZICOND-NEXT:    sltu a1, a4, a1
-; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
-; RV32ZICOND-NEXT:    czero.nez a0, a0, a0
-; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    and a0, a0, a1
 ; RV32ZICOND-NEXT:    sw a3, 0(a2)
 ; RV32ZICOND-NEXT:    sw a4, 4(a2)
 ; RV32ZICOND-NEXT:    ret
 ;
 ; RV64ZICOND-LABEL: uaddo.i64.constant_2048:
 ; RV64ZICOND:       # %bb.0: # %entry
 ; RV64ZICOND-NEXT:    addi a2, a0, 2047
 ; RV64ZICOND-NEXT:    addi a2, a2, 1

 ;
 ; RV32ZICOND-LABEL: uaddo.i64.constant_2049:
 ; RV32ZICOND:       # %bb.0: # %entry
 ; RV32ZICOND-NEXT:    addi a3, a0, 2047
 ; RV32ZICOND-NEXT:    addi a3, a3, 2
 ; RV32ZICOND-NEXT:    sltu a0, a3, a0
 ; RV32ZICOND-NEXT:    add a4, a1, a0
 ; RV32ZICOND-NEXT:    sltu a1, a4, a1
-; RV32ZICOND-NEXT:    czero.eqz a1, a1, a0
-; RV32ZICOND-NEXT:    czero.nez a0, a0, a0
-; RV32ZICOND-NEXT:    or a0, a0, a1
+; RV32ZICOND-NEXT:    and a0, a0, a1
 ; RV32ZICOND-NEXT:    sw a3, 0(a2)
 ; RV32ZICOND-NEXT:    sw a4, 4(a2)
 ; RV32ZICOND-NEXT:    ret
 ;
 ; RV64ZICOND-LABEL: uaddo.i64.constant_2049:
 ; RV64ZICOND:       # %bb.0: # %entry
 ; RV64ZICOND-NEXT:    addi a2, a0, 2047
 ; RV64ZICOND-NEXT:    addi a2, a2, 2

 ; RV32ZICOND-LABEL: uaddo.i64.constant_setcc_on_overflow_flag:
 ; RV32ZICOND:       # %bb.0: # %entry
 ; RV32ZICOND-NEXT:    lw a1, 0(a0)
 ; RV32ZICOND-NEXT:    lw a2, 4(a0)
 ; RV32ZICOND-NEXT:    addi a0, a1, 2
 ; RV32ZICOND-NEXT:    sltu a3, a0, a1
 ; RV32ZICOND-NEXT:    add a1, a2, a3
 ; RV32ZICOND-NEXT:    sltu a2, a1, a2
-; RV32ZICOND-NEXT:    czero.eqz a2, a2, a3
-; RV32ZICOND-NEXT:    czero.nez a3, a3, a3
-; RV32ZICOND-NEXT:    or a2, a3, a2
+; RV32ZICOND-NEXT:    and a2, a3, a2
 ; RV32ZICOND-NEXT:    bnez a2, .LBB69_2
 ; RV32ZICOND-NEXT:  # %bb.1: # %IfOverflow
 ; RV32ZICOND-NEXT:    li a0, 0
 ; RV32ZICOND-NEXT:    li a1, 0
 ; RV32ZICOND-NEXT:  .LBB69_2: # %IfNoOverflow
 ; RV32ZICOND-NEXT:    ret
 ;
 ; RV64ZICOND-LABEL: uaddo.i64.constant_setcc_on_overflow_flag: