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Differential D156666

Intrinsics: Add type overload to stacksave and stackstore
ClosedPublic

Authored by arsenm on Jul 31 2023, 4:08 AM.

Details

Reviewers
doru1004
JonChesterfield
jdoerfert
aemerson
bkramer
efriedma
sstefan1
krzysz00
nicolasvasilache
aartbik
ftynse
dcaballe
nikic
Summary

This allows use with non-0 address space stacks. llvm_ptr_ty should
never be used. This could use some more percolation up through mlir,
but this is enough to fix existing tests.

Diff Detail

Event Timeline

arsenm created this revision.Jul 31 2023, 4:08 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 31 2023, 4:08 AM
Herald added subscribers: ormris, ChuanqiXu, okura and 6 others. · View Herald Transcript
arsenm requested review of this revision.Jul 31 2023, 4:08 AM
Herald added a reviewer: sstefan1. · View Herald TranscriptJul 31 2023, 4:08 AM
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Herald added subscribers: wangpc, jplehr, sstefan1, wdng. · View Herald Transcript
Harbormaster completed remote builds in B249160: Diff 545583.Jul 31 2023, 4:09 AM
arsenm added a child revision: D156667: GlobalISel: Don't expand stacksave/stackrestore in IRTranslator.Jul 31 2023, 4:20 AM
arsenm added a child revision: D156669: AMDGPU: Handle llvm.stacksave and llvm.stackrestore.Jul 31 2023, 4:24 AM
arsenm updated this revision to Diff 545596.Jul 31 2023, 4:50 AM

Update documentation

Harbormaster completed remote builds in B249169: Diff 545596.Jul 31 2023, 4:51 AM
efriedma added a comment.Jul 31 2023, 2:16 PM

This seems generally reasonable.

clang/lib/CodeGen/CGBuiltin.cpp
3911

Why not CreateStackSave? (same question for CGDecl.)

clang/lib/CodeGen/CGDecl.cpp
1631

Does this CreateTempAlloca call need to be updated?

arsenm updated this revision to Diff 545844.Jul 31 2023, 4:02 PM
arsenm marked an inline comment as done.

Fix temp slot type, oversized and overaligned for AMDGPU since it used the default address space pointer but wasn't broken.

Also assert types match and use the Create* functions

arsenm added inline comments.Jul 31 2023, 4:06 PM
clang/lib/CodeGen/CGBuiltin.cpp
3911

I was considering possible multiple stack handling or something, where you'd want to use the current instance's type. It shouldn't matter in reality

Harbormaster completed remote builds in B249337: Diff 545844.Jul 31 2023, 6:42 PM
arsenm added a comment.Aug 9 2023, 7:14 AM

ping

Herald added a subscriber: hoy. · View Herald TranscriptAug 9 2023, 7:14 AM
nikic added a subscriber: nikic.Aug 9 2023, 7:17 AM

There is an assertion failure in llvmir-intrinsics.mlir.

arsenm updated this revision to Diff 548728.Aug 9 2023, 12:06 PM
arsenm edited the summary of this revision. (Show Details)
arsenm added a reviewer: krzysz00.
Herald added a reviewer: nicolasvasilache. · View Herald TranscriptAug 9 2023, 12:06 PM
Herald added a reviewer: aartbik. · View Herald Transcript
Herald added a reviewer: ftynse. · View Herald Transcript
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nikic accepted this revision.Aug 9 2023, 12:17 PM

LGTM, though I did not review test changes in detail.

This revision is now accepted and ready to land.Aug 9 2023, 12:17 PM
Herald added a subscriber: StephenFan. · View Herald TranscriptAug 9 2023, 12:17 PM
arsenm closed this revision.Aug 9 2023, 3:33 PM

25bc999d1fb2efccc3ece398550af738aea7d310

arsenm mentioned this in rG25bc999d1fb2: Intrinsics: Add type overload to stacksave and stackstore.Aug 9 2023, 3:33 PM
Harbormaster completed remote builds in B251468: Diff 548728.Aug 9 2023, 6:24 PM
JonChesterfield mentioned this in D158246: [amdgpu] WIP variadics.Aug 18 2023, 7:53 AM

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Diff 545844

clang/lib/CodeGen/CGBuiltin.cpp

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Address Buf = EmitPointerWithAlignment(E->getArg(0)); Address Buf = EmitPointerWithAlignment(E->getArg(0));
// Store the frame pointer to the setjmp buffer. // Store the frame pointer to the setjmp buffer.
Value *FrameAddr = Builder.CreateCall( Value *FrameAddr = Builder.CreateCall(
CGM.getIntrinsic(Intrinsic::frameaddress, AllocaInt8PtrTy), CGM.getIntrinsic(Intrinsic::frameaddress, AllocaInt8PtrTy),
ConstantInt::get(Int32Ty, 0)); ConstantInt::get(Int32Ty, 0));
Builder.CreateStore(FrameAddr, Buf); Builder.CreateStore(FrameAddr, Buf);
// Store the stack pointer to the setjmp buffer. // Store the stack pointer to the setjmp buffer.
efriedmaUnsubmitted
Not Done
ReplyInline Actions

Why not CreateStackSave? (same question for CGDecl.)

efriedma: Why not CreateStackSave? (same question for CGDecl.)
arsenmAuthorUnsubmitted
Done
ReplyInline Actions

I was considering possible multiple stack handling or something, where you'd want to use the current instance's type. It shouldn't matter in reality

arsenm: I was considering possible multiple stack handling or something, where you'd want to use the…
Value *StackAddr = Value *StackAddr = Builder.CreateStackSave();
Builder.CreateCall(CGM.getIntrinsic(Intrinsic::stacksave)); assert(Buf.getPointer()->getType() == StackAddr->getType());
Address StackSaveSlot = Builder.CreateConstInBoundsGEP(Buf, 2); Address StackSaveSlot = Builder.CreateConstInBoundsGEP(Buf, 2);
Builder.CreateStore(StackAddr, StackSaveSlot); Builder.CreateStore(StackAddr, StackSaveSlot);
// Call LLVM's EH setjmp, which is lightweight. // Call LLVM's EH setjmp, which is lightweight.
Function *F = CGM.getIntrinsic(Intrinsic::eh_sjlj_setjmp); Function *F = CGM.getIntrinsic(Intrinsic::eh_sjlj_setjmp);
return RValue::get(Builder.CreateCall(F, Buf.getPointer())); return RValue::get(Builder.CreateCall(F, Buf.getPointer()));
} }
case Builtin::BI__builtin_longjmp: { case Builtin::BI__builtin_longjmp: {
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clang/lib/CodeGen/CGCall.cpp

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args.addWriteback(srcLV, temp, valueToUse); args.addWriteback(srcLV, temp, valueToUse);
args.add(RValue::get(finalArgument), CRE->getType()); args.add(RValue::get(finalArgument), CRE->getType());
} }
void CallArgList::allocateArgumentMemory(CodeGenFunction &CGF) { void CallArgList::allocateArgumentMemory(CodeGenFunction &CGF) {
assert(!StackBase); assert(!StackBase);
// Save the stack. // Save the stack.
llvm::Function *F = CGF.CGM.getIntrinsic(llvm::Intrinsic::stacksave); StackBase = CGF.Builder.CreateStackSave("inalloca.save");
StackBase = CGF.Builder.CreateCall(F, {}, "inalloca.save");
} }
void CallArgList::freeArgumentMemory(CodeGenFunction &CGF) const { void CallArgList::freeArgumentMemory(CodeGenFunction &CGF) const {
if (StackBase) { if (StackBase) {
// Restore the stack after the call. // Restore the stack after the call.
llvm::Function *F = CGF.CGM.getIntrinsic(llvm::Intrinsic::stackrestore); CGF.Builder.CreateStackRestore(StackBase);
CGF.Builder.CreateCall(F, StackBase);
} }
} }
void CodeGenFunction::EmitNonNullArgCheck(RValue RV, QualType ArgType, void CodeGenFunction::EmitNonNullArgCheck(RValue RV, QualType ArgType,
SourceLocation ArgLoc, SourceLocation ArgLoc,
AbstractCallee AC, AbstractCallee AC,
unsigned ParmNum) { unsigned ParmNum) {
if (!AC.getDecl() || !(SanOpts.has(SanitizerKind::NonnullAttribute) || if (!AC.getDecl() || !(SanOpts.has(SanitizerKind::NonnullAttribute) ||
▲ Show 20 Lines • Show All 167 Lines • Show Last 20 Lines

clang/lib/CodeGen/CGDecl.cpp

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}; };
struct CallStackRestore final : EHScopeStack::Cleanup { struct CallStackRestore final : EHScopeStack::Cleanup {
Address Stack; Address Stack;
CallStackRestore(Address Stack) : Stack(Stack) {} CallStackRestore(Address Stack) : Stack(Stack) {}
bool isRedundantBeforeReturn() override { return true; } bool isRedundantBeforeReturn() override { return true; }
void Emit(CodeGenFunction &CGF, Flags flags) override { void Emit(CodeGenFunction &CGF, Flags flags) override {
llvm::Value *V = CGF.Builder.CreateLoad(Stack); llvm::Value *V = CGF.Builder.CreateLoad(Stack);
llvm::Function *F = CGF.CGM.getIntrinsic(llvm::Intrinsic::stackrestore); CGF.Builder.CreateStackRestore(V);
CGF.Builder.CreateCall(F, V);
} }
}; };
struct KmpcAllocFree final : EHScopeStack::Cleanup { struct KmpcAllocFree final : EHScopeStack::Cleanup {
std::pair<llvm::Value *, llvm::Value *> AddrSizePair; std::pair<llvm::Value *, llvm::Value *> AddrSizePair;
KmpcAllocFree(const std::pair<llvm::Value *, llvm::Value *> &AddrSizePair) KmpcAllocFree(const std::pair<llvm::Value *, llvm::Value *> &AddrSizePair)
: AddrSizePair(AddrSizePair) {} : AddrSizePair(AddrSizePair) {}
void Emit(CodeGenFunction &CGF, Flags EmissionFlags) override { void Emit(CodeGenFunction &CGF, Flags EmissionFlags) override {
▲ Show 20 Lines • Show All 334 Lines • ▼ Show 20 Lines
VarAllocated = true; VarAllocated = true;
} }
} }
if (!VarAllocated) { if (!VarAllocated) {
if (!DidCallStackSave) { if (!DidCallStackSave) {
// Save the stack. // Save the stack.
Address Stack = Address Stack =
CreateTempAlloca(Int8PtrTy, getPointerAlign(), "saved_stack"); CreateDefaultAlignTempAlloca(AllocaInt8PtrTy, "saved_stack");
efriedmaUnsubmitted
Done
ReplyInline Actions

Does this CreateTempAlloca call need to be updated?

efriedma: Does this CreateTempAlloca call need to be updated?
llvm::Function *F = CGM.getIntrinsic(llvm::Intrinsic::stacksave); llvm::Value *V = Builder.CreateStackSave();
llvm::Value *V = Builder.CreateCall(F); assert(V->getType() == AllocaInt8PtrTy);
Builder.CreateStore(V, Stack); Builder.CreateStore(V, Stack);
DidCallStackSave = true; DidCallStackSave = true;
// Push a cleanup block and restore the stack there. // Push a cleanup block and restore the stack there.
// FIXME: in general circumstances, this should be an EH cleanup. // FIXME: in general circumstances, this should be an EH cleanup.
pushStackRestore(NormalCleanup, Stack); pushStackRestore(NormalCleanup, Stack);
} }
▲ Show 20 Lines • Show All 167 Lines • Show Last 20 Lines

clang/test/CodeGen/2006-01-13-StackSave.c

// PR691 // PR691
// RUN: %clang_cc1 %s -emit-llvm -o - | FileCheck %s // RUN: %clang_cc1 %s -emit-llvm -o - | FileCheck %s
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
extern void external(int[*]); extern void external(int[*]);
void test(int N) { void test(int N) {
int i; int i;
for (i = 0; i < N; ++i) { for (i = 0; i < N; ++i) {
int VLA[i]; int VLA[i];
external(VLA); external(VLA);
} }
} }

clang/test/CodeGen/vla.c

Show All 34 Linesvoid g(int count) {
// Make sure we emit sizes correctly in some obscure cases // Make sure we emit sizes correctly in some obscure cases
int (*a[5])[count]; int (*a[5])[count];
int (*b)[][count]; int (*b)[][count];
} }
// rdar://8403108 // rdar://8403108
// CHECK-LABEL: define{{.*}} void @f_8403108 // CHECK-LABEL: define{{.*}} void @f_8403108
void f_8403108(unsigned x) { void f_8403108(unsigned x) {
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
char s1[x]; char s1[x];
while (1) { while (1) {
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
char s2[x]; char s2[x];
if (1) if (1)
break; break;
// CHECK: call void @llvm.stackrestore(ptr // CHECK: call void @llvm.stackrestore.p0(ptr
} }
// CHECK: call void @llvm.stackrestore(ptr // CHECK: call void @llvm.stackrestore.p0(ptr
} }
// pr7827 // pr7827
void function(short width, int data[][width]) {} // expected-note {{passing argument to parameter 'data' here}} void function(short width, int data[][width]) {} // expected-note {{passing argument to parameter 'data' here}}
void test(void) { void test(void) {
int bork[4][13]; int bork[4][13];
// CHECK: call void @function(i16 noundef signext 1, ptr noundef null) // CHECK: call void @function(i16 noundef signext 1, ptr noundef null)
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clang/test/CodeGenCXX/builtin-is-constant-evaluated.cpp

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// CHECK-ARR-LABEL: define{{.*}} void @_Z13test_arr_exprv // CHECK-ARR-LABEL: define{{.*}} void @_Z13test_arr_exprv
void test_arr_expr() { void test_arr_expr() {
// CHECK-ARR: %x1 = alloca [101 x i8], // CHECK-ARR: %x1 = alloca [101 x i8],
char x1[std::is_constant_evaluated() && __builtin_is_constant_evaluated() ? 101 : 1]; char x1[std::is_constant_evaluated() && __builtin_is_constant_evaluated() ? 101 : 1];
// CHECK-ARR: %x2 = alloca [42 x i8], // CHECK-ARR: %x2 = alloca [42 x i8],
char x2[std::is_constant_evaluated() && __builtin_is_constant_evaluated() ? 42 : RANDU()]; char x2[std::is_constant_evaluated() && __builtin_is_constant_evaluated() ? 42 : RANDU()];
// CHECK-ARR: call ptr @llvm.stacksave() // CHECK-ARR: call ptr @llvm.stacksave.p0()
// CHECK-ARR: %vla = alloca i8, i64 13, // CHECK-ARR: %vla = alloca i8, i64 13,
char x3[std::is_constant_evaluated() || __builtin_is_constant_evaluated() ? RANDU() : 13]; char x3[std::is_constant_evaluated() || __builtin_is_constant_evaluated() ? RANDU() : 13];
} }
// CHECK-ARR-LABEL: define{{.*}} void @_Z17test_new_arr_exprv // CHECK-ARR-LABEL: define{{.*}} void @_Z17test_new_arr_exprv
void test_new_arr_expr() { void test_new_arr_expr() {
// CHECK-ARR: call noalias noundef nonnull ptr @_Znam(i64 noundef 17) // CHECK-ARR: call noalias noundef nonnull ptr @_Znam(i64 noundef 17)
new char[std::is_constant_evaluated() || __builtin_is_constant_evaluated() ? 1 : 17]; new char[std::is_constant_evaluated() || __builtin_is_constant_evaluated() ? 1 : 17];
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clang/test/CodeGenCXX/c99-variable-length-array.cpp

// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple x86_64-apple-darwin10 -emit-llvm -o - %s | FileCheck %s
struct X { struct X {
X(); X();
~X(); ~X();
}; };
struct Y { struct Y {
Y(); Y();
~Y(); ~Y();
}; };
// CHECK-LABEL: define{{.*}} void @_Z1fiPPKc( // CHECK-LABEL: define{{.*}} void @_Z1fiPPKc(
void f(int argc, const char* argv[]) { void f(int argc, const char* argv[]) {
// CHECK: call void @_ZN1XC1Ev // CHECK: call void @_ZN1XC1Ev
X x; X x;
// CHECK: call ptr @llvm.stacksave( // CHECK: call ptr @llvm.stacksave.p0(
const char *argv2[argc]; const char *argv2[argc];
// CHECK: call void @_ZN1YC1Ev // CHECK: call void @_ZN1YC1Ev
Y y; Y y;
for (int i = 0; i != argc; ++i) for (int i = 0; i != argc; ++i)
argv2[i] = argv[i]; argv2[i] = argv[i];
// CHECK: call void @_ZN1YD1Ev // CHECK: call void @_ZN1YD1Ev
// CHECK: call void @llvm.stackrestore // CHECK: call void @llvm.stackrestore.p0
// CHECK: call void @_ZN1XD1Ev // CHECK: call void @_ZN1XD1Ev
// CHECK: ret void // CHECK: ret void
} }
namespace PR11744 { namespace PR11744 {
// Make sure this doesn't crash; there was a use-after-free issue // Make sure this doesn't crash; there was a use-after-free issue
// for this testcase. // for this testcase.
template<typename T> int f(int n) { template<typename T> int f(int n) {
T arr[3][n]; T arr[3][n];
return 3; return 3;
} }
int test = f<int>(0); int test = f<int>(0);
} }

clang/test/CodeGenCXX/inalloca-overaligned.cpp

Show All 31 Lines
int pass_inalloca_overaligned() { int pass_inalloca_overaligned() {
gvi32 = receive_inalloca_overaligned(NonTrivial(), OverAligned()); gvi32 = receive_inalloca_overaligned(NonTrivial(), OverAligned());
return gvi32; return gvi32;
} }
// CHECK-LABEL: define dso_local noundef i32 @"?pass_inalloca_overaligned@@Y{{.*}}" // CHECK-LABEL: define dso_local noundef i32 @"?pass_inalloca_overaligned@@Y{{.*}}"
// CHECK: [[TMP:%[^ ]*]] = alloca %struct.OverAligned, align 64 // CHECK: [[TMP:%[^ ]*]] = alloca %struct.OverAligned, align 64
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: alloca inalloca <{ %struct.NonTrivial, ptr }> // CHECK: alloca inalloca <{ %struct.NonTrivial, ptr }>
// Construct OverAligned into TMP. // Construct OverAligned into TMP.
// CHECK: call x86_thiscallcc noundef ptr @"??0OverAligned@@QAE@XZ"(ptr {{[^,]*}} [[TMP]]) // CHECK: call x86_thiscallcc noundef ptr @"??0OverAligned@@QAE@XZ"(ptr {{[^,]*}} [[TMP]])
// Construct NonTrivial into the GEP. // Construct NonTrivial into the GEP.
// CHECK: [[GEP:%[^ ]*]] = getelementptr inbounds <{ %struct.NonTrivial, ptr }>, ptr %{{.*}}, i32 0, i32 0 // CHECK: [[GEP:%[^ ]*]] = getelementptr inbounds <{ %struct.NonTrivial, ptr }>, ptr %{{.*}}, i32 0, i32 0
// CHECK: call x86_thiscallcc noundef ptr @"??0NonTrivial@@QAE@XZ"(ptr {{[^,]*}} [[GEP]]) // CHECK: call x86_thiscallcc noundef ptr @"??0NonTrivial@@QAE@XZ"(ptr {{[^,]*}} [[GEP]])
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clang/test/CodeGenCXX/inalloca-stmtexpr.cpp

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// FIXME: This can cause a stack leak. We should really have a "normal" cleanup // FIXME: This can cause a stack leak. We should really have a "normal" cleanup
// that goto branches through. // that goto branches through.
// CHECK-LABEL: define dso_local void @seqAbort() // CHECK-LABEL: define dso_local void @seqAbort()
// CHECK: alloca inalloca <{ %struct.Foo, %struct.Foo }> // CHECK: alloca inalloca <{ %struct.Foo, %struct.Foo }>
// CHECK: call noundef zeroext i1 @"?cond@@YA_NXZ"() // CHECK: call noundef zeroext i1 @"?cond@@YA_NXZ"()
// CHECK: br i1 // CHECK: br i1
// CHECK: br label %out // CHECK: br label %out
// CHECK: call void @"?inalloca@@YAXUFoo@@0@Z"(ptr inalloca(<{ %struct.Foo, %struct.Foo }>) %{{.*}}) // CHECK: call void @"?inalloca@@YAXUFoo@@0@Z"(ptr inalloca(<{ %struct.Foo, %struct.Foo }>) %{{.*}})
// CHECK: call void @llvm.stackrestore(ptr %inalloca.save) // CHECK: call void @llvm.stackrestore.p0(ptr %inalloca.save)
// CHECK: out: // CHECK: out:

clang/test/CodeGenCXX/inheriting-constructor.cpp

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Linesnamespace inalloca_nonvirt {
// No inlining implied for Itanium. // No inlining implied for Itanium.
// ITANIUM-LABEL: define linkonce_odr void @_ZN16inalloca_nonvirt1BCI1NS_1AEE1QiS1_OS1_( // ITANIUM-LABEL: define linkonce_odr void @_ZN16inalloca_nonvirt1BCI1NS_1AEE1QiS1_OS1_(
// ITANIUM: call void @_ZN16inalloca_nonvirt1BCI2NS_1AEE1QiS1_OS1_( // ITANIUM: call void @_ZN16inalloca_nonvirt1BCI2NS_1AEE1QiS1_OS1_(
// MSABI-LABEL: define internal void @"??__Eb@inalloca_nonvirt@@YAXXZ"( // MSABI-LABEL: define internal void @"??__Eb@inalloca_nonvirt@@YAXXZ"(
// On Win32, the inalloca call can't be forwarded so we force inlining. // On Win32, the inalloca call can't be forwarded so we force inlining.
// WIN32: %[[TMP:.*]] = alloca // WIN32: %[[TMP:.*]] = alloca
// WIN32: call ptr @llvm.stacksave() // WIN32: call ptr @llvm.stacksave.p0()
// WIN32: %[[ARGMEM:.*]] = alloca inalloca // WIN32: %[[ARGMEM:.*]] = alloca inalloca
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4)
// WIN32: %[[ARG3:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG3:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3)
// WIN32: %[[ARG1:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG1:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1)
// WIN32: call {{.*}} @"??0Z@@QAE@XZ"( // WIN32: call {{.*}} @"??0Z@@QAE@XZ"(
// WIN32: %[[ARG2:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG2:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: store i32 2, ptr %[[ARG2]] // WIN32: store i32 2, ptr %[[ARG2]]
// WIN32: %[[ARG4:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG4:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: store ptr %[[TMP]], ptr %[[ARG4]] // WIN32: store ptr %[[TMP]], ptr %[[ARG4]]
// WIN32: call {{.*}} @"??0A@inalloca_nonvirt@@QAE@UQ@@H0$$QAU2@@Z"(ptr{{[^,]*}}, ptr inalloca(<{{.*}}>) %[[ARGMEM]]) // WIN32: call {{.*}} @"??0A@inalloca_nonvirt@@QAE@UQ@@H0$$QAU2@@Z"(ptr{{[^,]*}}, ptr inalloca(<{{.*}}>) %[[ARGMEM]])
// WIN32: call void @llvm.stackrestore( // WIN32: call void @llvm.stackrestore.p0(
// WIN32: call {{.*}} @"??0Z@@QAE@XZ"( // WIN32: call {{.*}} @"??0Z@@QAE@XZ"(
// WIN32: call {{.*}} @"??1Q@@QAE@XZ"( // WIN32: call {{.*}} @"??1Q@@QAE@XZ"(
// On Win64, the Q arguments would be destroyed in the callee. We don't yet // On Win64, the Q arguments would be destroyed in the callee. We don't yet
// support that in the non-inlined case, so we force inlining. // support that in the non-inlined case, so we force inlining.
// WIN64: %[[TMP:.*]] = alloca // WIN64: %[[TMP:.*]] = alloca
// WIN64: %[[ARG3:.*]] = alloca // WIN64: %[[ARG3:.*]] = alloca
// WIN64: %[[ARG1:.*]] = alloca // WIN64: %[[ARG1:.*]] = alloca
// WIN64: call {{.*}} @"??0Q@@QEAA@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4) // WIN64: call {{.*}} @"??0Q@@QEAA@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4)
// WIN64: call {{.*}} @"??0Q@@QEAA@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3) // WIN64: call {{.*}} @"??0Q@@QEAA@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3)
// WIN64: call {{.*}} @"??0Q@@QEAA@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1) // WIN64: call {{.*}} @"??0Q@@QEAA@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1)
// WIN64: call {{.*}} @"??0Z@@QEAA@XZ"( // WIN64: call {{.*}} @"??0Z@@QEAA@XZ"(
// WIN64: call {{.*}} @"??0A@inalloca_nonvirt@@QEAA@UQ@@H0$$QEAU2@@Z"(ptr{{.*}}, ptr %[[ARG1]], i32 2, ptr %[[ARG3]], ptr{{.*}} %[[TMP]]) // WIN64: call {{.*}} @"??0A@inalloca_nonvirt@@QEAA@UQ@@H0$$QEAU2@@Z"(ptr{{.*}}, ptr %[[ARG1]], i32 2, ptr %[[ARG3]], ptr{{.*}} %[[TMP]])
// WIN64: call {{.*}} @"??0Z@@QEAA@XZ"( // WIN64: call {{.*}} @"??0Z@@QEAA@XZ"(
// WIN64: call void @"??1Q@@QEAA@XZ"(ptr {{[^,]*}} %[[TMP]]) // WIN64: call void @"??1Q@@QEAA@XZ"(ptr {{[^,]*}} %[[TMP]])
struct C : B { using B::B; }; struct C : B { using B::B; };
C c(1, 2, 3, 4); C c(1, 2, 3, 4);
// MSABI-LABEL: define internal void @"??__Ec@inalloca_nonvirt@@YAXXZ"( // MSABI-LABEL: define internal void @"??__Ec@inalloca_nonvirt@@YAXXZ"(
// On Win32, the inalloca call can't be forwarded so we force inlining. // On Win32, the inalloca call can't be forwarded so we force inlining.
// WIN32: %[[TMP:.*]] = alloca // WIN32: %[[TMP:.*]] = alloca
// WIN32: call ptr @llvm.stacksave() // WIN32: call ptr @llvm.stacksave.p0()
// WIN32: %[[ARGMEM:.*]] = alloca inalloca // WIN32: %[[ARGMEM:.*]] = alloca inalloca
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4)
// WIN32: %[[ARG3:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG3:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3)
// WIN32: %[[ARG1:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG1:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1)
// WIN32: call {{.*}} @"??0Z@@QAE@XZ"( // WIN32: call {{.*}} @"??0Z@@QAE@XZ"(
// WIN32: %[[ARG2:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG2:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: store i32 2, ptr %[[ARG2]] // WIN32: store i32 2, ptr %[[ARG2]]
// WIN32: %[[ARG4:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG4:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: store ptr %[[TMP]], ptr %[[ARG4]] // WIN32: store ptr %[[TMP]], ptr %[[ARG4]]
// WIN32: call {{.*}} @"??0A@inalloca_nonvirt@@QAE@UQ@@H0$$QAU2@@Z"(ptr{{[^,]*}}, ptr inalloca(<{{.*}}>) %[[ARGMEM]]) // WIN32: call {{.*}} @"??0A@inalloca_nonvirt@@QAE@UQ@@H0$$QAU2@@Z"(ptr{{[^,]*}}, ptr inalloca(<{{.*}}>) %[[ARGMEM]])
// WIN32: call void @llvm.stackrestore( // WIN32: call void @llvm.stackrestore.p0(
// WIN32: call {{.*}} @"??0Z@@QAE@XZ"( // WIN32: call {{.*}} @"??0Z@@QAE@XZ"(
// WIN32: call {{.*}} @"??1Q@@QAE@XZ"( // WIN32: call {{.*}} @"??1Q@@QAE@XZ"(
// On Win64, the Q arguments would be destroyed in the callee. We don't yet // On Win64, the Q arguments would be destroyed in the callee. We don't yet
// support that in the non-inlined case, so we force inlining. // support that in the non-inlined case, so we force inlining.
// WIN64: %[[TMP:.*]] = alloca // WIN64: %[[TMP:.*]] = alloca
// WIN64: %[[ARG3:.*]] = alloca // WIN64: %[[ARG3:.*]] = alloca
// WIN64: %[[ARG1:.*]] = alloca // WIN64: %[[ARG1:.*]] = alloca
Show All 10 Linesnamespace inalloca_virt {
struct A { A(Q, int, Q, Q&&); int n; }; struct A { A(Q, int, Q, Q&&); int n; };
struct B : Z, virtual A { Z z; using A::A; }; struct B : Z, virtual A { Z z; using A::A; };
B b(1, 2, 3, 4); B b(1, 2, 3, 4);
// MSABI-LABEL: define internal void @"??__Eb@inalloca_virt@@YAXXZ"( // MSABI-LABEL: define internal void @"??__Eb@inalloca_virt@@YAXXZ"(
// On Win32, the inalloca call can't be forwarded so we force inlining. // On Win32, the inalloca call can't be forwarded so we force inlining.
// WIN32: %[[TMP:.*]] = alloca // WIN32: %[[TMP:.*]] = alloca
// WIN32: call ptr @llvm.stacksave() // WIN32: call ptr @llvm.stacksave.p0()
// WIN32: %[[ARGMEM:.*]] = alloca inalloca // WIN32: %[[ARGMEM:.*]] = alloca inalloca
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4)
// WIN32: %[[ARG3:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG3:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3)
// WIN32: %[[ARG1:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG1:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1)
// FIXME: It's dumb to round-trip this though memory and generate a branch. // FIXME: It's dumb to round-trip this though memory and generate a branch.
// WIN32: store i32 1, ptr %[[IS_MOST_DERIVED_ADDR:.*]] // WIN32: store i32 1, ptr %[[IS_MOST_DERIVED_ADDR:.*]]
// WIN32: %[[IS_MOST_DERIVED:.*]] = load i32, ptr %[[IS_MOST_DERIVED_ADDR]] // WIN32: %[[IS_MOST_DERIVED:.*]] = load i32, ptr %[[IS_MOST_DERIVED_ADDR]]
// WIN32: %[[IS_MOST_DERIVED_i1:.*]] = icmp ne i32 %[[IS_MOST_DERIVED]], 0 // WIN32: %[[IS_MOST_DERIVED_i1:.*]] = icmp ne i32 %[[IS_MOST_DERIVED]], 0
// WIN32: br i1 %[[IS_MOST_DERIVED_i1]] // WIN32: br i1 %[[IS_MOST_DERIVED_i1]]
// //
// WIN32: store {{.*}} @"??_8B@inalloca_virt@@7B@" // WIN32: store {{.*}} @"??_8B@inalloca_virt@@7B@"
// WIN32: %[[ARG2:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG2:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: store i32 2, ptr %[[ARG2]] // WIN32: store i32 2, ptr %[[ARG2]]
// WIN32: %[[ARG4:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG4:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: store ptr %[[TMP]], ptr %[[ARG4]] // WIN32: store ptr %[[TMP]], ptr %[[ARG4]]
// WIN32: call {{.*}} @"??0A@inalloca_virt@@QAE@UQ@@H0$$QAU2@@Z"(ptr{{[^,]*}}, ptr inalloca(<{{.*}}>) %[[ARGMEM]]) // WIN32: call {{.*}} @"??0A@inalloca_virt@@QAE@UQ@@H0$$QAU2@@Z"(ptr{{[^,]*}}, ptr inalloca(<{{.*}}>) %[[ARGMEM]])
// WIN32: call void @llvm.stackrestore( // WIN32: call void @llvm.stackrestore.p0(
// WIN32: br // WIN32: br
// //
// Note that if we jumped directly to here we would fail to stackrestore and // Note that if we jumped directly to here we would fail to stackrestore and
// destroy the parameters, but that's not actually possible. // destroy the parameters, but that's not actually possible.
// WIN32: call {{.*}} @"??0Z@@QAE@XZ"( // WIN32: call {{.*}} @"??0Z@@QAE@XZ"(
// WIN32: call {{.*}} @"??0Z@@QAE@XZ"( // WIN32: call {{.*}} @"??0Z@@QAE@XZ"(
// WIN32: call {{.*}} @"??1Q@@QAE@XZ"( // WIN32: call {{.*}} @"??1Q@@QAE@XZ"(
Show All 15 Linesnamespace inalloca_virt {
struct C : B { using B::B; }; struct C : B { using B::B; };
C c(1, 2, 3, 4); C c(1, 2, 3, 4);
// ITANIUM-LABEL: define linkonce_odr void @_ZN13inalloca_virt1CD1Ev( // ITANIUM-LABEL: define linkonce_odr void @_ZN13inalloca_virt1CD1Ev(
// MSABI-LABEL: define internal void @"??__Ec@inalloca_virt@@YAXXZ"( // MSABI-LABEL: define internal void @"??__Ec@inalloca_virt@@YAXXZ"(
// On Win32, the inalloca call can't be forwarded so we force inlining. // On Win32, the inalloca call can't be forwarded so we force inlining.
// WIN32: %[[TMP:.*]] = alloca // WIN32: %[[TMP:.*]] = alloca
// WIN32: call ptr @llvm.stacksave() // WIN32: call ptr @llvm.stacksave.p0()
// WIN32: %[[ARGMEM:.*]] = alloca inalloca // WIN32: %[[ARGMEM:.*]] = alloca inalloca
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[TMP]], i32 4)
// WIN32: %[[ARG3:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG3:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG3]], i32 3)
// WIN32: %[[ARG1:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG1:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1) // WIN32: call {{.*}} @"??0Q@@QAE@H@Z"(ptr {{[^,]*}} %[[ARG1]], i32 1)
// WIN32: store i32 1, ptr %[[IS_MOST_DERIVED_ADDR:.*]] // WIN32: store i32 1, ptr %[[IS_MOST_DERIVED_ADDR:.*]]
// WIN32: %[[IS_MOST_DERIVED:.*]] = load i32, ptr %[[IS_MOST_DERIVED_ADDR]] // WIN32: %[[IS_MOST_DERIVED:.*]] = load i32, ptr %[[IS_MOST_DERIVED_ADDR]]
// WIN32: %[[IS_MOST_DERIVED_i1:.*]] = icmp ne i32 %[[IS_MOST_DERIVED]], 0 // WIN32: %[[IS_MOST_DERIVED_i1:.*]] = icmp ne i32 %[[IS_MOST_DERIVED]], 0
// WIN32: br i1 %[[IS_MOST_DERIVED_i1]] // WIN32: br i1 %[[IS_MOST_DERIVED_i1]]
// //
// WIN32: store {{.*}} @"??_8C@inalloca_virt@@7B@" // WIN32: store {{.*}} @"??_8C@inalloca_virt@@7B@"
// WIN32: %[[ARG2:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG2:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: store i32 2, ptr %[[ARG2]] // WIN32: store i32 2, ptr %[[ARG2]]
// WIN32: %[[ARG4:.*]] = getelementptr {{.*}} %[[ARGMEM]] // WIN32: %[[ARG4:.*]] = getelementptr {{.*}} %[[ARGMEM]]
// WIN32: store ptr %[[TMP]], ptr %[[ARG4]] // WIN32: store ptr %[[TMP]], ptr %[[ARG4]]
// WIN32: call {{.*}} @"??0A@inalloca_virt@@QAE@UQ@@H0$$QAU2@@Z"(ptr{{[^,]*}}, ptr inalloca(<{{.*}}>) %[[ARGMEM]]) // WIN32: call {{.*}} @"??0A@inalloca_virt@@QAE@UQ@@H0$$QAU2@@Z"(ptr{{[^,]*}}, ptr inalloca(<{{.*}}>) %[[ARGMEM]])
// WIN32: call void @llvm.stackrestore( // WIN32: call void @llvm.stackrestore.p0(
// WIN32: br // WIN32: br
// //
// WIN32: call {{.*}} @"??0Z@@QAE@XZ"( // WIN32: call {{.*}} @"??0Z@@QAE@XZ"(
// WIN32: call {{.*}} @"??0Z@@QAE@XZ"( // WIN32: call {{.*}} @"??0Z@@QAE@XZ"(
// WIN32: call {{.*}} @"??1Q@@QAE@XZ"( // WIN32: call {{.*}} @"??1Q@@QAE@XZ"(
// On Win64, the Q arguments would be destroyed in the callee. We don't yet // On Win64, the Q arguments would be destroyed in the callee. We don't yet
// support that in the non-inlined case, so we force inlining. // support that in the non-inlined case, so we force inlining.
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

clang/test/CodeGenCXX/microsoft-abi-arg-order.cpp

Show All 33 Lines
void call_foo() { void call_foo() {
foo(A(1), A(2), A(3)); foo(A(1), A(2), A(3));
} }
// Order of evaluation should be right to left, and we should clean up the right // Order of evaluation should be right to left, and we should clean up the right
// things as we unwind. // things as we unwind.
// //
// X86-LABEL: define dso_local void @"?call_foo@@YAXXZ"() // X86-LABEL: define dso_local void @"?call_foo@@YAXXZ"()
// X86: call ptr @llvm.stacksave() // X86: call ptr @llvm.stacksave.p0()
// X86: %[[argmem:[^ ]*]] = alloca inalloca [[argmem_ty]] // X86: %[[argmem:[^ ]*]] = alloca inalloca [[argmem_ty]]
// X86: %[[arg3:[^ ]*]] = getelementptr inbounds [[argmem_ty]], ptr %[[argmem]], i32 0, i32 2 // X86: %[[arg3:[^ ]*]] = getelementptr inbounds [[argmem_ty]], ptr %[[argmem]], i32 0, i32 2
// X86: call x86_thiscallcc noundef ptr @"??0A@@QAE@H@Z"(ptr {{[^,]*}} %[[arg3]], i32 noundef 3) // X86: call x86_thiscallcc noundef ptr @"??0A@@QAE@H@Z"(ptr {{[^,]*}} %[[arg3]], i32 noundef 3)
// X86: %[[arg2:[^ ]*]] = getelementptr inbounds [[argmem_ty]], ptr %[[argmem]], i32 0, i32 1 // X86: %[[arg2:[^ ]*]] = getelementptr inbounds [[argmem_ty]], ptr %[[argmem]], i32 0, i32 1
// X86: invoke x86_thiscallcc noundef ptr @"??0A@@QAE@H@Z"(ptr {{[^,]*}} %[[arg2]], i32 noundef 2) // X86: invoke x86_thiscallcc noundef ptr @"??0A@@QAE@H@Z"(ptr {{[^,]*}} %[[arg2]], i32 noundef 2)
// X86: %[[arg1:[^ ]*]] = getelementptr inbounds [[argmem_ty]], ptr %[[argmem]], i32 0, i32 0 // X86: %[[arg1:[^ ]*]] = getelementptr inbounds [[argmem_ty]], ptr %[[argmem]], i32 0, i32 0
// X86: invoke x86_thiscallcc noundef ptr @"??0A@@QAE@H@Z"(ptr {{[^,]*}} %[[arg1]], i32 noundef 1) // X86: invoke x86_thiscallcc noundef ptr @"??0A@@QAE@H@Z"(ptr {{[^,]*}} %[[arg1]], i32 noundef 1)
// X86: call void @"?foo@@YAXUA@@00@Z"(ptr inalloca([[argmem_ty]]) %[[argmem]]) // X86: call void @"?foo@@YAXUA@@00@Z"(ptr inalloca([[argmem_ty]]) %[[argmem]])
// X86: call void @llvm.stackrestore // X86: call void @llvm.stackrestore.p0
// X86: ret void // X86: ret void
// //
// lpad2: // lpad2:
// X86: cleanuppad within none [] // X86: cleanuppad within none []
// X86: call x86_thiscallcc void @"??1A@@QAE@XZ"(ptr {{[^,]*}} %[[arg2]]) // X86: call x86_thiscallcc void @"??1A@@QAE@XZ"(ptr {{[^,]*}} %[[arg2]])
// X86: cleanupret // X86: cleanupret
// //
// ehcleanup: // ehcleanup:
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clang/test/CodeGenCXX/microsoft-abi-eh-cleanups.cpp

Show All 10 Lines
int TakesTwo(A a, A b); int TakesTwo(A a, A b);
void HasEHCleanup() { void HasEHCleanup() {
TakesTwo(getA(), getA()); TakesTwo(getA(), getA());
} }
// With exceptions, we need to clean up at least one of these temporaries. // With exceptions, we need to clean up at least one of these temporaries.
// WIN32-LABEL: define dso_local void @"?HasEHCleanup@@YAXXZ"() {{.*}} { // WIN32-LABEL: define dso_local void @"?HasEHCleanup@@YAXXZ"() {{.*}} {
// WIN32: %[[base:.*]] = call ptr @llvm.stacksave() // WIN32: %[[base:.*]] = call ptr @llvm.stacksave.p0()
// If this call throws, we have to restore the stack. // If this call throws, we have to restore the stack.
// WIN32: call void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}}) // WIN32: call void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}})
// If this call throws, we have to cleanup the first temporary. // If this call throws, we have to cleanup the first temporary.
// WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}}) // WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}})
// If this call throws, we have to cleanup the stacksave. // If this call throws, we have to cleanup the stacksave.
// WIN32: call noundef i32 @"?TakesTwo@@YAHUA@@0@Z" // WIN32: call noundef i32 @"?TakesTwo@@YAHUA@@0@Z"
// WIN32: call void @llvm.stackrestore // WIN32: call void @llvm.stackrestore
// WIN32: ret void // WIN32: ret void
// //
// There should be one dtor call for unwinding from the second getA. // There should be one dtor call for unwinding from the second getA.
// WIN32: cleanuppad // WIN32: cleanuppad
// WIN32: call x86_thiscallcc void @"??1A@@QAE@XZ"({{.*}}) // WIN32: call x86_thiscallcc void @"??1A@@QAE@XZ"({{.*}})
// WIN32-NOT: @"??1A@@QAE@XZ" // WIN32-NOT: @"??1A@@QAE@XZ"
// WIN32: } // WIN32: }
// This test verifies the fix for a crash that occurred after // This test verifies the fix for a crash that occurred after
// fa87fa97fb79. // fa87fa97fb79.
void HasEHCleanupNoexcept() noexcept { void HasEHCleanupNoexcept() noexcept {
TakesTwo(getA(), getA()); TakesTwo(getA(), getA());
} }
// With exceptions, we need to clean up at least one of these temporaries. // With exceptions, we need to clean up at least one of these temporaries.
// WIN32-LABEL: define dso_local void @"?HasEHCleanupNoexcept@@YAXXZ"() {{.*}} { // WIN32-LABEL: define dso_local void @"?HasEHCleanupNoexcept@@YAXXZ"() {{.*}} {
// WIN32: %[[base:.*]] = call ptr @llvm.stacksave() // WIN32: %[[base:.*]] = call ptr @llvm.stacksave.p0()
// WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}}) // WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}})
// WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}}) // WIN32: invoke void @"?getA@@YA?AUA@@XZ"(ptr sret(%struct.A) align 4 %{{.*}})
// WIN32: invoke noundef i32 @"?TakesTwo@@YAHUA@@0@Z" // WIN32: invoke noundef i32 @"?TakesTwo@@YAHUA@@0@Z"
// WIN32: call void @llvm.stackrestore // WIN32: call void @llvm.stackrestore
// WIN32: ret void // WIN32: ret void
// //
// Since all the calls terminate, there should be no dtors on the unwind // Since all the calls terminate, there should be no dtors on the unwind
// WIN32: cleanuppad // WIN32: cleanuppad
// WIN32-NOT: @"??1A@@QAE@XZ" // WIN32-NOT: @"??1A@@QAE@XZ"
// WIN32: } // WIN32: }
void TakeRef(const A &a); void TakeRef(const A &a);
int HasDeactivatedCleanups() { int HasDeactivatedCleanups() {
return TakesTwo((TakeRef(A()), A()), (TakeRef(A()), A())); return TakesTwo((TakeRef(A()), A()), (TakeRef(A()), A()));
} }
// WIN32-LABEL: define dso_local noundef i32 @"?HasDeactivatedCleanups@@YAHXZ"() {{.*}} { // WIN32-LABEL: define dso_local noundef i32 @"?HasDeactivatedCleanups@@YAHXZ"() {{.*}} {
// WIN32: %[[isactive:.*]] = alloca i1 // WIN32: %[[isactive:.*]] = alloca i1
// WIN32: call ptr @llvm.stacksave() // WIN32: call ptr @llvm.stacksave.p0()
// WIN32: %[[argmem:.*]] = alloca inalloca [[argmem_ty:<{ %struct.A, %struct.A }>]] // WIN32: %[[argmem:.*]] = alloca inalloca [[argmem_ty:<{ %struct.A, %struct.A }>]]
// WIN32: %[[arg1:.*]] = getelementptr inbounds [[argmem_ty]], ptr %[[argmem]], i32 0, i32 1 // WIN32: %[[arg1:.*]] = getelementptr inbounds [[argmem_ty]], ptr %[[argmem]], i32 0, i32 1
// WIN32: call x86_thiscallcc noundef ptr @"??0A@@QAE@XZ" // WIN32: call x86_thiscallcc noundef ptr @"??0A@@QAE@XZ"
// WIN32: invoke void @"?TakeRef@@YAXABUA@@@Z" // WIN32: invoke void @"?TakeRef@@YAXABUA@@@Z"
// //
// WIN32: invoke x86_thiscallcc noundef ptr @"??0A@@QAE@XZ"(ptr {{[^,]*}} %[[arg1]]) // WIN32: invoke x86_thiscallcc noundef ptr @"??0A@@QAE@XZ"(ptr {{[^,]*}} %[[arg1]])
// WIN32: store i1 true, ptr %[[isactive]] // WIN32: store i1 true, ptr %[[isactive]]
// //
Show All 19 Lines
int CouldThrow(); int CouldThrow();
int HasConditionalCleanup(bool cond) { int HasConditionalCleanup(bool cond) {
return (cond ? TakesTwo(A(), A()) : CouldThrow()); return (cond ? TakesTwo(A(), A()) : CouldThrow());
} }
// WIN32-LABEL: define dso_local noundef i32 @"?HasConditionalCleanup@@YAH_N@Z"(i1 noundef zeroext %{{.*}}) {{.*}} { // WIN32-LABEL: define dso_local noundef i32 @"?HasConditionalCleanup@@YAH_N@Z"(i1 noundef zeroext %{{.*}}) {{.*}} {
// WIN32: store i1 false // WIN32: store i1 false
// WIN32: br i1 // WIN32: br i1
// WIN32: call ptr @llvm.stacksave() // WIN32: call ptr @llvm.stacksave.p0()
// WIN32: call x86_thiscallcc noundef ptr @"??0A@@QAE@XZ"(ptr {{[^,]*}} %{{.*}}) // WIN32: call x86_thiscallcc noundef ptr @"??0A@@QAE@XZ"(ptr {{[^,]*}} %{{.*}})
// WIN32: store i1 true // WIN32: store i1 true
// WIN32: invoke x86_thiscallcc noundef ptr @"??0A@@QAE@XZ"(ptr {{[^,]*}} %{{.*}}) // WIN32: invoke x86_thiscallcc noundef ptr @"??0A@@QAE@XZ"(ptr {{[^,]*}} %{{.*}})
// WIN32: call noundef i32 @"?TakesTwo@@YAHUA@@0@Z" // WIN32: call noundef i32 @"?TakesTwo@@YAHUA@@0@Z"
// //
// WIN32: call void @llvm.stackrestore // WIN32: call void @llvm.stackrestore
// //
// WIN32: call noundef i32 @"?CouldThrow@@YAHXZ"() // WIN32: call noundef i32 @"?CouldThrow@@YAHXZ"()
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clang/test/CodeGenCXX/vla-consruct.cpp

Show All 29 Linesvoid test(int n) {
// CHECK-NEXT: [[exn_slot:%.+]] = alloca ptr // CHECK-NEXT: [[exn_slot:%.+]] = alloca ptr
// CHECK-NEXT: [[ehselector_slot:%.+]] = alloca i32 // CHECK-NEXT: [[ehselector_slot:%.+]] = alloca i32
// CHECK-NEXT: store i32 [[n]], ptr [[n_addr]] // CHECK-NEXT: store i32 [[n]], ptr [[n_addr]]
// CHECK-NEXT: [[t0:%.+]] = load i32, ptr [[n_addr]] // CHECK-NEXT: [[t0:%.+]] = load i32, ptr [[n_addr]]
// CHECK-NEXT: [[t1:%.+]] = zext i32 [[t0]] to i64 // CHECK-NEXT: [[t1:%.+]] = zext i32 [[t0]] to i64
// CHECK-NEXT: [[t2:%.+]] = load i32, ptr [[n_addr]] // CHECK-NEXT: [[t2:%.+]] = load i32, ptr [[n_addr]]
// CHECK-NEXT: [[add:%.+]] = add nsw i32 [[t2]], 1 // CHECK-NEXT: [[add:%.+]] = add nsw i32 [[t2]], 1
// CHECK-NEXT: [[t3:%.+]] = zext i32 [[add]] to i64 // CHECK-NEXT: [[t3:%.+]] = zext i32 [[add]] to i64
// CHECK-NEXT: [[t4:%.+]] = call ptr @llvm.stacksave() // CHECK-NEXT: [[t4:%.+]] = call ptr @llvm.stacksave.p0()
// CHECK-NEXT: store ptr [[t4]], ptr [[saved_stack]] // CHECK-NEXT: store ptr [[t4]], ptr [[saved_stack]]
// CHECK-NEXT: [[t5:%.+]] = mul nuw i64 [[t1]], [[t3]] // CHECK-NEXT: [[t5:%.+]] = mul nuw i64 [[t1]], [[t3]]
// CHECK-NEXT: [[vla:%.+]] = alloca [[struct_S]], i64 [[t5]] // CHECK-NEXT: [[vla:%.+]] = alloca [[struct_S]], i64 [[t5]]
// CHECK-NEXT: store i64 [[t1]], ptr [[vla_expr]] // CHECK-NEXT: store i64 [[t1]], ptr [[vla_expr]]
// CHECK-NEXT: store i64 [[t3]], ptr [[vla_expr1]] // CHECK-NEXT: store i64 [[t3]], ptr [[vla_expr1]]
// CHECK-NEXT: [[t6:%.+]] = mul nuw i64 [[t1]], [[t3]] // CHECK-NEXT: [[t6:%.+]] = mul nuw i64 [[t1]], [[t3]]
// CHECK-NEXT: [[isempty:%.+]] = icmp eq i64 [[t6]], 0 // CHECK-NEXT: [[isempty:%.+]] = icmp eq i64 [[t6]], 0
// CHECK-NEXT: br i1 [[isempty]], label %[[arrayctor_cont:.+]], label %[[new_ctorloop:.+]] // CHECK-NEXT: br i1 [[isempty]], label %[[arrayctor_cont:.+]], label %[[new_ctorloop:.+]]
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesvoid test(int n) {
// CHECK-NEXT: [[arraydestroy_elementPast:%.+]] = phi ptr [ [[t17]], %[[invoke_cont]] ], [ [[arraydestroy_element:%.+]], %[[arraydestroy_body]] ] // CHECK-NEXT: [[arraydestroy_elementPast:%.+]] = phi ptr [ [[t17]], %[[invoke_cont]] ], [ [[arraydestroy_element:%.+]], %[[arraydestroy_body]] ]
// CHECK-NEXT: [[arraydestroy_element]] = getelementptr inbounds [[struct_S]], ptr [[arraydestroy_elementPast]] // CHECK-NEXT: [[arraydestroy_element]] = getelementptr inbounds [[struct_S]], ptr [[arraydestroy_elementPast]]
// CHECK-NEXT: call void @[[dtor:.+]](ptr {{[^,]*}} [[arraydestroy_element]]) // CHECK-NEXT: call void @[[dtor:.+]](ptr {{[^,]*}} [[arraydestroy_element]])
// CHECK-NEXT: [[arraydestroy_done:%.+]] = icmp eq ptr [[arraydestroy_element]], [[vla]] // CHECK-NEXT: [[arraydestroy_done:%.+]] = icmp eq ptr [[arraydestroy_element]], [[vla]]
// CHECK-NEXT: br i1 [[arraydestroy_done]], label %[[arraydestroy_done2]], label %[[arraydestroy_body]] // CHECK-NEXT: br i1 [[arraydestroy_done]], label %[[arraydestroy_done2]], label %[[arraydestroy_body]]
// CHECK: [[arraydestroy_done2]] // CHECK: [[arraydestroy_done2]]
// CHECK-NEXT: [[t17:%.+]] = load ptr, ptr [[saved_stack]] // CHECK-NEXT: [[t17:%.+]] = load ptr, ptr [[saved_stack]]
// CHECK-NEXT: call void @llvm.stackrestore(ptr [[t17]]) // CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[t17]])
// CHECK: ret void // CHECK: ret void
// CHECK: [[lpad]] // CHECK: [[lpad]]
// CHECK-NEXT: [[t19:%.+]] = landingpad { ptr, i32 } // CHECK-NEXT: [[t19:%.+]] = landingpad { ptr, i32 }
// CHECK: [[t20:%.+]] = extractvalue { ptr, i32 } [[t19]], 0 // CHECK: [[t20:%.+]] = extractvalue { ptr, i32 } [[t19]], 0
// CHECK-NEXT: store ptr [[t20]], ptr [[exn_slot]] // CHECK-NEXT: store ptr [[t20]], ptr [[exn_slot]]
// CHECK-NEXT: [[t21:%.+]] = extractvalue { ptr, i32 } [[t19]], 1 // CHECK-NEXT: [[t21:%.+]] = extractvalue { ptr, i32 } [[t19]], 1
// CHECK-NEXT: store i32 [[t21]], ptr [[ehselector_slot]] // CHECK-NEXT: store i32 [[t21]], ptr [[ehselector_slot]]
Show All 35 Lines

clang/test/CodeGenCXX/vla-lambda-capturing.cpp

Show All 31 Lines
} }
// CHECK: void [[G_LAMBDA]](ptr // CHECK: void [[G_LAMBDA]](ptr
// CHECK: [[THIS:%.+]] = load ptr, ptr // CHECK: [[THIS:%.+]] = load ptr, ptr
// CHECK: [[N_ADDR:%.+]] = getelementptr inbounds [[CAP_TYPE1]], ptr [[THIS]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[N_ADDR:%.+]] = getelementptr inbounds [[CAP_TYPE1]], ptr [[THIS]], i{{.+}} 0, i{{.+}} 0
// CHECK: [[N:%.+]] = load [[INTPTR_T]], ptr [[N_ADDR]] // CHECK: [[N:%.+]] = load [[INTPTR_T]], ptr [[N_ADDR]]
// CHECK: [[BUFFER_ADDR:%.+]] = getelementptr inbounds [[CAP_TYPE1]], ptr [[THIS]], i{{.+}} 0, i{{.+}} 1 // CHECK: [[BUFFER_ADDR:%.+]] = getelementptr inbounds [[CAP_TYPE1]], ptr [[THIS]], i{{.+}} 0, i{{.+}} 1
// CHECK: [[BUFFER:%.+]] = load ptr, ptr [[BUFFER_ADDR]] // CHECK: [[BUFFER:%.+]] = load ptr, ptr [[BUFFER_ADDR]]
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: alloca [[INTPTR_T]], [[INTPTR_T]] [[N]] // CHECK: alloca [[INTPTR_T]], [[INTPTR_T]] [[N]]
// CHECK: call void @llvm.stackrestore( // CHECK: call void @llvm.stackrestore.p0(
// CHECK: ret void // CHECK: ret void
template <typename T> template <typename T>
void f(T n, T m) { void f(T n, T m) {
intptr_t buffer[n + m]; intptr_t buffer[n + m];
[&buffer]() { [&buffer]() {
__typeof(buffer) x; __typeof(buffer) x;
}(); }();
Show All 26 Linesint main() {
// CHECK: call {{.*}}void [[B_INT:@.+]]([[INTPTR_T]] noundef [[INTPTR_T_ATTR]]12, [[INTPTR_T]] noundef [[INTPTR_T_ATTR]]13) // CHECK: call {{.*}}void [[B_INT:@.+]]([[INTPTR_T]] noundef [[INTPTR_T_ATTR]]12, [[INTPTR_T]] noundef [[INTPTR_T_ATTR]]13)
b((intptr_t)12, (intptr_t)13); b((intptr_t)12, (intptr_t)13);
// CHECK: ret i32 0 // CHECK: ret i32 0
return 0; return 0;
} }
// CHECK: define linkonce_odr {{.*}}void [[F_INT]]([[INTPTR_T]] // CHECK: define linkonce_odr {{.*}}void [[F_INT]]([[INTPTR_T]]
// CHECK: [[SIZE:%.+]] = add // CHECK: [[SIZE:%.+]] = add
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: [[BUFFER_ADDR:%.+]] = alloca [[INTPTR_T]], [[INTPTR_T]] [[SIZE]] // CHECK: [[BUFFER_ADDR:%.+]] = alloca [[INTPTR_T]], [[INTPTR_T]] [[SIZE]]
// CHECK: [[CAP_SIZE_REF:%.+]] = getelementptr inbounds [[CAP_TYPE2]], ptr [[CAP_ARG:%.+]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[CAP_SIZE_REF:%.+]] = getelementptr inbounds [[CAP_TYPE2]], ptr [[CAP_ARG:%.+]], i{{.+}} 0, i{{.+}} 0
// CHECK: store [[INTPTR_T]] [[SIZE]], ptr [[CAP_SIZE_REF]] // CHECK: store [[INTPTR_T]] [[SIZE]], ptr [[CAP_SIZE_REF]]
// CHECK: [[CAP_BUFFER_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE2]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 1 // CHECK: [[CAP_BUFFER_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE2]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 1
// CHECK: store ptr [[BUFFER_ADDR]], ptr [[CAP_BUFFER_ADDR_REF]] // CHECK: store ptr [[BUFFER_ADDR]], ptr [[CAP_BUFFER_ADDR_REF]]
// CHECK: call{{.*}} void [[F_INT_LAMBDA:@.+]](ptr {{[^,]*}} [[CAP_ARG]]) // CHECK: call{{.*}} void [[F_INT_LAMBDA:@.+]](ptr {{[^,]*}} [[CAP_ARG]])
// CHECK: call void @llvm.stackrestore( // CHECK: call void @llvm.stackrestore.p0(
// CHECK: ret void // CHECK: ret void
// CHECK: void [[B_INT]]([[INTPTR_T]] // CHECK: void [[B_INT]]([[INTPTR_T]]
// CHECK: [[SIZE1:%.+]] = call {{.*}}[[INTPTR_T]] // CHECK: [[SIZE1:%.+]] = call {{.*}}[[INTPTR_T]]
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: [[BUFFER2_ADDR:%.+]] = alloca [[INTPTR_T]], [[INTPTR_T]] [[SIZE1]] // CHECK: [[BUFFER2_ADDR:%.+]] = alloca [[INTPTR_T]], [[INTPTR_T]] [[SIZE1]]
// CHECK: [[SIZE2:%.+]] = add // CHECK: [[SIZE2:%.+]] = add
// CHECK: [[BUFFER1_ADDR:%.+]] = alloca [[INTPTR_T]], [[INTPTR_T]] // CHECK: [[BUFFER1_ADDR:%.+]] = alloca [[INTPTR_T]], [[INTPTR_T]]
// CHECK: [[CAP_N_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG:%.+]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[CAP_N_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG:%.+]], i{{.+}} 0, i{{.+}} 0
// CHECK: store ptr {{%.+}}, ptr [[CAP_N_ADDR_REF]] // CHECK: store ptr {{%.+}}, ptr [[CAP_N_ADDR_REF]]
// CHECK: [[CAP_SIZE2_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 1 // CHECK: [[CAP_SIZE2_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 1
// CHECK: store i{{[0-9]+}} [[SIZE2]], ptr [[CAP_SIZE2_REF]] // CHECK: store i{{[0-9]+}} [[SIZE2]], ptr [[CAP_SIZE2_REF]]
// CHECK: [[CAP_SIZE1_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 2 // CHECK: [[CAP_SIZE1_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 2
// CHECK: store i{{[0-9]+}} [[SIZE1]], ptr [[CAP_SIZE1_REF]] // CHECK: store i{{[0-9]+}} [[SIZE1]], ptr [[CAP_SIZE1_REF]]
// CHECK: [[CAP_BUFFER1_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 3 // CHECK: [[CAP_BUFFER1_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 3
// CHECK: store ptr [[BUFFER1_ADDR]], ptr [[CAP_BUFFER1_ADDR_REF]] // CHECK: store ptr [[BUFFER1_ADDR]], ptr [[CAP_BUFFER1_ADDR_REF]]
// CHECK: [[CAP_BUFFER2_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 4 // CHECK: [[CAP_BUFFER2_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[CAP_ARG]], i{{.+}} 0, i{{.+}} 4
// CHECK: store ptr [[BUFFER2_ADDR]], ptr [[CAP_BUFFER2_ADDR_REF]] // CHECK: store ptr [[BUFFER2_ADDR]], ptr [[CAP_BUFFER2_ADDR_REF]]
// CHECK: call{{.*}} void [[B_INT_LAMBDA:@.+]](ptr {{[^,]*}} [[CAP_ARG]]) // CHECK: call{{.*}} void [[B_INT_LAMBDA:@.+]](ptr {{[^,]*}} [[CAP_ARG]])
// CHECK: call void @llvm.stackrestore( // CHECK: call void @llvm.stackrestore.p0(
// CHECK: ret void // CHECK: ret void
// CHECK: define linkonce_odr{{.*}} void [[F_INT_LAMBDA]](ptr // CHECK: define linkonce_odr{{.*}} void [[F_INT_LAMBDA]](ptr
// CHECK: [[THIS:%.+]] = load ptr, ptr // CHECK: [[THIS:%.+]] = load ptr, ptr
// CHECK: [[SIZE_REF:%.+]] = getelementptr inbounds [[CAP_TYPE2]], ptr [[THIS]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[SIZE_REF:%.+]] = getelementptr inbounds [[CAP_TYPE2]], ptr [[THIS]], i{{.+}} 0, i{{.+}} 0
// CHECK: [[SIZE:%.+]] = load [[INTPTR_T]], ptr [[SIZE_REF]] // CHECK: [[SIZE:%.+]] = load [[INTPTR_T]], ptr [[SIZE_REF]]
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: alloca [[INTPTR_T]], [[INTPTR_T]] [[SIZE]] // CHECK: alloca [[INTPTR_T]], [[INTPTR_T]] [[SIZE]]
// CHECK: call void @llvm.stackrestore( // CHECK: call void @llvm.stackrestore.p0(
// CHECK: ret void // CHECK: ret void
// CHECK: define linkonce_odr{{.*}} void [[B_INT_LAMBDA]](ptr // CHECK: define linkonce_odr{{.*}} void [[B_INT_LAMBDA]](ptr
// CHECK: [[SIZE2_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[THIS:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // CHECK: [[SIZE2_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[THIS:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
// CHECK: [[SIZE2:%.+]] = load i{{[0-9]+}}, ptr [[SIZE2_REF]] // CHECK: [[SIZE2:%.+]] = load i{{[0-9]+}}, ptr [[SIZE2_REF]]
// CHECK: [[SIZE1_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[THIS]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 // CHECK: [[SIZE1_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[THIS]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
// CHECK: [[SIZE1:%.+]] = load i{{[0-9]+}}, ptr [[SIZE1_REF]] // CHECK: [[SIZE1:%.+]] = load i{{[0-9]+}}, ptr [[SIZE1_REF]]
// CHECK: [[BUFFER1_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[THIS]], i{{[0-9]+}} 0, i{{[0-9]+}} 3 // CHECK: [[BUFFER1_ADDR_REF:%.+]] = getelementptr inbounds [[CAP_TYPE3]], ptr [[THIS]], i{{[0-9]+}} 0, i{{[0-9]+}} 3
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clang/test/CodeGenObjC/arc.m

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
id x[n]; id x[n];
// Capture the VLA size. // Capture the VLA size.
// CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[N]], align 4 // CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[N]], align 4
// CHECK-NEXT: [[DIM:%.*]] = zext i32 [[T0]] to i64 // CHECK-NEXT: [[DIM:%.*]] = zext i32 [[T0]] to i64
// Save the stack pointer. // Save the stack pointer.
// CHECK-NEXT: [[T0:%.*]] = call ptr @llvm.stacksave() // CHECK-NEXT: [[T0:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK-NEXT: store ptr [[T0]], ptr [[SAVED_STACK]] // CHECK-NEXT: store ptr [[T0]], ptr [[SAVED_STACK]]
// Allocate the VLA. // Allocate the VLA.
// CHECK-NEXT: [[VLA:%.*]] = alloca ptr, i64 [[DIM]], align 16 // CHECK-NEXT: [[VLA:%.*]] = alloca ptr, i64 [[DIM]], align 16
// Store the VLA #elements expression. // Store the VLA #elements expression.
// CHECK-NEXT: store i64 [[DIM]], ptr [[VLA_EXPR]], align 8 // CHECK-NEXT: store i64 [[DIM]], ptr [[VLA_EXPR]], align 8
Show All 9 Lines
// CHECK: [[AFTER:%.*]] = phi ptr [ [[END]], {{%.*}} ], [ [[CUR:%.*]], {{%.*}} ] // CHECK: [[AFTER:%.*]] = phi ptr [ [[END]], {{%.*}} ], [ [[CUR:%.*]], {{%.*}} ]
// CHECK-NEXT: [[CUR:%.*]] = getelementptr inbounds ptr, ptr [[AFTER]], i64 -1 // CHECK-NEXT: [[CUR:%.*]] = getelementptr inbounds ptr, ptr [[AFTER]], i64 -1
// CHECK-NEXT: [[T0:%.*]] = load ptr, ptr [[CUR]] // CHECK-NEXT: [[T0:%.*]] = load ptr, ptr [[CUR]]
// CHECK-NEXT: call void @llvm.objc.release(ptr [[T0]]) [[NUW]], !clang.imprecise_release // CHECK-NEXT: call void @llvm.objc.release(ptr [[T0]]) [[NUW]], !clang.imprecise_release
// CHECK-NEXT: [[EQ:%.*]] = icmp eq ptr [[CUR]], [[VLA]] // CHECK-NEXT: [[EQ:%.*]] = icmp eq ptr [[CUR]], [[VLA]]
// CHECK-NEXT: br i1 [[EQ]], // CHECK-NEXT: br i1 [[EQ]],
// CHECK: [[T0:%.*]] = load ptr, ptr [[SAVED_STACK]] // CHECK: [[T0:%.*]] = load ptr, ptr [[SAVED_STACK]]
// CHECK-NEXT: call void @llvm.stackrestore(ptr [[T0]]) // CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[T0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
} }
void test21(unsigned n) { void test21(unsigned n) {
// CHECK-LABEL: define{{.*}} void @test21 // CHECK-LABEL: define{{.*}} void @test21
// CHECK: [[N:%.*]] = alloca i32, align 4 // CHECK: [[N:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr // CHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr
// CHECK-NEXT: [[VLA_EXPR:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[VLA_EXPR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i32 {{%.*}}, ptr [[N]], align 4 // CHECK-NEXT: store i32 {{%.*}}, ptr [[N]], align 4
id x[2][n][3]; id x[2][n][3];
// Capture the VLA size. // Capture the VLA size.
// CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[N]], align 4 // CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[N]], align 4
// CHECK-NEXT: [[DIM:%.*]] = zext i32 [[T0]] to i64 // CHECK-NEXT: [[DIM:%.*]] = zext i32 [[T0]] to i64
// CHECK-NEXT: [[T0:%.*]] = call ptr @llvm.stacksave() // CHECK-NEXT: [[T0:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK-NEXT: store ptr [[T0]], ptr [[SAVED_STACK]] // CHECK-NEXT: store ptr [[T0]], ptr [[SAVED_STACK]]
// Allocate the VLA. // Allocate the VLA.
// CHECK-NEXT: [[T0:%.*]] = mul nuw i64 2, [[DIM]] // CHECK-NEXT: [[T0:%.*]] = mul nuw i64 2, [[DIM]]
// CHECK-NEXT: [[VLA:%.*]] = alloca [3 x ptr], i64 [[T0]], align 16 // CHECK-NEXT: [[VLA:%.*]] = alloca [3 x ptr], i64 [[T0]], align 16
// Store the VLA #elements expression. // Store the VLA #elements expression.
Show All 15 Lines
// CHECK: [[AFTER:%.*]] = phi ptr [ [[END]], {{%.*}} ], [ [[CUR:%.*]], {{%.*}} ] // CHECK: [[AFTER:%.*]] = phi ptr [ [[END]], {{%.*}} ], [ [[CUR:%.*]], {{%.*}} ]
// CHECK-NEXT: [[CUR:%.*]] = getelementptr inbounds ptr, ptr [[AFTER]], i64 -1 // CHECK-NEXT: [[CUR:%.*]] = getelementptr inbounds ptr, ptr [[AFTER]], i64 -1
// CHECK-NEXT: [[T0:%.*]] = load ptr, ptr [[CUR]] // CHECK-NEXT: [[T0:%.*]] = load ptr, ptr [[CUR]]
// CHECK-NEXT: call void @llvm.objc.release(ptr [[T0]]) [[NUW]], !clang.imprecise_release // CHECK-NEXT: call void @llvm.objc.release(ptr [[T0]]) [[NUW]], !clang.imprecise_release
// CHECK-NEXT: [[EQ:%.*]] = icmp eq ptr [[CUR]], [[BEGIN]] // CHECK-NEXT: [[EQ:%.*]] = icmp eq ptr [[CUR]], [[BEGIN]]
// CHECK-NEXT: br i1 [[EQ]], // CHECK-NEXT: br i1 [[EQ]],
// CHECK: [[T0:%.*]] = load ptr, ptr [[SAVED_STACK]] // CHECK: [[T0:%.*]] = load ptr, ptr [[SAVED_STACK]]
// CHECK-NEXT: call void @llvm.stackrestore(ptr [[T0]]) // CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[T0]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
} }
// rdar://problem/8922540 // rdar://problem/8922540
// Note that we no longer emit .release_ivars flags. // Note that we no longer emit .release_ivars flags.
// rdar://problem/12492434 // rdar://problem/12492434
// Note that we set the flag saying that we need destruction *and* // Note that we set the flag saying that we need destruction *and*
// the flag saying that we don't also need construction. // the flag saying that we don't also need construction.
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clang/test/OpenMP/amdgcn_target_device_vla.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[I4:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[I4:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[N:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[N:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
// CHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8, addrspace(5)
// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[J11:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[J11:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr
// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr // CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr
// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr // CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr
// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr // CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr
// CHECK-NEXT: [[M_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_ADDR]] to ptr // CHECK-NEXT: [[M_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[M_ADDR]] to ptr
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// CHECK: omp.inner.for.body: // CHECK: omp.inner.for.body:
// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 // CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK-NEXT: store i32 [[ADD]], ptr [[I4_ASCAST]], align 4 // CHECK-NEXT: store i32 [[ADD]], ptr [[I4_ASCAST]], align 4
// CHECK-NEXT: store i32 10, ptr [[N_ASCAST]], align 4 // CHECK-NEXT: store i32 10, ptr [[N_ASCAST]], align 4
// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[N_ASCAST]], align 4 // CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[N_ASCAST]], align 4
// CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
// CHECK-NEXT: [[TMP16:%.*]] = call ptr @llvm.stacksave() // CHECK-NEXT: [[TMP16:%.*]] = call ptr addrspace(5) @llvm.stacksave.p5()
// CHECK-NEXT: store ptr [[TMP16]], ptr [[SAVED_STACK_ASCAST]], align 8 // CHECK-NEXT: store ptr addrspace(5) [[TMP16]], ptr [[SAVED_STACK_ASCAST]], align 4
// CHECK-NEXT: [[VLA7:%.*]] = alloca i32, i64 [[TMP15]], align 4, addrspace(5) // CHECK-NEXT: [[VLA7:%.*]] = alloca i32, i64 [[TMP15]], align 4, addrspace(5)
// CHECK-NEXT: [[VLA7_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA7]] to ptr // CHECK-NEXT: [[VLA7_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA7]] to ptr
// CHECK-NEXT: store i64 [[TMP15]], ptr [[__VLA_EXPR0_ASCAST]], align 8 // CHECK-NEXT: store i64 [[TMP15]], ptr [[__VLA_EXPR0_ASCAST]], align 8
// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4_ASCAST]], align 4 // CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4_ASCAST]], align 4
// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4_ASCAST]], align 4 // CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4_ASCAST]], align 4
// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 // CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM]] // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM]]
// CHECK-NEXT: store i32 [[TMP17]], ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: store i32 [[TMP17]], ptr [[ARRAYIDX]], align 4
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// CHECK-NEXT: store i32 [[ADD19]], ptr [[ARRAYIDX18]], align 4 // CHECK-NEXT: store i32 [[ADD19]], ptr [[ARRAYIDX18]], align 4
// CHECK-NEXT: br label [[FOR_INC20:%.*]] // CHECK-NEXT: br label [[FOR_INC20:%.*]]
// CHECK: for.inc20: // CHECK: for.inc20:
// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[J11_ASCAST]], align 4 // CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[J11_ASCAST]], align 4
// CHECK-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP30]], 1 // CHECK-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP30]], 1
// CHECK-NEXT: store i32 [[INC21]], ptr [[J11_ASCAST]], align 4 // CHECK-NEXT: store i32 [[INC21]], ptr [[J11_ASCAST]], align 4
// CHECK-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP17:![0-9]+]]
// CHECK: for.end22: // CHECK: for.end22:
// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[SAVED_STACK_ASCAST]], align 8 // CHECK-NEXT: [[TMP31:%.*]] = load ptr addrspace(5), ptr [[SAVED_STACK_ASCAST]], align 4
// CHECK-NEXT: call void @llvm.stackrestore(ptr [[TMP31]]) // CHECK-NEXT: call void @llvm.stackrestore.p5(ptr addrspace(5) [[TMP31]])
// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK: omp.body.continue: // CHECK: omp.body.continue:
// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK: omp.inner.for.inc: // CHECK: omp.inner.for.inc:
// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 // CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 // CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
// CHECK-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP32]], [[TMP33]] // CHECK-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP32]], [[TMP33]]
// CHECK-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV_ASCAST]], align 4 // CHECK-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV_ASCAST]], align 4
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clang/test/OpenMP/debug-info-openmp-array.cpp

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// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32 [[M]], ptr [[M_ADDR]], align 4 // CHECK1-NEXT: store i32 [[M]], ptr [[M_ADDR]], align 4
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[M_ADDR]], metadata [[META12:![0-9]+]], metadata !DIExpression()), !dbg [[DBG13:![0-9]+]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[M_ADDR]], metadata [[META12:![0-9]+]], metadata !DIExpression()), !dbg [[DBG13:![0-9]+]]
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[I]], metadata [[META14:![0-9]+]], metadata !DIExpression()), !dbg [[DBG15:![0-9]+]]
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[M_ADDR]], align 4, !dbg [[DBG16:![0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[M_ADDR]], align 4, !dbg [[DBG16:![0-9]+]]
// CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG17:![0-9]+]] // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG17:![0-9]+]]
// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave(), !dbg [[DBG17]] // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG17]]
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG17]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG17]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG17]] // CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG17]]
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG17]] // CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG17]]
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[__VLA_EXPR0]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20:![0-9]+]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[__VLA_EXPR0]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG20:![0-9]+]]
// CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA]], metadata [[META21:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25:![0-9]+]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA]], metadata [[META21:![0-9]+]], metadata !DIExpression()), !dbg [[DBG25:![0-9]+]]
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 3, ptr @_Z1fi.omp_outlined, ptr [[M_ADDR]], i64 [[TMP1]], ptr [[VLA]]), !dbg [[DBG26:![0-9]+]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 3, ptr @_Z1fi.omp_outlined, ptr [[M_ADDR]], i64 [[TMP1]], ptr [[VLA]]), !dbg [[DBG26:![0-9]+]]
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG27:![0-9]+]] // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG27:![0-9]+]]
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP3]]), !dbg [[DBG27]] // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP3]]), !dbg [[DBG27]]
// CHECK1-NEXT: ret void, !dbg [[DBG27]] // CHECK1-NEXT: ret void, !dbg [[DBG27]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_Z1fi.omp_outlined_debug__ // CHECK1-LABEL: define {{[^@]+}}@_Z1fi.omp_outlined_debug__
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[CEN:%.*]]) #[[ATTR3:[0-9]+]] !dbg [[DBG28:![0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[CEN:%.*]]) #[[ATTR3:[0-9]+]] !dbg [[DBG28:![0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp

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// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]] // CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1 // CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1
// CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP13]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP13]], align 16
// CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP13]] // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP13]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP16]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP16]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP96]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP96]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]]
// CHECK1: omp.arraycpy.done36: // CHECK1: omp.arraycpy.done36:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP105]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP105]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META12:![0-9]+]] // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !12
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !12
// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !12
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !12
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !12
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !12
// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR6]] // CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR6]]
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !12
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP12]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP12]], align 8
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META12]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !12
// CHECK1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP16]], ptr [[TMP15]], ptr [[TMP14]]) // CHECK1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP16]], ptr [[TMP15]], ptr [[TMP14]])
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 1 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 1
// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
// CHECK1-NEXT: [[TMP24:%.*]] = sext i32 [[TMP23]] to i64 // CHECK1-NEXT: [[TMP24:%.*]] = sext i32 [[TMP23]] to i64
// CHECK1-NEXT: [[LB_ADD_LEN_I:%.*]] = add nsw i64 -1, [[TMP24]] // CHECK1-NEXT: [[LB_ADD_LEN_I:%.*]] = add nsw i64 -1, [[TMP24]]
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8
// CHECK1-NEXT: [[ARRAYIDX2_I:%.*]] = getelementptr inbounds ptr, ptr [[TMP26]], i64 9 // CHECK1-NEXT: [[ARRAYIDX2_I:%.*]] = getelementptr inbounds ptr, ptr [[TMP26]], i64 9
// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[ARRAYIDX2_I]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[ARRAYIDX2_I]], align 8
// CHECK1-NEXT: [[ARRAYIDX3_I:%.*]] = getelementptr inbounds i8, ptr [[TMP27]], i64 [[LB_ADD_LEN_I]] // CHECK1-NEXT: [[ARRAYIDX3_I:%.*]] = getelementptr inbounds i8, ptr [[TMP27]], i64 [[LB_ADD_LEN_I]]
// CHECK1-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[ARRAYIDX3_I]] to i64 // CHECK1-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[ARRAYIDX3_I]] to i64
// CHECK1-NEXT: [[TMP29:%.*]] = ptrtoint ptr [[TMP20]] to i64 // CHECK1-NEXT: [[TMP29:%.*]] = ptrtoint ptr [[TMP20]] to i64
// CHECK1-NEXT: [[TMP30:%.*]] = sub i64 [[TMP28]], [[TMP29]] // CHECK1-NEXT: [[TMP30:%.*]] = sub i64 [[TMP28]], [[TMP29]]
// CHECK1-NEXT: [[TMP31:%.*]] = add nuw i64 [[TMP30]], 1 // CHECK1-NEXT: [[TMP31:%.*]] = add nuw i64 [[TMP30]], 1
// CHECK1-NEXT: [[TMP32:%.*]] = mul nuw i64 [[TMP31]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP32:%.*]] = mul nuw i64 [[TMP31]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: store i64 [[TMP31]], ptr @{{reduction_size[.].+[.]}}, align 8, !noalias [[META12]] // CHECK1-NEXT: store i64 [[TMP31]], ptr @{{reduction_size[.].+[.]}}, align 8, !noalias !12
// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP12]], align 8 // CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP12]], align 8
// CHECK1-NEXT: [[TMP34:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP16]], ptr [[TMP33]], ptr [[TMP20]]) // CHECK1-NEXT: [[TMP34:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP16]], ptr [[TMP33]], ptr [[TMP20]])
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[TMP35]], align 8
// CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[TMP36]], align 8 // CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[TMP36]], align 8
// CHECK1-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64 // CHECK1-NEXT: [[TMP38:%.*]] = ptrtoint ptr [[TMP37]] to i64
// CHECK1-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP20]] to i64 // CHECK1-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[TMP20]] to i64
// CHECK1-NEXT: [[TMP40:%.*]] = sub i64 [[TMP38]], [[TMP39]] // CHECK1-NEXT: [[TMP40:%.*]] = sub i64 [[TMP38]], [[TMP39]]
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[TMP34]], i64 [[TMP40]] // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr i8, ptr [[TMP34]], i64 [[TMP40]]
// CHECK1-NEXT: store ptr [[TMP4_I]], ptr [[TMP_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: store ptr [[TMP4_I]], ptr [[TMP_I]], align 8, !noalias !12
// CHECK1-NEXT: store ptr [[TMP41]], ptr [[TMP4_I]], align 8, !noalias [[META12]] // CHECK1-NEXT: store ptr [[TMP41]], ptr [[TMP4_I]], align 8, !noalias !12
// CHECK1-NEXT: ret i32 0 // CHECK1-NEXT: ret i32 0
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined.omp_outlined.omp.reduction.reduction_func // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l14.omp_outlined.omp_outlined.omp.reduction.reduction_func
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/for_reduction_codegen.cpp

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// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]]
// CHECK1: arrayctor.cont9: // CHECK1: arrayctor.cont9:
// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[VAR3]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[VAR3]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]])
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @main.omp_outlined.1, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[VEC]], ptr [[ARRS]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @main.omp_outlined.1, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[VEC]], ptr [[ARRS]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @main.omp_outlined.2, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[ARRS]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @main.omp_outlined.2, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[ARRS]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @main.omp_outlined.3, i64 10, i64 [[TMP2]], ptr [[VLA]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @main.omp_outlined.3, i64 10, i64 [[TMP2]], ptr [[VLA]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.4, ptr [[VAR2]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.4, ptr [[VAR2]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.5, ptr [[VAR2]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.5, ptr [[VAR2]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.6, ptr [[VAR2]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.6, ptr [[VAR2]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.7, ptr [[VAR2]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.7, ptr [[VAR2]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.8, ptr [[VVAR2]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.8, ptr [[VVAR2]])
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VAR3]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VAR3]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.9, ptr [[TMP5]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.9, ptr [[TMP5]])
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[VAR3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[VAR3]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.10, ptr [[TMP6]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.10, ptr [[TMP6]])
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VAR3]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VAR3]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.11, ptr [[TMP7]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.11, ptr [[TMP7]])
// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[VAR3]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[VAR3]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.12, ptr [[TMP8]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.12, ptr [[TMP8]])
// CHECK1-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() // CHECK1-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v()
// CHECK1-NEXT: store i32 [[CALL10]], ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 [[CALL10]], ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP9]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP9]])
// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[VVAR2]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[VVAR2]], i32 0, i32 0
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 5 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 5
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[ARRAYCTOR_CONT9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[ARRAYCTOR_CONT9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5:[0-9]+]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5:[0-9]+]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
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// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[TMP8]] // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[TMP8]]
// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX5]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX5]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64 // CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64
// CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]] // CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1 // CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1
// CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA7:%.*]] = alloca i32, i64 [[TMP13]], align 16 // CHECK1-NEXT: [[VLA7:%.*]] = alloca i32, i64 [[TMP13]], align 16
// CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[VLA7]], i64 [[TMP13]] // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[VLA7]], i64 [[TMP13]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA7]], [[TMP16]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA7]], [[TMP16]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP69]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP69]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA15]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA15]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE56]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE56]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done56: // CHECK1: arraydestroy.done56:
// CHECK1-NEXT: [[TMP70:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP70:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP70]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP70]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1.omp.reduction.reduction_func // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1.omp.reduction.reduction_func
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARRS_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARRS_ADDR]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4 // CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
// CHECK1-NEXT: [[TMP6:%.*]] = udiv exact i64 [[TMP5]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP6:%.*]] = udiv exact i64 [[TMP5]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP6]], align 16 // CHECK1-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP6]], align 16
// CHECK1-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[VLA3]], i64 [[TMP6]] // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[VLA3]], i64 [[TMP6]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA3]], [[TMP8]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA3]], [[TMP8]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN44]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN44]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE45:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE45:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done45: // CHECK1: arraydestroy.done45:
// CHECK1-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP42]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP42]])
// CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP44]]) // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP44]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.2.omp.reduction.reduction_func // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.2.omp.reduction.reduction_func
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] {
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// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8
// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP4]], i64 6 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP4]], i64 6
// CHECK1-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64
// CHECK1-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64 // CHECK1-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64
// CHECK1-NEXT: [[TMP7:%.*]] = sub i64 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[TMP7:%.*]] = sub i64 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: [[TMP8:%.*]] = sdiv exact i64 [[TMP7]], ptrtoint (ptr getelementptr ([[STRUCT_S]], ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP8:%.*]] = sdiv exact i64 [[TMP7]], ptrtoint (ptr getelementptr ([[STRUCT_S]], ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP9:%.*]] = add nuw i64 [[TMP8]], 1 // CHECK1-NEXT: [[TMP9:%.*]] = add nuw i64 [[TMP8]], 1
// CHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], ptrtoint (ptr getelementptr ([[STRUCT_S]], ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], ptrtoint (ptr getelementptr ([[STRUCT_S]], ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP11:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP11]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP11]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca [[STRUCT_S]], i64 [[TMP9]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca [[STRUCT_S]], i64 [[TMP9]], align 16
// CHECK1-NEXT: store i64 [[TMP9]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP9]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr [[STRUCT_S]], ptr [[VLA]], i64 [[TMP9]] // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr [[STRUCT_S]], ptr [[VLA]], i64 [[TMP9]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP12]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP12]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done21: // CHECK1: arraydestroy.done21:
// CHECK1-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP42]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP42]])
// CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP44]]) // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP44]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.4.omp.reduction.reduction_func // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.4.omp.reduction.reduction_func
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] {
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// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8
// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP3]], i64 0, i64 3 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP3]], i64 0, i64 3
// CHECK1-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64 // CHECK1-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64
// CHECK1-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64
// CHECK1-NEXT: [[TMP6:%.*]] = sub i64 [[TMP4]], [[TMP5]] // CHECK1-NEXT: [[TMP6:%.*]] = sub i64 [[TMP4]], [[TMP5]]
// CHECK1-NEXT: [[TMP7:%.*]] = sdiv exact i64 [[TMP6]], ptrtoint (ptr getelementptr ([[STRUCT_S:%.*]], ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP7:%.*]] = sdiv exact i64 [[TMP6]], ptrtoint (ptr getelementptr ([[STRUCT_S:%.*]], ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP8:%.*]] = add nuw i64 [[TMP7]], 1 // CHECK1-NEXT: [[TMP8:%.*]] = add nuw i64 [[TMP7]], 1
// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], ptrtoint (ptr getelementptr ([[STRUCT_S]], ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], ptrtoint (ptr getelementptr ([[STRUCT_S]], ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP10:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP10:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP10]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca [[STRUCT_S]], i64 [[TMP8]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca [[STRUCT_S]], i64 [[TMP8]], align 16
// CHECK1-NEXT: store i64 [[TMP8]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP8]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr [[STRUCT_S]], ptr [[VLA]], i64 [[TMP8]] // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr [[STRUCT_S]], ptr [[VLA]], i64 [[TMP8]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP11]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP11]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done20: // CHECK1: arraydestroy.done20:
// CHECK1-NEXT: [[TMP40:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP40:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP40]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP40]])
// CHECK1-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4 // CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP42]]) // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP42]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.11.omp.reduction.reduction_func // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.11.omp.reduction.reduction_func
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] {
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clang/test/OpenMP/for_reduction_codegen_UDR.cpp

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// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]]
// CHECK1: arrayctor.cont9: // CHECK1: arrayctor.cont9:
// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[VAR3]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[VAR3]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]])
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined.8, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[VEC]], ptr [[ARRS]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined.8, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[VEC]], ptr [[ARRS]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @main.omp_outlined.11, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[ARRS]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @main.omp_outlined.11, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[ARRS]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.12, ptr [[VAR2]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.12, ptr [[VAR2]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.13, ptr [[VVAR2]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.13, ptr [[VVAR2]])
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VAR3]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VAR3]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.14, ptr [[TMP5]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.14, ptr [[TMP5]])
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[VAR3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[VAR3]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.15, ptr [[TMP6]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.15, ptr [[TMP6]])
// CHECK1-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() // CHECK1-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v()
// CHECK1-NEXT: store i32 [[CALL10]], ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 [[CALL10]], ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP7]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP7]])
// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [5 x %struct.S.0], ptr [[VVAR2]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [5 x %struct.S.0], ptr [[VVAR2]], i32 0, i32 0
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 5 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 5
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP8]], [[ARRAYCTOR_CONT9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP8]], [[ARRAYCTOR_CONT9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
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// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[TMP8]] // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[TMP8]]
// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX5]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX5]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64 // CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64
// CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]] // CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1 // CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1
// CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA7:%.*]] = alloca i32, i64 [[TMP13]], align 16 // CHECK1-NEXT: [[VLA7:%.*]] = alloca i32, i64 [[TMP13]], align 16
// CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[VLA7]], i64 [[TMP13]] // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[VLA7]], i64 [[TMP13]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA7]], [[TMP16]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA7]], [[TMP16]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[ARRAYIDX3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[ARRAYIDX3]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP67]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP67]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA16]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA16]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE63]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE63]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done63: // CHECK1: arraydestroy.done63:
// CHECK1-NEXT: [[TMP68:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP68:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP68]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP68]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..9 // CHECK1-LABEL: define {{[^@]+}}@.omp_combiner..9
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARRS_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARRS_ADDR]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 [[TMP0]], [[TMP1]]
// CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4 // CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
// CHECK1-NEXT: [[TMP6:%.*]] = udiv exact i64 [[TMP5]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP6:%.*]] = udiv exact i64 [[TMP5]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP6]], align 16 // CHECK1-NEXT: [[VLA3:%.*]] = alloca i32, i64 [[TMP6]], align 16
// CHECK1-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[VLA3]], i64 [[TMP6]] // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[VLA3]], i64 [[TMP6]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA3]], [[TMP8]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA3]], [[TMP8]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done52: // CHECK1: arraydestroy.done52:
// CHECK1-NEXT: [[TMP40:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP40:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP40]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP40]])
// CHECK1-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4 // CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP42]]) // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP42]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.11.omp.reduction.reduction_func // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.11.omp.reduction.reduction_func
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] {
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// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8
// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP4]], i64 6 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP4]], i64 6
// CHECK1-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64
// CHECK1-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64 // CHECK1-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64
// CHECK1-NEXT: [[TMP7:%.*]] = sub i64 [[TMP5]], [[TMP6]] // CHECK1-NEXT: [[TMP7:%.*]] = sub i64 [[TMP5]], [[TMP6]]
// CHECK1-NEXT: [[TMP8:%.*]] = sdiv exact i64 [[TMP7]], ptrtoint (ptr getelementptr ([[STRUCT_S_0]], ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP8:%.*]] = sdiv exact i64 [[TMP7]], ptrtoint (ptr getelementptr ([[STRUCT_S_0]], ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP9:%.*]] = add nuw i64 [[TMP8]], 1 // CHECK1-NEXT: [[TMP9:%.*]] = add nuw i64 [[TMP8]], 1
// CHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], ptrtoint (ptr getelementptr ([[STRUCT_S_0]], ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], ptrtoint (ptr getelementptr ([[STRUCT_S_0]], ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP11:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP11]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP11]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca [[STRUCT_S_0]], i64 [[TMP9]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca [[STRUCT_S_0]], i64 [[TMP9]], align 16
// CHECK1-NEXT: store i64 [[TMP9]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP9]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr [[STRUCT_S_0]], ptr [[VLA]], i64 [[TMP9]] // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr [[STRUCT_S_0]], ptr [[VLA]], i64 [[TMP9]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP12]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP12]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[ARRAYIDX1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[ARRAYIDX1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA]]
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY]]
// CHECK1: arraydestroy.done27: // CHECK1: arraydestroy.done27:
// CHECK1-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP42]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP42]])
// CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP44]]) // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP44]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.12.omp.reduction.reduction_func // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.12.omp.reduction.reduction_func
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] { // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] {
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// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4
// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1
// CHECK3-NEXT: store i32 [[INC]], ptr [[I]], align 4 // CHECK3-NEXT: store i32 [[INC]], ptr [[I]], align 4
// CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
// CHECK3: for.end: // CHECK3: for.end:
// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK3-NEXT: [[TMP10:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP10:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP10]], ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: store ptr [[TMP10]], ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: [[TMP11:%.*]] = mul nuw i64 10, [[TMP9]] // CHECK3-NEXT: [[TMP11:%.*]] = mul nuw i64 10, [[TMP9]]
// CHECK3-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP11]], align 16 // CHECK3-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP11]], align 16
// CHECK3-NEXT: store i64 [[TMP9]], ptr [[__VLA_EXPR0]], align 8 // CHECK3-NEXT: store i64 [[TMP9]], ptr [[__VLA_EXPR0]], align 8
// CHECK3-NEXT: store i32 0, ptr [[I15]], align 4 // CHECK3-NEXT: store i32 0, ptr [[I15]], align 4
// CHECK3-NEXT: br label [[FOR_COND16:%.*]] // CHECK3-NEXT: br label [[FOR_COND16:%.*]]
// CHECK3: for.cond16: // CHECK3: for.cond16:
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I15]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I15]], align 4
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// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[I62]], align 4 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[I62]], align 4
// CHECK3-NEXT: [[INC67:%.*]] = add nsw i32 [[TMP33]], 1 // CHECK3-NEXT: [[INC67:%.*]] = add nsw i32 [[TMP33]], 1
// CHECK3-NEXT: store i32 [[INC67]], ptr [[I62]], align 4 // CHECK3-NEXT: store i32 [[INC67]], ptr [[I62]], align 4
// CHECK3-NEXT: br label [[FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK3-NEXT: br label [[FOR_COND63]], !llvm.loop [[LOOP13:![0-9]+]]
// CHECK3: for.end68: // CHECK3: for.end68:
// CHECK3-NEXT: [[CALL69:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() // CHECK3-NEXT: [[CALL69:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v()
// CHECK3-NEXT: store i32 [[CALL69]], ptr [[RETVAL]], align 4 // CHECK3-NEXT: store i32 [[CALL69]], ptr [[RETVAL]], align 4
// CHECK3-NEXT: [[TMP34:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: [[TMP34:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP34]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP34]])
// CHECK3-NEXT: [[ARRAY_BEGIN70:%.*]] = getelementptr inbounds [5 x %struct.S.0], ptr [[VVAR2]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAY_BEGIN70:%.*]] = getelementptr inbounds [5 x %struct.S.0], ptr [[VVAR2]], i32 0, i32 0
// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN70]], i64 5 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN70]], i64 5
// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK3: arraydestroy.body: // CHECK3: arraydestroy.body:
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[FOR_END68]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[FOR_END68]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]] // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR7]]
// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN70]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN70]]
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clang/test/OpenMP/for_reduction_task_codegen.cpp

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP10:%.*]] = sub i64 [[TMP8]], [[TMP9]] // CHECK1-NEXT: [[TMP10:%.*]] = sub i64 [[TMP8]], [[TMP9]]
// CHECK1-NEXT: [[TMP11:%.*]] = sdiv exact i64 [[TMP10]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP11:%.*]] = sdiv exact i64 [[TMP10]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP12:%.*]] = add nuw i64 [[TMP11]], 1 // CHECK1-NEXT: [[TMP12:%.*]] = add nuw i64 [[TMP11]], 1
// CHECK1-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP12]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP12]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP14:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP14:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP14]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP12]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP12]], align 16
// CHECK1-NEXT: store i64 [[TMP12]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP12]] // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP12]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP15]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP15]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP95]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP95]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]]
// CHECK1: omp.arraycpy.done36: // CHECK1: omp.arraycpy.done36:
// CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP86]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP86]], ptr @.gomp_critical_user_.reduction.var)
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP104:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP104:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP104]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP104]])
// CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP105]], align 4 // CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[TMP105]], align 4
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP106]]) // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP106]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
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clang/test/OpenMP/for_scan_codegen.cpp

Show All 11 Lines
void foo(); void foo();
void bar(); void bar();
// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n) // CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n)
void baz(int n) { void baz(int n) {
static float a[10]; static float a[10];
static double b; static double b;
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]]
// float a_buffer[10][n]; // float a_buffer[10][n];
// CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]],
// double b_buffer[10]; // double b_buffer[10];
// CHECK: [[B_BUF:%.+]] = alloca double, i64 10, // CHECK: [[B_BUF:%.+]] = alloca double, i64 10,
#pragma omp for reduction(inscan, +:a[:n], b) #pragma omp for reduction(inscan, +:a[:n], b)
for (int i = 0; i < 10; ++i) { for (int i = 0; i < 10; ++i) {
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// CHECK: [[INPUT_PHASE:.+]]: // CHECK: [[INPUT_PHASE:.+]]:
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// a_buffer[i][0..n] = a_priv[[0..n]; // a_buffer[i][0..n] = a_priv[[0..n];
// CHECK: [[BASE_IDX_I:%.+]] = load i32, ptr [[IV_ADDR:%.+]], // CHECK: [[BASE_IDX_I:%.+]] = load i32, ptr [[IV_ADDR:%.+]],
// CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64
// CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]]
// CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]]
// CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0
// CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4
// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false)
// b_buffer[i] = b_priv; // b_buffer[i] = b_priv;
// CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX]] // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX]]
// CHECK: [[B_PRIV:%.+]] = load double, ptr [[B_PRIV_ADDR]], // CHECK: [[B_PRIV:%.+]] = load double, ptr [[B_PRIV_ADDR]],
// CHECK: store double [[B_PRIV]], ptr [[B_BUF_IDX]], // CHECK: store double [[B_PRIV]], ptr [[B_BUF_IDX]],
// CHECK: br label %[[LOOP_CONTINUE:.+]] // CHECK: br label %[[LOOP_CONTINUE:.+]]
// CHECK: [[DISPATCH]]: // CHECK: [[DISPATCH]]:
// CHECK: br label %[[INPUT_PHASE]] // CHECK: br label %[[INPUT_PHASE]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
foo(); foo();
#pragma omp scan inclusive(a[:n], b) #pragma omp scan inclusive(a[:n], b)
// CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01)
// CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]])
// CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32 // CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32
// CHECK: br label %[[OUTER_BODY:[^,]+]] // CHECK: br label %[[OUTER_BODY:[^,]+]]
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines#pragma omp scan inclusive(a[:n], b)
// CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1 // CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1
// k2pow <<= 1; // k2pow <<= 1;
// CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1 // CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1
// CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]] // CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]]
// CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]] // CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]]
// CHECK: [[OUTER_EXIT]]: // CHECK: [[OUTER_EXIT]]:
bar(); bar();
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// Skip the before scan body. // Skip the before scan body.
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// CHECK: [[EXIT_INSCAN:[^,]+]]: // CHECK: [[EXIT_INSCAN:[^,]+]]:
Show All 15 Lines#pragma omp scan inclusive(a[:n], b)
// CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]], // CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]],
// CHECK: br label %[[SCAN_PHASE:[^,]+]] // CHECK: br label %[[SCAN_PHASE:[^,]+]]
// CHECK: [[SCAN_PHASE]]: // CHECK: [[SCAN_PHASE]]:
// CHECK: call void @{{.+}}bar{{.+}}() // CHECK: call void @{{.+}}bar{{.+}}()
// CHECK: br label %[[EXIT_INSCAN]] // CHECK: br label %[[EXIT_INSCAN]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @llvm.stackrestore(ptr // CHECK: call void @llvm.stackrestore.p0(ptr
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
} }
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]]
// float a_buffer[10][n]; // float a_buffer[10][n];
// CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]],
// double b_buffer[10]; // double b_buffer[10];
// CHECK: [[B_BUF:%.+]] = alloca double, i64 10, // CHECK: [[B_BUF:%.+]] = alloca double, i64 10,
#pragma omp for reduction(inscan, +:a[:n], b) #pragma omp for reduction(inscan, +:a[:n], b)
for (int i = 0; i < 10; ++i) { for (int i = 0; i < 10; ++i) {
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// Skip the before scan body. // Skip the before scan body.
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// CHECK: [[EXIT_INSCAN:[^,]+]]: // CHECK: [[EXIT_INSCAN:[^,]+]]:
Show All 16 Lines for (int i = 0; i < 10; ++i) {
// CHECK: [[DISPATCH]]: // CHECK: [[DISPATCH]]:
// CHECK: br label %[[INPUT_PHASE:[^,]+]] // CHECK: br label %[[INPUT_PHASE:[^,]+]]
// CHECK: [[INPUT_PHASE]]: // CHECK: [[INPUT_PHASE]]:
// CHECK: call void @{{.+}}bar{{.+}}() // CHECK: call void @{{.+}}bar{{.+}}()
// CHECK: br label %[[EXIT_INSCAN]] // CHECK: br label %[[EXIT_INSCAN]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
foo(); foo();
#pragma omp scan exclusive(a[:n], b) #pragma omp scan exclusive(a[:n], b)
// CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01)
// CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]])
// CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32 // CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32
// CHECK: br label %[[OUTER_BODY:[^,]+]] // CHECK: br label %[[OUTER_BODY:[^,]+]]
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines#pragma omp scan exclusive(a[:n], b)
// CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1 // CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1
// k2pow <<= 1; // k2pow <<= 1;
// CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1 // CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1
// CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]] // CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]]
// CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]] // CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]]
// CHECK: [[OUTER_EXIT]]: // CHECK: [[OUTER_EXIT]]:
bar(); bar();
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// CHECK: [[SCAN_PHASE:.+]]: // CHECK: [[SCAN_PHASE:.+]]:
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// CHECK: br label %[[LOOP_CONTINUE:.+]] // CHECK: br label %[[LOOP_CONTINUE:.+]]
Show All 14 Lines#pragma omp scan exclusive(a[:n], b)
// b_priv = b_buffer[i]; // b_priv = b_buffer[i];
// CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX_SUB_1]] // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX_SUB_1]]
// CHECK: [[B_BUF_IDX_VAL:%.+]] = load double, ptr [[B_BUF_IDX]], // CHECK: [[B_BUF_IDX_VAL:%.+]] = load double, ptr [[B_BUF_IDX]],
// CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]], // CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]],
// CHECK: br label %[[SCAN_PHASE]] // CHECK: br label %[[SCAN_PHASE]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @llvm.stackrestore(ptr // CHECK: call void @llvm.stackrestore.p0(ptr
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
} }
} }
#endif #endif

clang/test/OpenMP/for_simd_scan_codegen.cpp

Show All 11 Lines
void foo(); void foo();
void bar(); void bar();
// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n) // CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n)
void baz(int n) { void baz(int n) {
static float a[10]; static float a[10];
static double b; static double b;
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]]
// float a_buffer[10][n]; // float a_buffer[10][n];
// CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]],
// double b_buffer[10]; // double b_buffer[10];
// CHECK: [[B_BUF:%.+]] = alloca double, i64 10, // CHECK: [[B_BUF:%.+]] = alloca double, i64 10,
#pragma omp for simd reduction(inscan, +:a[:n], b) #pragma omp for simd reduction(inscan, +:a[:n], b)
for (int i = 0; i < 10; ++i) { for (int i = 0; i < 10; ++i) {
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// CHECK: [[INPUT_PHASE:.+]]: // CHECK: [[INPUT_PHASE:.+]]:
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// a_buffer[i][0..n] = a_priv[[0..n]; // a_buffer[i][0..n] = a_priv[[0..n];
// CHECK: [[BASE_IDX_I:%.+]] = load i32, ptr [[IV_ADDR:%.+]], // CHECK: [[BASE_IDX_I:%.+]] = load i32, ptr [[IV_ADDR:%.+]],
// CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64
// CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]]
// CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]]
// CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0
// CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4
// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false)
// b_buffer[i] = b_priv; // b_buffer[i] = b_priv;
// CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX]] // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX]]
// CHECK: [[B_PRIV:%.+]] = load double, ptr [[B_PRIV_ADDR]], // CHECK: [[B_PRIV:%.+]] = load double, ptr [[B_PRIV_ADDR]],
// CHECK: store double [[B_PRIV]], ptr [[B_BUF_IDX]], // CHECK: store double [[B_PRIV]], ptr [[B_BUF_IDX]],
// CHECK: br label %[[LOOP_CONTINUE:.+]] // CHECK: br label %[[LOOP_CONTINUE:.+]]
// CHECK: [[DISPATCH]]: // CHECK: [[DISPATCH]]:
// CHECK: br label %[[INPUT_PHASE]] // CHECK: br label %[[INPUT_PHASE]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
foo(); foo();
#pragma omp scan inclusive(a[:n], b) #pragma omp scan inclusive(a[:n], b)
// CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01)
// CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]])
// CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32 // CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32
// CHECK: br label %[[OUTER_BODY:[^,]+]] // CHECK: br label %[[OUTER_BODY:[^,]+]]
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines#pragma omp scan inclusive(a[:n], b)
// CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1 // CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1
// k2pow <<= 1; // k2pow <<= 1;
// CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1 // CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1
// CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]] // CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]]
// CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]] // CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]]
// CHECK: [[OUTER_EXIT]]: // CHECK: [[OUTER_EXIT]]:
bar(); bar();
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// Skip the before scan body. // Skip the before scan body.
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// CHECK: [[EXIT_INSCAN:[^,]+]]: // CHECK: [[EXIT_INSCAN:[^,]+]]:
Show All 15 Lines#pragma omp scan inclusive(a[:n], b)
// CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]], // CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]],
// CHECK: br label %[[SCAN_PHASE:[^,]+]] // CHECK: br label %[[SCAN_PHASE:[^,]+]]
// CHECK: [[SCAN_PHASE]]: // CHECK: [[SCAN_PHASE]]:
// CHECK: call void @{{.+}}bar{{.+}}() // CHECK: call void @{{.+}}bar{{.+}}()
// CHECK: br label %[[EXIT_INSCAN]] // CHECK: br label %[[EXIT_INSCAN]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @llvm.stackrestore(ptr // CHECK: call void @llvm.stackrestore.p0(ptr
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
} }
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]]
// float a_buffer[10][n]; // float a_buffer[10][n];
// CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]],
// double b_buffer[10]; // double b_buffer[10];
// CHECK: [[B_BUF:%.+]] = alloca double, i64 10, // CHECK: [[B_BUF:%.+]] = alloca double, i64 10,
#pragma omp for simd reduction(inscan, +:a[:n], b) #pragma omp for simd reduction(inscan, +:a[:n], b)
for (int i = 0; i < 10; ++i) { for (int i = 0; i < 10; ++i) {
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// Skip the before scan body. // Skip the before scan body.
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// CHECK: [[EXIT_INSCAN:[^,]+]]: // CHECK: [[EXIT_INSCAN:[^,]+]]:
Show All 16 Lines for (int i = 0; i < 10; ++i) {
// CHECK: [[DISPATCH]]: // CHECK: [[DISPATCH]]:
// CHECK: br label %[[INPUT_PHASE:[^,]+]] // CHECK: br label %[[INPUT_PHASE:[^,]+]]
// CHECK: [[INPUT_PHASE]]: // CHECK: [[INPUT_PHASE]]:
// CHECK: call void @{{.+}}bar{{.+}}() // CHECK: call void @{{.+}}bar{{.+}}()
// CHECK: br label %[[EXIT_INSCAN]] // CHECK: br label %[[EXIT_INSCAN]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
foo(); foo();
#pragma omp scan exclusive(a[:n], b) #pragma omp scan exclusive(a[:n], b)
// CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01)
// CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]])
// CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32 // CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32
// CHECK: br label %[[OUTER_BODY:[^,]+]] // CHECK: br label %[[OUTER_BODY:[^,]+]]
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines#pragma omp scan exclusive(a[:n], b)
// CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1 // CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1
// k2pow <<= 1; // k2pow <<= 1;
// CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1 // CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1
// CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]] // CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]]
// CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]] // CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]]
// CHECK: [[OUTER_EXIT]]: // CHECK: [[OUTER_EXIT]]:
bar(); bar();
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// CHECK: [[SCAN_PHASE:.+]]: // CHECK: [[SCAN_PHASE:.+]]:
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// CHECK: br label %[[LOOP_CONTINUE:.+]] // CHECK: br label %[[LOOP_CONTINUE:.+]]
Show All 14 Lines#pragma omp scan exclusive(a[:n], b)
// b_priv = b_buffer[i]; // b_priv = b_buffer[i];
// CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX_SUB_1]] // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX_SUB_1]]
// CHECK: [[B_BUF_IDX_VAL:%.+]] = load double, ptr [[B_BUF_IDX]], // CHECK: [[B_BUF_IDX_VAL:%.+]] = load double, ptr [[B_BUF_IDX]],
// CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]], // CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]],
// CHECK: br label %[[SCAN_PHASE]] // CHECK: br label %[[SCAN_PHASE]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @llvm.stackrestore(ptr // CHECK: call void @llvm.stackrestore.p0(ptr
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
} }
} }
#endif #endif
// CHECK: !{!"llvm.loop.vectorize.enable", i1 true} // CHECK: !{!"llvm.loop.vectorize.enable", i1 true}

clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK1: arrayctor.cont: // CHECK1: arrayctor.cont:
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 // CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1
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// CHECK1-NEXT: store i32 1, ptr [[TMP41]], align 8 // CHECK1-NEXT: store i32 1, ptr [[TMP41]], align 8
// CHECK1-NEXT: [[TMP42:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]]) // CHECK1-NEXT: [[TMP42:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]])
// CHECK1-NEXT: store ptr [[TMP42]], ptr [[DOTTASK_RED_6]], align 8 // CHECK1-NEXT: store ptr [[TMP42]], ptr [[DOTTASK_RED_6]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED_6]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED_6]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP43]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP43]])
// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
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clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK1: arrayctor.cont: // CHECK1: arrayctor.cont:
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 // CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1
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// CHECK1-NEXT: store i32 1, ptr [[TMP41]], align 8 // CHECK1-NEXT: store i32 1, ptr [[TMP41]], align 8
// CHECK1-NEXT: [[TMP42:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]]) // CHECK1-NEXT: [[TMP42:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]])
// CHECK1-NEXT: store ptr [[TMP42]], ptr [[DOTTASK_RED_6]], align 8 // CHECK1-NEXT: store ptr [[TMP42]], ptr [[DOTTASK_RED_6]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED_6]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED_6]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP43]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP43]])
// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
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// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK3-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK3: arrayctor.cont: // CHECK3: arrayctor.cont:
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16
// CHECK3-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK3-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK3-NEXT: store i64 4, ptr [[DOTOMP_UB]], align 8 // CHECK3-NEXT: store i64 4, ptr [[DOTOMP_UB]], align 8
// CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 // CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
// CHECK3-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
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// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
// CHECK3: omp.inner.for.end: // CHECK3: omp.inner.for.end:
// CHECK3-NEXT: store i32 5, ptr [[I]], align 4 // CHECK3-NEXT: store i32 5, ptr [[I]], align 4
// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 5 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 5
// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK3: arraydestroy.body: // CHECK3: arraydestroy.body:
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]
// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
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clang/test/OpenMP/parallel_codegen.cpp

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// CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @main.omp_outlined, i64 [[TMP1]], ptr [[VLA]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @main.omp_outlined, i64 [[TMP1]], ptr [[VLA]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP1]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP1]])
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @main.omp_outlined.2, i64 [[TMP1]], ptr [[VLA]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @main.omp_outlined.2, i64 [[TMP1]], ptr [[VLA]])
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]])
// CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP4]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP4]])
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK1-NEXT: ret i32 [[TMP5]] // CHECK1-NEXT: ret i32 [[TMP5]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] personality ptr @__gxx_personality_v0 { // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] personality ptr @__gxx_personality_v0 {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[GLOBAL:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP0]], align 16 // CHECK1-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP0]], align 16
// CHECK1-NEXT: store i64 [[TMP0]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP0]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @main.omp_outlined.1.omp_outlined, i64 [[TMP0]], ptr [[VLA1]], ptr [[GLOBAL]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @main.omp_outlined.1.omp_outlined, i64 [[TMP0]], ptr [[VLA1]], ptr [[GLOBAL]])
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP2]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP2]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1.omp_outlined // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1.omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR2]] personality ptr @__gxx_personality_v0 { // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR2]] personality ptr @__gxx_personality_v0 {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK2-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]]
// CHECK2-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK2-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGV_ADDR]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG21:![0-9]+]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGV_ADDR]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG21:![0-9]+]]
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG22:![0-9]+]] // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG22:![0-9]+]]
// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG23:![0-9]+]] // CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG23:![0-9]+]]
// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave(), !dbg [[DBG23]] // CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG23]]
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG23]] // CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG23]]
// CHECK2-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG23]] // CHECK2-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG23]]
// CHECK2-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG23]] // CHECK2-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG23]]
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[__VLA_EXPR0]], metadata [[META24:![0-9]+]], metadata !DIExpression()), !dbg [[DBG26:![0-9]+]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[__VLA_EXPR0]], metadata [[META24:![0-9]+]], metadata !DIExpression()), !dbg [[DBG26:![0-9]+]]
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG31:![0-9]+]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA]], metadata [[META27:![0-9]+]], metadata !DIExpression()), !dbg [[DBG31:![0-9]+]]
// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @main.omp_outlined, i64 [[TMP1]], ptr [[VLA]]), !dbg [[DBG32:![0-9]+]] // CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @main.omp_outlined, i64 [[TMP1]], ptr [[VLA]]), !dbg [[DBG32:![0-9]+]]
// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB5:[0-9]+]], i32 1, ptr @main.omp_outlined.2, i64 [[TMP1]]), !dbg [[DBG33:![0-9]+]] // CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB5:[0-9]+]], i32 1, ptr @main.omp_outlined.2, i64 [[TMP1]]), !dbg [[DBG33:![0-9]+]]
// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB9:[0-9]+]], i32 2, ptr @main.omp_outlined.4, i64 [[TMP1]], ptr [[VLA]]), !dbg [[DBG34:![0-9]+]] // CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB9:[0-9]+]], i32 2, ptr @main.omp_outlined.4, i64 [[TMP1]], ptr [[VLA]]), !dbg [[DBG34:![0-9]+]]
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG35:![0-9]+]] // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG35:![0-9]+]]
// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]]), !dbg [[DBG36:![0-9]+]] // CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]]), !dbg [[DBG36:![0-9]+]]
// CHECK2-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4, !dbg [[DBG37:![0-9]+]] // CHECK2-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4, !dbg [[DBG37:![0-9]+]]
// CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG38:![0-9]+]] // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG38:![0-9]+]]
// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP4]]), !dbg [[DBG38]] // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP4]]), !dbg [[DBG38]]
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4, !dbg [[DBG38]] // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4, !dbg [[DBG38]]
// CHECK2-NEXT: ret i32 [[TMP5]], !dbg [[DBG38]] // CHECK2-NEXT: ret i32 [[TMP5]], !dbg [[DBG38]]
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__ // CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG39:![0-9]+]] { // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR3:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG39:![0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79:![0-9]+]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTGLOBAL_TID__ADDR]], metadata [[META78:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79:![0-9]+]]
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTBOUND_TID__ADDR]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA_ADDR]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
// CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG82:![0-9]+]] // CHECK2-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG82:![0-9]+]]
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[GLOBAL]], metadata [[META83:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[GLOBAL]], metadata [[META83:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
// CHECK2-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave(), !dbg [[DBG82]] // CHECK2-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG82]]
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG82]] // CHECK2-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG82]]
// CHECK2-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP0]], align 16, !dbg [[DBG82]] // CHECK2-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP0]], align 16, !dbg [[DBG82]]
// CHECK2-NEXT: store i64 [[TMP0]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG82]] // CHECK2-NEXT: store i64 [[TMP0]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG82]]
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[__VLA_EXPR0]], metadata [[META84:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[__VLA_EXPR0]], metadata [[META84:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
// CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA1]], metadata [[META85:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]] // CHECK2-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA1]], metadata [[META85:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79]]
// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @main.omp_outlined_debug__.1.omp_outlined, i64 [[TMP0]], ptr [[VLA1]], ptr [[GLOBAL]]), !dbg [[DBG82]] // CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @main.omp_outlined_debug__.1.omp_outlined, i64 [[TMP0]], ptr [[VLA1]], ptr [[GLOBAL]]), !dbg [[DBG82]]
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG86:![0-9]+]] // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG86:![0-9]+]]
// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP2]]), !dbg [[DBG86]] // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP2]]), !dbg [[DBG86]]
// CHECK2-NEXT: ret void, !dbg [[DBG88:![0-9]+]] // CHECK2-NEXT: ret void, !dbg [[DBG88:![0-9]+]]
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__.1.omp_outlined_debug__ // CHECK2-LABEL: define {{[^@]+}}@main.omp_outlined_debug__.1.omp_outlined_debug__
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 !dbg [[DBG89:![0-9]+]] { // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[GLOBAL:%.*]]) #[[ATTR3]] personality ptr @__gxx_personality_v0 !dbg [[DBG89:![0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK3-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK3-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK3-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK3-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 // CHECK3-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16
// CHECK3-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK3-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK3-NEXT: br label [[OMP_PARALLEL:%.*]] // CHECK3-NEXT: br label [[OMP_PARALLEL:%.*]]
// CHECK3: omp_parallel: // CHECK3: omp_parallel:
// CHECK3-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0 // CHECK3-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
// CHECK3-NEXT: store ptr [[VLA]], ptr [[GEP_VLA]], align 8 // CHECK3-NEXT: store ptr [[VLA]], ptr [[GEP_VLA]], align 8
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main..omp_par, ptr [[STRUCTARG]]) // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main..omp_par, ptr [[STRUCTARG]])
// CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] // CHECK3-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
// CHECK3: omp.par.outlined.exit: // CHECK3: omp.par.outlined.exit:
// CHECK3-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] // CHECK3-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]]
// CHECK3: omp.par.exit.split: // CHECK3: omp.par.exit.split:
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]]) // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]])
// CHECK3-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK3-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP4]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP4]])
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK3-NEXT: ret i32 [[TMP5]] // CHECK3-NEXT: ret i32 [[TMP5]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@main..omp_par // CHECK3-LABEL: define {{[^@]+}}@main..omp_par
// CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK3-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK3-NEXT: omp.par.entry: // CHECK3-NEXT: omp.par.entry:
// CHECK3-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
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// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK4-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK4-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK4-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]] // CHECK4-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGC_ADDR]], metadata [[META18:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]]
// CHECK4-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK4-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK4-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGV_ADDR]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19]] // CHECK4-NEXT: call void @llvm.dbg.declare(metadata ptr [[ARGV_ADDR]], metadata [[META20:![0-9]+]], metadata !DIExpression()), !dbg [[DBG19]]
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG21:![0-9]+]] // CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4, !dbg [[DBG21:![0-9]+]]
// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG21]] // CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG21]]
// CHECK4-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave(), !dbg [[DBG21]] // CHECK4-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG21]]
// CHECK4-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG21]] // CHECK4-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG21]]
// CHECK4-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG21]] // CHECK4-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16, !dbg [[DBG21]]
// CHECK4-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG21]] // CHECK4-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG21]]
// CHECK4-NEXT: call void @llvm.dbg.declare(metadata ptr [[__VLA_EXPR0]], metadata [[META22:![0-9]+]], metadata !DIExpression()), !dbg [[DBG24:![0-9]+]] // CHECK4-NEXT: call void @llvm.dbg.declare(metadata ptr [[__VLA_EXPR0]], metadata [[META22:![0-9]+]], metadata !DIExpression()), !dbg [[DBG24:![0-9]+]]
// CHECK4-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA]], metadata [[META25:![0-9]+]], metadata !DIExpression()), !dbg [[DBG21]] // CHECK4-NEXT: call void @llvm.dbg.declare(metadata ptr [[VLA]], metadata [[META25:![0-9]+]], metadata !DIExpression()), !dbg [[DBG21]]
// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG29:![0-9]+]] // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG29:![0-9]+]]
// CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]] // CHECK4-NEXT: br label [[OMP_PARALLEL:%.*]]
// CHECK4: omp_parallel: // CHECK4: omp_parallel:
// CHECK4-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0 // CHECK4-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
// CHECK4-NEXT: store ptr [[VLA]], ptr [[GEP_VLA]], align 8 // CHECK4-NEXT: store ptr [[VLA]], ptr [[GEP_VLA]], align 8
// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG30:![0-9]+]] // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main..omp_par, ptr [[STRUCTARG]]), !dbg [[DBG30:![0-9]+]]
// CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] // CHECK4-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
// CHECK4: omp.par.outlined.exit: // CHECK4: omp.par.outlined.exit:
// CHECK4-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] // CHECK4-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]]
// CHECK4: omp.par.exit.split: // CHECK4: omp.par.exit.split:
// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG31:![0-9]+]] // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARGV_ADDR]], align 8, !dbg [[DBG31:![0-9]+]]
// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]]), !dbg [[DBG31]] // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIPPcEiT_(ptr noundef [[TMP3]]), !dbg [[DBG31]]
// CHECK4-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4, !dbg [[DBG31]] // CHECK4-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4, !dbg [[DBG31]]
// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG32:![0-9]+]] // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG32:![0-9]+]]
// CHECK4-NEXT: call void @llvm.stackrestore(ptr [[TMP4]]), !dbg [[DBG32]] // CHECK4-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP4]]), !dbg [[DBG32]]
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4, !dbg [[DBG32]] // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4, !dbg [[DBG32]]
// CHECK4-NEXT: ret i32 [[TMP5]], !dbg [[DBG32]] // CHECK4-NEXT: ret i32 [[TMP5]], !dbg [[DBG32]]
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@main..omp_par // CHECK4-LABEL: define {{[^@]+}}@main..omp_par
// CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG33:![0-9]+]] { // CHECK4-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG33:![0-9]+]] {
// CHECK4-NEXT: omp.par.entry: // CHECK4-NEXT: omp.par.entry:
// CHECK4-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0 // CHECK4-NEXT: [[GEP_VLA:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
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clang/test/OpenMP/parallel_firstprivate_codegen.cpp

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// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]
// CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 8, ptr @_Z10array_funcPfP2StiPe.omp_outlined, ptr [[TMP8]], ptr [[N_ADDR]], i64 [[TMP1]], ptr [[TMP9]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]]) // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 8, ptr @_Z10array_funcPfP2StiPe.omp_outlined, ptr [[TMP8]], ptr [[N_ADDR]], i64 [[TMP1]], ptr [[TMP9]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]])
// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe.omp_outlined // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe.omp_outlined
// CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[S:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[S:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8
// CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8
// CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
// CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8
// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP8]], i1 false) // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP8]], i1 false)
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i64 0 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i64 0
// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPe(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 [[TMP11]], ptr [[TMP12]]) // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPe(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 [[TMP11]], ptr [[TMP12]])
// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe
// CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] align 2 { // CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] align 2 {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]
// CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A]], align 4 // CHECK17-NEXT: store i32 [[TMP8]], ptr [[A]], align 4
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 8, ptr @_ZN2St7St_funcEPS_iPe.omp_outlined, i64 [[TMP1]], ptr [[TMP9]], ptr [[THIS1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], ptr [[N_ADDR]], ptr [[TMP10]]) // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 8, ptr @_ZN2St7St_funcEPS_iPe.omp_outlined, i64 [[TMP1]], ptr [[TMP9]], ptr [[THIS1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], ptr [[N_ADDR]], ptr [[TMP10]])
// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe.omp_outlined // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe.omp_outlined
// CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], ptr [[S:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], ptr [[S:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/parallel_for_codegen.cpp

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// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]])
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP5]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined // CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 { // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 // CHECK1-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
// CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK1: omp.dispatch.cond: // CHECK1: omp.dispatch.cond:
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// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]] // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]]
// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK1: omp.dispatch.end: // CHECK1: omp.dispatch.end:
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])
// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP24]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// CHECK1: terminate.lpad: // CHECK1: terminate.lpad:
// CHECK1-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 }
// CHECK1-NEXT: catch ptr null // CHECK1-NEXT: catch ptr null
// CHECK1-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0 // CHECK1-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0
// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]] // CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]]
// CHECK1-NEXT: unreachable // CHECK1-NEXT: unreachable
// //
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// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16
// CHECK2-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK2-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) // CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]])
// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP5]]) // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined // CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 { // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // CHECK2-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 // CHECK2-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK2-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 // CHECK2-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16
// CHECK2-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK2-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
// CHECK2-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) // CHECK2-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK2: omp.dispatch.cond: // CHECK2: omp.dispatch.cond:
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// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]] // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]]
// CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4 // CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK2: omp.dispatch.end: // CHECK2: omp.dispatch.end:
// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])
// CHECK2-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK2-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP24]]) // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// CHECK2: terminate.lpad: // CHECK2: terminate.lpad:
// CHECK2-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 } // CHECK2-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 }
// CHECK2-NEXT: catch ptr null // CHECK2-NEXT: catch ptr null
// CHECK2-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0 // CHECK2-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0
// CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]] // CHECK2-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]]
// CHECK2-NEXT: unreachable // CHECK2-NEXT: unreachable
// //
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// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]]
// CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG105]] // CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG105]]
// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave(), !dbg [[DBG105]] // CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG105]]
// CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG105]] // CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG105]]
// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG105]] // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG105]]
// CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG105]] // CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG105]]
// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG106:![0-9]+]] // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG106:![0-9]+]]
// CHECK5-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4, !dbg [[DBG106]] // CHECK5-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4, !dbg [[DBG106]]
// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8, !dbg [[DBG106]] // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8, !dbg [[DBG106]]
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB32:[0-9]+]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG106]] // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB32:[0-9]+]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG106]]
// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG107:![0-9]+]] // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG107:![0-9]+]]
// CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP5]]), !dbg [[DBG107]] // CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]]), !dbg [[DBG107]]
// CHECK5-NEXT: ret void, !dbg [[DBG107]] // CHECK5-NEXT: ret void, !dbg [[DBG107]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined // CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined
// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 !dbg [[DBG108:![0-9]+]] { // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 !dbg [[DBG108:![0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // CHECK5-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK5-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 // CHECK5-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG109:![0-9]+]] // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG109:![0-9]+]]
// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG109]] // CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG109]]
// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110:![0-9]+]] // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110:![0-9]+]]
// CHECK5-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]] // CHECK5-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]] // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG110]] // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG110]]
// CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave(), !dbg [[DBG109]] // CHECK5-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG109]]
// CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]] // CHECK5-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]]
// CHECK5-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG109]] // CHECK5-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG109]]
// CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG109]] // CHECK5-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG109]]
// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG109]] // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG109]]
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG109]] // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG109]]
// CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG109]] // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG109]]
// CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG109]] // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG109]]
// CHECK5: omp.dispatch.cond: // CHECK5: omp.dispatch.cond:
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// CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]] // CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]] // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
// CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG110]] // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG110]]
// CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]] // CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
// CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP113:![0-9]+]] // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP113:![0-9]+]]
// CHECK5: omp.dispatch.end: // CHECK5: omp.dispatch.end:
// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG109]] // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG109]]
// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]] // CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]]
// CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP24]]), !dbg [[DBG109]] // CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]]), !dbg [[DBG109]]
// CHECK5-NEXT: ret void, !dbg [[DBG111]] // CHECK5-NEXT: ret void, !dbg [[DBG111]]
// CHECK5: terminate.lpad: // CHECK5: terminate.lpad:
// CHECK5-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: [[TMP25:%.*]] = landingpad { ptr, i32 }
// CHECK5-NEXT: catch ptr null, !dbg [[DBG111]] // CHECK5-NEXT: catch ptr null, !dbg [[DBG111]]
// CHECK5-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0, !dbg [[DBG111]] // CHECK5-NEXT: [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0, !dbg [[DBG111]]
// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG111]] // CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG111]]
// CHECK5-NEXT: unreachable, !dbg [[DBG111]] // CHECK5-NEXT: unreachable, !dbg [[DBG111]]
// //
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// CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
// CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 // CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
// CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK6-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
// CHECK6-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK6-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK6-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK6-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK6-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK6-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 // CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16
// CHECK6-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK6-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK6-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK6-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK6-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) // CHECK6-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]])
// CHECK6-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK6-NEXT: [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK6-NEXT: call void @llvm.stackrestore(ptr [[TMP5]]) // CHECK6-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP5]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined // CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined
// CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] { // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] {
// CHECK6-NEXT: entry: // CHECK6-NEXT: entry:
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
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// CHECK6-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // CHECK6-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK6-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 // CHECK6-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
// CHECK6-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK6-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK6-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4 // CHECK6-NEXT: store i32 16908288, ptr [[DOTOMP_UB]], align 4
// CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK6-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK6-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK6-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK6-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK6-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK6-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 // CHECK6-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16
// CHECK6-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK6-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK6-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
// CHECK6-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5) // CHECK6-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
// CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK6: omp.dispatch.cond: // CHECK6: omp.dispatch.cond:
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// CHECK6-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK6-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
// CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]] // CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]]
// CHECK6-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4 // CHECK6-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4
// CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK6: omp.dispatch.end: // CHECK6: omp.dispatch.end:
// CHECK6-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK6-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])
// CHECK6-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK6-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK6-NEXT: call void @llvm.stackrestore(ptr [[TMP24]]) // CHECK6-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])
// CHECK6-NEXT: ret void // CHECK6-NEXT: ret void
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_Z9incrementv // CHECK11-LABEL: define {{[^@]+}}@_Z9incrementv
// CHECK11-SAME: () #[[ATTR0:[0-9]+]] { // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
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clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp

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// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]] // CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1 // CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1
// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]] // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP94]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP94]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]]
// CHECK1: omp.arraycpy.done36: // CHECK1: omp.arraycpy.done36:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP103:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP103:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP103]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP103]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/parallel_for_scan_codegen.cpp

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void foo(int n); void foo(int n);
void bar(); void bar();
// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n) // CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n)
void baz(int n) { void baz(int n) {
static float a[10]; static float a[10];
static double b; static double b;
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]]
// float a_buffer[10][n]; // float a_buffer[10][n];
// CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]],
// double b_buffer[10]; // double b_buffer[10];
// CHECK: [[B_BUF:%.+]] = alloca double, i64 10, // CHECK: [[B_BUF:%.+]] = alloca double, i64 10,
// CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call( // CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(
// CHECK: [[LAST:%.+]] = mul nsw i64 9, % // CHECK: [[LAST:%.+]] = mul nsw i64 9, %
// CHECK: [[LAST_REF:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[LAST]] // CHECK: [[LAST_REF:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[LAST]]
// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 16 @_ZZ3baziE1a, ptr align 4 [[LAST_REF]], i64 %{{.+}}, i1 false) // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 16 @_ZZ3baziE1a, ptr align 4 [[LAST_REF]], i64 %{{.+}}, i1 false)
// CHECK: [[LAST_REF_B:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 9 // CHECK: [[LAST_REF_B:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 9
// CHECK: [[LAST_VAL:%.+]] = load double, ptr [[LAST_REF_B]], // CHECK: [[LAST_VAL:%.+]] = load double, ptr [[LAST_REF_B]],
// CHECK: store double [[LAST_VAL]], ptr @_ZZ3baziE1b, // CHECK: store double [[LAST_VAL]], ptr @_ZZ3baziE1b,
// CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]]
// float a_buffer[10][n]; // float a_buffer[10][n];
// CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]],
// double b_buffer[10]; // double b_buffer[10];
// CHECK: [[B_BUF:%.+]] = alloca double, i64 10, // CHECK: [[B_BUF:%.+]] = alloca double, i64 10,
// CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call( // CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(
// CHECK: call void @llvm.stackrestore(ptr // CHECK: call void @llvm.stackrestore.p0(ptr
#pragma omp parallel for reduction(inscan, +:a[:n], b) #pragma omp parallel for reduction(inscan, +:a[:n], b)
for (int i = 0; i < 10; ++i) { for (int i = 0; i < 10; ++i) {
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// CHECK: [[INPUT_PHASE:.+]]: // CHECK: [[INPUT_PHASE:.+]]:
// CHECK: call void @{{.+}}foo{{.+}}( // CHECK: call void @{{.+}}foo{{.+}}(
// a_buffer[i][0..n] = a_priv[[0..n]; // a_buffer[i][0..n] = a_priv[[0..n];
// CHECK: [[BASE_IDX_I:%.+]] = load i32, ptr [[IV_ADDR:%.+]], // CHECK: [[BASE_IDX_I:%.+]] = load i32, ptr [[IV_ADDR:%.+]],
// CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64
// CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]]
// CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF:%.+]], i64 [[IDX]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF:%.+]], i64 [[IDX]]
// CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0
// CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4
// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false)
// b_buffer[i] = b_priv; // b_buffer[i] = b_priv;
// CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF:%.+]], i64 [[BASE_IDX]] // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF:%.+]], i64 [[BASE_IDX]]
// CHECK: [[B_PRIV:%.+]] = load double, ptr [[B_PRIV_ADDR]], // CHECK: [[B_PRIV:%.+]] = load double, ptr [[B_PRIV_ADDR]],
// CHECK: store double [[B_PRIV]], ptr [[B_BUF_IDX]], // CHECK: store double [[B_PRIV]], ptr [[B_BUF_IDX]],
// CHECK: br label %[[LOOP_CONTINUE:.+]] // CHECK: br label %[[LOOP_CONTINUE:.+]]
// CHECK: [[DISPATCH]]: // CHECK: [[DISPATCH]]:
// CHECK: br label %[[INPUT_PHASE]] // CHECK: br label %[[INPUT_PHASE]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
foo(n); foo(n);
#pragma omp scan inclusive(a[:n], b) #pragma omp scan inclusive(a[:n], b)
// CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01)
// CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]])
// CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32 // CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32
// CHECK: br label %[[OUTER_BODY:[^,]+]] // CHECK: br label %[[OUTER_BODY:[^,]+]]
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines#pragma omp scan inclusive(a[:n], b)
// CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1 // CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1
// k2pow <<= 1; // k2pow <<= 1;
// CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1 // CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1
// CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]] // CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]]
// CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]] // CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]]
// CHECK: [[OUTER_EXIT]]: // CHECK: [[OUTER_EXIT]]:
bar(); bar();
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// Skip the before scan body. // Skip the before scan body.
// CHECK: call void @{{.+}}foo{{.+}}( // CHECK: call void @{{.+}}foo{{.+}}(
// CHECK: [[EXIT_INSCAN:[^,]+]]: // CHECK: [[EXIT_INSCAN:[^,]+]]:
Show All 15 Lines#pragma omp scan inclusive(a[:n], b)
// CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]], // CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]],
// CHECK: br label %[[SCAN_PHASE:[^,]+]] // CHECK: br label %[[SCAN_PHASE:[^,]+]]
// CHECK: [[SCAN_PHASE]]: // CHECK: [[SCAN_PHASE]]:
// CHECK: call void @{{.+}}bar{{.+}}() // CHECK: call void @{{.+}}bar{{.+}}()
// CHECK: br label %[[EXIT_INSCAN]] // CHECK: br label %[[EXIT_INSCAN]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
} }
#pragma omp parallel for reduction(inscan, +:a[:n], b) #pragma omp parallel for reduction(inscan, +:a[:n], b)
for (int i = 0; i < 10; ++i) { for (int i = 0; i < 10; ++i) {
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// Skip the before scan body. // Skip the before scan body.
// CHECK: call void @{{.+}}foo{{.+}}( // CHECK: call void @{{.+}}foo{{.+}}(
// CHECK: [[EXIT_INSCAN:[^,]+]]: // CHECK: [[EXIT_INSCAN:[^,]+]]:
Show All 16 Lines for (int i = 0; i < 10; ++i) {
// CHECK: [[DISPATCH]]: // CHECK: [[DISPATCH]]:
// CHECK: br label %[[INPUT_PHASE:[^,]+]] // CHECK: br label %[[INPUT_PHASE:[^,]+]]
// CHECK: [[INPUT_PHASE]]: // CHECK: [[INPUT_PHASE]]:
// CHECK: call void @{{.+}}bar{{.+}}() // CHECK: call void @{{.+}}bar{{.+}}()
// CHECK: br label %[[EXIT_INSCAN]] // CHECK: br label %[[EXIT_INSCAN]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
foo(n); foo(n);
#pragma omp scan exclusive(a[:n], b) #pragma omp scan exclusive(a[:n], b)
// CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01)
// CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]])
// CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32 // CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32
// CHECK: br label %[[OUTER_BODY:[^,]+]] // CHECK: br label %[[OUTER_BODY:[^,]+]]
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines#pragma omp scan exclusive(a[:n], b)
// CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1 // CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1
// k2pow <<= 1; // k2pow <<= 1;
// CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1 // CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1
// CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]] // CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]]
// CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]] // CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]]
// CHECK: [[OUTER_EXIT]]: // CHECK: [[OUTER_EXIT]]:
bar(); bar();
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// CHECK: [[SCAN_PHASE:.+]]: // CHECK: [[SCAN_PHASE:.+]]:
// CHECK: call void @{{.+}}foo{{.+}}( // CHECK: call void @{{.+}}foo{{.+}}(
// CHECK: br label %[[LOOP_CONTINUE:.+]] // CHECK: br label %[[LOOP_CONTINUE:.+]]
Show All 14 Lines#pragma omp scan exclusive(a[:n], b)
// b_priv = b_buffer[i]; // b_priv = b_buffer[i];
// CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX_SUB_1]] // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX_SUB_1]]
// CHECK: [[B_BUF_IDX_VAL:%.+]] = load double, ptr [[B_BUF_IDX]], // CHECK: [[B_BUF_IDX_VAL:%.+]] = load double, ptr [[B_BUF_IDX]],
// CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]], // CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]],
// CHECK: br label %[[SCAN_PHASE]] // CHECK: br label %[[SCAN_PHASE]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
} }
} }
#endif #endif

clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp

Show All 12 Lines
void foo(); void foo();
void bar(); void bar();
// CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n) // CHECK: define{{.*}} void @{{.*}}baz{{.*}}(i32 noundef %n)
void baz(int n) { void baz(int n) {
static float a[10]; static float a[10];
static double b; static double b;
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]]
// float a_buffer[10][n]; // float a_buffer[10][n];
// CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]],
// CHECK: [[B_BUF:%.+]] = alloca double, i64 10, // CHECK: [[B_BUF:%.+]] = alloca double, i64 10,
// CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call( // CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(
// CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]] // CHECK: [[A_BUF_SIZE:%.+]] = mul nuw i64 10, [[NUM_ELEMS:%[^,]+]]
// float a_buffer[10][n]; // float a_buffer[10][n];
// CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]], // CHECK: [[A_BUF:%.+]] = alloca float, i64 [[A_BUF_SIZE]],
// double b_buffer[10]; // double b_buffer[10];
// CHECK: [[B_BUF:%.+]] = alloca double, i64 10, // CHECK: [[B_BUF:%.+]] = alloca double, i64 10,
// CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call( // CHECK: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(
// CHECK: call void @llvm.stackrestore(ptr // CHECK: call void @llvm.stackrestore.p0(ptr
#pragma omp parallel for simd reduction(inscan, +:a[:n], b) #pragma omp parallel for simd reduction(inscan, +:a[:n], b)
for (int i = 0; i < 10; ++i) { for (int i = 0; i < 10; ++i) {
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// CHECK: [[INPUT_PHASE:.+]]: // CHECK: [[INPUT_PHASE:.+]]:
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// a_buffer[i][0..n] = a_priv[[0..n]; // a_buffer[i][0..n] = a_priv[[0..n];
// CHECK: [[BASE_IDX_I:%.+]] = load i32, ptr [[IV_ADDR:%.+]], // CHECK: [[BASE_IDX_I:%.+]] = load i32, ptr [[IV_ADDR:%.+]],
// CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64
// CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]]
// CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF:%.+]], i64 [[IDX]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF:%.+]], i64 [[IDX]]
// CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0
// CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4
// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false)
// b_buffer[i] = b_priv; // b_buffer[i] = b_priv;
// CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF:%.+]], i64 [[BASE_IDX]] // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF:%.+]], i64 [[BASE_IDX]]
// CHECK: [[B_PRIV:%.+]] = load double, ptr [[B_PRIV_ADDR]], // CHECK: [[B_PRIV:%.+]] = load double, ptr [[B_PRIV_ADDR]],
// CHECK: store double [[B_PRIV]], ptr [[B_BUF_IDX]], // CHECK: store double [[B_PRIV]], ptr [[B_BUF_IDX]],
// CHECK: br label %[[LOOP_CONTINUE:.+]] // CHECK: br label %[[LOOP_CONTINUE:.+]]
// CHECK: [[DISPATCH]]: // CHECK: [[DISPATCH]]:
// CHECK: br label %[[INPUT_PHASE]] // CHECK: br label %[[INPUT_PHASE]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
foo(); foo();
#pragma omp scan inclusive(a[:n], b) #pragma omp scan inclusive(a[:n], b)
// CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01)
// CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]])
// CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32 // CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32
// CHECK: br label %[[OUTER_BODY:[^,]+]] // CHECK: br label %[[OUTER_BODY:[^,]+]]
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines#pragma omp scan inclusive(a[:n], b)
// CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1 // CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1
// k2pow <<= 1; // k2pow <<= 1;
// CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1 // CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1
// CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]] // CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]]
// CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]] // CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]]
// CHECK: [[OUTER_EXIT]]: // CHECK: [[OUTER_EXIT]]:
bar(); bar();
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// Skip the before scan body. // Skip the before scan body.
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// CHECK: [[EXIT_INSCAN:[^,]+]]: // CHECK: [[EXIT_INSCAN:[^,]+]]:
Show All 15 Lines#pragma omp scan inclusive(a[:n], b)
// CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]], // CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]],
// CHECK: br label %[[SCAN_PHASE:[^,]+]] // CHECK: br label %[[SCAN_PHASE:[^,]+]]
// CHECK: [[SCAN_PHASE]]: // CHECK: [[SCAN_PHASE]]:
// CHECK: call void @{{.+}}bar{{.+}}() // CHECK: call void @{{.+}}bar{{.+}}()
// CHECK: br label %[[EXIT_INSCAN]] // CHECK: br label %[[EXIT_INSCAN]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
} }
#pragma omp parallel for simd reduction(inscan, +:a[:n], b) #pragma omp parallel for simd reduction(inscan, +:a[:n], b)
for (int i = 0; i < 10; ++i) { for (int i = 0; i < 10; ++i) {
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// Skip the before scan body. // Skip the before scan body.
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// CHECK: [[EXIT_INSCAN:[^,]+]]: // CHECK: [[EXIT_INSCAN:[^,]+]]:
Show All 16 Lines for (int i = 0; i < 10; ++i) {
// CHECK: [[DISPATCH]]: // CHECK: [[DISPATCH]]:
// CHECK: br label %[[INPUT_PHASE:[^,]+]] // CHECK: br label %[[INPUT_PHASE:[^,]+]]
// CHECK: [[INPUT_PHASE]]: // CHECK: [[INPUT_PHASE]]:
// CHECK: call void @{{.+}}bar{{.+}}() // CHECK: call void @{{.+}}bar{{.+}}()
// CHECK: br label %[[EXIT_INSCAN]] // CHECK: br label %[[EXIT_INSCAN]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
// CHECK: call void @__kmpc_barrier( // CHECK: call void @__kmpc_barrier(
foo(); foo();
#pragma omp scan exclusive(a[:n], b) #pragma omp scan exclusive(a[:n], b)
// CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01) // CHECK: [[LOG2_10:%.+]] = call double @llvm.log2.f64(double 1.000000e+01)
// CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]]) // CHECK: [[CEIL_LOG2_10:%.+]] = call double @llvm.ceil.f64(double [[LOG2_10]])
// CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32 // CHECK: [[CEIL_LOG2_10_INT:%.+]] = fptoui double [[CEIL_LOG2_10]] to i32
// CHECK: br label %[[OUTER_BODY:[^,]+]] // CHECK: br label %[[OUTER_BODY:[^,]+]]
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines#pragma omp scan exclusive(a[:n], b)
// CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1 // CHECK: [[K_NEXT]] = add nuw i32 [[K]], 1
// k2pow <<= 1; // k2pow <<= 1;
// CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1 // CHECK: [[K2POW_NEXT]] = shl nuw i64 [[K2POW]], 1
// CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]] // CHECK: [[CMP:%.+]] = icmp ne i32 [[K_NEXT]], [[CEIL_LOG2_10_INT]]
// CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]] // CHECK: br i1 [[CMP]], label %[[OUTER_BODY]], label %[[OUTER_EXIT:[^,]+]]
// CHECK: [[OUTER_EXIT]]: // CHECK: [[OUTER_EXIT]]:
bar(); bar();
// CHECK: call void @__kmpc_for_static_init_4( // CHECK: call void @__kmpc_for_static_init_4(
// CHECK: call ptr @llvm.stacksave() // CHECK: call ptr @llvm.stacksave.p0()
// CHECK: store float 0.000000e+00, ptr % // CHECK: store float 0.000000e+00, ptr %
// CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]], // CHECK: store double 0.000000e+00, ptr [[B_PRIV_ADDR:%.+]],
// CHECK: br label %[[DISPATCH:[^,]+]] // CHECK: br label %[[DISPATCH:[^,]+]]
// CHECK: [[SCAN_PHASE:.+]]: // CHECK: [[SCAN_PHASE:.+]]:
// CHECK: call void @{{.+}}foo{{.+}}() // CHECK: call void @{{.+}}foo{{.+}}()
// CHECK: br label %[[LOOP_CONTINUE:.+]] // CHECK: br label %[[LOOP_CONTINUE:.+]]
Show All 14 Lines#pragma omp scan exclusive(a[:n], b)
// b_priv = b_buffer[i]; // b_priv = b_buffer[i];
// CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX_SUB_1]] // CHECK: [[B_BUF_IDX:%.+]] = getelementptr inbounds double, ptr [[B_BUF]], i64 [[BASE_IDX_SUB_1]]
// CHECK: [[B_BUF_IDX_VAL:%.+]] = load double, ptr [[B_BUF_IDX]], // CHECK: [[B_BUF_IDX_VAL:%.+]] = load double, ptr [[B_BUF_IDX]],
// CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]], // CHECK: store double [[B_BUF_IDX_VAL]], ptr [[B_PRIV_ADDR]],
// CHECK: br label %[[SCAN_PHASE]] // CHECK: br label %[[SCAN_PHASE]]
// CHECK: [[LOOP_CONTINUE]]: // CHECK: [[LOOP_CONTINUE]]:
// CHECK: call void @llvm.stackrestore(ptr % // CHECK: call void @llvm.stackrestore.p0(ptr %
// CHECK: call void @__kmpc_for_static_fini( // CHECK: call void @__kmpc_for_static_fini(
} }
} }
// CHECK: !{!"llvm.loop.vectorize.enable", i1 true} // CHECK: !{!"llvm.loop.vectorize.enable", i1 true}
#endif #endif

clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]] // CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1 // CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1
// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]] // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP87]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP87]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]]
// CHECK1: omp.arraycpy.done32: // CHECK1: omp.arraycpy.done32:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP96:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP96:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP96]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP96]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
▲ Show 20 Lines • Show All 167 Lines • Show Last 20 Lines

clang/test/OpenMP/parallel_reduction_codegen.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[X_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[X_ADDR]], align 8
// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i64 0 // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i64 0
// CHECK1-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK1-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64
// CHECK1-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]] // CHECK1-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]]
// CHECK1-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1 // CHECK1-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1
// CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16
// CHECK1-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[VLA]], i64 [[TMP6]] // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[VLA]], i64 [[TMP6]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP9]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP9]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP25]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP25]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]]
// CHECK1: omp.arraycpy.done21: // CHECK1: omp.arraycpy.done21:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP34]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP34]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs.omp_outlined.omp.reduction.reduction_func // CHECK1-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs.omp_outlined.omp.reduction.reduction_func
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[X_ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[X_ADDR]], align 8
// CHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i64 0 // CHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i64 0
// CHECK3-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64 // CHECK3-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64
// CHECK3-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK3-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64
// CHECK3-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]] // CHECK3-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]]
// CHECK3-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK3-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64)
// CHECK3-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1 // CHECK3-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1
// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64)
// CHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16
// CHECK3-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8 // CHECK3-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[VLA]], i64 [[TMP6]] // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[VLA]], i64 [[TMP6]]
// CHECK3-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP9]] // CHECK3-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP9]]
// CHECK3-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK3-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK3: omp.arrayinit.body: // CHECK3: omp.arrayinit.body:
// CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1
// CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1
// CHECK3-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP25]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP25]]
// CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]]
// CHECK3: omp.arraycpy.done21: // CHECK3: omp.arraycpy.done21:
// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK3: .omp.reduction.default: // CHECK3: .omp.reduction.default:
// CHECK3-NEXT: [[TMP34:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: [[TMP34:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP34]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP34]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs.omp_outlined.omp.reduction.reduction_func // CHECK3-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs.omp_outlined.omp.reduction.reduction_func
// CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[X_ADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[X_ADDR]], align 8
// CHECK4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i64 0 // CHECK4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i64 0
// CHECK4-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64 // CHECK4-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64
// CHECK4-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK4-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64
// CHECK4-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]] // CHECK4-NEXT: [[TMP4:%.*]] = sub i64 [[TMP2]], [[TMP3]]
// CHECK4-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK4-NEXT: [[TMP5:%.*]] = sdiv exact i64 [[TMP4]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64)
// CHECK4-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1 // CHECK4-NEXT: [[TMP6:%.*]] = add nuw i64 [[TMP5]], 1
// CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64)
// CHECK4-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // CHECK4-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK4-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // CHECK4-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8
// CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16 // CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP6]], align 16
// CHECK4-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8 // CHECK4-NEXT: store i64 [[TMP6]], ptr [[__VLA_EXPR0]], align 8
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[VLA]], i64 [[TMP6]] // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[VLA]], i64 [[TMP6]]
// CHECK4-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP9]] // CHECK4-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP9]]
// CHECK4-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK4-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK4: omp.arrayinit.body: // CHECK4: omp.arrayinit.body:
// CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK4-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr i16, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST11]], i32 1
// CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1 // CHECK4-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr i16, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST10]], i32 1
// CHECK4-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP25]] // CHECK4-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP25]]
// CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]] // CHECK4-NEXT: br i1 [[OMP_ARRAYCPY_DONE20]], label [[OMP_ARRAYCPY_DONE21]], label [[OMP_ARRAYCPY_BODY9]]
// CHECK4: omp.arraycpy.done21: // CHECK4: omp.arraycpy.done21:
// CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK4: .omp.reduction.default: // CHECK4: .omp.reduction.default:
// CHECK4-NEXT: [[TMP34:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK4-NEXT: [[TMP34:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK4-NEXT: call void @llvm.stackrestore(ptr [[TMP34]]) // CHECK4-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP34]])
// CHECK4-NEXT: ret void // CHECK4-NEXT: ret void
// //
// //
// CHECK4-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs.omp_outlined.omp.reduction.reduction_func // CHECK4-LABEL: define {{[^@]+}}@_Z14foo_array_sectPs.omp_outlined.omp.reduction.reduction_func
// CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
// CHECK4-NEXT: entry: // CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/parallel_reduction_task_codegen.cpp

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// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]] // CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1 // CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1
// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]] // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP83]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP83]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]]
// CHECK1: omp.arraycpy.done32: // CHECK1: omp.arraycpy.done32:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP92:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP92:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP92]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP92]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp

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// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]] // CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1 // CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1
// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]] // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP95]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP95]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]]
// CHECK1: omp.arraycpy.done32: // CHECK1: omp.arraycpy.done32:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP104:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP104:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP104]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP104]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/reduction_implicit_map.cpp

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// CHECK1-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX6]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX6]], i64 0, i64 0
// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY7]], i64 1 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY7]], i64 1
// CHECK1-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[ARRAYIDX8]] to i64 // CHECK1-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[ARRAYIDX8]] to i64
// CHECK1-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[TMP3:%.*]] = sub i64 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: [[TMP4:%.*]] = sdiv exact i64 [[TMP3]], ptrtoint (ptr getelementptr (double, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP4:%.*]] = sdiv exact i64 [[TMP3]], ptrtoint (ptr getelementptr (double, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP5:%.*]] = add nuw i64 [[TMP4]], 1 // CHECK1-NEXT: [[TMP5:%.*]] = add nuw i64 [[TMP4]], 1
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], ptrtoint (ptr getelementptr (double, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], ptrtoint (ptr getelementptr (double, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP7:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP5]], align 8 // CHECK1-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP5]], align 8
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr double, ptr [[VLA]], i64 [[TMP5]] // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr double, ptr [[VLA]], i64 [[TMP5]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP8]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP8]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT30]] = getelementptr double, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST29]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT30]] = getelementptr double, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST29]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT31]] = getelementptr double, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST28]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT31]] = getelementptr double, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST28]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE32:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT30]], [[TMP52]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE32:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT30]], [[TMP52]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_DONE33]], label [[OMP_ARRAYCPY_BODY27]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_DONE33]], label [[OMP_ARRAYCPY_BODY27]]
// CHECK1: omp.arraycpy.done33: // CHECK1: omp.arraycpy.done33:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP55:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP55:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP55]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP55]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/sections_reduction_task_codegen.cpp

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// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP7]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP10:%.*]] = sub i64 [[TMP8]], [[TMP9]] // CHECK1-NEXT: [[TMP10:%.*]] = sub i64 [[TMP8]], [[TMP9]]
// CHECK1-NEXT: [[TMP11:%.*]] = sdiv exact i64 [[TMP10]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP11:%.*]] = sdiv exact i64 [[TMP10]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP12:%.*]] = add nuw i64 [[TMP11]], 1 // CHECK1-NEXT: [[TMP12:%.*]] = add nuw i64 [[TMP11]], 1
// CHECK1-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP12]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP12]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP14:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP14:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP14]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP12]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP12]], align 16
// CHECK1-NEXT: store i64 [[TMP12]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP12]] // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP12]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP15]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP15]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP96]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP96]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]]
// CHECK1: omp.arraycpy.done32: // CHECK1: omp.arraycpy.done32:
// CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP87]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP87]], ptr @.gomp_critical_user_.reduction.var)
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP105]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP105]])
// CHECK1-NEXT: [[TMP106:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP106:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP106]], align 4 // CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[TMP106]], align 4
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP107]]) // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP107]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
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clang/test/OpenMP/target_codegen.cpp

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a += ftemplate<int>(n); a += ftemplate<int>(n);
return a; return a;
} }
// //
// CHECK: define {{.*}}[[FS1]] // CHECK: define {{.*}}[[FS1]]
// //
// CHECK: ptr @llvm.stacksave() // CHECK: ptr @llvm.stacksave.p0()
// CHECK-64: store i32 %{{.+}}, ptr [[B_CADDR:%.+]], // CHECK-64: store i32 %{{.+}}, ptr [[B_CADDR:%.+]],
// CHECK-64: [[B_CVAL:%.+]] = load i[[SZ]], ptr [[B_CADDR]], // CHECK-64: [[B_CVAL:%.+]] = load i[[SZ]], ptr [[B_CADDR]],
// CHECK-32: store i32 %{{.+}}, ptr %__vla_expr // CHECK-32: store i32 %{{.+}}, ptr %__vla_expr
// CHECK-32: store i32 %{{.+}}, ptr [[B_CADDR:%.+]], // CHECK-32: store i32 %{{.+}}, ptr [[B_CADDR:%.+]],
// CHECK-32: [[B_CVAL:%.+]] = load i[[SZ]], ptr [[B_CADDR]], // CHECK-32: [[B_CVAL:%.+]] = load i[[SZ]], ptr [[B_CADDR]],
// CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 60 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 60
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clang/test/OpenMP/target_firstprivate_codegen.cpp

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// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 8 // CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 8
// CHECK0-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK0-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 // CHECK0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
// CHECK0-NEXT: store i32 0, ptr [[A]], align 4 // CHECK0-NEXT: store i32 0, ptr [[A]], align 4
// CHECK0-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK0-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // CHECK0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // CHECK0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// CHECK0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // CHECK0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// CHECK0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // CHECK0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// CHECK0-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 // CHECK0-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0
// CHECK0-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] // CHECK0-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]
// CHECK0: omp_offload.failed12: // CHECK0: omp_offload.failed12:
// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]] // CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]]
// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT13]] // CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT13]]
// CHECK0: omp_offload.cont13: // CHECK0: omp_offload.cont13:
// CHECK0-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 // CHECK0-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4
// CHECK0-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK0-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) // CHECK0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])
// CHECK0-NEXT: ret i32 [[TMP115]] // CHECK0-NEXT: ret i32 [[TMP115]]
// //
// //
// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 // CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
// CHECK0-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK0-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK0-NEXT: entry: // CHECK0-NEXT: entry:
// CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK0-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8
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// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 // CHECK0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
// CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 // CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// CHECK0-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 // CHECK0-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK0-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 // CHECK0-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
// CHECK0-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 // CHECK0-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
// CHECK0-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 // CHECK0-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) // CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false)
// CHECK0-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // CHECK0-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK0-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8
// CHECK0-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 // CHECK0-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
// CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK0-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK0-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) // CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false)
// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) // CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false)
// CHECK0-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] // CHECK0-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
// CHECK0-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 // CHECK0-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8
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// CHECK0-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] // CHECK0-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]]
// CHECK0-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 // CHECK0-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3
// CHECK0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 // CHECK0-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8
// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 // CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0
// CHECK0-NEXT: store i64 1, ptr [[X]], align 8 // CHECK0-NEXT: store i64 1, ptr [[X]], align 8
// CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 // CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1
// CHECK0-NEXT: store i8 1, ptr [[Y]], align 8 // CHECK0-NEXT: store i8 1, ptr [[Y]], align 8
// CHECK0-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK0-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK0-NEXT: ret void // CHECK0-NEXT: ret void
// //
// //
// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 // CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
// CHECK0-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { // CHECK0-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
// CHECK0-NEXT: entry: // CHECK0-NEXT: entry:
// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK0-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 // CHECK0-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8
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// CHECK0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK0-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK0-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK0-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK0-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK0-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK0-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK0-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK0-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK0-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK0-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK0-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK0-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// CHECK0-NEXT: [[TMP43:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK0-NEXT: [[TMP43:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP43]] // CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP43]]
// CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK0-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK0-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK0-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32 // CHECK0-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32
// CHECK0-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4 // CHECK0-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4
// CHECK0-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]] // CHECK0-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]]
// CHECK0-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK0-NEXT: call void @llvm.stackrestore(ptr [[TMP46]]) // CHECK0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP46]])
// CHECK0-NEXT: ret i32 [[ADD3]] // CHECK0-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK0-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK0-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK0-NEXT: entry: // CHECK0-NEXT: entry:
// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK0-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK0-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK0-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 // CHECK0-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
// CHECK0-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // CHECK0-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK0-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // CHECK0-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
// CHECK0-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK0-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK0-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK0-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 // CHECK0-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 // CHECK0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// CHECK0-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK0-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK0-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
// CHECK0-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 // CHECK0-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
// CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 // CHECK0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8
// CHECK0-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // CHECK0-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
// CHECK0-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 // CHECK0-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
// CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) // CHECK0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false)
// CHECK0-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK0-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // CHECK0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
// CHECK0-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK0-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
// CHECK0-NEXT: store double [[ADD]], ptr [[A]], align 8 // CHECK0-NEXT: store double [[ADD]], ptr [[A]], align 8
// CHECK0-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 // CHECK0-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
// CHECK0-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 // CHECK0-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8
// CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 // CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
// CHECK0-NEXT: store double [[INC]], ptr [[A4]], align 8 // CHECK0-NEXT: store double [[INC]], ptr [[A4]], align 8
// CHECK0-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 // CHECK0-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// CHECK0-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK0-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] // CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]]
// CHECK0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK0-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 // CHECK0-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
// CHECK0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK0-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// CHECK0-NEXT: ret void // CHECK0-NEXT: ret void
// //
// //
// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 // CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
// CHECK0-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK0-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK0-NEXT: entry: // CHECK0-NEXT: entry:
// CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK0-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 // CHECK0-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 8
// CHECK1-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // CHECK1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// CHECK1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // CHECK1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// CHECK1-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 // CHECK1-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0
// CHECK1-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] // CHECK1-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]
// CHECK1: omp_offload.failed12: // CHECK1: omp_offload.failed12:
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]]
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT13]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT13]]
// CHECK1: omp_offload.cont13: // CHECK1: omp_offload.cont13:
// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])
// CHECK1-NEXT: ret i32 [[TMP115]] // CHECK1-NEXT: ret i32 [[TMP115]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false)
// CHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 // CHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false)
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false)
// CHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] // CHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
// CHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 // CHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8
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// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]]
// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3
// CHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 // CHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8
// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0
// CHECK1-NEXT: store i64 1, ptr [[X]], align 8 // CHECK1-NEXT: store i64 1, ptr [[X]], align 8
// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1
// CHECK1-NEXT: store i8 1, ptr [[Y]], align 8 // CHECK1-NEXT: store i8 1, ptr [[Y]], align 8
// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
// CHECK1-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// CHECK1-NEXT: [[TMP43:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK1-NEXT: [[TMP43:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP43]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP43]]
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK1-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK1-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32
// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]]
// CHECK1-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP46]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP46]])
// CHECK1-NEXT: ret i32 [[ADD3]] // CHECK1-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 // CHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
// CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 // CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false)
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8 // CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8
// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
// CHECK1-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
// CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8 // CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8
// CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// CHECK1-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK1-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]]
// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 // CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
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// CHECK2-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 4 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 4
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 4 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 4
// CHECK2-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK2-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 // CHECK2-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4
// CHECK2-NEXT: store i32 0, ptr [[A]], align 4 // CHECK2-NEXT: store i32 0, ptr [[A]], align 4
// CHECK2-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK2-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK2-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK2-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK2-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// CHECK2-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK2-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// CHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0
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// CHECK2-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 // CHECK2-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0
// CHECK2-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] // CHECK2-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]
// CHECK2: omp_offload.failed12: // CHECK2: omp_offload.failed12:
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]] // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]]
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT13]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT13]]
// CHECK2: omp_offload.cont13: // CHECK2: omp_offload.cont13:
// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4
// CHECK2-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])
// CHECK2-NEXT: ret i32 [[TMP115]] // CHECK2-NEXT: ret i32 [[TMP115]]
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
// CHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4
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// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false)
// CHECK2-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // CHECK2-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK2-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4
// CHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 // CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false)
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false)
// CHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] // CHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
// CHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 // CHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8
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// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] // CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]]
// CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 // CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3
// CHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 // CHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8
// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0
// CHECK2-NEXT: store i64 1, ptr [[X]], align 4 // CHECK2-NEXT: store i64 1, ptr [[X]], align 4
// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1
// CHECK2-NEXT: store i8 1, ptr [[Y]], align 4 // CHECK2-NEXT: store i8 1, ptr [[Y]], align 4
// CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
// CHECK2-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK2-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4
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// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK2-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK2-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK2-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK2-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// CHECK2-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// CHECK2-NEXT: [[TMP43:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK2-NEXT: [[TMP43:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP43]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP43]]
// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK2-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK2-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32 // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32
// CHECK2-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4 // CHECK2-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]] // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]]
// CHECK2-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP46]]) // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP46]])
// CHECK2-NEXT: ret i32 [[ADD3]] // CHECK2-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK2-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK2-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // CHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// CHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 // CHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
// CHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 // CHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
// CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 // CHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
// CHECK2-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK2-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK2-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4
// CHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// CHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 // CHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
// CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// CHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 // CHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
// CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false)
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: store double [[ADD]], ptr [[A]], align 4 // CHECK2-NEXT: store double [[ADD]], ptr [[A]], align 4
// CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
// CHECK2-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
// CHECK2-NEXT: store double [[INC]], ptr [[A4]], align 4 // CHECK2-NEXT: store double [[INC]], ptr [[A4]], align 4
// CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 // CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// CHECK2-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] // CHECK2-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]]
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]]
// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 // CHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// CHECK2-NEXT: ret void // CHECK2-NEXT: ret void
// //
// //
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
// CHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry: // CHECK2-NEXT: entry:
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x ptr], align 4
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x ptr], align 4
// CHECK3-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0
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// CHECK3-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0 // CHECK3-NEXT: [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0
// CHECK3-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]] // CHECK3-NEXT: br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]
// CHECK3: omp_offload.failed12: // CHECK3: omp_offload.failed12:
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]] // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(ptr [[TMP91]], ptr [[E]]) #[[ATTR3]]
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT13]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT13]]
// CHECK3: omp_offload.cont13: // CHECK3: omp_offload.cont13:
// CHECK3-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4
// CHECK3-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])
// CHECK3-NEXT: ret i32 [[TMP115]] // CHECK3-NEXT: ret i32 [[TMP115]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 4
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// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false)
// CHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 // CHECK3-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false)
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false)
// CHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] // CHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
// CHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 // CHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8
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// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]]
// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3
// CHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 // CHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8
// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0
// CHECK3-NEXT: store i64 1, ptr [[X]], align 4 // CHECK3-NEXT: store i64 1, ptr [[X]], align 4
// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1
// CHECK3-NEXT: store i8 1, ptr [[Y]], align 4 // CHECK3-NEXT: store i8 1, ptr [[Y]], align 4
// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
// CHECK3-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4
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// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// CHECK3-NEXT: [[TMP43:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK3-NEXT: [[TMP43:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP43]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP43]]
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK3-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK3-NEXT: [[TMP44:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP44]] to i32
// CHECK3-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP45:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]] // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP45]]
// CHECK3-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP46:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP46]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP46]])
// CHECK3-NEXT: ret i32 [[ADD3]] // CHECK3-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// CHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 // CHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false)
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
// CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4 // CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4
// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
// CHECK3-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4
// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
// CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4 // CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4
// CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// CHECK3-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] // CHECK3-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]]
// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 // CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
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// SIMD-ONLY0-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 // SIMD-ONLY0-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
// SIMD-ONLY0-NEXT: [[P:%.*]] = alloca ptr, align 64 // SIMD-ONLY0-NEXT: [[P:%.*]] = alloca ptr, align 64
// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
// SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY0-NEXT: store i16 0, ptr [[AA]], align 2 // SIMD-ONLY0-NEXT: store i16 0, ptr [[AA]], align 2
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// SIMD-ONLY0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // SIMD-ONLY0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// SIMD-ONLY0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // SIMD-ONLY0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// SIMD-ONLY0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // SIMD-ONLY0-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// SIMD-ONLY0-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8 // SIMD-ONLY0-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0 // SIMD-ONLY0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8
// SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// SIMD-ONLY0-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY0-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // SIMD-ONLY0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// SIMD-ONLY0-NEXT: ret i32 [[TMP14]] // SIMD-ONLY0-NEXT: ret i32 [[TMP14]]
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z3bariPd // SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z3bariPd
// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // SIMD-ONLY0-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY0-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY0-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// SIMD-ONLY0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // SIMD-ONLY0-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double // SIMD-ONLY0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
// SIMD-ONLY0-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 // SIMD-ONLY0-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
// SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] // SIMD-ONLY0-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
// SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]] // SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]]
// SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1 // SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1
// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2
// SIMD-ONLY0-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 // SIMD-ONLY0-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY0-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] // SIMD-ONLY0-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // SIMD-ONLY0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// SIMD-ONLY0-NEXT: ret i32 [[ADD9]] // SIMD-ONLY0-NEXT: ret i32 [[ADD9]]
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZL7fstatici // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZL7fstatici
// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4
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// SIMD-ONLY01-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 // SIMD-ONLY01-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
// SIMD-ONLY01-NEXT: [[P:%.*]] = alloca ptr, align 64 // SIMD-ONLY01-NEXT: [[P:%.*]] = alloca ptr, align 64
// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY01-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 // SIMD-ONLY01-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
// SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY01-NEXT: store i16 0, ptr [[AA]], align 2 // SIMD-ONLY01-NEXT: store i16 0, ptr [[AA]], align 2
// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // SIMD-ONLY01-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY01-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY01-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY01-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// SIMD-ONLY01-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // SIMD-ONLY01-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // SIMD-ONLY01-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // SIMD-ONLY01-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// SIMD-ONLY01-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // SIMD-ONLY01-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// SIMD-ONLY01-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // SIMD-ONLY01-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// SIMD-ONLY01-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8 // SIMD-ONLY01-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8
// SIMD-ONLY01-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 // SIMD-ONLY01-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// SIMD-ONLY01-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0 // SIMD-ONLY01-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0
// SIMD-ONLY01-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY01-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8
// SIMD-ONLY01-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // SIMD-ONLY01-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// SIMD-ONLY01-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY01-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8
// SIMD-ONLY01-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY01-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
// SIMD-ONLY01-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY01-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY01-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // SIMD-ONLY01-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// SIMD-ONLY01-NEXT: ret i32 [[TMP14]] // SIMD-ONLY01-NEXT: ret i32 [[TMP14]]
// //
// //
// SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3bariPd // SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3bariPd
// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
// SIMD-ONLY01-NEXT: entry: // SIMD-ONLY01-NEXT: entry:
// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// SIMD-ONLY01-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY01-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY01-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY01-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // SIMD-ONLY01-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // SIMD-ONLY01-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY01-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY01-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY01-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // SIMD-ONLY01-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// SIMD-ONLY01-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // SIMD-ONLY01-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY01-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double // SIMD-ONLY01-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
// SIMD-ONLY01-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 // SIMD-ONLY01-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
// SIMD-ONLY01-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY01-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] // SIMD-ONLY01-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
// SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]] // SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]]
// SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1 // SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1
// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2
// SIMD-ONLY01-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 // SIMD-ONLY01-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY01-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] // SIMD-ONLY01-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY01-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // SIMD-ONLY01-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// SIMD-ONLY01-NEXT: ret i32 [[ADD9]] // SIMD-ONLY01-NEXT: ret i32 [[ADD9]]
// //
// //
// SIMD-ONLY01-LABEL: define {{[^@]+}}@_ZL7fstatici // SIMD-ONLY01-LABEL: define {{[^@]+}}@_ZL7fstatici
// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// SIMD-ONLY01-NEXT: entry: // SIMD-ONLY01-NEXT: entry:
// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4
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// SIMD-ONLY02-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // SIMD-ONLY02-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
// SIMD-ONLY02-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 // SIMD-ONLY02-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
// SIMD-ONLY02-NEXT: [[P:%.*]] = alloca ptr, align 64 // SIMD-ONLY02-NEXT: [[P:%.*]] = alloca ptr, align 64
// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY02-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 // SIMD-ONLY02-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4
// SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY02-NEXT: store i16 0, ptr [[AA]], align 2 // SIMD-ONLY02-NEXT: store i16 0, ptr [[AA]], align 2
// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY02-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY02-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY02-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// SIMD-ONLY02-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // SIMD-ONLY02-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// SIMD-ONLY02-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // SIMD-ONLY02-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// SIMD-ONLY02-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // SIMD-ONLY02-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// SIMD-ONLY02-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 // SIMD-ONLY02-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0
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// SIMD-ONLY02-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4 // SIMD-ONLY02-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4
// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4
// SIMD-ONLY02-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0 // SIMD-ONLY02-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0
// SIMD-ONLY02-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY02-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4
// SIMD-ONLY02-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 // SIMD-ONLY02-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
// SIMD-ONLY02-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY02-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4
// SIMD-ONLY02-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY02-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
// SIMD-ONLY02-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // SIMD-ONLY02-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// SIMD-ONLY02-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY02-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])
// SIMD-ONLY02-NEXT: ret i32 [[TMP12]] // SIMD-ONLY02-NEXT: ret i32 [[TMP12]]
// //
// //
// SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3bariPd // SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3bariPd
// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
// SIMD-ONLY02-NEXT: entry: // SIMD-ONLY02-NEXT: entry:
// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
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// SIMD-ONLY02-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
// SIMD-ONLY02-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // SIMD-ONLY02-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY02-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // SIMD-ONLY02-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY02-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY02-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY02-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// SIMD-ONLY02-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // SIMD-ONLY02-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY02-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double // SIMD-ONLY02-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
// SIMD-ONLY02-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 // SIMD-ONLY02-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
// SIMD-ONLY02-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY02-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] // SIMD-ONLY02-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
// SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]] // SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]]
// SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1 // SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1
// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2
// SIMD-ONLY02-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 // SIMD-ONLY02-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY02-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] // SIMD-ONLY02-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// SIMD-ONLY02-NEXT: call void @llvm.stackrestore(ptr [[TMP10]]) // SIMD-ONLY02-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]])
// SIMD-ONLY02-NEXT: ret i32 [[ADD9]] // SIMD-ONLY02-NEXT: ret i32 [[ADD9]]
// //
// //
// SIMD-ONLY02-LABEL: define {{[^@]+}}@_ZL7fstatici // SIMD-ONLY02-LABEL: define {{[^@]+}}@_ZL7fstatici
// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// SIMD-ONLY02-NEXT: entry: // SIMD-ONLY02-NEXT: entry:
// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4
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// SIMD-ONLY03-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // SIMD-ONLY03-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
// SIMD-ONLY03-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 // SIMD-ONLY03-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
// SIMD-ONLY03-NEXT: [[P:%.*]] = alloca ptr, align 64 // SIMD-ONLY03-NEXT: [[P:%.*]] = alloca ptr, align 64
// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 // SIMD-ONLY03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4
// SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY03-NEXT: store i16 0, ptr [[AA]], align 2 // SIMD-ONLY03-NEXT: store i16 0, ptr [[AA]], align 2
// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY03-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY03-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY03-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// SIMD-ONLY03-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // SIMD-ONLY03-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// SIMD-ONLY03-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // SIMD-ONLY03-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// SIMD-ONLY03-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // SIMD-ONLY03-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// SIMD-ONLY03-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 // SIMD-ONLY03-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0
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// SIMD-ONLY03-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4 // SIMD-ONLY03-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4
// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4
// SIMD-ONLY03-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0 // SIMD-ONLY03-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0
// SIMD-ONLY03-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY03-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4
// SIMD-ONLY03-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 // SIMD-ONLY03-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
// SIMD-ONLY03-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY03-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4
// SIMD-ONLY03-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY03-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
// SIMD-ONLY03-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // SIMD-ONLY03-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// SIMD-ONLY03-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY03-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])
// SIMD-ONLY03-NEXT: ret i32 [[TMP12]] // SIMD-ONLY03-NEXT: ret i32 [[TMP12]]
// //
// //
// SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3bariPd // SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3bariPd
// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
// SIMD-ONLY03-NEXT: entry: // SIMD-ONLY03-NEXT: entry:
// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
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// SIMD-ONLY03-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
// SIMD-ONLY03-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // SIMD-ONLY03-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY03-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // SIMD-ONLY03-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY03-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY03-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY03-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// SIMD-ONLY03-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // SIMD-ONLY03-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY03-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double // SIMD-ONLY03-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
// SIMD-ONLY03-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 // SIMD-ONLY03-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
// SIMD-ONLY03-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY03-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] // SIMD-ONLY03-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
// SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]] // SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]]
// SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1 // SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1
// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2
// SIMD-ONLY03-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 // SIMD-ONLY03-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY03-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] // SIMD-ONLY03-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// SIMD-ONLY03-NEXT: call void @llvm.stackrestore(ptr [[TMP10]]) // SIMD-ONLY03-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]])
// SIMD-ONLY03-NEXT: ret i32 [[ADD9]] // SIMD-ONLY03-NEXT: ret i32 [[ADD9]]
// //
// //
// SIMD-ONLY03-LABEL: define {{[^@]+}}@_ZL7fstatici // SIMD-ONLY03-LABEL: define {{[^@]+}}@_ZL7fstatici
// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// SIMD-ONLY03-NEXT: entry: // SIMD-ONLY03-NEXT: entry:
// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4
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// TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 // TCHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 // TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// TCHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 // TCHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// TCHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 // TCHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
// TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 // TCHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
// TCHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 // TCHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) // TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false)
// TCHECK-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // TCHECK-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// TCHECK-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // TCHECK-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8
// TCHECK-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 // TCHECK-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
// TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// TCHECK-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 // TCHECK-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4
// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) // TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false)
// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) // TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false)
// TCHECK-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] // TCHECK-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
// TCHECK-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 // TCHECK-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8
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// TCHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] // TCHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]]
// TCHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 // TCHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3
// TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 // TCHECK-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8
// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 // TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0
// TCHECK-NEXT: store i64 1, ptr [[X]], align 8 // TCHECK-NEXT: store i64 1, ptr [[X]], align 8
// TCHECK-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 // TCHECK-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1
// TCHECK-NEXT: store i8 1, ptr [[Y]], align 8 // TCHECK-NEXT: store i8 1, ptr [[Y]], align 8
// TCHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // TCHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// TCHECK-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// TCHECK-NEXT: ret void // TCHECK-NEXT: ret void
// //
// //
// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
// TCHECK-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // TCHECK-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
// TCHECK-NEXT: entry: // TCHECK-NEXT: entry:
// TCHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// TCHECK-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8
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// TCHECK-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 // TCHECK-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
// TCHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // TCHECK-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// TCHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // TCHECK-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
// TCHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // TCHECK-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // TCHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // TCHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// TCHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 // TCHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 // TCHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// TCHECK-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // TCHECK-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// TCHECK-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // TCHECK-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// TCHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // TCHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
// TCHECK-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 // TCHECK-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
// TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // TCHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// TCHECK-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 // TCHECK-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8
// TCHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // TCHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
// TCHECK-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 // TCHECK-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
// TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) // TCHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false)
// TCHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 // TCHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4
// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
// TCHECK-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 // TCHECK-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// TCHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 // TCHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
// TCHECK-NEXT: store double [[ADD]], ptr [[A]], align 8 // TCHECK-NEXT: store double [[ADD]], ptr [[A]], align 8
// TCHECK-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 // TCHECK-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
// TCHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 // TCHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8
// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 // TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
// TCHECK-NEXT: store double [[INC]], ptr [[A4]], align 8 // TCHECK-NEXT: store double [[INC]], ptr [[A4]], align 8
// TCHECK-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 // TCHECK-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// TCHECK-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] // TCHECK-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] // TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]]
// TCHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // TCHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// TCHECK-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 // TCHECK-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
// TCHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // TCHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// TCHECK-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // TCHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// TCHECK-NEXT: ret void // TCHECK-NEXT: ret void
// //
// //
// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 // TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
// TCHECK-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
// TCHECK-NEXT: entry: // TCHECK-NEXT: entry:
// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // TCHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
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// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 // TCHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 // TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// TCHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 // TCHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// TCHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 // TCHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
// TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 // TCHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
// TCHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 // TCHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false) // TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i64 40, i1 false)
// TCHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // TCHECK1-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// TCHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8 // TCHECK1-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 8
// TCHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4 // TCHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
// TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// TCHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4 // TCHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP1]], 4
// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false) // TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i64 [[TMP9]], i1 false)
// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false) // TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i64 400, i1 false)
// TCHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]] // TCHECK1-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
// TCHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8 // TCHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP10]], align 8
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// TCHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]] // TCHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i64 [[TMP14]]
// TCHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3 // TCHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3
// TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 // TCHECK1-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8
// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 // TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0
// TCHECK1-NEXT: store i64 1, ptr [[X]], align 8 // TCHECK1-NEXT: store i64 1, ptr [[X]], align 8
// TCHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 // TCHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1
// TCHECK1-NEXT: store i8 1, ptr [[Y]], align 8 // TCHECK1-NEXT: store i8 1, ptr [[Y]], align 8
// TCHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // TCHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// TCHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// TCHECK1-NEXT: ret void // TCHECK1-NEXT: ret void
// //
// //
// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
// TCHECK1-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // TCHECK1-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
// TCHECK1-NEXT: entry: // TCHECK1-NEXT: entry:
// TCHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
// TCHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 8
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// TCHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 // TCHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
// TCHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 // TCHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
// TCHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 // TCHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
// TCHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // TCHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
// TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // TCHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // TCHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// TCHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 // TCHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
// TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 // TCHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
// TCHECK1-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // TCHECK1-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// TCHECK1-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // TCHECK1-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// TCHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // TCHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
// TCHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2 // TCHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
// TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // TCHECK1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// TCHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8 // TCHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR1]], align 8
// TCHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]] // TCHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
// TCHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2 // TCHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
// TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false) // TCHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i64 [[TMP7]], i1 false)
// TCHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 // TCHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4
// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
// TCHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 // TCHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// TCHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 // TCHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
// TCHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8 // TCHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8
// TCHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 // TCHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
// TCHECK1-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8 // TCHECK1-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 8
// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 // TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
// TCHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8 // TCHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8
// TCHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 // TCHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// TCHECK1-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]] // TCHECK1-NEXT: [[TMP10:%.*]] = mul nsw i64 1, [[TMP2]]
// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]] // TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i64 [[TMP10]]
// TCHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // TCHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// TCHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 // TCHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
// TCHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // TCHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// TCHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // TCHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// TCHECK1-NEXT: ret void // TCHECK1-NEXT: ret void
// //
// //
// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 // TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
// TCHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
// TCHECK1-NEXT: entry: // TCHECK1-NEXT: entry:
// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 // TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 // TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
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// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 // TCHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 // TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 // TCHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 // TCHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
// TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 // TCHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
// TCHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 // TCHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) // TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false)
// TCHECK2-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // TCHECK2-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// TCHECK2-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 // TCHECK2-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4
// TCHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 // TCHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
// TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// TCHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 // TCHECK2-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4
// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) // TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false)
// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) // TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false)
// TCHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] // TCHECK2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
// TCHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 // TCHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8
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// TCHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] // TCHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]]
// TCHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 // TCHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3
// TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 // TCHECK2-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8
// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 // TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0
// TCHECK2-NEXT: store i64 1, ptr [[X]], align 4 // TCHECK2-NEXT: store i64 1, ptr [[X]], align 4
// TCHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 // TCHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1
// TCHECK2-NEXT: store i8 1, ptr [[Y]], align 4 // TCHECK2-NEXT: store i8 1, ptr [[Y]], align 4
// TCHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // TCHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// TCHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// TCHECK2-NEXT: ret void // TCHECK2-NEXT: ret void
// //
// //
// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
// TCHECK2-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // TCHECK2-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
// TCHECK2-NEXT: entry: // TCHECK2-NEXT: entry:
// TCHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
// TCHECK2-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4
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// TCHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // TCHECK2-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// TCHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 // TCHECK2-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
// TCHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 // TCHECK2-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
// TCHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 // TCHECK2-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
// TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // TCHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // TCHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 // TCHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 // TCHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
// TCHECK2-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // TCHECK2-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// TCHECK2-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 // TCHECK2-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4
// TCHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // TCHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// TCHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 // TCHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
// TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // TCHECK2-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// TCHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // TCHECK2-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// TCHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // TCHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// TCHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 // TCHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
// TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) // TCHECK2-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false)
// TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 // TCHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4
// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
// TCHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 // TCHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// TCHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 // TCHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
// TCHECK2-NEXT: store double [[ADD]], ptr [[A]], align 4 // TCHECK2-NEXT: store double [[ADD]], ptr [[A]], align 4
// TCHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 // TCHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
// TCHECK2-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 // TCHECK2-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4
// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 // TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
// TCHECK2-NEXT: store double [[INC]], ptr [[A4]], align 4 // TCHECK2-NEXT: store double [[INC]], ptr [[A4]], align 4
// TCHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 // TCHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// TCHECK2-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] // TCHECK2-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]]
// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] // TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]]
// TCHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // TCHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// TCHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 // TCHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
// TCHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // TCHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// TCHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // TCHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// TCHECK2-NEXT: ret void // TCHECK2-NEXT: ret void
// //
// //
// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 // TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
// TCHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK2-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
// TCHECK2-NEXT: entry: // TCHECK2-NEXT: entry:
// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
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// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 // TCHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 // TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 // TCHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 // TCHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
// TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 // TCHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
// TCHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 // TCHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false) // TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[B5]], ptr align 4 [[TMP0]], i32 40, i1 false)
// TCHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave() // TCHECK3-NEXT: [[TMP8:%.*]] = call ptr @llvm.stacksave.p0()
// TCHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4 // TCHECK3-NEXT: store ptr [[TMP8]], ptr [[SAVED_STACK]], align 4
// TCHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4 // TCHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
// TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// TCHECK3-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4 // TCHECK3-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP1]], 4
// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false) // TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VLA6]], ptr align 4 [[TMP2]], i32 [[TMP9]], i1 false)
// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false) // TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[C7]], ptr align 8 [[TMP3]], i32 400, i1 false)
// TCHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]] // TCHECK3-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
// TCHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8 // TCHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP10]], align 8
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// TCHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]] // TCHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[VLA8]], i32 [[TMP14]]
// TCHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3 // TCHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3
// TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8 // TCHECK3-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX15]], align 8
// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0 // TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 0
// TCHECK3-NEXT: store i64 1, ptr [[X]], align 4 // TCHECK3-NEXT: store i64 1, ptr [[X]], align 4
// TCHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1 // TCHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D9]], i32 0, i32 1
// TCHECK3-NEXT: store i8 1, ptr [[Y]], align 4 // TCHECK3-NEXT: store i8 1, ptr [[Y]], align 4
// TCHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // TCHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// TCHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// TCHECK3-NEXT: ret void // TCHECK3-NEXT: ret void
// //
// //
// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111 // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
// TCHECK3-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] { // TCHECK3-SAME: (ptr noundef [[PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
// TCHECK3-NEXT: entry: // TCHECK3-NEXT: entry:
// TCHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
// TCHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[E_ADDR:%.*]] = alloca ptr, align 4
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// TCHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 // TCHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
// TCHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 // TCHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
// TCHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 // TCHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
// TCHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 // TCHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
// TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // TCHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // TCHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 // TCHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
// TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 // TCHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
// TCHECK3-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // TCHECK3-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// TCHECK3-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4 // TCHECK3-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 4
// TCHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // TCHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// TCHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2 // TCHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
// TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // TCHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// TCHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // TCHECK3-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// TCHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // TCHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// TCHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2 // TCHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
// TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false) // TCHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 2 [[VLA3]], ptr align 2 [[TMP3]], i32 [[TMP7]], i1 false)
// TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4 // TCHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B_ADDR]], align 4
// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double // TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
// TCHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 // TCHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
// TCHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 // TCHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
// TCHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4 // TCHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4
// TCHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 // TCHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
// TCHECK3-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4 // TCHECK3-NEXT: [[TMP9:%.*]] = load double, ptr [[A4]], align 4
// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 // TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
// TCHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4 // TCHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4
// TCHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 // TCHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
// TCHECK3-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]] // TCHECK3-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP2]]
// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]] // TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA3]], i32 [[TMP10]]
// TCHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // TCHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// TCHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2 // TCHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
// TCHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // TCHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// TCHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // TCHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// TCHECK3-NEXT: ret void // TCHECK3-NEXT: ret void
// //
// //
// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128 // TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
// TCHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { // TCHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
// TCHECK3-NEXT: entry: // TCHECK3-NEXT: entry:
// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 // TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
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// SIMD-ONLY1-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 // SIMD-ONLY1-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
// SIMD-ONLY1-NEXT: [[P:%.*]] = alloca ptr, align 64 // SIMD-ONLY1-NEXT: [[P:%.*]] = alloca ptr, align 64
// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 // SIMD-ONLY1-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
// SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY1-NEXT: store i16 0, ptr [[AA]], align 2 // SIMD-ONLY1-NEXT: store i16 0, ptr [[AA]], align 2
// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY1-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// SIMD-ONLY1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // SIMD-ONLY1-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // SIMD-ONLY1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// SIMD-ONLY1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // SIMD-ONLY1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// SIMD-ONLY1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // SIMD-ONLY1-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// SIMD-ONLY1-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8 // SIMD-ONLY1-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8
// SIMD-ONLY1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// SIMD-ONLY1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0 // SIMD-ONLY1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0
// SIMD-ONLY1-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY1-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8
// SIMD-ONLY1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // SIMD-ONLY1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// SIMD-ONLY1-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY1-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8
// SIMD-ONLY1-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY1-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
// SIMD-ONLY1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY1-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // SIMD-ONLY1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// SIMD-ONLY1-NEXT: ret i32 [[TMP14]] // SIMD-ONLY1-NEXT: ret i32 [[TMP14]]
// //
// //
// SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z3bariPd // SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z3bariPd
// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
// SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: entry:
// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // SIMD-ONLY1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// SIMD-ONLY1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // SIMD-ONLY1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double // SIMD-ONLY1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
// SIMD-ONLY1-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 // SIMD-ONLY1-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
// SIMD-ONLY1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] // SIMD-ONLY1-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
// SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]] // SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]]
// SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1 // SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1
// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2
// SIMD-ONLY1-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 // SIMD-ONLY1-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] // SIMD-ONLY1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
// SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY1-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // SIMD-ONLY1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// SIMD-ONLY1-NEXT: ret i32 [[ADD9]] // SIMD-ONLY1-NEXT: ret i32 [[ADD9]]
// //
// //
// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZL7fstatici // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZL7fstatici
// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: entry:
// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4
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// SIMD-ONLY11-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 // SIMD-ONLY11-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
// SIMD-ONLY11-NEXT: [[P:%.*]] = alloca ptr, align 64 // SIMD-ONLY11-NEXT: [[P:%.*]] = alloca ptr, align 64
// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8 // SIMD-ONLY11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
// SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY11-NEXT: store i16 0, ptr [[AA]], align 2 // SIMD-ONLY11-NEXT: store i16 0, ptr [[AA]], align 2
// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // SIMD-ONLY11-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// SIMD-ONLY11-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // SIMD-ONLY11-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // SIMD-ONLY11-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // SIMD-ONLY11-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// SIMD-ONLY11-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // SIMD-ONLY11-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// SIMD-ONLY11-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // SIMD-ONLY11-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// SIMD-ONLY11-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8 // SIMD-ONLY11-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 8
// SIMD-ONLY11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 // SIMD-ONLY11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
// SIMD-ONLY11-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0 // SIMD-ONLY11-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 0
// SIMD-ONLY11-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY11-NEXT: [[TMP13:%.*]] = load double, ptr [[ARRAYIDX13]], align 8
// SIMD-ONLY11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 // SIMD-ONLY11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
// SIMD-ONLY11-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8 // SIMD-ONLY11-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 8
// SIMD-ONLY11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY11-NEXT: [[TMP14:%.*]] = load i32, ptr [[A]], align 4
// SIMD-ONLY11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY11-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // SIMD-ONLY11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// SIMD-ONLY11-NEXT: ret i32 [[TMP14]] // SIMD-ONLY11-NEXT: ret i32 [[TMP14]]
// //
// //
// SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z3bariPd // SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z3bariPd
// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
// SIMD-ONLY11-NEXT: entry: // SIMD-ONLY11-NEXT: entry:
// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // SIMD-ONLY11-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // SIMD-ONLY11-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY11-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY11-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY11-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // SIMD-ONLY11-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// SIMD-ONLY11-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // SIMD-ONLY11-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double // SIMD-ONLY11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
// SIMD-ONLY11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 // SIMD-ONLY11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
// SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]] // SIMD-ONLY11-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
// SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]] // SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP8]]
// SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1 // SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i64 1
// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2
// SIMD-ONLY11-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32 // SIMD-ONLY11-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
// SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY11-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]] // SIMD-ONLY11-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
// SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY11-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // SIMD-ONLY11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// SIMD-ONLY11-NEXT: ret i32 [[ADD9]] // SIMD-ONLY11-NEXT: ret i32 [[ADD9]]
// //
// //
// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZL7fstatici // SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZL7fstatici
// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// SIMD-ONLY11-NEXT: entry: // SIMD-ONLY11-NEXT: entry:
// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4
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// SIMD-ONLY12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // SIMD-ONLY12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
// SIMD-ONLY12-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 // SIMD-ONLY12-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
// SIMD-ONLY12-NEXT: [[P:%.*]] = alloca ptr, align 64 // SIMD-ONLY12-NEXT: [[P:%.*]] = alloca ptr, align 64
// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY12-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 // SIMD-ONLY12-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4
// SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY12-NEXT: store i16 0, ptr [[AA]], align 2 // SIMD-ONLY12-NEXT: store i16 0, ptr [[AA]], align 2
// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY12-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY12-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY12-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// SIMD-ONLY12-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // SIMD-ONLY12-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// SIMD-ONLY12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // SIMD-ONLY12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// SIMD-ONLY12-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // SIMD-ONLY12-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// SIMD-ONLY12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 // SIMD-ONLY12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0
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// SIMD-ONLY12-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4 // SIMD-ONLY12-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4
// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4
// SIMD-ONLY12-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0 // SIMD-ONLY12-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0
// SIMD-ONLY12-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY12-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4
// SIMD-ONLY12-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 // SIMD-ONLY12-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
// SIMD-ONLY12-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY12-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4
// SIMD-ONLY12-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY12-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
// SIMD-ONLY12-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // SIMD-ONLY12-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// SIMD-ONLY12-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY12-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])
// SIMD-ONLY12-NEXT: ret i32 [[TMP12]] // SIMD-ONLY12-NEXT: ret i32 [[TMP12]]
// //
// //
// SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z3bariPd // SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z3bariPd
// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
// SIMD-ONLY12-NEXT: entry: // SIMD-ONLY12-NEXT: entry:
// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
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// SIMD-ONLY12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
// SIMD-ONLY12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // SIMD-ONLY12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // SIMD-ONLY12-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY12-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY12-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY12-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// SIMD-ONLY12-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // SIMD-ONLY12-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double // SIMD-ONLY12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
// SIMD-ONLY12-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 // SIMD-ONLY12-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
// SIMD-ONLY12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// SIMD-ONLY12-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] // SIMD-ONLY12-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
// SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]] // SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]]
// SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1 // SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1
// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2
// SIMD-ONLY12-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 // SIMD-ONLY12-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY12-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] // SIMD-ONLY12-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// SIMD-ONLY12-NEXT: call void @llvm.stackrestore(ptr [[TMP10]]) // SIMD-ONLY12-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]])
// SIMD-ONLY12-NEXT: ret i32 [[ADD9]] // SIMD-ONLY12-NEXT: ret i32 [[ADD9]]
// //
// //
// SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZL7fstatici // SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZL7fstatici
// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// SIMD-ONLY12-NEXT: entry: // SIMD-ONLY12-NEXT: entry:
// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4
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// SIMD-ONLY13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 // SIMD-ONLY13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
// SIMD-ONLY13-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4 // SIMD-ONLY13-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
// SIMD-ONLY13-NEXT: [[P:%.*]] = alloca ptr, align 64 // SIMD-ONLY13-NEXT: [[P:%.*]] = alloca ptr, align 64
// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY13-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4 // SIMD-ONLY13-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4
// SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: store i32 0, ptr [[A]], align 4
// SIMD-ONLY13-NEXT: store i16 0, ptr [[AA]], align 2 // SIMD-ONLY13-NEXT: store i16 0, ptr [[AA]], align 2
// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY13-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY13-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY13-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// SIMD-ONLY13-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // SIMD-ONLY13-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// SIMD-ONLY13-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // SIMD-ONLY13-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// SIMD-ONLY13-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // SIMD-ONLY13-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// SIMD-ONLY13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0 // SIMD-ONLY13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], ptr [[E]], i32 0, i32 0
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// SIMD-ONLY13-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4 // SIMD-ONLY13-NEXT: store double [[CONV11]], ptr [[ARRAYIDX12]], align 4
// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4
// SIMD-ONLY13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0 // SIMD-ONLY13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[TMP10]], i32 0
// SIMD-ONLY13-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY13-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX13]], align 4
// SIMD-ONLY13-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 // SIMD-ONLY13-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
// SIMD-ONLY13-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4 // SIMD-ONLY13-NEXT: store double [[INC]], ptr [[ARRAYIDX13]], align 4
// SIMD-ONLY13-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4 // SIMD-ONLY13-NEXT: [[TMP12:%.*]] = load i32, ptr [[A]], align 4
// SIMD-ONLY13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // SIMD-ONLY13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// SIMD-ONLY13-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])
// SIMD-ONLY13-NEXT: ret i32 [[TMP12]] // SIMD-ONLY13-NEXT: ret i32 [[TMP12]]
// //
// //
// SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z3bariPd // SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z3bariPd
// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
// SIMD-ONLY13-NEXT: entry: // SIMD-ONLY13-NEXT: entry:
// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4 // SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
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// SIMD-ONLY13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
// SIMD-ONLY13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // SIMD-ONLY13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// SIMD-ONLY13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // SIMD-ONLY13-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // SIMD-ONLY13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// SIMD-ONLY13-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // SIMD-ONLY13-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double // SIMD-ONLY13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
// SIMD-ONLY13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 // SIMD-ONLY13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
// SIMD-ONLY13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 // SIMD-ONLY13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
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// SIMD-ONLY13-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]] // SIMD-ONLY13-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
// SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]] // SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP7]]
// SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1 // SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX6]], i32 1
// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2 // SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i16, ptr [[ARRAYIDX7]], align 2
// SIMD-ONLY13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32 // SIMD-ONLY13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4 // SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, ptr [[B]], align 4
// SIMD-ONLY13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]] // SIMD-ONLY13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// SIMD-ONLY13-NEXT: call void @llvm.stackrestore(ptr [[TMP10]]) // SIMD-ONLY13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP10]])
// SIMD-ONLY13-NEXT: ret i32 [[ADD9]] // SIMD-ONLY13-NEXT: ret i32 [[ADD9]]
// //
// //
// SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZL7fstatici // SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZL7fstatici
// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// SIMD-ONLY13-NEXT: entry: // SIMD-ONLY13-NEXT: entry:
// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4 // SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_has_device_addr_codegen_01.cpp

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// CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK-NEXT: store float 0.000000e+00, ptr [[A]], align 4 // CHECK-NEXT: store float 0.000000e+00, ptr [[A]], align 4
// CHECK-NEXT: store ptr [[A]], ptr [[PTR]], align 8 // CHECK-NEXT: store ptr [[A]], ptr [[PTR]], align 8
// CHECK-NEXT: store ptr [[A]], ptr [[REF]], align 8 // CHECK-NEXT: store ptr [[A]], ptr [[REF]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[A]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[A]], align 4
// CHECK-NEXT: [[CONV:%.*]] = fptosi float [[TMP0]] to i32 // CHECK-NEXT: [[CONV:%.*]] = fptosi float [[TMP0]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[CONV]] to i64 // CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[CONV]] to i64
// CHECK-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // CHECK-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// CHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 8 dereferenceable(40) [[S]]) // CHECK-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 8 dereferenceable(40) [[S]])
// CHECK-NEXT: call void @_ZN1S3fooEv(ptr noundef nonnull align 8 dereferenceable(40) [[S]]) // CHECK-NEXT: call void @_ZN1S3fooEv(ptr noundef nonnull align 8 dereferenceable(40) [[S]])
// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[REF]], align 8 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[REF]], align 8
// CHECK-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // CHECK-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8
// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[PTR]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[PTR]], align 8
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// CHECK: omp_offload.failed: // CHECK: omp_offload.failed:
// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27(ptr [[A]], ptr [[TMP4]], ptr [[TMP5]], ptr [[ARR]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR5:[0-9]+]] // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27(ptr [[A]], ptr [[TMP4]], ptr [[TMP5]], ptr [[ARR]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR5:[0-9]+]]
// CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK: omp_offload.cont: // CHECK: omp_offload.cont:
// CHECK-NEXT: [[TMP41:%.*]] = load float, ptr [[A]], align 4 // CHECK-NEXT: [[TMP41:%.*]] = load float, ptr [[A]], align 4
// CHECK-NEXT: [[CONV1:%.*]] = fptosi float [[TMP41]] to i32 // CHECK-NEXT: [[CONV1:%.*]] = fptosi float [[TMP41]] to i32
// CHECK-NEXT: store i32 [[CONV1]], ptr [[RETVAL]], align 4 // CHECK-NEXT: store i32 [[CONV1]], ptr [[RETVAL]], align 4
// CHECK-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK-NEXT: [[TMP42:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK-NEXT: call void @llvm.stackrestore(ptr [[TMP42]]) // CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP42]])
// CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: [[TMP43:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK-NEXT: ret i32 [[TMP43]] // CHECK-NEXT: ret i32 [[TMP43]]
// //
// //
// CHECK-LABEL: define {{[^@]+}}@_ZN1SC1Ev // CHECK-LABEL: define {{[^@]+}}@_ZN1SC1Ev
// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat { // CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat {
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
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// SIMD-ONLY0-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[TMP:%.*]] = alloca ptr, align 8
// SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4 // SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4
// SIMD-ONLY0-NEXT: store float 0.000000e+00, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: store float 0.000000e+00, ptr [[A]], align 4
// SIMD-ONLY0-NEXT: store ptr [[A]], ptr [[PTR]], align 8 // SIMD-ONLY0-NEXT: store ptr [[A]], ptr [[PTR]], align 8
// SIMD-ONLY0-NEXT: store ptr [[A]], ptr [[REF]], align 8 // SIMD-ONLY0-NEXT: store ptr [[A]], ptr [[REF]], align 8
// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load float, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load float, ptr [[A]], align 4
// SIMD-ONLY0-NEXT: [[CONV:%.*]] = fptosi float [[TMP0]] to i32 // SIMD-ONLY0-NEXT: [[CONV:%.*]] = fptosi float [[TMP0]] to i32
// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = zext i32 [[CONV]] to i64 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = zext i32 [[CONV]] to i64
// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// SIMD-ONLY0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // SIMD-ONLY0-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// SIMD-ONLY0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // SIMD-ONLY0-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// SIMD-ONLY0-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 8 dereferenceable(40) [[S]]) // SIMD-ONLY0-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 8 dereferenceable(40) [[S]])
// SIMD-ONLY0-NEXT: call void @_ZN1S3fooEv(ptr noundef nonnull align 8 dereferenceable(40) [[S]]) // SIMD-ONLY0-NEXT: call void @_ZN1S3fooEv(ptr noundef nonnull align 8 dereferenceable(40) [[S]])
// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[REF]], align 8 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[REF]], align 8
// SIMD-ONLY0-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // SIMD-ONLY0-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8
// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load ptr, ptr [[REF]], align 8 // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load ptr, ptr [[REF]], align 8
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// SIMD-ONLY0-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 0 // SIMD-ONLY0-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 0
// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX4]], align 4 // SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
// SIMD-ONLY0-NEXT: [[INC5:%.*]] = fadd float [[TMP11]], 1.000000e+00 // SIMD-ONLY0-NEXT: [[INC5:%.*]] = fadd float [[TMP11]], 1.000000e+00
// SIMD-ONLY0-NEXT: store float [[INC5]], ptr [[ARRAYIDX4]], align 4 // SIMD-ONLY0-NEXT: store float [[INC5]], ptr [[ARRAYIDX4]], align 4
// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load float, ptr [[A]], align 4 // SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load float, ptr [[A]], align 4
// SIMD-ONLY0-NEXT: [[CONV6:%.*]] = fptosi float [[TMP12]] to i32 // SIMD-ONLY0-NEXT: [[CONV6:%.*]] = fptosi float [[TMP12]] to i32
// SIMD-ONLY0-NEXT: store i32 [[CONV6]], ptr [[RETVAL]], align 4 // SIMD-ONLY0-NEXT: store i32 [[CONV6]], ptr [[RETVAL]], align 4
// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // SIMD-ONLY0-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])
// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
// SIMD-ONLY0-NEXT: ret i32 [[TMP14]] // SIMD-ONLY0-NEXT: ret i32 [[TMP14]]
// //
// //
// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SC1Ev // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SC1Ev
// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat { // SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(40) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat {
// SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: entry:
// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/target_in_reduction_codegen.cpp

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// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK1: arrayctor.cont: // CHECK1: arrayctor.cont:
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 // CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1
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// CHECK1-NEXT: store i32 1, ptr [[TMP56]], align 8 // CHECK1-NEXT: store i32 1, ptr [[TMP56]], align 8
// CHECK1-NEXT: [[TMP58:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]]) // CHECK1-NEXT: [[TMP58:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]])
// CHECK1-NEXT: store ptr [[TMP58]], ptr [[DOTTASK_RED_6]], align 8 // CHECK1-NEXT: store ptr [[TMP58]], ptr [[DOTTASK_RED_6]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP59]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP59]])
// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0
// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP60]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP60]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
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clang/test/OpenMP/target_parallel_codegen.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
// CHECK1-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
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// CHECK1: omp_offload.cont18: // CHECK1: omp_offload.cont18:
// CHECK1-NEXT: br label [[OMP_IF_END20:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END20:%.*]]
// CHECK1: omp_if.else19: // CHECK1: omp_if.else19:
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]]
// CHECK1-NEXT: br label [[OMP_IF_END20]] // CHECK1-NEXT: br label [[OMP_IF_END20]]
// CHECK1: omp_if.end20: // CHECK1: omp_if.end20:
// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])
// CHECK1-NEXT: ret i32 [[TMP115]] // CHECK1-NEXT: ret i32 [[TMP115]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
// CHECK1-SAME: () #[[ATTR2:[0-9]+]] { // CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK1-NEXT: ret i32 [[ADD3]] // CHECK1-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x ptr], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x ptr], align 4
// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
// CHECK3-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1) // CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1)
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// CHECK3: omp_offload.cont18: // CHECK3: omp_offload.cont18:
// CHECK3-NEXT: br label [[OMP_IF_END20:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END20:%.*]]
// CHECK3: omp_if.else19: // CHECK3: omp_if.else19:
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]]
// CHECK3-NEXT: br label [[OMP_IF_END20]] // CHECK3-NEXT: br label [[OMP_IF_END20]]
// CHECK3: omp_if.end20: // CHECK3: omp_if.end20:
// CHECK3-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP115:%.*]] = load i32, ptr [[A]], align 4
// CHECK3-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])
// CHECK3-NEXT: ret i32 [[TMP115]] // CHECK3-NEXT: ret i32 [[TMP115]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
// CHECK3-SAME: () #[[ATTR2:[0-9]+]] { // CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined) // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
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// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK3-NEXT: ret i32 [[ADD3]] // CHECK3-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_parallel_for_codegen.cpp

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// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
// CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
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// CHECK1: omp_offload.cont19: // CHECK1: omp_offload.cont19:
// CHECK1-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END21:%.*]]
// CHECK1: omp_if.else20: // CHECK1: omp_if.else20:
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]]
// CHECK1-NEXT: br label [[OMP_IF_END21]] // CHECK1-NEXT: br label [[OMP_IF_END21]]
// CHECK1: omp_if.end21: // CHECK1: omp_if.end21:
// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP148]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP148]])
// CHECK1-NEXT: ret i32 [[TMP147]] // CHECK1-NEXT: ret i32 [[TMP147]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
// CHECK1-SAME: () #[[ATTR2:[0-9]+]] { // CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK1-NEXT: ret i32 [[ADD3]] // CHECK1-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4
// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
// CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
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// CHECK3: omp_offload.cont19: // CHECK3: omp_offload.cont19:
// CHECK3-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END21:%.*]]
// CHECK3: omp_if.else20: // CHECK3: omp_if.else20:
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]] // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]]
// CHECK3-NEXT: br label [[OMP_IF_END21]] // CHECK3-NEXT: br label [[OMP_IF_END21]]
// CHECK3: omp_if.end21: // CHECK3: omp_if.end21:
// CHECK3-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 4
// CHECK3-NEXT: [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP146]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP146]])
// CHECK3-NEXT: ret i32 [[TMP145]] // CHECK3-NEXT: ret i32 [[TMP145]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
// CHECK3-SAME: () #[[ATTR2:[0-9]+]] { // CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined) // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
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// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK3-NEXT: ret i32 [[ADD3]] // CHECK3-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
// CHECK17-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK17-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK17-NEXT: store i32 0, ptr [[A]], align 4 // CHECK17-NEXT: store i32 0, ptr [[A]], align 4
// CHECK17-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK17-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK17-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
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// CHECK17: omp_offload.cont19: // CHECK17: omp_offload.cont19:
// CHECK17-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK17-NEXT: br label [[OMP_IF_END21:%.*]]
// CHECK17: omp_if.else20: // CHECK17: omp_if.else20:
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]] // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]]
// CHECK17-NEXT: br label [[OMP_IF_END21]] // CHECK17-NEXT: br label [[OMP_IF_END21]]
// CHECK17: omp_if.end21: // CHECK17: omp_if.end21:
// CHECK17-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4 // CHECK17-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4
// CHECK17-NEXT: [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP148]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP148]])
// CHECK17-NEXT: ret i32 [[TMP147]] // CHECK17-NEXT: ret i32 [[TMP147]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
// CHECK17-SAME: () #[[ATTR2:[0-9]+]] { // CHECK17-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined) // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
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// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK17-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK17-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK17-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK17-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK17-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK17-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK17-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK17-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK17-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK17-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK17-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK17-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK17-NEXT: ret i32 [[ADD3]] // CHECK17-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4
// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
// CHECK19-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK19-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK19-NEXT: store i32 0, ptr [[A]], align 4 // CHECK19-NEXT: store i32 0, ptr [[A]], align 4
// CHECK19-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK19-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
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// CHECK19: omp_offload.cont19: // CHECK19: omp_offload.cont19:
// CHECK19-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK19-NEXT: br label [[OMP_IF_END21:%.*]]
// CHECK19: omp_if.else20: // CHECK19: omp_if.else20:
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]] // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]]
// CHECK19-NEXT: br label [[OMP_IF_END21]] // CHECK19-NEXT: br label [[OMP_IF_END21]]
// CHECK19: omp_if.end21: // CHECK19: omp_if.end21:
// CHECK19-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 4 // CHECK19-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 4
// CHECK19-NEXT: [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP146]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP146]])
// CHECK19-NEXT: ret i32 [[TMP145]] // CHECK19-NEXT: ret i32 [[TMP145]]
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
// CHECK19-SAME: () #[[ATTR2:[0-9]+]] { // CHECK19-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined) // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
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// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK19-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK19-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK19-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK19-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK19-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK19-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK19-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK19-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK19-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK19-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK19-NEXT: ret i32 [[ADD3]] // CHECK19-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp

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// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]] // CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1 // CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1
// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]] // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP94]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP94]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]]
// CHECK1: omp.arraycpy.done36: // CHECK1: omp.arraycpy.done36:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP103:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP103:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP103]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP103]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/target_parallel_for_simd_codegen.cpp

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// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
// CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
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// CHECK1: omp_offload.cont19: // CHECK1: omp_offload.cont19:
// CHECK1-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END21:%.*]]
// CHECK1: omp_if.else20: // CHECK1: omp_if.else20:
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]]
// CHECK1-NEXT: br label [[OMP_IF_END21]] // CHECK1-NEXT: br label [[OMP_IF_END21]]
// CHECK1: omp_if.end21: // CHECK1: omp_if.end21:
// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP134]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP134]])
// CHECK1-NEXT: ret i32 [[TMP133]] // CHECK1-NEXT: ret i32 [[TMP133]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
// CHECK1-SAME: () #[[ATTR2:[0-9]+]] { // CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
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// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK1-NEXT: ret i32 [[ADD3]] // CHECK1-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4
// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
// CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1) // CHECK3-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1)
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// CHECK3: omp_offload.cont19: // CHECK3: omp_offload.cont19:
// CHECK3-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END21:%.*]]
// CHECK3: omp_if.else20: // CHECK3: omp_if.else20:
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]]
// CHECK3-NEXT: br label [[OMP_IF_END21]] // CHECK3-NEXT: br label [[OMP_IF_END21]]
// CHECK3: omp_if.end21: // CHECK3: omp_if.end21:
// CHECK3-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4
// CHECK3-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP132]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP132]])
// CHECK3-NEXT: ret i32 [[TMP131]] // CHECK3-NEXT: ret i32 [[TMP131]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
// CHECK3-SAME: () #[[ATTR2:[0-9]+]] { // CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)
// CHECK3-NEXT: ret void // CHECK3-NEXT: ret void
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// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK3-NEXT: ret i32 [[ADD3]] // CHECK3-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
// CHECK5-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK5-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK5-NEXT: store i32 0, ptr [[A]], align 4 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4
// CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
// CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] // CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 // CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
// CHECK5-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
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// CHECK5: omp_offload.cont19: // CHECK5: omp_offload.cont19:
// CHECK5-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK5-NEXT: br label [[OMP_IF_END21:%.*]]
// CHECK5: omp_if.else20: // CHECK5: omp_if.else20:
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]] // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP76]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP78]]) #[[ATTR4]]
// CHECK5-NEXT: br label [[OMP_IF_END21]] // CHECK5-NEXT: br label [[OMP_IF_END21]]
// CHECK5: omp_if.end21: // CHECK5: omp_if.end21:
// CHECK5-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4 // CHECK5-NEXT: [[TMP133:%.*]] = load i32, ptr [[A]], align 4
// CHECK5-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK5-NEXT: [[TMP134:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP134]]) // CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP134]])
// CHECK5-NEXT: ret i32 [[TMP133]] // CHECK5-NEXT: ret i32 [[TMP133]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
// CHECK5-SAME: () #[[ATTR2:[0-9]+]] { // CHECK5-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)
// CHECK5-NEXT: ret void // CHECK5-NEXT: ret void
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// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK5-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK5-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
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// CHECK5-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK5-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP53]] // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP53]]
// CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK5-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK5-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2 // CHECK5-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2
// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i32 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i32
// CHECK5-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 4 // CHECK5-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 4
// CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]] // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]]
// CHECK5-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK5-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP56]]) // CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP56]])
// CHECK5-NEXT: ret i32 [[ADD6]] // CHECK5-NEXT: ret i32 [[ADD6]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4
// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
// CHECK7-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK7-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK7-NEXT: store i32 0, ptr [[A]], align 4 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4
// CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] // CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 // CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
// CHECK7-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1) // CHECK7-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1)
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// CHECK7: omp_offload.cont19: // CHECK7: omp_offload.cont19:
// CHECK7-NEXT: br label [[OMP_IF_END21:%.*]] // CHECK7-NEXT: br label [[OMP_IF_END21:%.*]]
// CHECK7: omp_if.else20: // CHECK7: omp_if.else20:
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]] // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP72]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP74]]) #[[ATTR4]]
// CHECK7-NEXT: br label [[OMP_IF_END21]] // CHECK7-NEXT: br label [[OMP_IF_END21]]
// CHECK7: omp_if.end21: // CHECK7: omp_if.end21:
// CHECK7-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4 // CHECK7-NEXT: [[TMP131:%.*]] = load i32, ptr [[A]], align 4
// CHECK7-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK7-NEXT: [[TMP132:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK7-NEXT: call void @llvm.stackrestore(ptr [[TMP132]]) // CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP132]])
// CHECK7-NEXT: ret i32 [[TMP131]] // CHECK7-NEXT: ret i32 [[TMP131]]
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96
// CHECK7-SAME: () #[[ATTR2:[0-9]+]] { // CHECK7-SAME: () #[[ATTR2:[0-9]+]] {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined) // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.omp_outlined)
// CHECK7-NEXT: ret void // CHECK7-NEXT: ret void
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// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK7-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK7-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
// CHECK7-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK7-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
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// CHECK7-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK7-NEXT: [[TMP53:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP53]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP53]]
// CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK7-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2 // CHECK7-NEXT: [[TMP54:%.*]] = load i16, ptr [[ARRAYIDX5]], align 2
// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i32 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP54]] to i32
// CHECK7-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 4 // CHECK7-NEXT: [[TMP55:%.*]] = load i32, ptr [[B]], align 4
// CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]] // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], [[TMP55]]
// CHECK7-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK7-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK7-NEXT: call void @llvm.stackrestore(ptr [[TMP56]]) // CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP56]])
// CHECK7-NEXT: ret i32 [[ADD6]] // CHECK7-NEXT: ret i32 [[ADD6]]
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK9-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[IT72:%.*]] = alloca i8, align 1 // CHECK9-NEXT: [[IT72:%.*]] = alloca i8, align 1
// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK9-NEXT: store i32 0, ptr [[A]], align 4 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4
// CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// CHECK9-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// CHECK9-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]
// CHECK9-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 // CHECK9-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1
// CHECK9-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]]
// CHECK9: omp.inner.for.end100: // CHECK9: omp.inner.for.end100:
// CHECK9-NEXT: store i8 96, ptr [[IT72]], align 1 // CHECK9-NEXT: store i8 96, ptr [[IT72]], align 1
// CHECK9-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4 // CHECK9-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4
// CHECK9-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP59]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP59]])
// CHECK9-NEXT: ret i32 [[TMP58]] // CHECK9-NEXT: ret i32 [[TMP58]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_Z3bari // CHECK9-LABEL: define {{[^@]+}}@_Z3bari
// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK9-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK9-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK9-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK9-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 // CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK9-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8 // CHECK9-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
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// CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]] // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]]
// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i64 1 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i64 1
// CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2 // CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2
// CHECK9-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32 // CHECK9-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]] // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]]
// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP16]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])
// CHECK9-NEXT: ret i32 [[ADD10]] // CHECK9-NEXT: ret i32 [[ADD10]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK11-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[IT72:%.*]] = alloca i8, align 1 // CHECK11-NEXT: [[IT72:%.*]] = alloca i8, align 1
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK11-NEXT: store i32 0, ptr [[A]], align 4 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4
// CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
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// CHECK11-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]
// CHECK11-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 // CHECK11-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1
// CHECK11-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]]
// CHECK11: omp.inner.for.end100: // CHECK11: omp.inner.for.end100:
// CHECK11-NEXT: store i8 96, ptr [[IT72]], align 1 // CHECK11-NEXT: store i8 96, ptr [[IT72]], align 1
// CHECK11-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4 // CHECK11-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4
// CHECK11-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP57]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP57]])
// CHECK11-NEXT: ret i32 [[TMP56]] // CHECK11-NEXT: ret i32 [[TMP56]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_Z3bari // CHECK11-LABEL: define {{[^@]+}}@_Z3bari
// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK11-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK11-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8 // CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
// CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK11-NEXT: store i64 [[TMP4]], ptr [[DOTOMP_IV]], align 8 // CHECK11-NEXT: store i64 [[TMP4]], ptr [[DOTOMP_IV]], align 8
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// CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]] // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]]
// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i32 1 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX7]], i32 1
// CHECK11-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2 // CHECK11-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX8]], align 2
// CHECK11-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32 // CHECK11-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 4
// CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]] // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]]
// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK11-NEXT: ret i32 [[ADD10]] // CHECK11-NEXT: ret i32 [[ADD10]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[IT72:%.*]] = alloca i8, align 1 // CHECK13-NEXT: [[IT72:%.*]] = alloca i8, align 1
// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK13-NEXT: store i32 0, ptr [[A]], align 4 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4
// CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// CHECK13-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // CHECK13-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// CHECK13-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]
// CHECK13-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 // CHECK13-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1
// CHECK13-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]]
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]]
// CHECK13: omp.inner.for.end100: // CHECK13: omp.inner.for.end100:
// CHECK13-NEXT: store i8 96, ptr [[IT72]], align 1 // CHECK13-NEXT: store i8 96, ptr [[IT72]], align 1
// CHECK13-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4 // CHECK13-NEXT: [[TMP58:%.*]] = load i32, ptr [[A]], align 4
// CHECK13-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP59:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP59]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP59]])
// CHECK13-NEXT: ret i32 [[TMP58]] // CHECK13-NEXT: ret i32 [[TMP58]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z3bari // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK13-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK13-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK13-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK13-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK13-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
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// CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK13-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]] // CHECK13-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]]
// CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i64 1 // CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i64 1
// CHECK13-NEXT: [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2 // CHECK13-NEXT: [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2
// CHECK13-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32 // CHECK13-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[B]], align 4 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[B]], align 4
// CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]] // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]]
// CHECK13-NEXT: [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP25]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP25]])
// CHECK13-NEXT: ret i32 [[ADD28]] // CHECK13-NEXT: ret i32 [[ADD28]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[IT72:%.*]] = alloca i8, align 1 // CHECK15-NEXT: [[IT72:%.*]] = alloca i8, align 1
// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK15-NEXT: store i32 0, ptr [[A]], align 4 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4
// CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
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// CHECK15-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]
// CHECK15-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 // CHECK15-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1
// CHECK15-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: store i32 [[ADD99]], ptr [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]]
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]]
// CHECK15: omp.inner.for.end100: // CHECK15: omp.inner.for.end100:
// CHECK15-NEXT: store i8 96, ptr [[IT72]], align 1 // CHECK15-NEXT: store i8 96, ptr [[IT72]], align 1
// CHECK15-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4 // CHECK15-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4
// CHECK15-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP57:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP57]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP57]])
// CHECK15-NEXT: ret i32 [[TMP56]] // CHECK15-NEXT: ret i32 [[TMP56]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z3bari // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8
// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK15-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK15-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 // CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
// CHECK15-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK15-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
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// CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK15-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]] // CHECK15-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]]
// CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i32 1 // CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX25]], i32 1
// CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2 // CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX26]], align 2
// CHECK15-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32 // CHECK15-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32
// CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[B]], align 4 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[B]], align 4
// CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]] // CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]]
// CHECK15-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP24]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])
// CHECK15-NEXT: ret i32 [[ADD28]] // CHECK15-NEXT: ret i32 [[ADD28]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]] // CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1 // CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1
// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]] // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT29]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT30]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP83]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE31:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT29]], [[TMP83]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE31]], label [[OMP_ARRAYCPY_DONE32]], label [[OMP_ARRAYCPY_BODY20]]
// CHECK1: omp.arraycpy.done32: // CHECK1: omp.arraycpy.done32:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP92:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP92:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP92]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP92]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/target_private_codegen.cpp

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines#pragma omp target private(a, aa)
// TCHECK: [[C:%.+]] = alloca [5 x [10 x double]], // TCHECK: [[C:%.+]] = alloca [5 x [10 x double]],
// TCHECK: [[D:%.+]] = alloca [[TT]], // TCHECK: [[D:%.+]] = alloca [[TT]],
// TCHECK: store i{{[0-9]+}} [[VLA]], ptr [[VLA_ADDR]], // TCHECK: store i{{[0-9]+}} [[VLA]], ptr [[VLA_ADDR]],
// TCHECK: store i{{[0-9]+}} [[VLA1]], ptr [[VLA_ADDR2]], // TCHECK: store i{{[0-9]+}} [[VLA1]], ptr [[VLA_ADDR2]],
// TCHECK: store i{{[0-9]+}} [[VLA3]], ptr [[VLA_ADDR4]], // TCHECK: store i{{[0-9]+}} [[VLA3]], ptr [[VLA_ADDR4]],
// TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR]], // TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR]],
// TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR2]], // TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR2]],
// TCHECK: [[VLA_ADDR_REF4:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR4]], // TCHECK: [[VLA_ADDR_REF4:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR4]],
// TCHECK: [[RET_STACK:%.+]] = call ptr @llvm.stacksave() // TCHECK: [[RET_STACK:%.+]] = call ptr @llvm.stacksave.p0()
// TCHECK: store ptr [[RET_STACK]], ptr [[SSTACK]], // TCHECK: store ptr [[RET_STACK]], ptr [[SSTACK]],
// TCHECK: [[VLA5:%.+]] = alloca float, i{{[0-9]+}} [[VLA_ADDR_REF]], // TCHECK: [[VLA5:%.+]] = alloca float, i{{[0-9]+}} [[VLA_ADDR_REF]],
// TCHECK: [[VLA6_SIZE:%.+]] = mul{{.+}} i{{[0-9]+}} [[VLA_ADDR_REF2]], [[VLA_ADDR_REF4]] // TCHECK: [[VLA6_SIZE:%.+]] = mul{{.+}} i{{[0-9]+}} [[VLA_ADDR_REF2]], [[VLA_ADDR_REF4]]
// TCHECK: [[VLA6:%.+]] = alloca double, i{{[0-9]+}} [[VLA6_SIZE]], // TCHECK: [[VLA6:%.+]] = alloca double, i{{[0-9]+}} [[VLA6_SIZE]],
// a = 1 // a = 1
// TCHECK: store i{{[0-9]+}} 1, ptr [[A]], // TCHECK: store i{{[0-9]+}} 1, ptr [[A]],
Show All 21 Lines#pragma omp target private(a, aa)
// store i{{[0-9]+}} 1, ptr [[X_FIELD]], // store i{{[0-9]+}} 1, ptr [[X_FIELD]],
// d.Y = 1 // d.Y = 1
// [[Y_FIELD:%.+]] = getelementptr inbounds [[TT]] ptr [[D]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 // [[Y_FIELD:%.+]] = getelementptr inbounds [[TT]] ptr [[D]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
// store i{{[0-9]+}} 1, ptr [[Y_FIELD]], // store i{{[0-9]+}} 1, ptr [[Y_FIELD]],
// finish // finish
// [[RELOAD_SSTACK:%.+]] = load ptr, ptr [[SSTACK]], // [[RELOAD_SSTACK:%.+]] = load ptr, ptr [[SSTACK]],
// call ovid @llvm.stackrestore(ptr [[RELOAD_SSTACK]]) // call ovid @llvm.stackrestore.p0(ptr [[RELOAD_SSTACK]])
// ret void // ret void
return a; return a;
} }
template<typename tx> template<typename tx>
tx ftemplate(int n) { tx ftemplate(int n) {
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines#pragma omp target private(b,c)
// TCHECK: [[B:%.+]] = alloca i{{[0-9]+}}, // TCHECK: [[B:%.+]] = alloca i{{[0-9]+}},
// TCHECK: [[SSTACK:%.+]] = alloca ptr, // TCHECK: [[SSTACK:%.+]] = alloca ptr,
// TCHECK: store ptr [[TH]], ptr [[TH_ADDR]], // TCHECK: store ptr [[TH]], ptr [[TH_ADDR]],
// TCHECK: store i{{[0-9]+}} [[VLA]], ptr [[VLA_ADDR]], // TCHECK: store i{{[0-9]+}} [[VLA]], ptr [[VLA_ADDR]],
// TCHECK: store i{{[0-9]+}} [[VLA1]], ptr [[VLA_ADDR2]], // TCHECK: store i{{[0-9]+}} [[VLA1]], ptr [[VLA_ADDR2]],
// TCHECK: [[TH_ADDR_REF:%.+]] = load ptr, ptr [[TH_ADDR]], // TCHECK: [[TH_ADDR_REF:%.+]] = load ptr, ptr [[TH_ADDR]],
// TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR]], // TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR]],
// TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR2]], // TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, ptr [[VLA_ADDR2]],
// TCHECK: [[RET_STACK:%.+]] = call ptr @llvm.stacksave() // TCHECK: [[RET_STACK:%.+]] = call ptr @llvm.stacksave.p0()
// TCHECK: store ptr [[RET_STACK:%.+]], ptr [[SSTACK]], // TCHECK: store ptr [[RET_STACK:%.+]], ptr [[SSTACK]],
// this->a = (double)b + 1.5; // this->a = (double)b + 1.5;
// TCHECK: [[VLA_IND:%.+]] = mul{{.+}} i{{[0-9]+}} [[VLA_ADDR_REF]], [[VLA_ADDR_REF2]] // TCHECK: [[VLA_IND:%.+]] = mul{{.+}} i{{[0-9]+}} [[VLA_ADDR_REF]], [[VLA_ADDR_REF2]]
// TCHECK: [[VLA3:%.+]] = alloca i{{[0-9]+}}, i{{[0-9]+}} [[VLA_IND]], // TCHECK: [[VLA3:%.+]] = alloca i{{[0-9]+}}, i{{[0-9]+}} [[VLA_IND]],
// TCHECK: [[B_VAL:%.+]] = load i{{[0-9]+}}, ptr [[B]], // TCHECK: [[B_VAL:%.+]] = load i{{[0-9]+}}, ptr [[B]],
// TCHECK: [[B_CONV:%.+]] = sitofp i{{[0-9]+}} [[B_VAL]] to double // TCHECK: [[B_CONV:%.+]] = sitofp i{{[0-9]+}} [[B_VAL]] to double
// TCHECK: [[NEW_A_VAL:%.+]] = fadd double [[B_CONV]], 1.5{{.+}}+00 // TCHECK: [[NEW_A_VAL:%.+]] = fadd double [[B_CONV]], 1.5{{.+}}+00
// TCHECK: [[A_FIELD:%.+]] = getelementptr inbounds [[S1]], ptr [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // TCHECK: [[A_FIELD:%.+]] = getelementptr inbounds [[S1]], ptr [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
// TCHECK: store double [[NEW_A_VAL]], ptr [[A_FIELD]], // TCHECK: store double [[NEW_A_VAL]], ptr [[A_FIELD]],
// c[1][1] = ++a; // c[1][1] = ++a;
// TCHECK: [[A_FIELD4:%.+]] = getelementptr inbounds [[S1]], ptr [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 // TCHECK: [[A_FIELD4:%.+]] = getelementptr inbounds [[S1]], ptr [[TH_ADDR_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
// TCHECK: [[A_FIELD4_VAL:%.+]] = load double, ptr [[A_FIELD4]], // TCHECK: [[A_FIELD4_VAL:%.+]] = load double, ptr [[A_FIELD4]],
// TCHECK: [[A_FIELD_INC:%.+]] = fadd double [[A_FIELD4_VAL]], 1.0{{.+}}+00 // TCHECK: [[A_FIELD_INC:%.+]] = fadd double [[A_FIELD4_VAL]], 1.0{{.+}}+00
// TCHECK: store double [[A_FIELD_INC]], ptr [[A_FIELD4]], // TCHECK: store double [[A_FIELD_INC]], ptr [[A_FIELD4]],
// TCHECK: [[A_FIELD_INC_CONV:%.+]] = fptosi double [[A_FIELD_INC]] to i{{[0-9]+}} // TCHECK: [[A_FIELD_INC_CONV:%.+]] = fptosi double [[A_FIELD_INC]] to i{{[0-9]+}}
// TCHECK: [[C_IND:%.+]] = mul{{.+}} i{{[0-9]+}} 1, [[VLA_ADDR_REF2]] // TCHECK: [[C_IND:%.+]] = mul{{.+}} i{{[0-9]+}} 1, [[VLA_ADDR_REF2]]
// TCHECK: [[C_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, ptr [[VLA3]], i{{[0-9]+}} [[C_IND]] // TCHECK: [[C_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, ptr [[VLA3]], i{{[0-9]+}} [[C_IND]]
// TCHECK: [[C_1_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, ptr [[C_1_REF]], i{{[0-9]+}} 1 // TCHECK: [[C_1_1_REF:%.+]] = getelementptr inbounds i{{[0-9]+}}, ptr [[C_1_REF]], i{{[0-9]+}} 1
// TCHECK: store i{{[0-9]+}} [[A_FIELD_INC_CONV]], ptr [[C_1_1_REF]], // TCHECK: store i{{[0-9]+}} [[A_FIELD_INC_CONV]], ptr [[C_1_1_REF]],
// finish // finish
// TCHECK: [[RELOAD_SSTACK:%.+]] = load ptr, ptr [[SSTACK]], // TCHECK: [[RELOAD_SSTACK:%.+]] = load ptr, ptr [[SSTACK]],
// TCHECK: call void @llvm.stackrestore(ptr [[RELOAD_SSTACK]]) // TCHECK: call void @llvm.stackrestore.p0(ptr [[RELOAD_SSTACK]])
// TCHECK: ret void // TCHECK: ret void
}; };
int bar(int n){ int bar(int n){
int a = 0; int a = 0;
a += foo(n); a += foo(n);
S1 S; S1 S;
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clang/test/OpenMP/target_simd_codegen.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
a += ftemplate<int>(n); a += ftemplate<int>(n);
return a; return a;
} }
// //
// CHECK: define {{.*}}[[FS1]] // CHECK: define {{.*}}[[FS1]]
// //
// CHECK: ptr @llvm.stacksave() // CHECK: ptr @llvm.stacksave.p0()
// CHECK-32: store i32 %{{.+}}, ptr %__vla_expr // CHECK-32: store i32 %{{.+}}, ptr %__vla_expr
// OMP51: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 60 // OMP51: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 60
// CHECK-64: store i32 %{{.+}}, ptr [[B_ADDR:%.+]], // CHECK-64: store i32 %{{.+}}, ptr [[B_ADDR:%.+]],
// CHECK-64: [[B_CVAL:%.+]] = load i[[SZ]], ptr [[B_ADDR]], // CHECK-64: [[B_CVAL:%.+]] = load i[[SZ]], ptr [[B_ADDR]],
// CHECK-32: store i32 %{{.+}}, ptr [[B_ADDR:%.+]], // CHECK-32: store i32 %{{.+}}, ptr [[B_ADDR:%.+]],
// CHECK-32: [[B_CVAL:%.+]] = load i[[SZ]], ptr [[B_ADDR]], // CHECK-32: [[B_CVAL:%.+]] = load i[[SZ]], ptr [[B_ADDR]],
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clang/test/OpenMP/target_teams_codegen.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [1 x ptr], align 8
// CHECK1-NEXT: [[KERNEL_ARGS37:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS37:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
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// CHECK1-NEXT: [[TMP191:%.*]] = icmp ne i32 [[TMP190]], 0 // CHECK1-NEXT: [[TMP191:%.*]] = icmp ne i32 [[TMP190]], 0
// CHECK1-NEXT: br i1 [[TMP191]], label [[OMP_OFFLOAD_FAILED38:%.*]], label [[OMP_OFFLOAD_CONT39:%.*]] // CHECK1-NEXT: br i1 [[TMP191]], label [[OMP_OFFLOAD_FAILED38:%.*]], label [[OMP_OFFLOAD_CONT39:%.*]]
// CHECK1: omp_offload.failed38: // CHECK1: omp_offload.failed38:
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP171]]) #[[ATTR3]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP171]]) #[[ATTR3]]
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT39]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT39]]
// CHECK1: omp_offload.cont39: // CHECK1: omp_offload.cont39:
// CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP193]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP193]])
// CHECK1-NEXT: ret i32 [[TMP192]] // CHECK1-NEXT: ret i32 [[TMP192]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK1-NEXT: ret i32 [[ADD3]] // CHECK1-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [1 x ptr], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS35:%.*]] = alloca [1 x ptr], align 4
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [1 x ptr], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS36:%.*]] = alloca [1 x ptr], align 4
// CHECK3-NEXT: [[KERNEL_ARGS37:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS37:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
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// CHECK3-NEXT: [[TMP191:%.*]] = icmp ne i32 [[TMP190]], 0 // CHECK3-NEXT: [[TMP191:%.*]] = icmp ne i32 [[TMP190]], 0
// CHECK3-NEXT: br i1 [[TMP191]], label [[OMP_OFFLOAD_FAILED38:%.*]], label [[OMP_OFFLOAD_CONT39:%.*]] // CHECK3-NEXT: br i1 [[TMP191]], label [[OMP_OFFLOAD_FAILED38:%.*]], label [[OMP_OFFLOAD_CONT39:%.*]]
// CHECK3: omp_offload.failed38: // CHECK3: omp_offload.failed38:
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP171]]) #[[ATTR3]] // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP171]]) #[[ATTR3]]
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT39]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT39]]
// CHECK3: omp_offload.cont39: // CHECK3: omp_offload.cont39:
// CHECK3-NEXT: [[TMP192:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP192:%.*]] = load i32, ptr [[A]], align 4
// CHECK3-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP193]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP193]])
// CHECK3-NEXT: ret i32 [[TMP192]] // CHECK3-NEXT: ret i32 [[TMP192]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK3-NEXT: ret i32 [[ADD3]] // CHECK3-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_codegen.cpp

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// CHECK1-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP25:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
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// CHECK1: omp_offload.cont28: // CHECK1: omp_offload.cont28:
// CHECK1-NEXT: br label [[OMP_IF_END30:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END30:%.*]]
// CHECK1: omp_if.else29: // CHECK1: omp_if.else29:
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP97]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP99]]) #[[ATTR3]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP97]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP99]]) #[[ATTR3]]
// CHECK1-NEXT: br label [[OMP_IF_END30]] // CHECK1-NEXT: br label [[OMP_IF_END30]]
// CHECK1: omp_if.end30: // CHECK1: omp_if.end30:
// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[TMP155:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP155:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP155]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP155]])
// CHECK1-NEXT: ret i32 [[TMP154]] // CHECK1-NEXT: ret i32 [[TMP154]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK1-NEXT: ret i32 [[ADD3]] // CHECK1-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
// CHECK3-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP25:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
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// CHECK3: omp_offload.cont28: // CHECK3: omp_offload.cont28:
// CHECK3-NEXT: br label [[OMP_IF_END30:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END30:%.*]]
// CHECK3: omp_if.else29: // CHECK3: omp_if.else29:
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP95]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP97]]) #[[ATTR3]] // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP95]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP97]]) #[[ATTR3]]
// CHECK3-NEXT: br label [[OMP_IF_END30]] // CHECK3-NEXT: br label [[OMP_IF_END30]]
// CHECK3: omp_if.end30: // CHECK3: omp_if.end30:
// CHECK3-NEXT: [[TMP154:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP154:%.*]] = load i32, ptr [[A]], align 4
// CHECK3-NEXT: [[TMP155:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP155:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP155]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP155]])
// CHECK3-NEXT: ret i32 [[TMP154]] // CHECK3-NEXT: ret i32 [[TMP154]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK3-NEXT: ret i32 [[ADD3]] // CHECK3-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp

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// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp

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// CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK9: omp_offload.failed32: // CHECK9: omp_offload.failed32:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP75]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP77]]) #[[ATTR3]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP75]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP77]]) #[[ATTR3]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]]
// CHECK9: omp_offload.cont33: // CHECK9: omp_offload.cont33:
// CHECK9-NEXT: [[TMP114:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP114:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP114]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP114]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP115:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP115:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP115]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP115]])
// CHECK9-NEXT: [[TMP116:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP116:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP116]] // CHECK9-NEXT: ret i32 [[TMP116]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK11: omp_offload.failed32: // CHECK11: omp_offload.failed32:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP76]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP78]]) #[[ATTR3]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP76]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP78]]) #[[ATTR3]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT33]]
// CHECK11: omp_offload.cont33: // CHECK11: omp_offload.cont33:
// CHECK11-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP116]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP116]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP117:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP117:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP117]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP117]])
// CHECK11-NEXT: [[TMP118:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP118:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP118]] // CHECK11-NEXT: ret i32 [[TMP118]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i32 10, ptr [[M]], align 4 // CHECK9-NEXT: store i32 10, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK9: omp_offload.failed32: // CHECK9: omp_offload.failed32:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i64 [[TMP75]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP77]]) #[[ATTR3]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i64 [[TMP75]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP77]]) #[[ATTR3]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]]
// CHECK9: omp_offload.cont33: // CHECK9: omp_offload.cont33:
// CHECK9-NEXT: [[TMP114:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP114:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP114]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP114]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP115:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP115:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP115]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP115]])
// CHECK9-NEXT: [[TMP116:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP116:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP116]] // CHECK9-NEXT: ret i32 [[TMP116]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 10, ptr [[M]], align 4 // CHECK11-NEXT: store i32 10, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK11: omp_offload.failed32: // CHECK11: omp_offload.failed32:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i32 [[TMP76]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP78]]) #[[ATTR3]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i32 [[TMP76]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP78]]) #[[ATTR3]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT33]]
// CHECK11: omp_offload.cont33: // CHECK11: omp_offload.cont33:
// CHECK11-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP116]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP116]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP117:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP117:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP117]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP117]])
// CHECK11-NEXT: [[TMP118:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP118:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP118]] // CHECK11-NEXT: ret i32 [[TMP118]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp

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// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]] // CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1 // CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1
// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]] // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT32]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST25]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT32]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST25]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST24]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST24]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE34:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT32]], [[TMP81]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE34:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT32]], [[TMP81]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE34]], label [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_BODY23]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE34]], label [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_BODY23]]
// CHECK1: omp.arraycpy.done35: // CHECK1: omp.arraycpy.done35:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP90]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP90]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]] // CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1 // CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1
// CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP13]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP13]], align 16
// CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP13]] // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP13]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP16]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP16]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP96]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP96]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]]
// CHECK1: omp.arraycpy.done36: // CHECK1: omp.arraycpy.done36:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP105]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP105]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init..3 // CHECK1-LABEL: define {{[^@]+}}@.red_init..3
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp

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// CHECK13-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK13-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i32 10, ptr [[M]], align 4 // CHECK13-NEXT: store i32 10, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK13: omp_offload.failed64: // CHECK13: omp_offload.failed64:
// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP153]]) #[[ATTR3]] // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP153]]) #[[ATTR3]]
// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT65]]
// CHECK13: omp_offload.cont65: // CHECK13: omp_offload.cont65:
// CHECK13-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP190]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP190]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP191:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP191:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP191]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP191]])
// CHECK13-NEXT: [[TMP192:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP192:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP192]] // CHECK13-NEXT: ret i32 [[TMP192]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139
// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK15-NEXT: [[DOTCAPTURE_EXPR_57:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_57:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK15-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: store i32 10, ptr [[M]], align 4 // CHECK15-NEXT: store i32 10, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK15-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK15: omp_offload.failed64: // CHECK15: omp_offload.failed64:
// CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP156]]) #[[ATTR3]] // CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP156]]) #[[ATTR3]]
// CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT65]]
// CHECK15: omp_offload.cont65: // CHECK15: omp_offload.cont65:
// CHECK15-NEXT: [[TMP194:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP194:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP194]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP194]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP195:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP195:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP195]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP195]])
// CHECK15-NEXT: [[TMP196:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP196:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP196]] // CHECK15-NEXT: ret i32 [[TMP196]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139
// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK17-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK17-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK17-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK17-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK17-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK17-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK17-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK17-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK17-NEXT: store i32 100, ptr [[N]], align 4 // CHECK17-NEXT: store i32 100, ptr [[N]], align 4
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK17-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK17-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i32 10, ptr [[M]], align 4 // CHECK17-NEXT: store i32 10, ptr [[M]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK17-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK17-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK17: omp_offload.failed64: // CHECK17: omp_offload.failed64:
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP153]]) #[[ATTR3]] // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP153]]) #[[ATTR3]]
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT65]]
// CHECK17: omp_offload.cont65: // CHECK17: omp_offload.cont65:
// CHECK17-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK17-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP190]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP190]])
// CHECK17-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK17-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK17-NEXT: [[TMP191:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP191:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP191]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP191]])
// CHECK17-NEXT: [[TMP192:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK17-NEXT: [[TMP192:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK17-NEXT: ret i32 [[TMP192]] // CHECK17-NEXT: ret i32 [[TMP192]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139
// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK19-NEXT: [[DOTCAPTURE_EXPR_57:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_57:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK19-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK19-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK19-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK19-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK19-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK19-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK19-NEXT: store i32 100, ptr [[N]], align 4 // CHECK19-NEXT: store i32 100, ptr [[N]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: store i32 10, ptr [[M]], align 4 // CHECK19-NEXT: store i32 10, ptr [[M]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
▲ Show 20 Lines • Show All 334 Lines • ▼ Show 20 Lines
// CHECK19: omp_offload.failed64: // CHECK19: omp_offload.failed64:
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP156]]) #[[ATTR3]] // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP156]]) #[[ATTR3]]
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT65]]
// CHECK19: omp_offload.cont65: // CHECK19: omp_offload.cont65:
// CHECK19-NEXT: [[TMP194:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK19-NEXT: [[TMP194:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP194]]) // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP194]])
// CHECK19-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK19-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK19-NEXT: [[TMP195:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP195:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP195]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP195]])
// CHECK19-NEXT: [[TMP196:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK19-NEXT: [[TMP196:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK19-NEXT: ret i32 [[TMP196]] // CHECK19-NEXT: ret i32 [[TMP196]]
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139
// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp

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// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: store i32 2, ptr [[M]], align 4 // CHECK13-NEXT: store i32 2, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4
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// CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
// CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4 // CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13-NEXT: br label [[SIMD_IF_END]]
// CHECK13: simd.if.end: // CHECK13: simd.if.end:
// CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP29]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP29]])
// CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP30]] // CHECK13-NEXT: ret i32 [[TMP30]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: store i32 2, ptr [[M]], align 4 // CHECK15-NEXT: store i32 2, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4
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// CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
// CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4 // CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15-NEXT: br label [[SIMD_IF_END]]
// CHECK15: simd.if.end: // CHECK15: simd.if.end:
// CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP27]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP27]])
// CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP28]] // CHECK15-NEXT: ret i32 [[TMP28]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

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// CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i32 10, ptr [[M]], align 4 // CHECK9-NEXT: store i32 10, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK9: omp_offload.failed32: // CHECK9: omp_offload.failed32:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i64 [[TMP75]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP77]]) #[[ATTR3]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i64 [[TMP75]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP77]]) #[[ATTR3]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]]
// CHECK9: omp_offload.cont33: // CHECK9: omp_offload.cont33:
// CHECK9-NEXT: [[TMP114:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP114:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP114]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP114]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP115:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP115:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP115]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP115]])
// CHECK9-NEXT: [[TMP116:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP116:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP116]] // CHECK9-NEXT: ret i32 [[TMP116]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 10, ptr [[M]], align 4 // CHECK11-NEXT: store i32 10, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK11: omp_offload.failed32: // CHECK11: omp_offload.failed32:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i32 [[TMP76]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP78]]) #[[ATTR3]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108(i32 [[TMP76]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP78]]) #[[ATTR3]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT33]]
// CHECK11: omp_offload.cont33: // CHECK11: omp_offload.cont33:
// CHECK11-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP116]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP116]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP117:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP117:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP117]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP117]])
// CHECK11-NEXT: [[TMP118:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP118:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP118]] // CHECK11-NEXT: ret i32 [[TMP118]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: [[DOTOMP_IV51:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV51:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[I52:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I52:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i32 10, ptr [[M]], align 4 // CHECK13-NEXT: store i32 10, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
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// CHECK13-NEXT: [[ADD67:%.*]] = add nsw i32 0, [[MUL66]] // CHECK13-NEXT: [[ADD67:%.*]] = add nsw i32 0, [[MUL66]]
// CHECK13-NEXT: store i32 [[ADD67]], ptr [[I52]], align 4 // CHECK13-NEXT: store i32 [[ADD67]], ptr [[I52]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END68]] // CHECK13-NEXT: br label [[SIMD_IF_END68]]
// CHECK13: simd.if.end68: // CHECK13: simd.if.end68:
// CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP38:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP38:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP38]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP38]])
// CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP39]] // CHECK13-NEXT: ret i32 [[TMP39]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_IV50:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV50:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I51:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I51:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: store i32 10, ptr [[M]], align 4 // CHECK15-NEXT: store i32 10, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
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// CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 0, [[MUL64]] // CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 0, [[MUL64]]
// CHECK15-NEXT: store i32 [[ADD65]], ptr [[I51]], align 4 // CHECK15-NEXT: store i32 [[ADD65]], ptr [[I51]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END66]] // CHECK15-NEXT: br label [[SIMD_IF_END66]]
// CHECK15: simd.if.end66: // CHECK15: simd.if.end66:
// CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP37:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP37:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP37]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP37]])
// CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP38]] // CHECK15-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp

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// CHECK13-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK13-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i32 10, ptr [[M]], align 4 // CHECK13-NEXT: store i32 10, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK13: omp_offload.failed64: // CHECK13: omp_offload.failed64:
// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP153]]) #[[ATTR3]] // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP153]]) #[[ATTR3]]
// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT65]]
// CHECK13: omp_offload.cont65: // CHECK13: omp_offload.cont65:
// CHECK13-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP190]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP190]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP191:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP191:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP191]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP191]])
// CHECK13-NEXT: [[TMP192:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP192:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP192]] // CHECK13-NEXT: ret i32 [[TMP192]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139
// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK15-NEXT: [[DOTCAPTURE_EXPR_57:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_57:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK15-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: store i32 10, ptr [[M]], align 4 // CHECK15-NEXT: store i32 10, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK15-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK15: omp_offload.failed64: // CHECK15: omp_offload.failed64:
// CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP156]]) #[[ATTR3]] // CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP156]]) #[[ATTR3]]
// CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT65]]
// CHECK15: omp_offload.cont65: // CHECK15: omp_offload.cont65:
// CHECK15-NEXT: [[TMP194:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP194:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP194]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP194]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP195:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP195:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP195]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP195]])
// CHECK15-NEXT: [[TMP196:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP196:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP196]] // CHECK15-NEXT: ret i32 [[TMP196]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139
// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK17-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK17-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK17-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK17-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK17-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK17-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK17-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK17-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK17-NEXT: store i32 100, ptr [[N]], align 4 // CHECK17-NEXT: store i32 100, ptr [[N]], align 4
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK17-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK17-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i32 10, ptr [[M]], align 4 // CHECK17-NEXT: store i32 10, ptr [[M]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK17-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK17-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK17: omp_offload.failed64: // CHECK17: omp_offload.failed64:
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP153]]) #[[ATTR3]] // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP153]]) #[[ATTR3]]
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT65]]
// CHECK17: omp_offload.cont65: // CHECK17: omp_offload.cont65:
// CHECK17-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK17-NEXT: [[TMP190:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP190]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP190]])
// CHECK17-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK17-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK17-NEXT: [[TMP191:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP191:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP191]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP191]])
// CHECK17-NEXT: [[TMP192:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK17-NEXT: [[TMP192:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK17-NEXT: ret i32 [[TMP192]] // CHECK17-NEXT: ret i32 [[TMP192]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139
// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK19-NEXT: [[DOTCAPTURE_EXPR_57:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_57:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_58:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK19-NEXT: [[KERNEL_ARGS63:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK19-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK19-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK19-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK19-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK19-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK19-NEXT: store i32 100, ptr [[N]], align 4 // CHECK19-NEXT: store i32 100, ptr [[N]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: store i32 10, ptr [[M]], align 4 // CHECK19-NEXT: store i32 10, ptr [[M]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK19: omp_offload.failed64: // CHECK19: omp_offload.failed64:
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP156]]) #[[ATTR3]] // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l155(i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP156]]) #[[ATTR3]]
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT65]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT65]]
// CHECK19: omp_offload.cont65: // CHECK19: omp_offload.cont65:
// CHECK19-NEXT: [[TMP194:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK19-NEXT: [[TMP194:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP194]]) // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP194]])
// CHECK19-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK19-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK19-NEXT: [[TMP195:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP195:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP195]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP195]])
// CHECK19-NEXT: [[TMP196:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK19-NEXT: [[TMP196:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK19-NEXT: ret i32 [[TMP196]] // CHECK19-NEXT: ret i32 [[TMP196]]
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139
// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK21-NEXT: [[DOTOMP_IV110:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[DOTOMP_IV110:%.*]] = alloca i32, align 4
// CHECK21-NEXT: [[I111:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[I111:%.*]] = alloca i32, align 4
// CHECK21-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK21-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK21-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK21-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK21-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK21-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK21-NEXT: store i32 100, ptr [[N]], align 4 // CHECK21-NEXT: store i32 100, ptr [[N]], align 4
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK21-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK21-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK21-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK21-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK21-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK21-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK21-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK21-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK21-NEXT: store i32 10, ptr [[M]], align 4 // CHECK21-NEXT: store i32 10, ptr [[M]], align 4
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK21-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK21-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
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// CHECK21-NEXT: [[ADD126:%.*]] = add nsw i32 0, [[MUL125]] // CHECK21-NEXT: [[ADD126:%.*]] = add nsw i32 0, [[MUL125]]
// CHECK21-NEXT: store i32 [[ADD126]], ptr [[I111]], align 4 // CHECK21-NEXT: store i32 [[ADD126]], ptr [[I111]], align 4
// CHECK21-NEXT: br label [[SIMD_IF_END127]] // CHECK21-NEXT: br label [[SIMD_IF_END127]]
// CHECK21: simd.if.end127: // CHECK21: simd.if.end127:
// CHECK21-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK21-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP60]]) // CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP60]])
// CHECK21-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK21-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK21-NEXT: [[TMP61:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK21-NEXT: [[TMP61:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK21-NEXT: call void @llvm.stackrestore(ptr [[TMP61]]) // CHECK21-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP61]])
// CHECK21-NEXT: [[TMP62:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK21-NEXT: [[TMP62:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK21-NEXT: ret i32 [[TMP62]] // CHECK21-NEXT: ret i32 [[TMP62]]
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK21-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK21-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK21-NEXT: entry: // CHECK21-NEXT: entry:
// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK23-NEXT: [[I104:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[I104:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[DOTOMP_IV107:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[DOTOMP_IV107:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[I108:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[I108:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK23-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK23-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK23-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK23-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK23-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK23-NEXT: store i32 100, ptr [[N]], align 4 // CHECK23-NEXT: store i32 100, ptr [[N]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK23-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK23-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK23-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK23-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK23-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK23-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK23-NEXT: store i32 10, ptr [[M]], align 4 // CHECK23-NEXT: store i32 10, ptr [[M]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK23-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK23-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
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// CHECK23-NEXT: [[ADD122:%.*]] = add nsw i32 0, [[MUL121]] // CHECK23-NEXT: [[ADD122:%.*]] = add nsw i32 0, [[MUL121]]
// CHECK23-NEXT: store i32 [[ADD122]], ptr [[I108]], align 4 // CHECK23-NEXT: store i32 [[ADD122]], ptr [[I108]], align 4
// CHECK23-NEXT: br label [[SIMD_IF_END123]] // CHECK23-NEXT: br label [[SIMD_IF_END123]]
// CHECK23: simd.if.end123: // CHECK23: simd.if.end123:
// CHECK23-NEXT: [[TMP59:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK23-NEXT: [[TMP59:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK23-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP59]]) // CHECK23-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP59]])
// CHECK23-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK23-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK23-NEXT: [[TMP60:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK23-NEXT: [[TMP60:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK23-NEXT: call void @llvm.stackrestore(ptr [[TMP60]]) // CHECK23-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP60]])
// CHECK23-NEXT: [[TMP61:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK23-NEXT: [[TMP61:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK23-NEXT: ret i32 [[TMP61]] // CHECK23-NEXT: ret i32 [[TMP61]]
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK23-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK23-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK23-NEXT: entry: // CHECK23-NEXT: entry:
// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp

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// CHECK1-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP23:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK1-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
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// CHECK1: omp_offload.cont26: // CHECK1: omp_offload.cont26:
// CHECK1-NEXT: br label [[OMP_IF_END28:%.*]] // CHECK1-NEXT: br label [[OMP_IF_END28:%.*]]
// CHECK1: omp_if.else27: // CHECK1: omp_if.else27:
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]]
// CHECK1-NEXT: br label [[OMP_IF_END28]] // CHECK1-NEXT: br label [[OMP_IF_END28]]
// CHECK1: omp_if.end28: // CHECK1: omp_if.end28:
// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4
// CHECK1-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP149]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP149]])
// CHECK1-NEXT: ret i32 [[TMP148]] // CHECK1-NEXT: ret i32 [[TMP148]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
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// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK1-NEXT: ret i32 [[ADD3]] // CHECK1-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
// CHECK3-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP23:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
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// CHECK3: omp_offload.cont26: // CHECK3: omp_offload.cont26:
// CHECK3-NEXT: br label [[OMP_IF_END28:%.*]] // CHECK3-NEXT: br label [[OMP_IF_END28:%.*]]
// CHECK3: omp_if.else27: // CHECK3: omp_if.else27:
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]]
// CHECK3-NEXT: br label [[OMP_IF_END28]] // CHECK3-NEXT: br label [[OMP_IF_END28]]
// CHECK3: omp_if.end28: // CHECK3: omp_if.end28:
// CHECK3-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4
// CHECK3-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP149]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP149]])
// CHECK3-NEXT: ret i32 [[TMP148]] // CHECK3-NEXT: ret i32 [[TMP148]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
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// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
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// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]] // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]] // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK3-NEXT: ret i32 [[ADD3]] // CHECK3-NEXT: ret i32 [[ADD3]]
// //
// //
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK3-NEXT: entry: // CHECK3-NEXT: entry:
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK5-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP23:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK5-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK5-NEXT: store i32 0, ptr [[A]], align 4 // CHECK5-NEXT: store i32 0, ptr [[A]], align 4
// CHECK5-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK5-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
// CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] // CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
// CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 // CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
// CHECK5-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
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// CHECK5: omp_offload.cont26: // CHECK5: omp_offload.cont26:
// CHECK5-NEXT: br label [[OMP_IF_END28:%.*]] // CHECK5-NEXT: br label [[OMP_IF_END28:%.*]]
// CHECK5: omp_if.else27: // CHECK5: omp_if.else27:
// CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]]
// CHECK5-NEXT: br label [[OMP_IF_END28]] // CHECK5-NEXT: br label [[OMP_IF_END28]]
// CHECK5: omp_if.end28: // CHECK5: omp_if.end28:
// CHECK5-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4 // CHECK5-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4
// CHECK5-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK5-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP149]]) // CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP149]])
// CHECK5-NEXT: ret i32 [[TMP148]] // CHECK5-NEXT: ret i32 [[TMP148]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
// CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
// CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
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// CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK5-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK5-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK5-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK5-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
// CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
// CHECK5-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
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// CHECK5-NEXT: [[TMP50:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK5-NEXT: [[TMP50:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP50]] // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP50]]
// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
// CHECK5-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2 // CHECK5-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2
// CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP51]] to i32 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP51]] to i32
// CHECK5-NEXT: [[TMP52:%.*]] = load i32, ptr [[B]], align 4 // CHECK5-NEXT: [[TMP52:%.*]] = load i32, ptr [[B]], align 4
// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], [[TMP52]] // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], [[TMP52]]
// CHECK5-NEXT: [[TMP53:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK5-NEXT: [[TMP53:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK5-NEXT: call void @llvm.stackrestore(ptr [[TMP53]]) // CHECK5-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP53]])
// CHECK5-NEXT: ret i32 [[ADD5]] // CHECK5-NEXT: ret i32 [[ADD5]]
// //
// //
// CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK5-NEXT: entry: // CHECK5-NEXT: entry:
// CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
// CHECK7-NEXT: [[_TMP23:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[_TMP23:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK7-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK7-NEXT: store i32 0, ptr [[A]], align 4 // CHECK7-NEXT: store i32 0, ptr [[A]], align 4
// CHECK7-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK7-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] // CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
// CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 // CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
// CHECK7-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
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// CHECK7: omp_offload.cont26: // CHECK7: omp_offload.cont26:
// CHECK7-NEXT: br label [[OMP_IF_END28:%.*]] // CHECK7-NEXT: br label [[OMP_IF_END28:%.*]]
// CHECK7: omp_if.else27: // CHECK7: omp_if.else27:
// CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]] // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR4]]
// CHECK7-NEXT: br label [[OMP_IF_END28]] // CHECK7-NEXT: br label [[OMP_IF_END28]]
// CHECK7: omp_if.end28: // CHECK7: omp_if.end28:
// CHECK7-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4 // CHECK7-NEXT: [[TMP148:%.*]] = load i32, ptr [[A]], align 4
// CHECK7-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK7-NEXT: [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK7-NEXT: call void @llvm.stackrestore(ptr [[TMP149]]) // CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP149]])
// CHECK7-NEXT: ret i32 [[TMP148]] // CHECK7-NEXT: ret i32 [[TMP148]]
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
// CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
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// CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK7-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK7-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK7-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK7-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
// CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
// CHECK7-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK7-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
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// CHECK7-NEXT: [[TMP50:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK7-NEXT: [[TMP50:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP50]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP50]]
// CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
// CHECK7-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2 // CHECK7-NEXT: [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2
// CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP51]] to i32 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP51]] to i32
// CHECK7-NEXT: [[TMP52:%.*]] = load i32, ptr [[B]], align 4 // CHECK7-NEXT: [[TMP52:%.*]] = load i32, ptr [[B]], align 4
// CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], [[TMP52]] // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], [[TMP52]]
// CHECK7-NEXT: [[TMP53:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK7-NEXT: [[TMP53:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK7-NEXT: call void @llvm.stackrestore(ptr [[TMP53]]) // CHECK7-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP53]])
// CHECK7-NEXT: ret i32 [[ADD5]] // CHECK7-NEXT: ret i32 [[ADD5]]
// //
// //
// CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK7-NEXT: entry: // CHECK7-NEXT: entry:
// CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK9-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[I58:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I58:%.*]] = alloca i32, align 4
// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK9-NEXT: store i32 0, ptr [[A]], align 4 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4
// CHECK9-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK9-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// CHECK9-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// CHECK9-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]]
// CHECK9-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1 // CHECK9-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
// CHECK9-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]]
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]]
// CHECK9: omp.inner.for.end85: // CHECK9: omp.inner.for.end85:
// CHECK9-NEXT: store i32 10, ptr [[I58]], align 4 // CHECK9-NEXT: store i32 10, ptr [[I58]], align 4
// CHECK9-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4
// CHECK9-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK9-NEXT: ret i32 [[TMP46]] // CHECK9-NEXT: ret i32 [[TMP46]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_Z3bari // CHECK9-LABEL: define {{[^@]+}}@_Z3bari
// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK9-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK9-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK9-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK9-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK9-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
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// CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]] // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]]
// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX8]], i64 1 // CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX8]], i64 1
// CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX9]], align 2 // CHECK9-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX9]], align 2
// CHECK9-NEXT: [[CONV10:%.*]] = sext i16 [[TMP14]] to i32 // CHECK9-NEXT: [[CONV10:%.*]] = sext i16 [[TMP14]] to i32
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[B]], align 4
// CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]] // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]]
// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP16]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])
// CHECK9-NEXT: ret i32 [[ADD11]] // CHECK9-NEXT: ret i32 [[ADD11]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK11-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[I58:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I58:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK11-NEXT: store i32 0, ptr [[A]], align 4 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4
// CHECK11-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK11-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
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// CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
// CHECK11-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1 // CHECK11-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
// CHECK11-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
// CHECK11: omp.inner.for.end85: // CHECK11: omp.inner.for.end85:
// CHECK11-NEXT: store i32 10, ptr [[I58]], align 4 // CHECK11-NEXT: store i32 10, ptr [[I58]], align 4
// CHECK11-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4
// CHECK11-NEXT: [[TMP45:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP45:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP45]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP45]])
// CHECK11-NEXT: ret i32 [[TMP44]] // CHECK11-NEXT: ret i32 [[TMP44]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_Z3bari // CHECK11-LABEL: define {{[^@]+}}@_Z3bari
// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK11-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK11-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
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// CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]] // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]]
// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX8]], i32 1 // CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX8]], i32 1
// CHECK11-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX9]], align 2 // CHECK11-NEXT: [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX9]], align 2
// CHECK11-NEXT: [[CONV10:%.*]] = sext i16 [[TMP13]] to i32 // CHECK11-NEXT: [[CONV10:%.*]] = sext i16 [[TMP13]] to i32
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[B]], align 4
// CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]] // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]]
// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK11-NEXT: ret i32 [[ADD11]] // CHECK11-NEXT: ret i32 [[ADD11]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[I58:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I58:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK13-NEXT: store i32 0, ptr [[A]], align 4 // CHECK13-NEXT: store i32 0, ptr [[A]], align 4
// CHECK13-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK13-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 // CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
// CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 // CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
// CHECK13-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 // CHECK13-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
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// CHECK13-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK13-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
// CHECK13-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1 // CHECK13-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
// CHECK13-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK13-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
// CHECK13: omp.inner.for.end85: // CHECK13: omp.inner.for.end85:
// CHECK13-NEXT: store i32 10, ptr [[I58]], align 4 // CHECK13-NEXT: store i32 10, ptr [[I58]], align 4
// CHECK13-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4 // CHECK13-NEXT: [[TMP46:%.*]] = load i32, ptr [[A]], align 4
// CHECK13-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP47]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
// CHECK13-NEXT: ret i32 [[TMP46]] // CHECK13-NEXT: ret i32 [[TMP46]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z3bari // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK13-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK13-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK13-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK13-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] // CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
// CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 // CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
// CHECK13-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
// CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
// CHECK13-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK13-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
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// CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] // CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
// CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]] // CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]]
// CHECK13-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX26]], i64 1 // CHECK13-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX26]], i64 1
// CHECK13-NEXT: [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX27]], align 2 // CHECK13-NEXT: [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX27]], align 2
// CHECK13-NEXT: [[CONV28:%.*]] = sext i16 [[TMP23]] to i32 // CHECK13-NEXT: [[CONV28:%.*]] = sext i16 [[TMP23]] to i32
// CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[B]], align 4 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[B]], align 4
// CHECK13-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]] // CHECK13-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]]
// CHECK13-NEXT: [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP25]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP25]])
// CHECK13-NEXT: ret i32 [[ADD29]] // CHECK13-NEXT: ret i32 [[ADD29]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_LB55:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_UB56:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV57:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I58:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I58:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK15-NEXT: store i32 0, ptr [[A]], align 4 // CHECK15-NEXT: store i32 0, ptr [[A]], align 4
// CHECK15-NEXT: store i16 0, ptr [[AA]], align 2 // CHECK15-NEXT: store i16 0, ptr [[AA]], align 2
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
// CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 // CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4
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// CHECK15-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK15-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK15-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1 // CHECK15-NEXT: [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
// CHECK15-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK15-NEXT: store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK15: omp.inner.for.end85: // CHECK15: omp.inner.for.end85:
// CHECK15-NEXT: store i32 10, ptr [[I58]], align 4 // CHECK15-NEXT: store i32 10, ptr [[I58]], align 4
// CHECK15-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4 // CHECK15-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4
// CHECK15-NEXT: [[TMP45:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP45:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP45]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP45]])
// CHECK15-NEXT: ret i32 [[TMP44]] // CHECK15-NEXT: ret i32 [[TMP44]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z3bari // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK15-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
// CHECK15-NEXT: store i32 [[ADD]], ptr [[B]], align 4 // CHECK15-NEXT: store i32 [[ADD]], ptr [[B]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
// CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 // CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
// CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
// CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 // CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
// CHECK15-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK15-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
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// CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
// CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]] // CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]]
// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX26]], i32 1 // CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX26]], i32 1
// CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX27]], align 2 // CHECK15-NEXT: [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX27]], align 2
// CHECK15-NEXT: [[CONV28:%.*]] = sext i16 [[TMP22]] to i32 // CHECK15-NEXT: [[CONV28:%.*]] = sext i16 [[TMP22]] to i32
// CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[B]], align 4 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, ptr [[B]], align 4
// CHECK15-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]] // CHECK15-NEXT: [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]]
// CHECK15-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP24]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP24]])
// CHECK15-NEXT: ret i32 [[ADD29]] // CHECK15-NEXT: ret i32 [[ADD29]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
// CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp

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// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR4:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR4:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: store i32 2, ptr [[M]], align 4 // CHECK13-NEXT: store i32 2, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4
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// CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
// CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4 // CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13-NEXT: br label [[SIMD_IF_END]]
// CHECK13: simd.if.end: // CHECK13: simd.if.end:
// CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP29]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP29]])
// CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP30]] // CHECK13-NEXT: ret i32 [[TMP30]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: store i32 2, ptr [[M]], align 4 // CHECK15-NEXT: store i32 2, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4
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// CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
// CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4 // CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15-NEXT: br label [[SIMD_IF_END]]
// CHECK15: simd.if.end: // CHECK15: simd.if.end:
// CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP27]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP27]])
// CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP28]] // CHECK15-NEXT: ret i32 [[TMP28]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK9: omp_offload.failed32: // CHECK9: omp_offload.failed32:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP75]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP77]]) #[[ATTR4]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i64 [[TMP75]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP77]]) #[[ATTR4]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT33]]
// CHECK9: omp_offload.cont33: // CHECK9: omp_offload.cont33:
// CHECK9-NEXT: [[TMP114:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP114:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP114]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP114]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP115:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP115:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP115]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP115]])
// CHECK9-NEXT: [[TMP116:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP116:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP116]] // CHECK9-NEXT: ret i32 [[TMP116]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_26:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS31:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK11: omp_offload.failed32: // CHECK11: omp_offload.failed32:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP76]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP78]]) #[[ATTR4]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l102(i32 [[TMP76]], i32 [[TMP0]], ptr [[VLA]], i32 [[TMP78]]) #[[ATTR4]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT33]]
// CHECK11: omp_offload.cont33: // CHECK11: omp_offload.cont33:
// CHECK11-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP116:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP116]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP116]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP117:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP117:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP117]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP117]])
// CHECK11-NEXT: [[TMP118:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP118:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP118]] // CHECK11-NEXT: ret i32 [[TMP118]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: [[DOTOMP_IV51:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV51:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[I52:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I52:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK13-NEXT: [[ADD67:%.*]] = add nsw i32 0, [[MUL66]] // CHECK13-NEXT: [[ADD67:%.*]] = add nsw i32 0, [[MUL66]]
// CHECK13-NEXT: store i32 [[ADD67]], ptr [[I52]], align 4 // CHECK13-NEXT: store i32 [[ADD67]], ptr [[I52]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END68]] // CHECK13-NEXT: br label [[SIMD_IF_END68]]
// CHECK13: simd.if.end68: // CHECK13: simd.if.end68:
// CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP38:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP38:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP38]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP38]])
// CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP39]] // CHECK13-NEXT: ret i32 [[TMP39]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_IV50:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV50:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I51:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I51:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 0, [[MUL64]] // CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 0, [[MUL64]]
// CHECK15-NEXT: store i32 [[ADD65]], ptr [[I51]], align 4 // CHECK15-NEXT: store i32 [[ADD65]], ptr [[I51]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END66]] // CHECK15-NEXT: br label [[SIMD_IF_END66]]
// CHECK15: simd.if.end66: // CHECK15: simd.if.end66:
// CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP37:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP37:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP37]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP37]])
// CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP38]] // CHECK15-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/target_teams_generic_loop_collapse_codegen.cpp

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// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l81
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/task_affinity_codegen.cpp

Show All 40 Lines#pragma omp task affinity(([a][10][a])p)
; ;
// CHECK: [[TD:%.+]] = call ptr @__kmpc_omp_task_alloc(ptr @{{.+}}, i32 [[GTID]], i32 1, i64 40, i64 1, ptr @{{.+}}) // CHECK: [[TD:%.+]] = call ptr @__kmpc_omp_task_alloc(ptr @{{.+}}, i32 [[GTID]], i32 1, i64 40, i64 1, ptr @{{.+}})
// CHECK: [[A_VAL:%.+]] = load i32, ptr [[A_ADDR]], // CHECK: [[A_VAL:%.+]] = load i32, ptr [[A_ADDR]],
// CHECK: [[SUB:%.+]] = sub nsw i32 [[A_VAL]], 0 // CHECK: [[SUB:%.+]] = sub nsw i32 [[A_VAL]], 0
// CHECK: [[CONV:%.+]] = zext i32 [[SUB]] to i64 // CHECK: [[CONV:%.+]] = zext i32 [[SUB]] to i64
// <num_elem> = <num_iters> + 1 constant affinity for affinity(a) // <num_elem> = <num_iters> + 1 constant affinity for affinity(a)
// CHECK: [[NUM_ELEMS:%.+]] = add nuw i64 1, [[CONV]] // CHECK: [[NUM_ELEMS:%.+]] = add nuw i64 1, [[CONV]]
// CHECK: [[SV:%.+]] = call ptr @llvm.stacksave() // CHECK: [[SV:%.+]] = call ptr @llvm.stacksave.p0()
// CHECK: store ptr [[SV]], ptr [[SV_ADDR:%.+]], // CHECK: store ptr [[SV]], ptr [[SV_ADDR:%.+]],
// kmp_task_affinity_info_t affs[<num_elem>]; // kmp_task_affinity_info_t affs[<num_elem>];
// CHECK: [[AFFS_ADDR:%.+]] = alloca %struct.kmp_task_affinity_info_t, i64 [[NUM_ELEMS]], // CHECK: [[AFFS_ADDR:%.+]] = alloca %struct.kmp_task_affinity_info_t, i64 [[NUM_ELEMS]],
// store i64 %21, ptr %__vla_expr0, align 8 // store i64 %21, ptr %__vla_expr0, align 8
// CHECK: [[NAFFS:%.+]] = trunc i64 [[NUM_ELEMS]] to i32 // CHECK: [[NAFFS:%.+]] = trunc i64 [[NUM_ELEMS]] to i32
// CHECK: [[AFFS_0_ADDR:%.+]] = getelementptr %struct.kmp_task_affinity_info_t, ptr [[AFFS_ADDR]], i64 0 // CHECK: [[AFFS_0_ADDR:%.+]] = getelementptr %struct.kmp_task_affinity_info_t, ptr [[AFFS_ADDR]], i64 0
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines#pragma omp task affinity(([a][10][a])p)
// CHECK: [[CNT:%.+]] = load i32, ptr [[CNT_ADDR]], // CHECK: [[CNT:%.+]] = load i32, ptr [[CNT_ADDR]],
// CHECK: [[CNT_NEXT:%.+]] = add nsw i32 [[CNT]], 1 // CHECK: [[CNT_NEXT:%.+]] = add nsw i32 [[CNT]], 1
// CHECK: store i32 [[CNT_NEXT]], ptr [[CNT_ADDR]], // CHECK: store i32 [[CNT_NEXT]], ptr [[CNT_ADDR]],
// CHECK: br label %[[CONT]] // CHECK: br label %[[CONT]]
// CHECK: [[DONE]]: // CHECK: [[DONE]]:
// CHECK: call i32 @__kmpc_omp_reg_task_with_affinity(ptr @{{.+}} i32 [[GTID]], ptr [[TD]], i32 [[NAFFS]], ptr [[AFFS_ADDR]]) // CHECK: call i32 @__kmpc_omp_reg_task_with_affinity(ptr @{{.+}} i32 [[GTID]], ptr [[TD]], i32 [[NAFFS]], ptr [[AFFS_ADDR]])
// CHECK: [[SV:%.+]] = load ptr, ptr [[SV_ADDR]], // CHECK: [[SV:%.+]] = load ptr, ptr [[SV_ADDR]],
// CHECK: call void @llvm.stackrestore(ptr [[SV]]) // CHECK: call void @llvm.stackrestore.p0(ptr [[SV]])
#pragma omp task affinity(iterator(i=0:a): p[i]) affinity(a) #pragma omp task affinity(iterator(i=0:a): p[i]) affinity(a)
; ;
return 0; return 0;
} }
#endif #endif

clang/test/OpenMP/task_codegen.c

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesint main(void) {
// CHECK: [[SZ:%.+]] = load i64, ptr [[DEPOBJ_SIZE_ADDR1]], align 8 // CHECK: [[SZ:%.+]] = load i64, ptr [[DEPOBJ_SIZE_ADDR1]], align 8
// CHECK: [[SIZE3:%.+]] = add nuw i64 [[SZ]], [[SIZE2]] // CHECK: [[SIZE3:%.+]] = add nuw i64 [[SZ]], [[SIZE2]]
// CHECK: store i64 [[SIZE3]], ptr [[DEPOBJ_SIZE_ADDR1]], align 8 // CHECK: store i64 [[SIZE3]], ptr [[DEPOBJ_SIZE_ADDR1]], align 8
// CHECK: [[SZ:%.+]] = load i64, ptr [[DEPOBJ_SIZE_ADDR]], align 8 // CHECK: [[SZ:%.+]] = load i64, ptr [[DEPOBJ_SIZE_ADDR]], align 8
// CHECK: [[SZ1:%.+]] = load i64, ptr [[DEPOBJ_SIZE_ADDR1]], align 8 // CHECK: [[SZ1:%.+]] = load i64, ptr [[DEPOBJ_SIZE_ADDR1]], align 8
// CHECK: [[SIZE1:%.+]] = add nuw i64 0, [[SZ]] // CHECK: [[SIZE1:%.+]] = add nuw i64 0, [[SZ]]
// CHECK: [[SIZE2:%.+]] = add nuw i64 [[SIZE1]], [[SZ1]] // CHECK: [[SIZE2:%.+]] = add nuw i64 [[SIZE1]], [[SZ1]]
// CHECK: [[SIZE:%.+]] = add nuw i64 [[SIZE2]], 2 // CHECK: [[SIZE:%.+]] = add nuw i64 [[SIZE2]], 2
// CHECK: [[SV:%.+]] = call ptr @llvm.stacksave() // CHECK: [[SV:%.+]] = call ptr @llvm.stacksave.p0()
// CHECK: store ptr [[SV]], ptr [[SV_ADDR:%.+]], align 8 // CHECK: store ptr [[SV]], ptr [[SV_ADDR:%.+]], align 8
// CHECK: [[VLA:%.+]] = alloca %struct.kmp_depend_info, i64 [[SIZE]], // CHECK: [[VLA:%.+]] = alloca %struct.kmp_depend_info, i64 [[SIZE]],
// CHECK: [[SIZE32:%.+]] = trunc i64 [[SIZE]] to i32 // CHECK: [[SIZE32:%.+]] = trunc i64 [[SIZE]] to i32
// CHECK: [[A_ADDR_CAST:%.+]] = ptrtoint ptr [[A_ADDR]] to i64 // CHECK: [[A_ADDR_CAST:%.+]] = ptrtoint ptr [[A_ADDR]] to i64
// CHECK: [[VLA0:%.+]] = getelementptr %struct.kmp_depend_info, ptr [[VLA]], i64 0 // CHECK: [[VLA0:%.+]] = getelementptr %struct.kmp_depend_info, ptr [[VLA]], i64 0
// CHECK: [[BASE_ADDR:%.+]] = getelementptr inbounds %struct.kmp_depend_info, ptr [[VLA0]], i{{.+}} 0, i{{.+}} 0 // CHECK: [[BASE_ADDR:%.+]] = getelementptr inbounds %struct.kmp_depend_info, ptr [[VLA0]], i{{.+}} 0, i{{.+}} 0
// CHECK: store i64 [[A_ADDR_CAST]], ptr [[BASE_ADDR]], align 16 // CHECK: store i64 [[A_ADDR_CAST]], ptr [[BASE_ADDR]], align 16
// CHECK: [[SIZE_ADDR:%.+]] = getelementptr inbounds %struct.kmp_depend_info, ptr [[VLA0]], i{{.+}} 0, i{{.+}} 1 // CHECK: [[SIZE_ADDR:%.+]] = getelementptr inbounds %struct.kmp_depend_info, ptr [[VLA0]], i{{.+}} 0, i{{.+}} 1
Show All 32 Linesint main(void) {
// CHECK: [[BYTES:%.+]] = mul nuw i64 24, [[SIZE]] // CHECK: [[BYTES:%.+]] = mul nuw i64 24, [[SIZE]]
// CHECK: [[POS:%.+]] = load i64, ptr [[DEP_COUNTER_ADDR]], align 8 // CHECK: [[POS:%.+]] = load i64, ptr [[DEP_COUNTER_ADDR]], align 8
// CHECK: [[VLA_X:%.+]] = getelementptr %struct.kmp_depend_info, ptr [[VLA]], i64 [[POS]] // CHECK: [[VLA_X:%.+]] = getelementptr %struct.kmp_depend_info, ptr [[VLA]], i64 [[POS]]
// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align {{.+}} [[VLA_X]], ptr align {{.+}} [[BC]], i64 [[BYTES]], i1 false) // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align {{.+}} [[VLA_X]], ptr align {{.+}} [[BC]], i64 [[BYTES]], i1 false)
// CHECK: [[ADD:%.+]] = add nuw i64 [[POS]], [[SIZE]] // CHECK: [[ADD:%.+]] = add nuw i64 [[POS]], [[SIZE]]
// CHECK: store i64 [[ADD]], ptr [[DEP_COUNTER_ADDR]], align 8 // CHECK: store i64 [[ADD]], ptr [[DEP_COUNTER_ADDR]], align 8
// CHECK: call i32 @__kmpc_omp_task_with_deps(ptr @{{.+}}, i32 [[GTID]], ptr [[ALLOC]], i32 [[SIZE32]], ptr [[VLA]], i32 0, ptr null) // CHECK: call i32 @__kmpc_omp_task_with_deps(ptr @{{.+}}, i32 [[GTID]], ptr [[ALLOC]], i32 [[SIZE32]], ptr [[VLA]], i32 0, ptr null)
// CHECK: [[SV:%.+]] = load ptr, ptr [[SV_ADDR]], align 8 // CHECK: [[SV:%.+]] = load ptr, ptr [[SV_ADDR]], align 8
// CHECK: call void @llvm.stackrestore(ptr [[SV]]) // CHECK: call void @llvm.stackrestore.p0(ptr [[SV]])
#pragma omp task depend(in: a, ([3][a][a])&b) depend(depobj: d, x) detach(evt) #pragma omp task depend(in: a, ([3][a][a])&b) depend(depobj: d, x) detach(evt)
{ {
#pragma omp taskgroup #pragma omp taskgroup
{ {
#pragma omp task #pragma omp task
foo(); foo();
} }
} }
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clang/test/OpenMP/task_codegen.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK1-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK1: arrayctor.cont: // CHECK1: arrayctor.cont:
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]] // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]]
// CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP5]], align 8 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP5]], align 8
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
// CHECK1-NEXT: store ptr [[S]], ptr [[TMP6]], align 8 // CHECK1-NEXT: store ptr [[S]], ptr [[TMP6]], align 8
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// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[C]], align 128 // CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[C]], align 128
// CHECK1-NEXT: store i32 [[TMP147]], ptr [[TMP146]], align 128 // CHECK1-NEXT: store i32 [[TMP147]], ptr [[TMP146]], align 128
// CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP144]], i32 0, i32 2 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP144]], i32 0, i32 2
// CHECK1-NEXT: store i32 0, ptr [[TMP148]], align 16 // CHECK1-NEXT: store i32 0, ptr [[TMP148]], align 16
// CHECK1-NEXT: [[TMP149:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP143]]) // CHECK1-NEXT: [[TMP149:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP143]])
// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr @a, align 4 // CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr @a, align 4
// CHECK1-NEXT: store i32 [[TMP150]], ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 [[TMP150]], ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP151:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP151:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP151]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP151]])
// CHECK1-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0
// CHECK1-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN32]], i64 2 // CHECK1-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN32]], i64 2
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP152]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP152]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]]
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// CHECK1-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK1-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK1-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK1-51-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK1-51-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK1-51-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-51-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK1-51-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1-51-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK1-51: arrayctor.cont: // CHECK1-51: arrayctor.cont:
// CHECK1-51-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4 // CHECK1-51-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4
// CHECK1-51-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-51-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-51-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-51-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-51-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]] // CHECK1-51-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]]
// CHECK1-51-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16 // CHECK1-51-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16
// CHECK1-51-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-51-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
// CHECK1-51-NEXT: store ptr [[B]], ptr [[TMP5]], align 8 // CHECK1-51-NEXT: store ptr [[B]], ptr [[TMP5]], align 8
// CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
// CHECK1-51-NEXT: store ptr [[S]], ptr [[TMP6]], align 8 // CHECK1-51-NEXT: store ptr [[S]], ptr [[TMP6]], align 8
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// CHECK1-51-NEXT: [[TMP175:%.*]] = load i32, ptr [[C]], align 128 // CHECK1-51-NEXT: [[TMP175:%.*]] = load i32, ptr [[C]], align 128
// CHECK1-51-NEXT: store i32 [[TMP175]], ptr [[TMP174]], align 128 // CHECK1-51-NEXT: store i32 [[TMP175]], ptr [[TMP174]], align 128
// CHECK1-51-NEXT: [[TMP176:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP172]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP176:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP172]], i32 0, i32 2
// CHECK1-51-NEXT: store i32 0, ptr [[TMP176]], align 16 // CHECK1-51-NEXT: store i32 0, ptr [[TMP176]], align 16
// CHECK1-51-NEXT: [[TMP177:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP171]]) // CHECK1-51-NEXT: [[TMP177:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP171]])
// CHECK1-51-NEXT: [[TMP178:%.*]] = load i32, ptr @a, align 4 // CHECK1-51-NEXT: [[TMP178:%.*]] = load i32, ptr @a, align 4
// CHECK1-51-NEXT: store i32 [[TMP178]], ptr [[RETVAL]], align 4 // CHECK1-51-NEXT: store i32 [[TMP178]], ptr [[RETVAL]], align 4
// CHECK1-51-NEXT: [[TMP179:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-51-NEXT: [[TMP179:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-51-NEXT: call void @llvm.stackrestore(ptr [[TMP179]]) // CHECK1-51-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP179]])
// CHECK1-51-NEXT: [[ARRAY_BEGIN42:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 // CHECK1-51-NEXT: [[ARRAY_BEGIN42:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0
// CHECK1-51-NEXT: [[TMP180:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN42]], i64 2 // CHECK1-51-NEXT: [[TMP180:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN42]], i64 2
// CHECK1-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1-51: arraydestroy.body: // CHECK1-51: arraydestroy.body:
// CHECK1-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP180]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP180]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
// CHECK1-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN42]] // CHECK1-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN42]]
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// CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK2-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK2: arrayctor.cont: // CHECK2: arrayctor.cont:
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4
// CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK2-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK2-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK2-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK2-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]] // CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]]
// CHECK2-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16 // CHECK2-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16
// CHECK2-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK2-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
// CHECK2-NEXT: store ptr [[B]], ptr [[TMP5]], align 8 // CHECK2-NEXT: store ptr [[B]], ptr [[TMP5]], align 8
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
// CHECK2-NEXT: store ptr [[S]], ptr [[TMP6]], align 8 // CHECK2-NEXT: store ptr [[S]], ptr [[TMP6]], align 8
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// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[C]], align 128 // CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[C]], align 128
// CHECK2-NEXT: store i32 [[TMP147]], ptr [[TMP146]], align 128 // CHECK2-NEXT: store i32 [[TMP147]], ptr [[TMP146]], align 128
// CHECK2-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP144]], i32 0, i32 2 // CHECK2-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP144]], i32 0, i32 2
// CHECK2-NEXT: store i32 0, ptr [[TMP148]], align 16 // CHECK2-NEXT: store i32 0, ptr [[TMP148]], align 16
// CHECK2-NEXT: [[TMP149:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP143]]) // CHECK2-NEXT: [[TMP149:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP143]])
// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr @a, align 4 // CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr @a, align 4
// CHECK2-NEXT: store i32 [[TMP150]], ptr [[RETVAL]], align 4 // CHECK2-NEXT: store i32 [[TMP150]], ptr [[RETVAL]], align 4
// CHECK2-NEXT: [[TMP151:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK2-NEXT: [[TMP151:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK2-NEXT: call void @llvm.stackrestore(ptr [[TMP151]]) // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP151]])
// CHECK2-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 // CHECK2-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0
// CHECK2-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN32]], i64 2 // CHECK2-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN32]], i64 2
// CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK2: arraydestroy.body: // CHECK2: arraydestroy.body:
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP152]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP152]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
// CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]]
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// CHECK2-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK2-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK2-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK2-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK2-51-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK2-51-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK2-51-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK2-51-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK2-51-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK2-51-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK2-51: arrayctor.cont: // CHECK2-51: arrayctor.cont:
// CHECK2-51-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4 // CHECK2-51-NEXT: [[TMP1:%.*]] = load i32, ptr @a, align 4
// CHECK2-51-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK2-51-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK2-51-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK2-51-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK2-51-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]] // CHECK2-51-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]]
// CHECK2-51-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16 // CHECK2-51-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16
// CHECK2-51-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK2-51-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
// CHECK2-51-NEXT: store ptr [[B]], ptr [[TMP5]], align 8 // CHECK2-51-NEXT: store ptr [[B]], ptr [[TMP5]], align 8
// CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
// CHECK2-51-NEXT: store ptr [[S]], ptr [[TMP6]], align 8 // CHECK2-51-NEXT: store ptr [[S]], ptr [[TMP6]], align 8
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// CHECK2-51-NEXT: [[TMP175:%.*]] = load i32, ptr [[C]], align 128 // CHECK2-51-NEXT: [[TMP175:%.*]] = load i32, ptr [[C]], align 128
// CHECK2-51-NEXT: store i32 [[TMP175]], ptr [[TMP174]], align 128 // CHECK2-51-NEXT: store i32 [[TMP175]], ptr [[TMP174]], align 128
// CHECK2-51-NEXT: [[TMP176:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP172]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP176:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP172]], i32 0, i32 2
// CHECK2-51-NEXT: store i32 0, ptr [[TMP176]], align 16 // CHECK2-51-NEXT: store i32 0, ptr [[TMP176]], align 16
// CHECK2-51-NEXT: [[TMP177:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP171]]) // CHECK2-51-NEXT: [[TMP177:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP171]])
// CHECK2-51-NEXT: [[TMP178:%.*]] = load i32, ptr @a, align 4 // CHECK2-51-NEXT: [[TMP178:%.*]] = load i32, ptr @a, align 4
// CHECK2-51-NEXT: store i32 [[TMP178]], ptr [[RETVAL]], align 4 // CHECK2-51-NEXT: store i32 [[TMP178]], ptr [[RETVAL]], align 4
// CHECK2-51-NEXT: [[TMP179:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK2-51-NEXT: [[TMP179:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK2-51-NEXT: call void @llvm.stackrestore(ptr [[TMP179]]) // CHECK2-51-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP179]])
// CHECK2-51-NEXT: [[ARRAY_BEGIN42:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 // CHECK2-51-NEXT: [[ARRAY_BEGIN42:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0
// CHECK2-51-NEXT: [[TMP180:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN42]], i64 2 // CHECK2-51-NEXT: [[TMP180:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN42]], i64 2
// CHECK2-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK2-51: arraydestroy.body: // CHECK2-51: arraydestroy.body:
// CHECK2-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP180]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP180]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK2-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK2-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
// CHECK2-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN42]] // CHECK2-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN42]]
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// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK3-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK3: arrayctor.cont: // CHECK3: arrayctor.cont:
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4
// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]] // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]]
// CHECK3-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16 // CHECK3-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16
// CHECK3-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK3-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
// CHECK3-NEXT: store ptr [[B]], ptr [[TMP4]], align 8 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP4]], align 8
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
// CHECK3-NEXT: store ptr [[S]], ptr [[TMP5]], align 8 // CHECK3-NEXT: store ptr [[S]], ptr [[TMP5]], align 8
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// CHECK3-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128 // CHECK3-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128
// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]])
// CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP143]], i32 0, i32 2 // CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP143]], i32 0, i32 2
// CHECK3-NEXT: store i32 0, ptr [[TMP147]], align 16 // CHECK3-NEXT: store i32 0, ptr [[TMP147]], align 16
// CHECK3-NEXT: [[TMP148:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM50]], ptr [[TMP142]]) // CHECK3-NEXT: [[TMP148:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM50]], ptr [[TMP142]])
// CHECK3-NEXT: [[TMP149:%.*]] = load i32, ptr @a, align 4 // CHECK3-NEXT: [[TMP149:%.*]] = load i32, ptr @a, align 4
// CHECK3-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4 // CHECK3-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4
// CHECK3-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP150]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP150]])
// CHECK3-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0
// CHECK3-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2 // CHECK3-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2
// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK3: arraydestroy.body: // CHECK3: arraydestroy.body:
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]]
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// CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK4-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK4: arrayctor.cont: // CHECK4: arrayctor.cont:
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4
// CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK4-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK4-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK4-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK4-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]] // CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]]
// CHECK4-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16 // CHECK4-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16
// CHECK4-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK4-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
// CHECK4-NEXT: store ptr [[B]], ptr [[TMP4]], align 8 // CHECK4-NEXT: store ptr [[B]], ptr [[TMP4]], align 8
// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
// CHECK4-NEXT: store ptr [[S]], ptr [[TMP5]], align 8 // CHECK4-NEXT: store ptr [[S]], ptr [[TMP5]], align 8
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// CHECK4-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128 // CHECK4-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128
// CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]])
// CHECK4-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP143]], i32 0, i32 2 // CHECK4-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP143]], i32 0, i32 2
// CHECK4-NEXT: store i32 0, ptr [[TMP147]], align 16 // CHECK4-NEXT: store i32 0, ptr [[TMP147]], align 16
// CHECK4-NEXT: [[TMP148:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM50]], ptr [[TMP142]]) // CHECK4-NEXT: [[TMP148:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM50]], ptr [[TMP142]])
// CHECK4-NEXT: [[TMP149:%.*]] = load i32, ptr @a, align 4 // CHECK4-NEXT: [[TMP149:%.*]] = load i32, ptr @a, align 4
// CHECK4-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4 // CHECK4-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4
// CHECK4-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK4-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK4-NEXT: call void @llvm.stackrestore(ptr [[TMP150]]) // CHECK4-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP150]])
// CHECK4-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 // CHECK4-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0
// CHECK4-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2 // CHECK4-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2
// CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK4: arraydestroy.body: // CHECK4: arraydestroy.body:
// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
// CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]]
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// CHECK3-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK3-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK3-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK3-51-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK3-51-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK3-51-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-51-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK3-51-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3-51-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK3-51: arrayctor.cont: // CHECK3-51: arrayctor.cont:
// CHECK3-51-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4 // CHECK3-51-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4
// CHECK3-51-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK3-51-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK3-51-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-51-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-51-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK3-51-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK3-51-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]] // CHECK3-51-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]]
// CHECK3-51-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16 // CHECK3-51-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16
// CHECK3-51-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK3-51-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
// CHECK3-51-NEXT: store ptr [[B]], ptr [[TMP4]], align 8 // CHECK3-51-NEXT: store ptr [[B]], ptr [[TMP4]], align 8
// CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
// CHECK3-51-NEXT: store ptr [[S]], ptr [[TMP5]], align 8 // CHECK3-51-NEXT: store ptr [[S]], ptr [[TMP5]], align 8
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// CHECK3-51-NEXT: store i32 [[TMP174]], ptr [[TMP173]], align 128 // CHECK3-51-NEXT: store i32 [[TMP174]], ptr [[TMP173]], align 128
// CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM62:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM62:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]])
// CHECK3-51-NEXT: [[TMP175:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP171]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP175:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP171]], i32 0, i32 2
// CHECK3-51-NEXT: store i32 0, ptr [[TMP175]], align 16 // CHECK3-51-NEXT: store i32 0, ptr [[TMP175]], align 16
// CHECK3-51-NEXT: [[TMP176:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM62]], ptr [[TMP170]]) // CHECK3-51-NEXT: [[TMP176:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM62]], ptr [[TMP170]])
// CHECK3-51-NEXT: [[TMP177:%.*]] = load i32, ptr @a, align 4 // CHECK3-51-NEXT: [[TMP177:%.*]] = load i32, ptr @a, align 4
// CHECK3-51-NEXT: store i32 [[TMP177]], ptr [[RETVAL]], align 4 // CHECK3-51-NEXT: store i32 [[TMP177]], ptr [[RETVAL]], align 4
// CHECK3-51-NEXT: [[TMP178:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-51-NEXT: [[TMP178:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK3-51-NEXT: call void @llvm.stackrestore(ptr [[TMP178]]) // CHECK3-51-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP178]])
// CHECK3-51-NEXT: [[ARRAY_BEGIN63:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 // CHECK3-51-NEXT: [[ARRAY_BEGIN63:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0
// CHECK3-51-NEXT: [[TMP179:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN63]], i64 2 // CHECK3-51-NEXT: [[TMP179:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN63]], i64 2
// CHECK3-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK3-51: arraydestroy.body: // CHECK3-51: arraydestroy.body:
// CHECK3-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP179]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP179]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK3-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK3-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
// CHECK3-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN63]] // CHECK3-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN63]]
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// CHECK4-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK4-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK4-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK4-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK4-51-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK4-51-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK4-51-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK4-51-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK4-51-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK4-51-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK4-51: arrayctor.cont: // CHECK4-51: arrayctor.cont:
// CHECK4-51-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4 // CHECK4-51-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4
// CHECK4-51-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK4-51-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK4-51-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK4-51-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK4-51-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK4-51-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK4-51-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]] // CHECK4-51-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]]
// CHECK4-51-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16 // CHECK4-51-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16
// CHECK4-51-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK4-51-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK4-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
// CHECK4-51-NEXT: store ptr [[B]], ptr [[TMP4]], align 8 // CHECK4-51-NEXT: store ptr [[B]], ptr [[TMP4]], align 8
// CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
// CHECK4-51-NEXT: store ptr [[S]], ptr [[TMP5]], align 8 // CHECK4-51-NEXT: store ptr [[S]], ptr [[TMP5]], align 8
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// CHECK4-51-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128 // CHECK4-51-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128
// CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]])
// CHECK4-51-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP143]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP143]], i32 0, i32 2
// CHECK4-51-NEXT: store i32 0, ptr [[TMP147]], align 16 // CHECK4-51-NEXT: store i32 0, ptr [[TMP147]], align 16
// CHECK4-51-NEXT: [[TMP148:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM50]], ptr [[TMP142]]) // CHECK4-51-NEXT: [[TMP148:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM50]], ptr [[TMP142]])
// CHECK4-51-NEXT: [[TMP149:%.*]] = load i32, ptr @a, align 4 // CHECK4-51-NEXT: [[TMP149:%.*]] = load i32, ptr @a, align 4
// CHECK4-51-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4 // CHECK4-51-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4
// CHECK4-51-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK4-51-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK4-51-NEXT: call void @llvm.stackrestore(ptr [[TMP150]]) // CHECK4-51-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP150]])
// CHECK4-51-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 // CHECK4-51-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0
// CHECK4-51-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2 // CHECK4-51-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2
// CHECK4-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK4-51: arraydestroy.body: // CHECK4-51: arraydestroy.body:
// CHECK4-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK4-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK4-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]]
// CHECK4-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK4-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]]
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clang/test/OpenMP/task_in_reduction_codegen.cpp

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// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK1: arrayctor.cont: // CHECK1: arrayctor.cont:
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 // CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1
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// CHECK1-NEXT: [[TMP44:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 8, ptr @.omp_task_entry..10) // CHECK1-NEXT: [[TMP44:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 8, ptr @.omp_task_entry..10)
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP44]], i32 0, i32 0 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP44]], i32 0, i32 0
// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP45]], i32 0, i32 0 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP45]], i32 0, i32 0
// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[TMP46]], align 8 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[TMP46]], align 8
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP47]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP47]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false)
// CHECK1-NEXT: [[TMP48:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP44]]) // CHECK1-NEXT: [[TMP48:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP44]])
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP49:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP49:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP49]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP49]])
// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0
// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP50]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP50]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
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clang/test/OpenMP/taskloop_in_reduction_codegen.cpp

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// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK1: arrayctor.cont: // CHECK1: arrayctor.cont:
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 // CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1
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// CHECK1-NEXT: store i32 1, ptr [[TMP41]], align 8 // CHECK1-NEXT: store i32 1, ptr [[TMP41]], align 8
// CHECK1-NEXT: [[TMP42:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]]) // CHECK1-NEXT: [[TMP42:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]])
// CHECK1-NEXT: store ptr [[TMP42]], ptr [[DOTTASK_RED_6]], align 8 // CHECK1-NEXT: store ptr [[TMP42]], ptr [[DOTTASK_RED_6]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED_6]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED_6]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP43]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP43]])
// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
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clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp

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// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK1: arrayctor.cont: // CHECK1: arrayctor.cont:
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 // CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1
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// CHECK1-NEXT: store i32 1, ptr [[TMP41]], align 8 // CHECK1-NEXT: store i32 1, ptr [[TMP41]], align 8
// CHECK1-NEXT: [[TMP42:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]]) // CHECK1-NEXT: [[TMP42:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 2, ptr [[DOTRD_INPUT_3]])
// CHECK1-NEXT: store ptr [[TMP42]], ptr [[DOTTASK_RED_6]], align 8 // CHECK1-NEXT: store ptr [[TMP42]], ptr [[DOTTASK_RED_6]], align 8
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED_6]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @main.omp_outlined, ptr [[A]], i64 [[TMP2]], ptr [[VLA]], ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED_6]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]])
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP43]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP43]])
// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body: // CHECK1: arraydestroy.body:
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
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// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
// CHECK3-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) // CHECK3-NEXT: call void @_ZN1SC1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
// CHECK3: arrayctor.cont: // CHECK3: arrayctor.cont:
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP1]], align 16
// CHECK3-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK3-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 // CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
// CHECK3-NEXT: store i64 4, ptr [[DOTOMP_UB]], align 8 // CHECK3-NEXT: store i64 4, ptr [[DOTOMP_UB]], align 8
// CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32 // CHECK3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
// CHECK3-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4
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// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
// CHECK3: omp.inner.for.end: // CHECK3: omp.inner.for.end:
// CHECK3-NEXT: store i32 5, ptr [[I]], align 4 // CHECK3-NEXT: store i32 5, ptr [[I]], align 4
// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP11]]) // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]])
// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 5 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 5
// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK3: arraydestroy.body: // CHECK3: arraydestroy.body:
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]]
// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
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clang/test/OpenMP/teams_distribute_codegen.cpp

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// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0
// CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK9-NEXT: ret i32 [[TMP38]] // CHECK9-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0
// CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK11-NEXT: ret i32 [[TMP38]] // CHECK11-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
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// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK25-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK25-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK25-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK25-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK25-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK25-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK25-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK25-NEXT: store i32 100, ptr [[N]], align 4 // CHECK25-NEXT: store i32 100, ptr [[N]], align 4
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK25-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK25-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK25-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK25-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK25-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK25-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK25-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK25-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK25-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK25: omp_offload.failed: // CHECK25: omp_offload.failed:
// CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK25: omp_offload.cont: // CHECK25: omp_offload.cont:
// CHECK25-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK25-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP38]]) // CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP38]])
// CHECK25-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK25-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK25-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK25-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK25-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK25-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK25-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK25-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK25-NEXT: ret i32 [[TMP40]] // CHECK25-NEXT: ret i32 [[TMP40]]
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162
// CHECK25-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK25-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK27-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK27-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK27-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK27-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK27-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK27-NEXT: store i32 100, ptr [[N]], align 4 // CHECK27-NEXT: store i32 100, ptr [[N]], align 4
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK27-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK27-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK27-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK27-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK27-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK27-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK27-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK27: omp_offload.failed: // CHECK27: omp_offload.failed:
// CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK27: omp_offload.cont: // CHECK27: omp_offload.cont:
// CHECK27-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK27-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP38]]) // CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP38]])
// CHECK27-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK27-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK27-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK27-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK27-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK27-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK27-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK27-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK27-NEXT: ret i32 [[TMP40]] // CHECK27-NEXT: ret i32 [[TMP40]]
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162
// CHECK27-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK27-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_collapse_codegen.cpp

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// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l82
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp

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// CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK9: omp_offload.failed31: // CHECK9: omp_offload.failed31:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP74]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP74]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]]
// CHECK9: omp_offload.cont32: // CHECK9: omp_offload.cont32:
// CHECK9-NEXT: [[TMP108:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP108:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP108]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP108]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP109:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP109:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP109]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP109]])
// CHECK9-NEXT: [[TMP110:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP110:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP110]] // CHECK9-NEXT: ret i32 [[TMP110]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK11: omp_offload.failed31: // CHECK11: omp_offload.failed31:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP75]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP75]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT32]]
// CHECK11: omp_offload.cont32: // CHECK11: omp_offload.cont32:
// CHECK11-NEXT: [[TMP110:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP110:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP110]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP110]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP111:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP111:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP111]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP111]])
// CHECK11-NEXT: [[TMP112:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP112:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP112]] // CHECK11-NEXT: ret i32 [[TMP112]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0
// CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK9-NEXT: ret i32 [[TMP38]] // CHECK9-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0
// CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK11-NEXT: ret i32 [[TMP38]] // CHECK11-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l73
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
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// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK25-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK25-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK25-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK25-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK25-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK25-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK25-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK25-NEXT: store i32 100, ptr [[N]], align 4 // CHECK25-NEXT: store i32 100, ptr [[N]], align 4
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK25-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK25-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK25-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK25-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK25-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK25-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK25-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK25-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK25-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK25: omp_offload.failed: // CHECK25: omp_offload.failed:
// CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK25: omp_offload.cont: // CHECK25: omp_offload.cont:
// CHECK25-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK25-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP38]]) // CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP38]])
// CHECK25-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK25-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK25-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK25-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK25-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK25-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK25-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK25-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK25-NEXT: ret i32 [[TMP40]] // CHECK25-NEXT: ret i32 [[TMP40]]
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162
// CHECK25-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK25-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK27-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK27-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK27-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK27-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK27-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK27-NEXT: store i32 100, ptr [[N]], align 4 // CHECK27-NEXT: store i32 100, ptr [[N]], align 4
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK27-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK27-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK27-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK27-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK27-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK27-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK27-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK27: omp_offload.failed: // CHECK27: omp_offload.failed:
// CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK27: omp_offload.cont: // CHECK27: omp_offload.cont:
// CHECK27-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK27-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP38]]) // CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP38]])
// CHECK27-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK27-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK27-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK27-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK27-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK27-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK27-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK27-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK27-NEXT: ret i32 [[TMP40]] // CHECK27-NEXT: ret i32 [[TMP40]]
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l162
// CHECK27-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK27-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp

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// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp

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// CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i32 10, ptr [[M]], align 4 // CHECK9-NEXT: store i32 10, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK9: omp_offload.failed31: // CHECK9: omp_offload.failed31:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP74]], i64 [[TMP76]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP74]], i64 [[TMP76]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]]
// CHECK9: omp_offload.cont32: // CHECK9: omp_offload.cont32:
// CHECK9-NEXT: [[TMP113:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP113:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP113]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP113]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP114:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP114:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP114]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP114]])
// CHECK9-NEXT: [[TMP115:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP115:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP115]] // CHECK9-NEXT: ret i32 [[TMP115]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 10, ptr [[M]], align 4 // CHECK11-NEXT: store i32 10, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK11: omp_offload.failed31: // CHECK11: omp_offload.failed31:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP75]], i32 [[TMP77]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP75]], i32 [[TMP77]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT32]]
// CHECK11: omp_offload.cont32: // CHECK11: omp_offload.cont32:
// CHECK11-NEXT: [[TMP115:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP115:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP115]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP115]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])
// CHECK11-NEXT: [[TMP117:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP117:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP117]] // CHECK11-NEXT: ret i32 [[TMP117]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_reduction_task_codegen.cpp

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// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]] // CHECK1-NEXT: [[TMP9:%.*]] = sub i64 [[TMP7]], [[TMP8]]
// CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = sdiv exact i64 [[TMP9]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1 // CHECK1-NEXT: [[TMP11:%.*]] = add nuw i64 [[TMP10]], 1
// CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP11]], align 16
// CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP11]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]] // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP11]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP14]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT32]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST25]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT32]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST25]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST24]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST24]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE34:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT32]], [[TMP81]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE34:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT32]], [[TMP81]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE34]], label [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_BODY23]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE34]], label [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_BODY23]]
// CHECK1: omp.arraycpy.done35: // CHECK1: omp.arraycpy.done35:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP90]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP90]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init. // CHECK1-LABEL: define {{[^@]+}}@.red_init.
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYIDX3]], align 8
// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 [[LB_ADD_LEN]] // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 [[LB_ADD_LEN]]
// CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64 // CHECK1-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[ARRAYIDX4]] to i64
// CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[ARRAYIDX2]] to i64
// CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]] // CHECK1-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]]
// CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP12:%.*]] = sdiv exact i64 [[TMP11]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1 // CHECK1-NEXT: [[TMP13:%.*]] = add nuw i64 [[TMP12]], 1
// CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
// CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave() // CHECK1-NEXT: [[TMP15:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP13]], align 16 // CHECK1-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP13]], align 16
// CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: store i64 [[TMP13]], ptr [[__VLA_EXPR0]], align 8
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP13]] // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[VLA]], i64 [[TMP13]]
// CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP16]] // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[VLA]], [[TMP16]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]]
// CHECK1: omp.arrayinit.body: // CHECK1: omp.arrayinit.body:
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[VLA]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ]
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// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT33]] = getelementptr i8, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST26]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT34]] = getelementptr i8, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST25]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP96]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE35:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT33]], [[TMP96]]
// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE35]], label [[OMP_ARRAYCPY_DONE36]], label [[OMP_ARRAYCPY_BODY24]]
// CHECK1: omp.arraycpy.done36: // CHECK1: omp.arraycpy.done36:
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
// CHECK1: .omp.reduction.default: // CHECK1: .omp.reduction.default:
// CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: [[TMP105:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP105]]) // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP105]])
// CHECK1-NEXT: ret void // CHECK1-NEXT: ret void
// //
// //
// CHECK1-LABEL: define {{[^@]+}}@.red_init..3 // CHECK1-LABEL: define {{[^@]+}}@.red_init..3
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry: // CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
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clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp

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// CHECK13-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK13-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i32 10, ptr [[M]], align 4 // CHECK13-NEXT: store i32 10, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK13: omp_offload.failed62: // CHECK13: omp_offload.failed62:
// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i64 [[TMP149]], i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i64 [[TMP149]], i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT63]] // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT63]]
// CHECK13: omp_offload.cont63: // CHECK13: omp_offload.cont63:
// CHECK13-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP188]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP188]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP189:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP189:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP189]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP189]])
// CHECK13-NEXT: [[TMP190:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP190:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP190]] // CHECK13-NEXT: ret i32 [[TMP190]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148
// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK15-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK15-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: store i32 10, ptr [[M]], align 4 // CHECK15-NEXT: store i32 10, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK15-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK15: omp_offload.failed62: // CHECK15: omp_offload.failed62:
// CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i32 [[TMP152]], i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]] // CHECK15-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i32 [[TMP152]], i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]]
// CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT63]] // CHECK15-NEXT: br label [[OMP_OFFLOAD_CONT63]]
// CHECK15: omp_offload.cont63: // CHECK15: omp_offload.cont63:
// CHECK15-NEXT: [[TMP192:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP192:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP192]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP192]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP193]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP193]])
// CHECK15-NEXT: [[TMP194:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP194:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP194]] // CHECK15-NEXT: ret i32 [[TMP194]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148
// CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK15-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK17-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK17-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK17-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK17-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK17-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK17-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK17-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK17-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK17-NEXT: store i32 100, ptr [[N]], align 4 // CHECK17-NEXT: store i32 100, ptr [[N]], align 4
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK17-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK17-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i32 10, ptr [[M]], align 4 // CHECK17-NEXT: store i32 10, ptr [[M]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK17-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK17-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK17-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK17: omp_offload.failed62: // CHECK17: omp_offload.failed62:
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i64 [[TMP149]], i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i64 [[TMP149]], i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT63]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT63]]
// CHECK17: omp_offload.cont63: // CHECK17: omp_offload.cont63:
// CHECK17-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK17-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP188]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP188]])
// CHECK17-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK17-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK17-NEXT: [[TMP189:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP189:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP189]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP189]])
// CHECK17-NEXT: [[TMP190:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK17-NEXT: [[TMP190:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK17-NEXT: ret i32 [[TMP190]] // CHECK17-NEXT: ret i32 [[TMP190]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148
// CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK19-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK19-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK19-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK19-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK19-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK19-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK19-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK19-NEXT: store i32 100, ptr [[N]], align 4 // CHECK19-NEXT: store i32 100, ptr [[N]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: store i32 10, ptr [[M]], align 4 // CHECK19-NEXT: store i32 10, ptr [[M]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK19: omp_offload.failed62: // CHECK19: omp_offload.failed62:
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i32 [[TMP152]], i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]] // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l168(i32 [[TMP152]], i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]]
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT63]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT63]]
// CHECK19: omp_offload.cont63: // CHECK19: omp_offload.cont63:
// CHECK19-NEXT: [[TMP192:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK19-NEXT: [[TMP192:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP192]]) // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP192]])
// CHECK19-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK19-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK19-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP193]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP193]])
// CHECK19-NEXT: [[TMP194:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK19-NEXT: [[TMP194:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK19-NEXT: ret i32 [[TMP194]] // CHECK19-NEXT: ret i32 [[TMP194]]
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l148
// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp

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// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [4 x i64], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [4 x i64], align 8
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[I_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[I_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[I_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[I_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4
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// CHECK9-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74(i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], i64 [[TMP6]]) #[[ATTR5:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74(i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], i64 [[TMP6]]) #[[ATTR5:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0
// CHECK9-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP44]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP44]])
// CHECK9-NEXT: ret i32 [[TMP43]] // CHECK9-NEXT: ret i32 [[TMP43]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74
// CHECK9-SAME: (i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
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// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [4 x i64], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [4 x i64], align 4
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[I_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[I_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[I_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[I_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
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// CHECK11-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74(i32 [[TMP0]], ptr [[VLA]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR5:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74(i32 [[TMP0]], ptr [[VLA]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR5:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0
// CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP44]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP44]])
// CHECK11-NEXT: ret i32 [[TMP43]] // CHECK11-NEXT: ret i32 [[TMP43]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l74
// CHECK11-SAME: (i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
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// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[I4:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I5:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK13-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 1 // CHECK13-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 1
// CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK13-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]]
// CHECK13-NEXT: store i32 [[ADD11]], ptr [[I]], align 4 // CHECK13-NEXT: store i32 [[ADD11]], ptr [[I]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13-NEXT: br label [[SIMD_IF_END]]
// CHECK13: simd.if.end: // CHECK13: simd.if.end:
// CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0 // CHECK13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0
// CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4
// CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP16]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])
// CHECK13-NEXT: ret i32 [[TMP15]] // CHECK13-NEXT: ret i32 [[TMP15]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z15teams_local_argv // CHECK15-LABEL: define {{[^@]+}}@_Z15teams_local_argv
// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { // CHECK15-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I4:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I5:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I5:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK15-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 1 // CHECK15-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 1
// CHECK15-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK15-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]]
// CHECK15-NEXT: store i32 [[ADD11]], ptr [[I]], align 4 // CHECK15-NEXT: store i32 [[ADD11]], ptr [[I]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15-NEXT: br label [[SIMD_IF_END]]
// CHECK15: simd.if.end: // CHECK15: simd.if.end:
// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0 // CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0
// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4
// CHECK15-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK15-NEXT: ret i32 [[TMP14]] // CHECK15-NEXT: ret i32 [[TMP14]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv
// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
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// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK25-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK25-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK25-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK25-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK25-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK25-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK25-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK25-NEXT: store i32 100, ptr [[N]], align 4 // CHECK25-NEXT: store i32 100, ptr [[N]], align 4
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK25-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK25-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK25-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK25-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK25-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK25-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
// CHECK25-NEXT: store i32 [[TMP3]], ptr [[I_CASTED]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], ptr [[I_CASTED]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, ptr [[I_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, ptr [[I_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
// CHECK25-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 // CHECK25-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4
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// CHECK25: omp_offload.failed: // CHECK25: omp_offload.failed:
// CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166(i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], i64 [[TMP6]]) #[[ATTR5:[0-9]+]] // CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166(i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], i64 [[TMP6]]) #[[ATTR5:[0-9]+]]
// CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK25: omp_offload.cont: // CHECK25: omp_offload.cont:
// CHECK25-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK25-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP43]]) // CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP43]])
// CHECK25-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK25-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK25-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK25-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK25-NEXT: call void @llvm.stackrestore(ptr [[TMP44]]) // CHECK25-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP44]])
// CHECK25-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK25-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK25-NEXT: ret i32 [[TMP45]] // CHECK25-NEXT: ret i32 [[TMP45]]
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166
// CHECK25-SAME: (i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK25-SAME: (i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[I:%.*]], i64 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
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// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK27-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK27-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK27-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK27-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK27-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK27-NEXT: store i32 100, ptr [[N]], align 4 // CHECK27-NEXT: store i32 100, ptr [[N]], align 4
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK27-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK27-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK27-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4
// CHECK27-NEXT: store i32 [[TMP2]], ptr [[I_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP2]], ptr [[I_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[I_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[I_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK27-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
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// CHECK27: omp_offload.failed: // CHECK27: omp_offload.failed:
// CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166(i32 [[TMP0]], ptr [[VLA]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR5:[0-9]+]] // CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166(i32 [[TMP0]], ptr [[VLA]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR5:[0-9]+]]
// CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK27: omp_offload.cont: // CHECK27: omp_offload.cont:
// CHECK27-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK27-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP43]]) // CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP43]])
// CHECK27-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK27-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK27-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK27-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK27-NEXT: call void @llvm.stackrestore(ptr [[TMP44]]) // CHECK27-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP44]])
// CHECK27-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK27-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK27-NEXT: ret i32 [[TMP45]] // CHECK27-NEXT: ret i32 [[TMP45]]
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l166
// CHECK27-SAME: (i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK27-SAME: (i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[I:%.*]], i32 noundef [[N:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
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// CHECK29-NEXT: [[I4:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK29-NEXT: [[I5:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[I5:%.*]] = alloca i32, align 4
// CHECK29-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK29-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK29-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK29-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK29-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK29-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK29-NEXT: store i32 100, ptr [[N]], align 4 // CHECK29-NEXT: store i32 100, ptr [[N]], align 4
// CHECK29-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK29-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK29-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK29-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK29-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK29-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK29-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK29-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK29-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK29-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK29-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK29-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK29-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK29-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK29-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK29-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK29-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK29-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK29-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]]
// CHECK29-NEXT: store i32 [[ADD11]], ptr [[I]], align 4 // CHECK29-NEXT: store i32 [[ADD11]], ptr [[I]], align 4
// CHECK29-NEXT: br label [[SIMD_IF_END]] // CHECK29-NEXT: br label [[SIMD_IF_END]]
// CHECK29: simd.if.end: // CHECK29: simd.if.end:
// CHECK29-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK29-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP15]]) // CHECK29-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP15]])
// CHECK29-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK29-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK29-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK29-NEXT: [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK29-NEXT: call void @llvm.stackrestore(ptr [[TMP16]]) // CHECK29-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP16]])
// CHECK29-NEXT: [[TMP17:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK29-NEXT: [[TMP17:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK29-NEXT: ret i32 [[TMP17]] // CHECK29-NEXT: ret i32 [[TMP17]]
// //
// //
// CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK29-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK29-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { // CHECK29-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat {
// CHECK29-NEXT: entry: // CHECK29-NEXT: entry:
// CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK29-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK31-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
// CHECK31-NEXT: [[I4:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK31-NEXT: [[I5:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[I5:%.*]] = alloca i32, align 4
// CHECK31-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK31-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK31-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK31-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK31-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK31-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK31-NEXT: store i32 100, ptr [[N]], align 4 // CHECK31-NEXT: store i32 100, ptr [[N]], align 4
// CHECK31-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK31-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK31-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK31-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK31-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK31-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK31-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK31-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK31-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK31-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK31-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK31-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK31-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK31-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK31-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK31-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK31-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]]
// CHECK31-NEXT: store i32 [[ADD11]], ptr [[I]], align 4 // CHECK31-NEXT: store i32 [[ADD11]], ptr [[I]], align 4
// CHECK31-NEXT: br label [[SIMD_IF_END]] // CHECK31-NEXT: br label [[SIMD_IF_END]]
// CHECK31: simd.if.end: // CHECK31: simd.if.end:
// CHECK31-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK31-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP14]]) // CHECK31-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP14]])
// CHECK31-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK31-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK31-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK31-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK31-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK31-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK31-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK31-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK31-NEXT: ret i32 [[TMP16]] // CHECK31-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK31-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK31-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat { // CHECK31-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR3:[0-9]+]] comdat {
// CHECK31-NEXT: entry: // CHECK31-NEXT: entry:
// CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK31-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp

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// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l86
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: store i32 2, ptr [[M]], align 4 // CHECK13-NEXT: store i32 2, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4
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// CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
// CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4 // CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13-NEXT: br label [[SIMD_IF_END]]
// CHECK13: simd.if.end: // CHECK13: simd.if.end:
// CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP29]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP29]])
// CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP30]] // CHECK13-NEXT: ret i32 [[TMP30]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: store i32 2, ptr [[M]], align 4 // CHECK15-NEXT: store i32 2, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4
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// CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
// CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4 // CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15-NEXT: br label [[SIMD_IF_END]]
// CHECK15: simd.if.end: // CHECK15: simd.if.end:
// CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP27]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP27]])
// CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP28]] // CHECK15-NEXT: ret i32 [[TMP28]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp

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// CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i32 10, ptr [[M]], align 4 // CHECK9-NEXT: store i32 10, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK9: omp_offload.failed31: // CHECK9: omp_offload.failed31:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l118(i64 [[TMP74]], i64 [[TMP76]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l118(i64 [[TMP74]], i64 [[TMP76]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]]
// CHECK9: omp_offload.cont32: // CHECK9: omp_offload.cont32:
// CHECK9-NEXT: [[TMP113:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP113:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP113]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP113]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP114:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP114:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP114]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP114]])
// CHECK9-NEXT: [[TMP115:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP115:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP115]] // CHECK9-NEXT: ret i32 [[TMP115]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 10, ptr [[M]], align 4 // CHECK11-NEXT: store i32 10, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK11: omp_offload.failed31: // CHECK11: omp_offload.failed31:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l118(i32 [[TMP75]], i32 [[TMP77]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l118(i32 [[TMP75]], i32 [[TMP77]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT32]]
// CHECK11: omp_offload.cont32: // CHECK11: omp_offload.cont32:
// CHECK11-NEXT: [[TMP115:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP115:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP115]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP115]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP116]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP116]])
// CHECK11-NEXT: [[TMP117:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP117:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP117]] // CHECK11-NEXT: ret i32 [[TMP117]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l108
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: [[DOTOMP_IV51:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV51:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[I52:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I52:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i32 10, ptr [[M]], align 4 // CHECK13-NEXT: store i32 10, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
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// CHECK13-NEXT: [[ADD67:%.*]] = add nsw i32 0, [[MUL66]] // CHECK13-NEXT: [[ADD67:%.*]] = add nsw i32 0, [[MUL66]]
// CHECK13-NEXT: store i32 [[ADD67]], ptr [[I52]], align 4 // CHECK13-NEXT: store i32 [[ADD67]], ptr [[I52]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END68]] // CHECK13-NEXT: br label [[SIMD_IF_END68]]
// CHECK13: simd.if.end68: // CHECK13: simd.if.end68:
// CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP38:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP38:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP38]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP38]])
// CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP39]] // CHECK13-NEXT: ret i32 [[TMP39]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_IV50:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV50:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I51:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I51:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: store i32 10, ptr [[M]], align 4 // CHECK15-NEXT: store i32 10, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
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// CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 0, [[MUL64]] // CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 0, [[MUL64]]
// CHECK15-NEXT: store i32 [[ADD65]], ptr [[I51]], align 4 // CHECK15-NEXT: store i32 [[ADD65]], ptr [[I51]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END66]] // CHECK15-NEXT: br label [[SIMD_IF_END66]]
// CHECK15: simd.if.end66: // CHECK15: simd.if.end66:
// CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP37:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP37:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP37]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP37]])
// CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP38]] // CHECK15-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp

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// CHECK13-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK13-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i32 10, ptr [[M]], align 4 // CHECK13-NEXT: store i32 10, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK13-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK13: omp_offload.failed62: // CHECK13: omp_offload.failed62:
// CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174(i64 [[TMP149]], i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174(i64 [[TMP149]], i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
// CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT63]] // CHECK13-NEXT: br label [[OMP_OFFLOAD_CONT63]]
// CHECK13: omp_offload.cont63: // CHECK13: omp_offload.cont63:
// CHECK13-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP188]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP188]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP189:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP189:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP189]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP189]])
// CHECK13-NEXT: [[TMP190:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP190:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP190]] // CHECK13-NEXT: ret i32 [[TMP190]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154
// CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK13-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK14-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4
// CHECK14-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK14-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK14-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK14-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK14-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK14-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK14-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK14-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK14-NEXT: store i32 100, ptr [[N]], align 4 // CHECK14-NEXT: store i32 100, ptr [[N]], align 4
// CHECK14-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK14-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK14-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK14-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK14-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK14-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK14-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK14-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK14-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK14-NEXT: store i32 10, ptr [[M]], align 4 // CHECK14-NEXT: store i32 10, ptr [[M]], align 4
// CHECK14-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK14-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK14-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK14-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK14-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK14-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
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// CHECK14: omp_offload.failed62: // CHECK14: omp_offload.failed62:
// CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174(i64 [[TMP149]], i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK14-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174(i64 [[TMP149]], i64 [[TMP151]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
// CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT63]] // CHECK14-NEXT: br label [[OMP_OFFLOAD_CONT63]]
// CHECK14: omp_offload.cont63: // CHECK14: omp_offload.cont63:
// CHECK14-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK14-NEXT: [[TMP188:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP188]]) // CHECK14-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP188]])
// CHECK14-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK14-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK14-NEXT: [[TMP189:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK14-NEXT: [[TMP189:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK14-NEXT: call void @llvm.stackrestore(ptr [[TMP189]]) // CHECK14-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP189]])
// CHECK14-NEXT: [[TMP190:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK14-NEXT: [[TMP190:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK14-NEXT: ret i32 [[TMP190]] // CHECK14-NEXT: ret i32 [[TMP190]]
// //
// //
// CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 // CHECK14-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154
// CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK14-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK14-NEXT: entry: // CHECK14-NEXT: entry:
// CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK17-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4
// CHECK17-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK17-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK17-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK17-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK17-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK17-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK17-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK17-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK17-NEXT: store i32 100, ptr [[N]], align 4 // CHECK17-NEXT: store i32 100, ptr [[N]], align 4
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK17-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK17-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK17-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK17-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK17-NEXT: store i32 10, ptr [[M]], align 4 // CHECK17-NEXT: store i32 10, ptr [[M]], align 4
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK17-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK17-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK17: omp_offload.failed62: // CHECK17: omp_offload.failed62:
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174(i32 [[TMP152]], i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]] // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174(i32 [[TMP152]], i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]]
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT63]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT63]]
// CHECK17: omp_offload.cont63: // CHECK17: omp_offload.cont63:
// CHECK17-NEXT: [[TMP192:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK17-NEXT: [[TMP192:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP192]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP192]])
// CHECK17-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK17-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK17-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK17-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP193]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP193]])
// CHECK17-NEXT: [[TMP194:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK17-NEXT: [[TMP194:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK17-NEXT: ret i32 [[TMP194]] // CHECK17-NEXT: ret i32 [[TMP194]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154
// CHECK17-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK19-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_55:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_56:%.*]] = alloca i32, align 4
// CHECK19-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK19-NEXT: [[KERNEL_ARGS61:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK19-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK19-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK19-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK19-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK19-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK19-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK19-NEXT: store i32 100, ptr [[N]], align 4 // CHECK19-NEXT: store i32 100, ptr [[N]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK19-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK19-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: store i32 10, ptr [[M]], align 4 // CHECK19-NEXT: store i32 10, ptr [[M]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
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// CHECK19: omp_offload.failed62: // CHECK19: omp_offload.failed62:
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174(i32 [[TMP152]], i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]] // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l174(i32 [[TMP152]], i32 [[TMP154]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]]
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT63]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT63]]
// CHECK19: omp_offload.cont63: // CHECK19: omp_offload.cont63:
// CHECK19-NEXT: [[TMP192:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK19-NEXT: [[TMP192:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP192]]) // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP192]])
// CHECK19-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK19-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK19-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP193:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP193]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP193]])
// CHECK19-NEXT: [[TMP194:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK19-NEXT: [[TMP194:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK19-NEXT: ret i32 [[TMP194]] // CHECK19-NEXT: ret i32 [[TMP194]]
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l154
// CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK21-NEXT: [[DOTOMP_IV110:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[DOTOMP_IV110:%.*]] = alloca i32, align 4
// CHECK21-NEXT: [[I111:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[I111:%.*]] = alloca i32, align 4
// CHECK21-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK21-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK21-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK21-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK21-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK21-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK21-NEXT: store i32 100, ptr [[N]], align 4 // CHECK21-NEXT: store i32 100, ptr [[N]], align 4
// CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK21-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK21-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK21-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK21-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK21-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK21-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK21-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK21-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK21-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK21-NEXT: store i32 10, ptr [[M]], align 4 // CHECK21-NEXT: store i32 10, ptr [[M]], align 4
// CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK21-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK21-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
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// CHECK21-NEXT: [[ADD126:%.*]] = add nsw i32 0, [[MUL125]] // CHECK21-NEXT: [[ADD126:%.*]] = add nsw i32 0, [[MUL125]]
// CHECK21-NEXT: store i32 [[ADD126]], ptr [[I111]], align 4 // CHECK21-NEXT: store i32 [[ADD126]], ptr [[I111]], align 4
// CHECK21-NEXT: br label [[SIMD_IF_END127]] // CHECK21-NEXT: br label [[SIMD_IF_END127]]
// CHECK21: simd.if.end127: // CHECK21: simd.if.end127:
// CHECK21-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK21-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP60]]) // CHECK21-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP60]])
// CHECK21-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK21-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK21-NEXT: [[TMP61:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK21-NEXT: [[TMP61:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK21-NEXT: call void @llvm.stackrestore(ptr [[TMP61]]) // CHECK21-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP61]])
// CHECK21-NEXT: [[TMP62:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK21-NEXT: [[TMP62:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK21-NEXT: ret i32 [[TMP62]] // CHECK21-NEXT: ret i32 [[TMP62]]
// //
// //
// CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK21-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK21-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK21-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK21-NEXT: entry: // CHECK21-NEXT: entry:
// CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK21-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK23-NEXT: [[I104:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[I104:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[DOTOMP_IV107:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[DOTOMP_IV107:%.*]] = alloca i32, align 4
// CHECK23-NEXT: [[I108:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[I108:%.*]] = alloca i32, align 4
// CHECK23-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK23-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK23-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK23-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK23-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK23-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK23-NEXT: store i32 100, ptr [[N]], align 4 // CHECK23-NEXT: store i32 100, ptr [[N]], align 4
// CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK23-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK23-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK23-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK23-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK23-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK23-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK23-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK23-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK23-NEXT: store i32 10, ptr [[M]], align 4 // CHECK23-NEXT: store i32 10, ptr [[M]], align 4
// CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK23-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK23-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
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// CHECK23-NEXT: [[ADD122:%.*]] = add nsw i32 0, [[MUL121]] // CHECK23-NEXT: [[ADD122:%.*]] = add nsw i32 0, [[MUL121]]
// CHECK23-NEXT: store i32 [[ADD122]], ptr [[I108]], align 4 // CHECK23-NEXT: store i32 [[ADD122]], ptr [[I108]], align 4
// CHECK23-NEXT: br label [[SIMD_IF_END123]] // CHECK23-NEXT: br label [[SIMD_IF_END123]]
// CHECK23: simd.if.end123: // CHECK23: simd.if.end123:
// CHECK23-NEXT: [[TMP59:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK23-NEXT: [[TMP59:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK23-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP59]]) // CHECK23-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP59]])
// CHECK23-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK23-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK23-NEXT: [[TMP60:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK23-NEXT: [[TMP60:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK23-NEXT: call void @llvm.stackrestore(ptr [[TMP60]]) // CHECK23-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP60]])
// CHECK23-NEXT: [[TMP61:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK23-NEXT: [[TMP61:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK23-NEXT: ret i32 [[TMP61]] // CHECK23-NEXT: ret i32 [[TMP61]]
// //
// //
// CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK23-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK23-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK23-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK23-NEXT: entry: // CHECK23-NEXT: entry:
// CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK23-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_simd_codegen.cpp

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// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0
// CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK9-NEXT: ret i32 [[TMP38]] // CHECK9-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0
// CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK11-NEXT: ret i32 [[TMP38]] // CHECK11-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l75
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK13-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1 // CHECK13-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1
// CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]
// CHECK13-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4 // CHECK13-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13-NEXT: br label [[SIMD_IF_END]]
// CHECK13: simd.if.end: // CHECK13: simd.if.end:
// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0 // CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0
// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4
// CHECK13-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK13-NEXT: ret i32 [[TMP14]] // CHECK13-NEXT: ret i32 [[TMP14]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z15teams_local_argv // CHECK15-LABEL: define {{[^@]+}}@_Z15teams_local_argv
// CHECK15-SAME: () #[[ATTR0:[0-9]+]] { // CHECK15-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
// CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK15-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1 // CHECK15-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 1
// CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] // CHECK15-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]
// CHECK15-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4 // CHECK15-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15-NEXT: br label [[SIMD_IF_END]]
// CHECK15: simd.if.end: // CHECK15: simd.if.end:
// CHECK15-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0 // CHECK15-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0
// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4
// CHECK15-NEXT: [[TMP14:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP14:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP14]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP14]])
// CHECK15-NEXT: ret i32 [[TMP13]] // CHECK15-NEXT: ret i32 [[TMP13]]
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv // CHECK17-LABEL: define {{[^@]+}}@_Z21teams_template_structv
// CHECK17-SAME: () #[[ATTR0:[0-9]+]] { // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 // CHECK17-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]]) // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(496) [[V]])
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// CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK21: omp.inner.for.body: // CHECK21: omp.inner.for.body:
// CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
// CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
// CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 1 // CHECK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 1
// CHECK21-NEXT: [[TMP10:%.*]] = load float, ptr [[B]], align 4, !nontemporal [[META5:![0-9]+]], !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[TMP10:%.*]] = load float, ptr [[B]], align 4, !nontemporal !5, !llvm.access.group [[ACC_GRP4]]
// CHECK21-NEXT: [[CONV:%.*]] = fptosi float [[TMP10]] to i32 // CHECK21-NEXT: [[CONV:%.*]] = fptosi float [[TMP10]] to i32
// CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0
// CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
// CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]]
// CHECK21-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP4]]
// CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK21: omp.body.continue: // CHECK21: omp.body.continue:
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// CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK23: omp.inner.for.body: // CHECK23: omp.inner.for.body:
// CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
// CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
// CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 1 // CHECK23-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 1
// CHECK23-NEXT: [[TMP10:%.*]] = load float, ptr [[B]], align 4, !nontemporal [[META6:![0-9]+]], !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: [[TMP10:%.*]] = load float, ptr [[B]], align 4, !nontemporal !6, !llvm.access.group [[ACC_GRP5]]
// CHECK23-NEXT: [[CONV:%.*]] = fptosi float [[TMP10]] to i32 // CHECK23-NEXT: [[CONV:%.*]] = fptosi float [[TMP10]] to i32
// CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0
// CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]]
// CHECK23-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
// CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK23: omp.body.continue: // CHECK23: omp.body.continue:
// CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] // CHECK29-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
// CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK29-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK29: omp.inner.for.body: // CHECK29: omp.inner.for.body:
// CHECK29-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK29-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
// CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1 // CHECK29-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
// CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK29-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK29-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
// CHECK29-NEXT: [[B3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 // CHECK29-NEXT: [[B3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
// CHECK29-NEXT: [[TMP6:%.*]] = load float, ptr [[B3]], align 4, !nontemporal [[META3:![0-9]+]], !llvm.access.group [[ACC_GRP2]] // CHECK29-NEXT: [[TMP6:%.*]] = load float, ptr [[B3]], align 4, !nontemporal !3, !llvm.access.group [[ACC_GRP2]]
// CHECK29-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 // CHECK29-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32
// CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
// CHECK29-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK29-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
// CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 // CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64
// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] // CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]]
// CHECK29-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK29-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
// CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK29: omp.body.continue: // CHECK29: omp.body.continue:
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// CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]] // CHECK31-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
// CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK31-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK31: omp.inner.for.body: // CHECK31: omp.inner.for.body:
// CHECK31-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK31-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
// CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1 // CHECK31-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
// CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK31-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK31-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
// CHECK31-NEXT: [[B3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 // CHECK31-NEXT: [[B3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1
// CHECK31-NEXT: [[TMP6:%.*]] = load float, ptr [[B3]], align 4, !nontemporal [[META4:![0-9]+]], !llvm.access.group [[ACC_GRP3]] // CHECK31-NEXT: [[TMP6:%.*]] = load float, ptr [[B3]], align 4, !nontemporal !4, !llvm.access.group [[ACC_GRP3]]
// CHECK31-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 // CHECK31-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32
// CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
// CHECK31-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK31-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP7]] // CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP7]]
// CHECK31-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK31-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
// CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK31: omp.body.continue: // CHECK31: omp.body.continue:
// CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK31-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
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// CHECK33-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK33-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK33-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK33-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK33-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK33-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK33-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK33-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK33-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK33-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK33-NEXT: store i32 100, ptr [[N]], align 4 // CHECK33-NEXT: store i32 100, ptr [[N]], align 4
// CHECK33-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK33-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK33-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK33-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK33-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK33-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK33-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK33-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK33-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK33-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK33-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK33-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK33-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK33-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK33-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK33-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK33-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK33-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK33-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK33-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK33-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK33-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK33: omp_offload.failed: // CHECK33: omp_offload.failed:
// CHECK33-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK33-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK33-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK33-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK33: omp_offload.cont: // CHECK33: omp_offload.cont:
// CHECK33-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK33-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK33-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP38]]) // CHECK33-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP38]])
// CHECK33-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK33-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK33-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK33-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK33-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK33-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK33-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK33-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK33-NEXT: ret i32 [[TMP40]] // CHECK33-NEXT: ret i32 [[TMP40]]
// //
// //
// CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 // CHECK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192
// CHECK33-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK33-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK33-NEXT: entry: // CHECK33-NEXT: entry:
// CHECK33-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK33-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK35-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK35-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK35-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK35-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK35-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK35-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK35-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK35-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK35-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK35-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK35-NEXT: store i32 100, ptr [[N]], align 4 // CHECK35-NEXT: store i32 100, ptr [[N]], align 4
// CHECK35-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK35-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK35-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK35-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK35-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK35-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK35-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK35-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK35-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK35-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK35-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK35-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK35-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK35-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK35-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK35-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK35-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK35-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK35-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK35-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK35: omp_offload.failed: // CHECK35: omp_offload.failed:
// CHECK35-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK35-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK35-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK35-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK35: omp_offload.cont: // CHECK35: omp_offload.cont:
// CHECK35-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK35-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK35-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP38]]) // CHECK35-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP38]])
// CHECK35-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK35-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK35-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK35-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK35-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK35-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK35-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK35-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK35-NEXT: ret i32 [[TMP40]] // CHECK35-NEXT: ret i32 [[TMP40]]
// //
// //
// CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 // CHECK35-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192
// CHECK35-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK35-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK35-NEXT: entry: // CHECK35-NEXT: entry:
// CHECK35-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK35-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK37-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK37-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK37-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK37-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK37-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK37-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK37-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK37-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK37-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK37-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK37-NEXT: store i32 100, ptr [[N]], align 4 // CHECK37-NEXT: store i32 100, ptr [[N]], align 4
// CHECK37-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK37-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK37-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK37-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK37-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK37-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK37-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK37-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK37-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK37-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK37-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK37-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK37-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK37-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK37-NEXT: store i32 [[TMP3]], ptr [[ARGC_CASTED]], align 4 // CHECK37-NEXT: store i32 [[TMP3]], ptr [[ARGC_CASTED]], align 4
// CHECK37-NEXT: [[TMP4:%.*]] = load i64, ptr [[ARGC_CASTED]], align 8 // CHECK37-NEXT: [[TMP4:%.*]] = load i64, ptr [[ARGC_CASTED]], align 8
// CHECK37-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4 // CHECK37-NEXT: [[TMP5:%.*]] = load i32, ptr [[N]], align 4
// CHECK37-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 // CHECK37-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4
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// CHECK37: omp_offload.failed: // CHECK37: omp_offload.failed:
// CHECK37-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK37-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK37-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK37-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK37: omp_offload.cont: // CHECK37: omp_offload.cont:
// CHECK37-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK37-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK37-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP43]]) // CHECK37-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP43]])
// CHECK37-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK37-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK37-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK37-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK37-NEXT: call void @llvm.stackrestore(ptr [[TMP44]]) // CHECK37-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP44]])
// CHECK37-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK37-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK37-NEXT: ret i32 [[TMP45]] // CHECK37-NEXT: ret i32 [[TMP45]]
// //
// //
// CHECK37-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 // CHECK37-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192
// CHECK37-SAME: (i64 noundef [[ARGC:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK37-SAME: (i64 noundef [[ARGC:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK37-NEXT: entry: // CHECK37-NEXT: entry:
// CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK37-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8
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// CHECK39-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK39-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK39-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK39-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK39-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK39-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK39-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK39-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK39-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK39-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK39-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK39-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK39-NEXT: store i32 100, ptr [[N]], align 4 // CHECK39-NEXT: store i32 100, ptr [[N]], align 4
// CHECK39-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK39-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK39-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK39-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK39-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK39-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK39-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK39-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK39-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK39-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK39-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK39-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK39-NEXT: store i32 [[TMP2]], ptr [[ARGC_CASTED]], align 4 // CHECK39-NEXT: store i32 [[TMP2]], ptr [[ARGC_CASTED]], align 4
// CHECK39-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARGC_CASTED]], align 4 // CHECK39-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARGC_CASTED]], align 4
// CHECK39-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK39-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK39-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK39-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
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// CHECK39: omp_offload.failed: // CHECK39: omp_offload.failed:
// CHECK39-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK39-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192(i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK39-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK39-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK39: omp_offload.cont: // CHECK39: omp_offload.cont:
// CHECK39-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK39-NEXT: [[TMP43:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK39-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP43]]) // CHECK39-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP43]])
// CHECK39-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK39-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK39-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK39-NEXT: [[TMP44:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK39-NEXT: call void @llvm.stackrestore(ptr [[TMP44]]) // CHECK39-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP44]])
// CHECK39-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK39-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK39-NEXT: ret i32 [[TMP45]] // CHECK39-NEXT: ret i32 [[TMP45]]
// //
// //
// CHECK39-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192 // CHECK39-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l192
// CHECK39-SAME: (i32 noundef [[ARGC:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK39-SAME: (i32 noundef [[ARGC:%.*]], i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK39-NEXT: entry: // CHECK39-NEXT: entry:
// CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK39-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK41-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK41-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK41-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK41-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK41-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK41-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK41-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK41-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK41-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK41-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK41-NEXT: store i32 100, ptr [[N]], align 4 // CHECK41-NEXT: store i32 100, ptr [[N]], align 4
// CHECK41-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK41-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK41-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK41-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK41-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK41-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK41-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK41-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK41-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK41-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK41-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK41-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK41-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK41-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK41-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK41-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK41-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK41-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK41-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK41-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK41-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK41-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK41-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] // CHECK41-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]
// CHECK41-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4 // CHECK41-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4
// CHECK41-NEXT: br label [[SIMD_IF_END]] // CHECK41-NEXT: br label [[SIMD_IF_END]]
// CHECK41: simd.if.end: // CHECK41: simd.if.end:
// CHECK41-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK41-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK41-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP14]]) // CHECK41-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP14]])
// CHECK41-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK41-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK41-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK41-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK41-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK41-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK41-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK41-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK41-NEXT: ret i32 [[TMP16]] // CHECK41-NEXT: ret i32 [[TMP16]]
// //
// //
// CHECK41-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK41-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK41-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK41-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK41-NEXT: entry: // CHECK41-NEXT: entry:
// CHECK41-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK41-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK43-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK43-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK43-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK43-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK43-NEXT: [[I3:%.*]] = alloca i32, align 4 // CHECK43-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK43-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK43-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK43-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK43-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK43-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK43-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK43-NEXT: store i32 100, ptr [[N]], align 4 // CHECK43-NEXT: store i32 100, ptr [[N]], align 4
// CHECK43-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK43-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK43-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK43-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK43-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK43-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK43-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK43-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK43-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK43-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK43-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK43-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK43-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK43-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK43-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK43-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK43-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK43-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK43-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK43-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK43-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] // CHECK43-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]]
// CHECK43-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4 // CHECK43-NEXT: store i32 [[ADD9]], ptr [[I3]], align 4
// CHECK43-NEXT: br label [[SIMD_IF_END]] // CHECK43-NEXT: br label [[SIMD_IF_END]]
// CHECK43: simd.if.end: // CHECK43: simd.if.end:
// CHECK43-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK43-NEXT: [[TMP13:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK43-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP13]]) // CHECK43-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP13]])
// CHECK43-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK43-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK43-NEXT: [[TMP14:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK43-NEXT: [[TMP14:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK43-NEXT: call void @llvm.stackrestore(ptr [[TMP14]]) // CHECK43-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP14]])
// CHECK43-NEXT: [[TMP15:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK43-NEXT: [[TMP15:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK43-NEXT: ret i32 [[TMP15]] // CHECK43-NEXT: ret i32 [[TMP15]]
// //
// //
// CHECK43-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK43-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK43-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK43-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK43-NEXT: entry: // CHECK43-NEXT: entry:
// CHECK43-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK43-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK45-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK45-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK45-NEXT: [[I4:%.*]] = alloca i32, align 4 // CHECK45-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK45-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK45-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK45-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK45-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK45-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK45-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK45-NEXT: store i32 100, ptr [[N]], align 4 // CHECK45-NEXT: store i32 100, ptr [[N]], align 4
// CHECK45-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK45-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK45-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK45-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK45-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK45-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK45-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK45-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK45-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK45-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK45-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK45-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK45-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK45-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK45-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 // CHECK45-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
// CHECK45-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK45-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK45-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK45-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
// CHECK45-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK45-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
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// CHECK45-NEXT: [[ADD22:%.*]] = add nsw i32 0, [[MUL21]] // CHECK45-NEXT: [[ADD22:%.*]] = add nsw i32 0, [[MUL21]]
// CHECK45-NEXT: store i32 [[ADD22]], ptr [[I4]], align 4 // CHECK45-NEXT: store i32 [[ADD22]], ptr [[I4]], align 4
// CHECK45-NEXT: br label [[SIMD_IF_END]] // CHECK45-NEXT: br label [[SIMD_IF_END]]
// CHECK45: simd.if.end: // CHECK45: simd.if.end:
// CHECK45-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK45-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK45-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP21]]) // CHECK45-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP21]])
// CHECK45-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK45-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK45-NEXT: [[TMP22:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK45-NEXT: [[TMP22:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK45-NEXT: call void @llvm.stackrestore(ptr [[TMP22]]) // CHECK45-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP22]])
// CHECK45-NEXT: [[TMP23:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK45-NEXT: [[TMP23:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK45-NEXT: ret i32 [[TMP23]] // CHECK45-NEXT: ret i32 [[TMP23]]
// //
// //
// CHECK45-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK45-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK45-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK45-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK45-NEXT: entry: // CHECK45-NEXT: entry:
// CHECK45-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK45-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK47-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK47-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK47-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK47-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK47-NEXT: [[I4:%.*]] = alloca i32, align 4 // CHECK47-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK47-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK47-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK47-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK47-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK47-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK47-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK47-NEXT: store i32 100, ptr [[N]], align 4 // CHECK47-NEXT: store i32 100, ptr [[N]], align 4
// CHECK47-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK47-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK47-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK47-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK47-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK47-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK47-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK47-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK47-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK47-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK47-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK47-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK47-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK47-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK47-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 // CHECK47-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
// CHECK47-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK47-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
// CHECK47-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK47-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
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// CHECK47-NEXT: [[ADD21:%.*]] = add nsw i32 0, [[MUL20]] // CHECK47-NEXT: [[ADD21:%.*]] = add nsw i32 0, [[MUL20]]
// CHECK47-NEXT: store i32 [[ADD21]], ptr [[I4]], align 4 // CHECK47-NEXT: store i32 [[ADD21]], ptr [[I4]], align 4
// CHECK47-NEXT: br label [[SIMD_IF_END]] // CHECK47-NEXT: br label [[SIMD_IF_END]]
// CHECK47: simd.if.end: // CHECK47: simd.if.end:
// CHECK47-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK47-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK47-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP20]]) // CHECK47-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP20]])
// CHECK47-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK47-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK47-NEXT: [[TMP21:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK47-NEXT: [[TMP21:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK47-NEXT: call void @llvm.stackrestore(ptr [[TMP21]]) // CHECK47-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP21]])
// CHECK47-NEXT: [[TMP22:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK47-NEXT: [[TMP22:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK47-NEXT: ret i32 [[TMP22]] // CHECK47-NEXT: ret i32 [[TMP22]]
// //
// //
// CHECK47-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK47-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK47-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK47-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK47-NEXT: entry: // CHECK47-NEXT: entry:
// CHECK47-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK47-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp

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// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: store i32 2, ptr [[M]], align 4 // CHECK13-NEXT: store i32 2, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4
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// CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]] // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
// CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4 // CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END]] // CHECK13-NEXT: br label [[SIMD_IF_END]]
// CHECK13: simd.if.end: // CHECK13: simd.if.end:
// CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP29]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP29]])
// CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP30]] // CHECK13-NEXT: ret i32 [[TMP30]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: store i32 2, ptr [[M]], align 4 // CHECK15-NEXT: store i32 2, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4
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// CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]] // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
// CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4 // CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END]] // CHECK15-NEXT: br label [[SIMD_IF_END]]
// CHECK15: simd.if.end: // CHECK15: simd.if.end:
// CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP27]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP27]])
// CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP28]] // CHECK15-NEXT: ret i32 [[TMP28]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_ // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp

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// CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK9: omp_offload.failed31: // CHECK9: omp_offload.failed31:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP74]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i64 [[TMP74]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT32]]
// CHECK9: omp_offload.cont32: // CHECK9: omp_offload.cont32:
// CHECK9-NEXT: [[TMP108:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP108:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP108]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP108]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP109:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP109:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP109]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP109]])
// CHECK9-NEXT: [[TMP110:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP110:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP110]] // CHECK9-NEXT: ret i32 [[TMP110]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_24:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_25:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK11: omp_offload.failed31: // CHECK11: omp_offload.failed31:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP75]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l110(i32 [[TMP75]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT32]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT32]]
// CHECK11: omp_offload.cont32: // CHECK11: omp_offload.cont32:
// CHECK11-NEXT: [[TMP110:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP110:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP110]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP110]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP111:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP111:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP111]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP111]])
// CHECK11-NEXT: [[TMP112:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP112:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP112]] // CHECK11-NEXT: ret i32 [[TMP112]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l100
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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// CHECK13-NEXT: [[DOTOMP_IV51:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IV51:%.*]] = alloca i32, align 4
// CHECK13-NEXT: [[I52:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I52:%.*]] = alloca i32, align 4
// CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK13-NEXT: store i32 100, ptr [[N]], align 4 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK13-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0
// CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK13-NEXT: [[ADD67:%.*]] = add nsw i32 0, [[MUL66]] // CHECK13-NEXT: [[ADD67:%.*]] = add nsw i32 0, [[MUL66]]
// CHECK13-NEXT: store i32 [[ADD67]], ptr [[I52]], align 4 // CHECK13-NEXT: store i32 [[ADD67]], ptr [[I52]], align 4
// CHECK13-NEXT: br label [[SIMD_IF_END68]] // CHECK13-NEXT: br label [[SIMD_IF_END68]]
// CHECK13: simd.if.end68: // CHECK13: simd.if.end68:
// CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]]) // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP37]])
// CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK13-NEXT: [[TMP38:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK13-NEXT: [[TMP38:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK13-NEXT: call void @llvm.stackrestore(ptr [[TMP38]]) // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP38]])
// CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK13-NEXT: ret i32 [[TMP39]] // CHECK13-NEXT: ret i32 [[TMP39]]
// //
// //
// CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK13-NEXT: entry: // CHECK13-NEXT: entry:
// CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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// CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I47:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[DOTOMP_IV50:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IV50:%.*]] = alloca i32, align 4
// CHECK15-NEXT: [[I51:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I51:%.*]] = alloca i32, align 4
// CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK15-NEXT: store i32 100, ptr [[N]], align 4 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK15-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
// CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
// CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
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// CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 0, [[MUL64]] // CHECK15-NEXT: [[ADD65:%.*]] = add nsw i32 0, [[MUL64]]
// CHECK15-NEXT: store i32 [[ADD65]], ptr [[I51]], align 4 // CHECK15-NEXT: store i32 [[ADD65]], ptr [[I51]], align 4
// CHECK15-NEXT: br label [[SIMD_IF_END66]] // CHECK15-NEXT: br label [[SIMD_IF_END66]]
// CHECK15: simd.if.end66: // CHECK15: simd.if.end66:
// CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK15-NEXT: [[TMP36:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]]) // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP36]])
// CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK15-NEXT: [[TMP37:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK15-NEXT: [[TMP37:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK15-NEXT: call void @llvm.stackrestore(ptr [[TMP37]]) // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP37]])
// CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK15-NEXT: ret i32 [[TMP38]] // CHECK15-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_ // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10EEiT_
// CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat { // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
// CHECK15-NEXT: entry: // CHECK15-NEXT: entry:
// CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_firstprivate_codegen.cpp

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// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]
// CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[A_ADDR]], align 8
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
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// CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, ptr [[KERNEL_ARGS]]) // CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, ptr [[KERNEL_ARGS]])
// CHECK17-NEXT: [[TMP57:%.*]] = icmp ne i32 [[TMP56]], 0 // CHECK17-NEXT: [[TMP57:%.*]] = icmp ne i32 [[TMP56]], 0
// CHECK17-NEXT: br i1 [[TMP57]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK17-NEXT: br i1 [[TMP57]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK17: omp_offload.failed: // CHECK17: omp_offload.failed:
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP1]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP1]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]]
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK17: omp_offload.cont: // CHECK17: omp_offload.cont:
// CHECK17-NEXT: [[TMP58:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP58:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP58]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP58]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152
// CHECK17-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK17-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8
// CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8
// CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
// CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8
// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP8]], i1 false) // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP8]], i1 false)
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i64 0 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i64 0
// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 signext [[TMP11]], ptr [[TMP12]]) // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 signext [[TMP11]], ptr [[TMP12]])
// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg
// CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 signext [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat { // CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 signext [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
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// CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]]
// CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
// CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
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// CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, ptr [[KERNEL_ARGS]]) // CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, ptr [[KERNEL_ARGS]])
// CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 // CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0
// CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK17: omp_offload.failed: // CHECK17: omp_offload.failed:
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(ptr [[TMP9]], i64 [[TMP1]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], ptr [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(ptr [[TMP9]], i64 [[TMP1]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], ptr [[THIS1]], i64 [[TMP12]]) #[[ATTR4]]
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK17: omp_offload.cont: // CHECK17: omp_offload.cont:
// CHECK17-NEXT: [[TMP70:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP70:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP70]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP70]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144
// CHECK17-SAME: (ptr [[S:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { // CHECK17-SAME: (ptr [[S:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
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// CHECK17-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 // CHECK17-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8
// CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8
// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8
// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 8 // CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 8
// CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
// CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]]
// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8
// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP9]], i1 false) // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP9]], i1 false)
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// CHECK17-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 // CHECK17-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128
// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8
// CHECK17-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1 // CHECK17-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[B10]], align 4 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[B10]], align 4
// CHECK17-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP14]] to i64 // CHECK17-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP14]] to i64
// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ptr [[TMP13]], i64 [[IDXPROM11]] // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ptr [[TMP13]], i64 [[IDXPROM11]]
// CHECK17-NEXT: store ppc_fp128 [[CONV9]], ptr [[ARRAYIDX12]], align 16 // CHECK17-NEXT: store ppc_fp128 [[CONV9]], ptr [[ARRAYIDX12]], align 16
// CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
// //
// //
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK17-SAME: () #[[ATTR5:[0-9]+]] { // CHECK17-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK17-NEXT: entry: // CHECK17-NEXT: entry:
// CHECK17-NEXT: call void @__tgt_register_requires(i64 1) // CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK17-NEXT: ret void // CHECK17-NEXT: ret void
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// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
// CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4
// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 4
// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 4 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4
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// CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, ptr [[KERNEL_ARGS]]) // CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, ptr [[KERNEL_ARGS]])
// CHECK19-NEXT: [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0 // CHECK19-NEXT: [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0
// CHECK19-NEXT: br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK19-NEXT: br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK19: omp_offload.failed: // CHECK19: omp_offload.failed:
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(ptr [[TMP5]], ptr [[TMP6]], i32 [[TMP0]], ptr [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], ptr [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(ptr [[TMP5]], ptr [[TMP6]], i32 [[TMP0]], ptr [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], ptr [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]]
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK19: omp_offload.cont: // CHECK19: omp_offload.cont:
// CHECK19-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP56]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP56]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152
// CHECK19-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK19-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4
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// CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4 // CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4
// CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4 // CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4
// CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4 // CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] // CHECK19-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]]
// CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]]
// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8
// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i32 [[TMP8]], i1 false) // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i32 [[TMP8]], i1 false)
// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 4 // CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i32 0 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i32 0
// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 4 // CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 4
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 // CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4
// CHECK19-NEXT: call void @_ZN2St7St_funcEPS_iPe(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 [[TMP11]], ptr [[TMP12]]) // CHECK19-NEXT: call void @_ZN2St7St_funcEPS_iPe(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 [[TMP11]], ptr [[TMP12]])
// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe // CHECK19-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe
// CHECK19-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { // CHECK19-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4
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// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
// CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4
// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
// CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4
// CHECK19-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK19-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
// CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
// CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
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// CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, ptr [[KERNEL_ARGS]]) // CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, ptr [[KERNEL_ARGS]])
// CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 // CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0
// CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK19: omp_offload.failed: // CHECK19: omp_offload.failed:
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(ptr [[TMP6]], i32 [[TMP0]], ptr [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], ptr [[VLA]], ptr [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(ptr [[TMP6]], i32 [[TMP0]], ptr [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], ptr [[VLA]], ptr [[THIS1]], i32 [[TMP9]]) #[[ATTR4]]
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK19: omp_offload.cont: // CHECK19: omp_offload.cont:
// CHECK19-NEXT: [[TMP68:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP68:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP68]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP68]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144
// CHECK19-SAME: (ptr [[S:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], ptr [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { // CHECK19-SAME: (ptr [[S:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], ptr [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
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// CHECK19-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 // CHECK19-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4
// CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
// CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4
// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4
// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 4 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 4
// CHECK19-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() // CHECK19-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK19-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]]
// CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR0]], align 4 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR0]], align 4
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 // CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]]
// CHECK19-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 // CHECK19-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8
// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i32 [[TMP9]], i1 false) // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i32 [[TMP9]], i1 false)
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// CHECK19-NEXT: store double [[CONV]], ptr [[ARRAYIDX8]], align 8 // CHECK19-NEXT: store double [[CONV]], ptr [[ARRAYIDX8]], align 8
// CHECK19-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 // CHECK19-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80
// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 // CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4
// CHECK19-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1 // CHECK19-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1
// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[B10]], align 4 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[B10]], align 4
// CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, ptr [[TMP13]], i32 [[TMP14]] // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, ptr [[TMP13]], i32 [[TMP14]]
// CHECK19-NEXT: store x86_fp80 [[CONV9]], ptr [[ARRAYIDX11]], align 4 // CHECK19-NEXT: store x86_fp80 [[CONV9]], ptr [[ARRAYIDX11]], align 4
// CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]])
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
// //
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
// CHECK19-SAME: () #[[ATTR5:[0-9]+]] { // CHECK19-SAME: () #[[ATTR5:[0-9]+]] {
// CHECK19-NEXT: entry: // CHECK19-NEXT: entry:
// CHECK19-NEXT: call void @__tgt_register_requires(i64 1) // CHECK19-NEXT: call void @__tgt_register_requires(i64 1)
// CHECK19-NEXT: ret void // CHECK19-NEXT: ret void
// //
Context not available.

clang/test/OpenMP/teams_generic_loop_codegen-1.cpp

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// CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 8
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 0
// CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK9-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK9-NEXT: ret i32 [[TMP38]] // CHECK9-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
// CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [3 x i64], align 4
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK11-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK11-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 0
// CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
// CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK11-NEXT: ret i32 [[TMP38]] // CHECK11-NEXT: ret i32 [[TMP38]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
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// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK25-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK25-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK25-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK25-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK25-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK25-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK25-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK25-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK25-NEXT: store i32 100, ptr [[N]], align 4 // CHECK25-NEXT: store i32 100, ptr [[N]], align 4
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK25-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK25-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK25-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK25-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 // CHECK25-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
// CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4 // CHECK25-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 4
// CHECK25-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK25-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[N]], align 4
// CHECK25-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4 // CHECK25-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4 // CHECK25-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], 4
// CHECK25-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false) // CHECK25-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 24, i1 false)
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// CHECK25: omp_offload.failed: // CHECK25: omp_offload.failed:
// CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK25-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161(i64 [[TMP4]], i64 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK25-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK25: omp_offload.cont: // CHECK25: omp_offload.cont:
// CHECK25-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK25-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP38]]) // CHECK25-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10EEiT_(i32 noundef signext [[TMP38]])
// CHECK25-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK25-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK25-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK25-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK25-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK25-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK25-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK25-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK25-NEXT: ret i32 [[TMP40]] // CHECK25-NEXT: ret i32 [[TMP40]]
// //
// //
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161
// CHECK25-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK25-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK25-NEXT: entry: // CHECK25-NEXT: entry:
// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK27-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK27-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK27-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK27-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK27-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK27-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK27-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK27-NEXT: store i32 100, ptr [[N]], align 4 // CHECK27-NEXT: store i32 100, ptr [[N]], align 4
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK27-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() // CHECK27-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK27-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4 // CHECK27-NEXT: store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
// CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4 // CHECK27-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP0]], align 4
// CHECK27-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK27-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[N]], align 4
// CHECK27-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4 // CHECK27-NEXT: store i32 [[TMP2]], ptr [[N_CASTED]], align 4
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK27-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4 // CHECK27-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP0]], 4
// CHECK27-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64 // CHECK27-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK27: omp_offload.failed: // CHECK27: omp_offload.failed:
// CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK27-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161(i32 [[TMP3]], i32 [[TMP0]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK27-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK27: omp_offload.cont: // CHECK27: omp_offload.cont:
// CHECK27-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK27-NEXT: [[TMP38:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP38]]) // CHECK27-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10EEiT_(i32 noundef [[TMP38]])
// CHECK27-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK27-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK27-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK27-NEXT: [[TMP39:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK27-NEXT: call void @llvm.stackrestore(ptr [[TMP39]]) // CHECK27-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP39]])
// CHECK27-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK27-NEXT: [[TMP40:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK27-NEXT: ret i32 [[TMP40]] // CHECK27-NEXT: ret i32 [[TMP40]]
// //
// //
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161
// CHECK27-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK27-SAME: (i32 noundef [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK27-NEXT: entry: // CHECK27-NEXT: entry:
// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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clang/test/OpenMP/teams_generic_loop_collapse_codgen.cpp

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// CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
// CHECK9-NEXT: store i32 100, ptr [[N]], align 4 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
// CHECK9-NEXT: store i32 2, ptr [[M]], align 4 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
// CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
// CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave() // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]] // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
// CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
// CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
// CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
// CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
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// CHECK9: omp_offload.failed: // CHECK9: omp_offload.failed:
// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont: // CHECK9: omp_offload.cont:
// CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
// CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
// CHECK9-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
// CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK9-NEXT: ret i32 [[TMP53]] // CHECK9-NEXT: ret i32 [[TMP53]]
// //
// //
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK9-NEXT: entry: // CHECK9-NEXT: entry:
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
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// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
// CHECK11-NEXT: store i32 100, ptr [[N]], align 4 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
// CHECK11-NEXT: store i32 2, ptr [[M]], align 4 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
// CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
// CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]] // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
// CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
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// CHECK11: omp_offload.failed: // CHECK11: omp_offload.failed:
// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont: // CHECK11: omp_offload.cont:
// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
// CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
// CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
// CHECK11-NEXT: call void @llvm.stackrestore(ptr [[TMP51]]) // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
// CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
// CHECK11-NEXT: ret i32 [[TMP52]] // CHECK11-NEXT: ret i32 [[TMP52]]
// //
// //
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK11-NEXT: entry: // CHECK11-NEXT: entry:
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
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llvm/docs/LangRef.rst

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``G<address space>`` ``G<address space>``
Specifies the address space to be used by default when creating global Specifies the address space to be used by default when creating global
variables. If omitted, the globals address space defaults to the default variables. If omitted, the globals address space defaults to the default
address space 0. address space 0.
Note: variable declarations without an address space are always created in Note: variable declarations without an address space are always created in
address space 0, this property only affects the default value to be used address space 0, this property only affects the default value to be used
when creating globals without additional contextual information (e.g. in when creating globals without additional contextual information (e.g. in
LLVM passes). LLVM passes).
.. _alloca_addrspace:
``A<address space>`` ``A<address space>``
Specifies the address space of objects created by '``alloca``'. Specifies the address space of objects created by '``alloca``'.
Defaults to the default address space of 0. Defaults to the default address space of 0.
``p[n]:<size>:<abi>[:<pref>][:<idx>]`` ``p[n]:<size>:<abi>[:<pref>][:<idx>]``
This specifies the *size* of a pointer and its ``<abi>`` and This specifies the *size* of a pointer and its ``<abi>`` and
``<pref>``\erred alignments for address space ``n``. ``<pref>`` is optional ``<pref>``\erred alignments for address space ``n``. ``<pref>`` is optional
and defaults to ``<abi>``. The fourth parameter ``<idx>`` is the size of the and defaults to ``<abi>``. The fourth parameter ``<idx>`` is the size of the
index that used for address calculation. If not index that used for address calculation. If not
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'``llvm.stacksave``' Intrinsic '``llvm.stacksave``' Intrinsic
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Syntax: Syntax:
""""""" """""""
:: ::
declare ptr @llvm.stacksave() declare ptr @llvm.stacksave.p0()
declare ptr addrspace(5) @llvm.stacksave.p5()
Overview: Overview:
""""""""" """""""""
The '``llvm.stacksave``' intrinsic is used to remember the current state The '``llvm.stacksave``' intrinsic is used to remember the current state
of the function stack, for use with of the function stack, for use with
:ref:`llvm.stackrestore <int_stackrestore>`. This is useful for :ref:`llvm.stackrestore <int_stackrestore>`. This is useful for
implementing language features like scoped automatic variable sized implementing language features like scoped automatic variable sized
arrays in C99. arrays in C99.
Semantics: Semantics:
"""""""""" """"""""""
This intrinsic returns an opaque pointer value that can be passed to This intrinsic returns an opaque pointer value that can be passed to
:ref:`llvm.stackrestore <int_stackrestore>`. When an :ref:`llvm.stackrestore <int_stackrestore>`. When an
``llvm.stackrestore`` intrinsic is executed with a value saved from ``llvm.stackrestore`` intrinsic is executed with a value saved from
``llvm.stacksave``, it effectively restores the state of the stack to ``llvm.stacksave``, it effectively restores the state of the stack to
the state it was in when the ``llvm.stacksave`` intrinsic executed. In the state it was in when the ``llvm.stacksave`` intrinsic executed. In
practice, this pops any :ref:`alloca <i_alloca>` blocks from the stack that practice, this pops any :ref:`alloca <i_alloca>` blocks from the stack
were allocated after the ``llvm.stacksave`` was executed. that were allocated after the ``llvm.stacksave`` was executed. The
address space should typically be the
:ref:`alloca address space <alloca_addrspace>`.
.. _int_stackrestore: .. _int_stackrestore:
'``llvm.stackrestore``' Intrinsic '``llvm.stackrestore``' Intrinsic
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Syntax: Syntax:
""""""" """""""
:: ::
declare void @llvm.stackrestore(ptr %ptr) declare void @llvm.stackrestore.p0(ptr %ptr)
declare void @llvm.stackrestore.p5(ptr addrspace(5) %ptr)
Overview: Overview:
""""""""" """""""""
The '``llvm.stackrestore``' intrinsic is used to restore the state of The '``llvm.stackrestore``' intrinsic is used to restore the state of
the function stack to the state it was in when the corresponding the function stack to the state it was in when the corresponding
:ref:`llvm.stacksave <int_stacksave>` intrinsic executed. This is :ref:`llvm.stacksave <int_stacksave>` intrinsic executed. This is
useful for implementing language features like scoped automatic variable useful for implementing language features like scoped automatic
sized arrays in C99. variable sized arrays in C99. The address space should typically be
the :ref:`alloca address space <alloca_addrspace>`.
Semantics: Semantics:
"""""""""" """"""""""
See the description for :ref:`llvm.stacksave <int_stacksave>`. See the description for :ref:`llvm.stacksave <int_stacksave>`.
.. _int_get_dynamic_area_offset: .. _int_get_dynamic_area_offset:
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llvm/docs/ReleaseNotes.rst

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* ... * ...
Update on required toolchains to build LLVM Update on required toolchains to build LLVM
------------------------------------------- -------------------------------------------
Changes to the LLVM IR Changes to the LLVM IR
---------------------- ----------------------
* The `llvm.stacksave` and `llvm.stackrestore` intrinsics now use
an overloaded pointer type to support non-0 address spaces.
Changes to LLVM infrastructure Changes to LLVM infrastructure
------------------------------ ------------------------------
Changes to building LLVM Changes to building LLVM
------------------------ ------------------------
Changes to TableGen Changes to TableGen
------------------- -------------------
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llvm/include/llvm/IR/DataLayout.h

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Align getStackAlignment() const { Align getStackAlignment() const {
assert(StackNaturalAlign && "StackNaturalAlign must be defined"); assert(StackNaturalAlign && "StackNaturalAlign must be defined");
return *StackNaturalAlign; return *StackNaturalAlign;
} }
unsigned getAllocaAddrSpace() const { return AllocaAddrSpace; } unsigned getAllocaAddrSpace() const { return AllocaAddrSpace; }
PointerType *getAllocaPtrType(LLVMContext &Ctx) const {
return PointerType::get(Ctx, AllocaAddrSpace);
}
/// Returns the alignment of function pointers, which may or may not be /// Returns the alignment of function pointers, which may or may not be
/// related to the alignment of functions. /// related to the alignment of functions.
/// \see getFunctionPtrAlignType /// \see getFunctionPtrAlignType
MaybeAlign getFunctionPtrAlign() const { return FunctionPtrAlign; } MaybeAlign getFunctionPtrAlign() const { return FunctionPtrAlign; }
/// Return the type of function pointer alignment. /// Return the type of function pointer alignment.
/// \see getFunctionPtrAlign /// \see getFunctionPtrAlign
FunctionPtrAlignType getFunctionPtrAlignType() const { FunctionPtrAlignType getFunctionPtrAlignType() const {
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llvm/include/llvm/IR/IRBuilder.h

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/// Create a call to the vector.insert intrinsic. /// Create a call to the vector.insert intrinsic.
CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec, CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
Value *Idx, const Twine &Name = "") { Value *Idx, const Twine &Name = "") {
return CreateIntrinsic(Intrinsic::vector_insert, return CreateIntrinsic(Intrinsic::vector_insert,
{DstType, SubVec->getType()}, {SrcVec, SubVec, Idx}, {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
nullptr, Name); nullptr, Name);
} }
/// Create a call to llvm.stacksave
CallInst *CreateStackSave(const Twine &Name = "") {
const DataLayout &DL = BB->getModule()->getDataLayout();
return CreateIntrinsic(Intrinsic::stacksave, {DL.getAllocaPtrType(Context)},
{}, nullptr, Name);
}
/// Create a call to llvm.stackrestore
CallInst *CreateStackRestore(Value *Ptr, const Twine &Name = "") {
return CreateIntrinsic(Intrinsic::stackrestore, {Ptr->getType()}, {Ptr},
nullptr, Name);
}
private: private:
/// Create a call to a masked intrinsic with given Id. /// Create a call to a masked intrinsic with given Id.
CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef<Value *> Ops, CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef<Value *> Ops,
ArrayRef<Type *> OverloadedTypes, ArrayRef<Type *> OverloadedTypes,
const Twine &Name = ""); const Twine &Name = "");
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Instruction creation methods: Terminators // Instruction creation methods: Terminators
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llvm/include/llvm/IR/Intrinsics.td

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// after EH tables are generated // after EH tables are generated
def int_seh_try_begin : Intrinsic<[], [], [IntrWriteMem, IntrWillReturn]>; def int_seh_try_begin : Intrinsic<[], [], [IntrWriteMem, IntrWillReturn]>;
def int_seh_try_end : Intrinsic<[], [], [IntrWriteMem, IntrWillReturn]>; def int_seh_try_end : Intrinsic<[], [], [IntrWriteMem, IntrWillReturn]>;
def int_seh_scope_begin : Intrinsic<[], [], [IntrNoMem]>; def int_seh_scope_begin : Intrinsic<[], [], [IntrNoMem]>;
def int_seh_scope_end : Intrinsic<[], [], [IntrNoMem]>; def int_seh_scope_end : Intrinsic<[], [], [IntrNoMem]>;
// Note: we treat stacksave/stackrestore as writemem because we don't otherwise // Note: we treat stacksave/stackrestore as writemem because we don't otherwise
// model their dependencies on allocas. // model their dependencies on allocas.
def int_stacksave : DefaultAttrsIntrinsic<[llvm_ptr_ty]>, def int_stacksave : DefaultAttrsIntrinsic<[llvm_anyptr_ty]>,
ClangBuiltin<"__builtin_stack_save">; ClangBuiltin<"__builtin_stack_save">;
def int_stackrestore : DefaultAttrsIntrinsic<[], [llvm_ptr_ty]>, def int_stackrestore : DefaultAttrsIntrinsic<[], [llvm_anyptr_ty]>,
ClangBuiltin<"__builtin_stack_restore">; ClangBuiltin<"__builtin_stack_restore">;
def int_get_dynamic_area_offset : DefaultAttrsIntrinsic<[llvm_anyint_ty]>; def int_get_dynamic_area_offset : DefaultAttrsIntrinsic<[llvm_anyint_ty]>;
def int_thread_pointer : DefaultAttrsIntrinsic<[llvm_ptr_ty], [], [IntrNoMem]>, def int_thread_pointer : DefaultAttrsIntrinsic<[llvm_ptr_ty], [], [IntrNoMem]>,
ClangBuiltin<"__builtin_thread_pointer">; ClangBuiltin<"__builtin_thread_pointer">;
// IntrInaccessibleMemOrArgMemOnly is a little more pessimistic than strictly // IntrInaccessibleMemOrArgMemOnly is a little more pessimistic than strictly
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llvm/lib/CodeGen/SjLjEHPrepare.cpp

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bool SjLjEHPrepare::runOnFunction(Function &F) { bool SjLjEHPrepare::runOnFunction(Function &F) {
Module &M = *F.getParent(); Module &M = *F.getParent();
RegisterFn = M.getOrInsertFunction( RegisterFn = M.getOrInsertFunction(
"_Unwind_SjLj_Register", Type::getVoidTy(M.getContext()), "_Unwind_SjLj_Register", Type::getVoidTy(M.getContext()),
PointerType::getUnqual(FunctionContextTy)); PointerType::getUnqual(FunctionContextTy));
UnregisterFn = M.getOrInsertFunction( UnregisterFn = M.getOrInsertFunction(
"_Unwind_SjLj_Unregister", Type::getVoidTy(M.getContext()), "_Unwind_SjLj_Unregister", Type::getVoidTy(M.getContext()),
PointerType::getUnqual(FunctionContextTy)); PointerType::getUnqual(FunctionContextTy));
FrameAddrFn = Intrinsic::getDeclaration(
&M, Intrinsic::frameaddress, PointerType *AllocaPtrTy = M.getDataLayout().getAllocaPtrType(M.getContext());
{Type::getInt8PtrTy(M.getContext(),
M.getDataLayout().getAllocaAddrSpace())}); FrameAddrFn =
StackAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::stacksave); Intrinsic::getDeclaration(&M, Intrinsic::frameaddress, {AllocaPtrTy});
StackRestoreFn = Intrinsic::getDeclaration(&M, Intrinsic::stackrestore); StackAddrFn =
Intrinsic::getDeclaration(&M, Intrinsic::stacksave, {AllocaPtrTy});
StackRestoreFn =
Intrinsic::getDeclaration(&M, Intrinsic::stackrestore, {AllocaPtrTy});
BuiltinSetupDispatchFn = BuiltinSetupDispatchFn =
Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_setup_dispatch); Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_setup_dispatch);
LSDAAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_lsda); LSDAAddrFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_lsda);
CallSiteFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_callsite); CallSiteFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_callsite);
FuncCtxFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_functioncontext); FuncCtxFn = Intrinsic::getDeclaration(&M, Intrinsic::eh_sjlj_functioncontext);
bool Res = setupEntryBlockAndCallSites(F); bool Res = setupEntryBlockAndCallSites(F);
return Res; return Res;
} }
Context not available.

llvm/lib/Target/X86/X86WinEHState.cpp

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Type *Int8PtrType = Builder.getInt8PtrTy(); Type *Int8PtrType = Builder.getInt8PtrTy();
Type *Int32Ty = Builder.getInt32Ty(); Type *Int32Ty = Builder.getInt32Ty();
Type *VoidTy = Builder.getVoidTy(); Type *VoidTy = Builder.getVoidTy();
if (Personality == EHPersonality::MSVC_CXX) { if (Personality == EHPersonality::MSVC_CXX) {
RegNodeTy = getCXXEHRegistrationType(); RegNodeTy = getCXXEHRegistrationType();
RegNode = Builder.CreateAlloca(RegNodeTy); RegNode = Builder.CreateAlloca(RegNodeTy);
// SavedESP = llvm.stacksave() // SavedESP = llvm.stacksave()
Value *SP = Builder.CreateCall( Value *SP = Builder.CreateStackSave();
Intrinsic::getDeclaration(TheModule, Intrinsic::stacksave), {});
Builder.CreateStore(SP, Builder.CreateStructGEP(RegNodeTy, RegNode, 0)); Builder.CreateStore(SP, Builder.CreateStructGEP(RegNodeTy, RegNode, 0));
// TryLevel = -1 // TryLevel = -1
StateFieldIndex = 2; StateFieldIndex = 2;
ParentBaseState = -1; ParentBaseState = -1;
insertStateNumberStore(&*Builder.GetInsertPoint(), ParentBaseState); insertStateNumberStore(&*Builder.GetInsertPoint(), ParentBaseState);
// Handler = __ehhandler$F // Handler = __ehhandler$F
Function *Trampoline = generateLSDAInEAXThunk(F); Function *Trampoline = generateLSDAInEAXThunk(F);
Link = Builder.CreateStructGEP(RegNodeTy, RegNode, 1); Link = Builder.CreateStructGEP(RegNodeTy, RegNode, 1);
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// Allocate local structures. // Allocate local structures.
RegNodeTy = getSEHRegistrationType(); RegNodeTy = getSEHRegistrationType();
RegNode = Builder.CreateAlloca(RegNodeTy); RegNode = Builder.CreateAlloca(RegNodeTy);
if (UseStackGuard) if (UseStackGuard)
EHGuardNode = Builder.CreateAlloca(Int32Ty); EHGuardNode = Builder.CreateAlloca(Int32Ty);
// SavedESP = llvm.stacksave() // SavedESP = llvm.stacksave()
Value *SP = Builder.CreateCall( Value *SP = Builder.CreateStackSave();
Intrinsic::getDeclaration(TheModule, Intrinsic::stacksave), {});
Builder.CreateStore(SP, Builder.CreateStructGEP(RegNodeTy, RegNode, 0)); Builder.CreateStore(SP, Builder.CreateStructGEP(RegNodeTy, RegNode, 0));
// TryLevel = -2 / -1 // TryLevel = -2 / -1
StateFieldIndex = 4; StateFieldIndex = 4;
ParentBaseState = UseStackGuard ? -2 : -1; ParentBaseState = UseStackGuard ? -2 : -1;
insertStateNumberStore(&*Builder.GetInsertPoint(), ParentBaseState); insertStateNumberStore(&*Builder.GetInsertPoint(), ParentBaseState);
// ScopeTable = llvm.x86.seh.lsda(F) // ScopeTable = llvm.x86.seh.lsda(F)
Value *LSDA = emitEHLSDA(Builder, F); Value *LSDA = emitEHLSDA(Builder, F);
LSDA = Builder.CreatePtrToInt(LSDA, Int32Ty); LSDA = Builder.CreatePtrToInt(LSDA, Int32Ty);
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llvm/lib/Transforms/Coroutines/CoroFrame.cpp

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return false; return false;
} }
/// Turn each of the given local allocas into a normal (dynamic) alloca /// Turn each of the given local allocas into a normal (dynamic) alloca
/// instruction. /// instruction.
static void lowerLocalAllocas(ArrayRef<CoroAllocaAllocInst*> LocalAllocas, static void lowerLocalAllocas(ArrayRef<CoroAllocaAllocInst*> LocalAllocas,
SmallVectorImpl<Instruction*> &DeadInsts) { SmallVectorImpl<Instruction*> &DeadInsts) {
for (auto *AI : LocalAllocas) { for (auto *AI : LocalAllocas) {
auto M = AI->getModule();
IRBuilder<> Builder(AI); IRBuilder<> Builder(AI);
// Save the stack depth. Try to avoid doing this if the stackrestore // Save the stack depth. Try to avoid doing this if the stackrestore
// is going to immediately precede a return or something. // is going to immediately precede a return or something.
Value *StackSave = nullptr; Value *StackSave = nullptr;
if (localAllocaNeedsStackSave(AI)) if (localAllocaNeedsStackSave(AI))
StackSave = Builder.CreateCall( StackSave = Builder.CreateStackSave();
Intrinsic::getDeclaration(M, Intrinsic::stacksave));
// Allocate memory. // Allocate memory.
auto Alloca = Builder.CreateAlloca(Builder.getInt8Ty(), AI->getSize()); auto Alloca = Builder.CreateAlloca(Builder.getInt8Ty(), AI->getSize());
Alloca->setAlignment(AI->getAlignment()); Alloca->setAlignment(AI->getAlignment());
for (auto *U : AI->users()) { for (auto *U : AI->users()) {
// Replace gets with the allocation. // Replace gets with the allocation.
if (isa<CoroAllocaGetInst>(U)) { if (isa<CoroAllocaGetInst>(U)) {
U->replaceAllUsesWith(Alloca); U->replaceAllUsesWith(Alloca);
// Replace frees with stackrestores. This is safe because // Replace frees with stackrestores. This is safe because
// alloca.alloc is required to obey a stack discipline, although we // alloca.alloc is required to obey a stack discipline, although we
// don't enforce that structurally. // don't enforce that structurally.
} else { } else {
auto FI = cast<CoroAllocaFreeInst>(U); auto FI = cast<CoroAllocaFreeInst>(U);
if (StackSave) { if (StackSave) {
Builder.SetInsertPoint(FI); Builder.SetInsertPoint(FI);
Builder.CreateCall( Builder.CreateStackRestore(StackSave);
Intrinsic::getDeclaration(M, Intrinsic::stackrestore),
StackSave);
} }
} }
DeadInsts.push_back(cast<Instruction>(U)); DeadInsts.push_back(cast<Instruction>(U));
} }
DeadInsts.push_back(AI); DeadInsts.push_back(AI);
} }
} }
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llvm/lib/Transforms/IPO/GlobalOpt.cpp

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assert((isa<CallInst>(CB) || isa<InvokeInst>(CB)) && assert((isa<CallInst>(CB) || isa<InvokeInst>(CB)) &&
"Unknown indirect call type"); "Unknown indirect call type");
CallBase *NewCB = CallBase::Create(CB, OpBundles, CB); CallBase *NewCB = CallBase::Create(CB, OpBundles, CB);
CB->replaceAllUsesWith(NewCB); CB->replaceAllUsesWith(NewCB);
NewCB->takeName(CB); NewCB->takeName(CB);
CB->eraseFromParent(); CB->eraseFromParent();
Builder.SetInsertPoint(PreallocatedSetup); Builder.SetInsertPoint(PreallocatedSetup);
auto *StackSave = auto *StackSave = Builder.CreateStackSave();
Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::stacksave));
Builder.SetInsertPoint(NewCB->getNextNonDebugInstruction()); Builder.SetInsertPoint(NewCB->getNextNonDebugInstruction());
Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::stackrestore), Builder.CreateStackRestore(StackSave);
StackSave);
// Replace @llvm.call.preallocated.arg() with alloca. // Replace @llvm.call.preallocated.arg() with alloca.
// Cannot modify users() while iterating over it, so make a copy. // Cannot modify users() while iterating over it, so make a copy.
// @llvm.call.preallocated.arg() can be called with the same index multiple // @llvm.call.preallocated.arg() can be called with the same index multiple
// times. So for each @llvm.call.preallocated.arg(), we see if we have // times. So for each @llvm.call.preallocated.arg(), we see if we have
// already created a Value* for the index, and if not, create an alloca and // already created a Value* for the index, and if not, create an alloca and
// bitcast right after the @llvm.call.preallocated.setup() so that it // bitcast right after the @llvm.call.preallocated.setup() so that it
// dominates all uses. // dominates all uses.
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llvm/lib/Transforms/Utils/InlineFunction.cpp

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IRBuilder<>(RI).CreateLifetimeEnd(AI, AllocaSize); IRBuilder<>(RI).CreateLifetimeEnd(AI, AllocaSize);
} }
} }
} }
// If the inlined code contained dynamic alloca instructions, wrap the inlined // If the inlined code contained dynamic alloca instructions, wrap the inlined
// code with llvm.stacksave/llvm.stackrestore intrinsics. // code with llvm.stacksave/llvm.stackrestore intrinsics.
if (InlinedFunctionInfo.ContainsDynamicAllocas) { if (InlinedFunctionInfo.ContainsDynamicAllocas) {
Module *M = Caller->getParent();
// Get the two intrinsics we care about.
Function *StackSave = Intrinsic::getDeclaration(M, Intrinsic::stacksave);
Function *StackRestore=Intrinsic::getDeclaration(M,Intrinsic::stackrestore);
// Insert the llvm.stacksave. // Insert the llvm.stacksave.
CallInst *SavedPtr = IRBuilder<>(&*FirstNewBlock, FirstNewBlock->begin()) CallInst *SavedPtr = IRBuilder<>(&*FirstNewBlock, FirstNewBlock->begin())
.CreateCall(StackSave, {}, "savedstack"); .CreateStackSave("savedstack");
// Insert a call to llvm.stackrestore before any return instructions in the // Insert a call to llvm.stackrestore before any return instructions in the
// inlined function. // inlined function.
for (ReturnInst *RI : Returns) { for (ReturnInst *RI : Returns) {
// Don't insert llvm.stackrestore calls between a musttail or deoptimize // Don't insert llvm.stackrestore calls between a musttail or deoptimize
// call and a return. The return will restore the stack pointer. // call and a return. The return will restore the stack pointer.
if (InlinedMustTailCalls && RI->getParent()->getTerminatingMustTailCall()) if (InlinedMustTailCalls && RI->getParent()->getTerminatingMustTailCall())
continue; continue;
if (InlinedDeoptimizeCalls && RI->getParent()->getTerminatingDeoptimizeCall()) if (InlinedDeoptimizeCalls && RI->getParent()->getTerminatingDeoptimizeCall())
continue; continue;
IRBuilder<>(RI).CreateCall(StackRestore, SavedPtr); IRBuilder<>(RI).CreateStackRestore(SavedPtr);
} }
} }
// If we are inlining for an invoke instruction, we must make sure to rewrite // If we are inlining for an invoke instruction, we must make sure to rewrite
// any call instructions into invoke instructions. This is sensitive to which // any call instructions into invoke instructions. This is sensitive to which
// funclet pads were top-level in the inlinee, so must be done before // funclet pads were top-level in the inlinee, so must be done before
// rewriting the "parent pad" links. // rewriting the "parent pad" links.
if (auto *II = dyn_cast<InvokeInst>(&CB)) { if (auto *II = dyn_cast<InvokeInst>(&CB)) {
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llvm/test/Bitcode/compatibility-3.6.ll

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call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0) ; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0)
%stack = call i8* @llvm.stacksave() %stack = call i8* @llvm.stacksave()
; CHECK: %stack = call ptr @llvm.stacksave() ; CHECK: %stack = call ptr @llvm.stacksave.p0()
call void @llvm.stackrestore(i8* %stack) call void @llvm.stackrestore(i8* %stack)
; CHECK: call void @llvm.stackrestore(ptr %stack) ; CHECK: call void @llvm.stackrestore.p0(ptr %stack)
call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0) call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0)
; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0) ; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0)
call void @llvm.pcmarker(i32 1) call void @llvm.pcmarker(i32 1)
; CHECK: call void @llvm.pcmarker(i32 1) ; CHECK: call void @llvm.pcmarker(i32 1)
call i64 @llvm.readcyclecounter() call i64 @llvm.readcyclecounter()
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llvm/test/Bitcode/compatibility-3.7.ll

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call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0) ; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0)
%stack = call i8* @llvm.stacksave() %stack = call i8* @llvm.stacksave()
; CHECK: %stack = call ptr @llvm.stacksave() ; CHECK: %stack = call ptr @llvm.stacksave.p0()
call void @llvm.stackrestore(i8* %stack) call void @llvm.stackrestore(i8* %stack)
; CHECK: call void @llvm.stackrestore(ptr %stack) ; CHECK: call void @llvm.stackrestore.p0(ptr %stack)
call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0) call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0)
; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0) ; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0)
call void @llvm.pcmarker(i32 1) call void @llvm.pcmarker(i32 1)
; CHECK: call void @llvm.pcmarker(i32 1) ; CHECK: call void @llvm.pcmarker(i32 1)
call i64 @llvm.readcyclecounter() call i64 @llvm.readcyclecounter()
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llvm/test/Bitcode/compatibility-3.8.ll

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call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0) ; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0)
%stack = call i8* @llvm.stacksave() %stack = call i8* @llvm.stacksave()
; CHECK: %stack = call ptr @llvm.stacksave() ; CHECK: %stack = call ptr @llvm.stacksave.p0()
call void @llvm.stackrestore(i8* %stack) call void @llvm.stackrestore(i8* %stack)
; CHECK: call void @llvm.stackrestore(ptr %stack) ; CHECK: call void @llvm.stackrestore.p0(ptr %stack)
call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0) call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0)
; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0) ; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0)
call void @llvm.pcmarker(i32 1) call void @llvm.pcmarker(i32 1)
; CHECK: call void @llvm.pcmarker(i32 1) ; CHECK: call void @llvm.pcmarker(i32 1)
call i64 @llvm.readcyclecounter() call i64 @llvm.readcyclecounter()
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llvm/test/Bitcode/compatibility-3.9.ll

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call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0) ; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0)
%stack = call i8* @llvm.stacksave() %stack = call i8* @llvm.stacksave()
; CHECK: %stack = call ptr @llvm.stacksave() ; CHECK: %stack = call ptr @llvm.stacksave.p0()
call void @llvm.stackrestore(i8* %stack) call void @llvm.stackrestore(i8* %stack)
; CHECK: call void @llvm.stackrestore(ptr %stack) ; CHECK: call void @llvm.stackrestore.p0(ptr %stack)
call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0) call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0)
; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0) ; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0)
call void @llvm.pcmarker(i32 1) call void @llvm.pcmarker(i32 1)
; CHECK: call void @llvm.pcmarker(i32 1) ; CHECK: call void @llvm.pcmarker(i32 1)
call i64 @llvm.readcyclecounter() call i64 @llvm.readcyclecounter()
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llvm/test/Bitcode/compatibility-4.0.ll

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call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0) ; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0)
%stack = call i8* @llvm.stacksave() %stack = call i8* @llvm.stacksave()
; CHECK: %stack = call ptr @llvm.stacksave() ; CHECK: %stack = call ptr @llvm.stacksave.p0()
call void @llvm.stackrestore(i8* %stack) call void @llvm.stackrestore(i8* %stack)
; CHECK: call void @llvm.stackrestore(ptr %stack) ; CHECK: call void @llvm.stackrestore.p0(ptr %stack)
call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0) call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0)
; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0) ; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0)
call void @llvm.pcmarker(i32 1) call void @llvm.pcmarker(i32 1)
; CHECK: call void @llvm.pcmarker(i32 1) ; CHECK: call void @llvm.pcmarker(i32 1)
call i64 @llvm.readcyclecounter() call i64 @llvm.readcyclecounter()
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llvm/test/Bitcode/compatibility-5.0.ll

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call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0) ; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0)
%stack = call i8* @llvm.stacksave() %stack = call i8* @llvm.stacksave()
; CHECK: %stack = call ptr @llvm.stacksave() ; CHECK: %stack = call ptr @llvm.stacksave.p0()
call void @llvm.stackrestore(i8* %stack) call void @llvm.stackrestore(i8* %stack)
; CHECK: call void @llvm.stackrestore(ptr %stack) ; CHECK: call void @llvm.stackrestore.p0(ptr %stack)
call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0) call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0)
; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0) ; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0)
call void @llvm.pcmarker(i32 1) call void @llvm.pcmarker(i32 1)
; CHECK: call void @llvm.pcmarker(i32 1) ; CHECK: call void @llvm.pcmarker(i32 1)
call i64 @llvm.readcyclecounter() call i64 @llvm.readcyclecounter()
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llvm/test/Bitcode/compatibility-6.0.ll

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call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0) ; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0)
%stack = call i8* @llvm.stacksave() %stack = call i8* @llvm.stacksave()
; CHECK: %stack = call ptr @llvm.stacksave() ; CHECK: %stack = call ptr @llvm.stacksave.p0()
call void @llvm.stackrestore(i8* %stack) call void @llvm.stackrestore(i8* %stack)
; CHECK: call void @llvm.stackrestore(ptr %stack) ; CHECK: call void @llvm.stackrestore.p0(ptr %stack)
call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0) call void @llvm.prefetch(i8* %stack, i32 0, i32 3, i32 0)
; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0) ; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0)
call void @llvm.pcmarker(i32 1) call void @llvm.pcmarker(i32 1)
; CHECK: call void @llvm.pcmarker(i32 1) ; CHECK: call void @llvm.pcmarker(i32 1)
call i64 @llvm.readcyclecounter() call i64 @llvm.readcyclecounter()
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llvm/test/Bitcode/compatibility.ll

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call i64 @llvm.read_register.i64(metadata !10) call i64 @llvm.read_register.i64(metadata !10)
; CHECK: call i64 @llvm.read_register.i64(metadata !10) ; CHECK: call i64 @llvm.read_register.i64(metadata !10)
call void @llvm.write_register.i32(metadata !10, i32 0) call void @llvm.write_register.i32(metadata !10, i32 0)
; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0) ; CHECK: call void @llvm.write_register.i32(metadata !10, i32 0)
call void @llvm.write_register.i64(metadata !10, i64 0) call void @llvm.write_register.i64(metadata !10, i64 0)
; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0) ; CHECK: call void @llvm.write_register.i64(metadata !10, i64 0)
%stack = call ptr @llvm.stacksave() %stack = call ptr @llvm.stacksave()
; CHECK: %stack = call ptr @llvm.stacksave() ; CHECK: %stack = call ptr @llvm.stacksave.p0()
call void @llvm.stackrestore(ptr %stack) call void @llvm.stackrestore(ptr %stack)
; CHECK: call void @llvm.stackrestore(ptr %stack) ; CHECK: call void @llvm.stackrestore.p0(ptr %stack)
call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0) call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0)
; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0) ; CHECK: call void @llvm.prefetch.p0(ptr %stack, i32 0, i32 3, i32 0)
call void @llvm.pcmarker(i32 1) call void @llvm.pcmarker(i32 1)
; CHECK: call void @llvm.pcmarker(i32 1) ; CHECK: call void @llvm.pcmarker(i32 1)
call i64 @llvm.readcyclecounter() call i64 @llvm.readcyclecounter()
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llvm/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s
; This is just an arbitrary intrinisic that shouldn't ever need to be ; This is just an arbitrary intrinisic that shouldn't be
; handled to ensure it doesn't crash. ; handled to ensure it doesn't crash.
declare void @llvm.stackrestore(ptr) #2 declare void @llvm.stackrestore.p5(ptr addrspace(5)) #2
; CHECK-LABEL: @try_promote_unhandled_intrinsic( ; CHECK-LABEL: @try_promote_unhandled_intrinsic(
; CHECK: alloca ; CHECK: alloca
; CHECK: call void @llvm.stackrestore(ptr %tmp) ; CHECK: call void @llvm.stackrestore.p5(ptr addrspace(5) %tmp)
define amdgpu_kernel void @try_promote_unhandled_intrinsic(ptr addrspace(1) %arg) #2 { define amdgpu_kernel void @try_promote_unhandled_intrinsic(ptr addrspace(1) %arg) #2 {
bb: bb:
%tmp = alloca i32, align 4 %tmp = alloca i32, addrspace(5)
%tmp2 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1 %tmp2 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1
%tmp3 = load i32, ptr addrspace(1) %tmp2 %tmp3 = load i32, ptr addrspace(1) %tmp2
store i32 %tmp3, ptr %tmp store i32 %tmp3, ptr addrspace(5) %tmp
call void @llvm.stackrestore(ptr %tmp) call void @llvm.stackrestore.p5(ptr addrspace(5) %tmp)
ret void ret void
} }
attributes #0 = { argmemonly nounwind } attributes #0 = { argmemonly nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind } attributes #2 = { nounwind }

llvm/test/Other/force-opaque-ptrs.ll

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; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; ;
unreachable unreachable
} }
define void @remangle_intrinsic() { define void @remangle_intrinsic() {
; CHECK-LABEL: define {{[^@]+}}@remangle_intrinsic() { ; CHECK-LABEL: define {{[^@]+}}@remangle_intrinsic() {
; CHECK-NEXT: [[A:%.*]] = alloca ptr, align 8 ; CHECK-NEXT: [[A:%.*]] = alloca ptr, align 8
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: call void @llvm.stackprotector(ptr null, ptr [[A]]) ; CHECK-NEXT: call void @llvm.stackprotector(ptr null, ptr [[A]])
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.masked.expandload.v2i64(ptr null, <2 x i1> zeroinitializer, <2 x i64> zeroinitializer) ; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.masked.expandload.v2i64(ptr null, <2 x i1> zeroinitializer, <2 x i64> zeroinitializer)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%a = alloca ptr %a = alloca ptr
call ptr @llvm.stacksave() call ptr @llvm.stacksave()
call void @llvm.stackprotector(ptr null, ptr %a) call void @llvm.stackprotector(ptr null, ptr %a)
call <2 x i64> @llvm.masked.expandload.v2i64(ptr null, <2 x i1> zeroinitializer, <2 x i64> zeroinitializer) call <2 x i64> @llvm.masked.expandload.v2i64(ptr null, <2 x i1> zeroinitializer, <2 x i64> zeroinitializer)
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llvm/test/Transforms/ArgumentPromotion/X86/thiscall.ll

Show All 40 Linesentry:
call void @ext(<{ %struct.a }>* inalloca(<{ %struct.a }>) %argmem) call void @ext(<{ %struct.a }>* inalloca(<{ %struct.a }>) %argmem)
ret void ret void
} }
; This is here to ensure @internalfun is live. ; This is here to ensure @internalfun is live.
define void @exportedfun(ptr %a) { define void @exportedfun(ptr %a) {
; ARGPROMOTION-LABEL: define {{[^@]+}}@exportedfun ; ARGPROMOTION-LABEL: define {{[^@]+}}@exportedfun
; ARGPROMOTION-SAME: (ptr [[A:%.*]]) { ; ARGPROMOTION-SAME: (ptr [[A:%.*]]) {
; ARGPROMOTION-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave() ; ARGPROMOTION-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave.p0()
; ARGPROMOTION-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4 ; ARGPROMOTION-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4
; ARGPROMOTION-NEXT: call x86_thiscallcc void @internalfun(ptr [[A]], ptr inalloca(<{ [[STRUCT_A]] }>) [[ARGMEM]]) ; ARGPROMOTION-NEXT: call x86_thiscallcc void @internalfun(ptr [[A]], ptr inalloca(<{ [[STRUCT_A]] }>) [[ARGMEM]])
; ARGPROMOTION-NEXT: call void @llvm.stackrestore(ptr [[INALLOCA_SAVE]]) ; ARGPROMOTION-NEXT: call void @llvm.stackrestore.p0(ptr [[INALLOCA_SAVE]])
; ARGPROMOTION-NEXT: ret void ; ARGPROMOTION-NEXT: ret void
; ;
; GLOBALOPT_ARGPROMOTION-LABEL: define {{[^@]+}}@exportedfun ; GLOBALOPT_ARGPROMOTION-LABEL: define {{[^@]+}}@exportedfun
; GLOBALOPT_ARGPROMOTION-SAME: (ptr [[A:%.*]]) local_unnamed_addr { ; GLOBALOPT_ARGPROMOTION-SAME: (ptr [[A:%.*]]) local_unnamed_addr {
; GLOBALOPT_ARGPROMOTION-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave() ; GLOBALOPT_ARGPROMOTION-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave.p0()
; GLOBALOPT_ARGPROMOTION-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4 ; GLOBALOPT_ARGPROMOTION-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4
; GLOBALOPT_ARGPROMOTION-NEXT: call fastcc void @internalfun(ptr [[ARGMEM]]) ; GLOBALOPT_ARGPROMOTION-NEXT: call fastcc void @internalfun(ptr [[ARGMEM]])
; GLOBALOPT_ARGPROMOTION-NEXT: call void @llvm.stackrestore(ptr [[INALLOCA_SAVE]]) ; GLOBALOPT_ARGPROMOTION-NEXT: call void @llvm.stackrestore.p0(ptr [[INALLOCA_SAVE]])
; GLOBALOPT_ARGPROMOTION-NEXT: ret void ; GLOBALOPT_ARGPROMOTION-NEXT: ret void
; ;
%inalloca.save = tail call ptr @llvm.stacksave() %inalloca.save = tail call ptr @llvm.stacksave()
%argmem = alloca inalloca <{ %struct.a }>, align 4 %argmem = alloca inalloca <{ %struct.a }>, align 4
call x86_thiscallcc void @internalfun(ptr %a, <{ %struct.a }>* inalloca(<{ %struct.a }>) %argmem) call x86_thiscallcc void @internalfun(ptr %a, <{ %struct.a }>* inalloca(<{ %struct.a }>) %argmem)
call void @llvm.stackrestore(ptr %inalloca.save) call void @llvm.stackrestore(ptr %inalloca.save)
ret void ret void
} }
declare x86_thiscallcc ptr @copy_ctor(ptr returned, ptr dereferenceable(1)) declare x86_thiscallcc ptr @copy_ctor(ptr returned, ptr dereferenceable(1))
declare void @ext(<{ %struct.a }>* inalloca(<{ %struct.a }>)) declare void @ext(<{ %struct.a }>* inalloca(<{ %struct.a }>))
declare ptr @llvm.stacksave() declare ptr @llvm.stacksave()
declare void @llvm.stackrestore(ptr) declare void @llvm.stackrestore(ptr)

llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll

Show All 26 Linesentry:
call void @ext(ptr inalloca(<{ %struct.a }>) %argmem) call void @ext(ptr inalloca(<{ %struct.a }>) %argmem)
ret void ret void
} }
; This is here to ensure @internalfun is live. ; This is here to ensure @internalfun is live.
define void @exportedfun(ptr %a) { define void @exportedfun(ptr %a) {
; TUNIT-LABEL: define {{[^@]+}}@exportedfun ; TUNIT-LABEL: define {{[^@]+}}@exportedfun
; TUNIT-SAME: (ptr nocapture nofree readnone [[A:%.*]]) { ; TUNIT-SAME: (ptr nocapture nofree readnone [[A:%.*]]) {
; TUNIT-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave() #[[ATTR1:[0-9]+]] ; TUNIT-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave.p0() #[[ATTR1:[0-9]+]]
; TUNIT-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4 ; TUNIT-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4
; TUNIT-NEXT: call x86_thiscallcc void @internalfun(ptr noalias nocapture nofree readnone undef, ptr noundef nonnull inalloca(<{ [[STRUCT_A]] }>) align 4 dereferenceable(1) [[ARGMEM]]) ; TUNIT-NEXT: call x86_thiscallcc void @internalfun(ptr noalias nocapture nofree readnone undef, ptr noundef nonnull inalloca(<{ [[STRUCT_A]] }>) align 4 dereferenceable(1) [[ARGMEM]])
; TUNIT-NEXT: call void @llvm.stackrestore(ptr nofree [[INALLOCA_SAVE]]) ; TUNIT-NEXT: call void @llvm.stackrestore.p0(ptr nofree [[INALLOCA_SAVE]])
; TUNIT-NEXT: ret void ; TUNIT-NEXT: ret void
; ;
; CGSCC-LABEL: define {{[^@]+}}@exportedfun ; CGSCC-LABEL: define {{[^@]+}}@exportedfun
; CGSCC-SAME: (ptr nocapture nofree readnone [[A:%.*]]) { ; CGSCC-SAME: (ptr nocapture nofree readnone [[A:%.*]]) {
; CGSCC-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave() #[[ATTR1:[0-9]+]] ; CGSCC-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave.p0() #[[ATTR1:[0-9]+]]
; CGSCC-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4 ; CGSCC-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4
; CGSCC-NEXT: call x86_thiscallcc void @internalfun(ptr noalias nocapture nofree readnone [[A]], ptr noundef nonnull inalloca(<{ [[STRUCT_A]] }>) align 4 dereferenceable(1) [[ARGMEM]]) ; CGSCC-NEXT: call x86_thiscallcc void @internalfun(ptr noalias nocapture nofree readnone [[A]], ptr noundef nonnull inalloca(<{ [[STRUCT_A]] }>) align 4 dereferenceable(1) [[ARGMEM]])
; CGSCC-NEXT: call void @llvm.stackrestore(ptr nofree [[INALLOCA_SAVE]]) ; CGSCC-NEXT: call void @llvm.stackrestore.p0(ptr nofree [[INALLOCA_SAVE]])
; CGSCC-NEXT: ret void ; CGSCC-NEXT: ret void
; ;
%inalloca.save = tail call ptr @llvm.stacksave() %inalloca.save = tail call ptr @llvm.stacksave()
%argmem = alloca inalloca <{ %struct.a }>, align 4 %argmem = alloca inalloca <{ %struct.a }>, align 4
call x86_thiscallcc void @internalfun(ptr %a, ptr inalloca(<{ %struct.a }>) %argmem) call x86_thiscallcc void @internalfun(ptr %a, ptr inalloca(<{ %struct.a }>) %argmem)
call void @llvm.stackrestore(ptr %inalloca.save) call void @llvm.stackrestore(ptr %inalloca.save)
ret void ret void
} }
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llvm/test/Transforms/GVNHoist/hoist-pr28606.ll

Show All 9 Lines
; Check that we don't clone the %x alloca and insert it in the live range of ; Check that we don't clone the %x alloca and insert it in the live range of
; %argmem, which would break the inalloca contract. ; %argmem, which would break the inalloca contract.
define void @test(i1 %b) { define void @test(i1 %b) {
; CHECK-LABEL: @test( ; CHECK-LABEL: @test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[X:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[X:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[INALLOCA_SAVE:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[INALLOCA_SAVE:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_S:%.*]] }>, align 4 ; CHECK-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_S:%.*]] }>, align 4
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARGMEM]], i32 0, i32 1 ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARGMEM]], i32 0, i32 1
; CHECK-NEXT: store ptr [[X]], ptr [[TMP1]], align 4 ; CHECK-NEXT: store ptr [[X]], ptr [[TMP0]], align 4
; CHECK-NEXT: br i1 [[B:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK-NEXT: br i1 [[B:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]]
; CHECK: true: ; CHECK: true:
; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARGMEM]], i32 0, i32 1 ; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARGMEM]], i32 0, i32 1
; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK-NEXT: br label [[EXIT:%.*]]
; CHECK: false: ; CHECK: false:
; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARGMEM]], i32 0, i32 1 ; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARGMEM]], i32 0, i32 1
; CHECK-NEXT: br label [[EXIT]] ; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: call void @f(ptr inalloca(<{ [[STRUCT_S]] }>) [[ARGMEM]]) ; CHECK-NEXT: call void @f(ptr inalloca(<{ [[STRUCT_S]] }>) [[ARGMEM]])
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[INALLOCA_SAVE]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[INALLOCA_SAVE]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%x = alloca i8 %x = alloca i8
%inalloca.save = call ptr @llvm.stacksave() %inalloca.save = call ptr @llvm.stacksave()
%argmem = alloca inalloca <{ %struct.S }>, align 4 %argmem = alloca inalloca <{ %struct.S }>, align 4
br i1 %b, label %true, label %false br i1 %b, label %true, label %false
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llvm/test/Transforms/GlobalOpt/preallocated.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines;
%rv = load i32, ptr %a %rv = load i32, ptr %a
ret i32 %rv ret i32 %rv
} }
declare void @foo(ptr) declare void @foo(ptr)
define i32 @call_preallocated_multiple_args() { define i32 @call_preallocated_multiple_args() {
; CHECK-LABEL: define {{[^@]+}}@call_preallocated_multiple_args() local_unnamed_addr { ; CHECK-LABEL: define {{[^@]+}}@call_preallocated_multiple_args() local_unnamed_addr {
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[PAARG:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[PAARG:%.*]] = alloca i32, align 4
; CHECK-NEXT: call void @foo(ptr [[PAARG]]) ; CHECK-NEXT: call void @foo(ptr [[PAARG]])
; CHECK-NEXT: call void @foo(ptr [[PAARG]]) ; CHECK-NEXT: call void @foo(ptr [[PAARG]])
; CHECK-NEXT: call void @foo(ptr [[PAARG]]) ; CHECK-NEXT: call void @foo(ptr [[PAARG]])
; CHECK-NEXT: [[R:%.*]] = call fastcc i32 @preallocated(ptr [[PAARG]]) ; CHECK-NEXT: [[R:%.*]] = call fastcc i32 @preallocated(ptr [[PAARG]])
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[TMP1]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP1]])
; CHECK-NEXT: ret i32 [[R]] ; CHECK-NEXT: ret i32 [[R]]
; ;
%c = call token @llvm.call.preallocated.setup(i32 1) %c = call token @llvm.call.preallocated.setup(i32 1)
%a1 = call ptr @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32) %a1 = call ptr @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32)
call void @foo(ptr %a1) call void @foo(ptr %a1)
%a2 = call ptr @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32) %a2 = call ptr @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32)
call void @foo(ptr %a2) call void @foo(ptr %a2)
%a3 = call ptr @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32) %a3 = call ptr @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32)
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llvm/test/Transforms/IndVarSimplify/sink-alloca.ll

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; Indvars shouldn't sink the first alloca between the stacksave and stackrestore ; Indvars shouldn't sink the first alloca between the stacksave and stackrestore
; intrinsics. ; intrinsics.
declare ptr @a(...) declare ptr @a(...)
declare ptr @llvm.stacksave() nounwind declare ptr @llvm.stacksave() nounwind
declare void @llvm.stackrestore(ptr) nounwind declare void @llvm.stackrestore(ptr) nounwind
define void @h(i64 %n) nounwind uwtable ssp { define void @h(i64 %n) nounwind uwtable ssp {
; CHECK: entry: ; CHECK: entry:
; CHECK-NEXT: %vla = alloca ptr ; CHECK-NEXT: %vla = alloca ptr
; CHECK-NEXT: %savedstack = call ptr @llvm.stacksave() ; CHECK-NEXT: %savedstack = call ptr @llvm.stacksave.p0()
entry: entry:
%vla = alloca ptr, i64 %n, align 16 %vla = alloca ptr, i64 %n, align 16
%savedstack = call ptr @llvm.stacksave() nounwind %savedstack = call ptr @llvm.stacksave() nounwind
%vla.i = alloca ptr, i64 %n, align 16 %vla.i = alloca ptr, i64 %n, align 16
br label %for.body.i br label %for.body.i
for.body.i: for.body.i:
%indvars.iv37.i = phi i64 [ %indvars.iv.next38.i, %for.body.i ], [ 0, %entry ] %indvars.iv37.i = phi i64 [ %indvars.iv.next38.i, %for.body.i ], [ 0, %entry ]
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llvm/test/Transforms/Inline/dynamic-alloca-simplified-large.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define void @caller2_below_threshold(ptr %p1, i1 %b) { define void @caller2_below_threshold(ptr %p1, i1 %b) {
; CHECK-LABEL: define {{[^@]+}}@caller2_below_threshold ; CHECK-LABEL: define {{[^@]+}}@caller2_below_threshold
; CHECK-SAME: (ptr [[P1:%.*]], i1 [[B:%.*]]) { ; CHECK-SAME: (ptr [[P1:%.*]], i1 [[B:%.*]]) {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[VLA_I:%.*]] = alloca float, i64 15000, align 16 ; CHECK-NEXT: [[VLA_I:%.*]] = alloca float, i64 15000, align 16
; CHECK-NEXT: [[COND:%.*]] = icmp eq i1 [[B]], true ; CHECK-NEXT: [[COND:%.*]] = icmp eq i1 [[B]], true
; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[SPLIT:%.*]] ; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[SPLIT:%.*]]
; CHECK: split: ; CHECK: split:
; CHECK-NEXT: [[SAVEDSTACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[SAVEDSTACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 60000, ptr [[VLA_I]]) ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 60000, ptr [[VLA_I]])
; CHECK-NEXT: call void @extern_call(ptr nonnull [[VLA_I]]) #[[ATTR3]] ; CHECK-NEXT: call void @extern_call(ptr nonnull [[VLA_I]]) #[[ATTR3]]
; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 60000, ptr [[VLA_I]]) ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 60000, ptr [[VLA_I]])
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[SAVEDSTACK]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[SAVEDSTACK]])
; CHECK-NEXT: br label [[EXIT]] ; CHECK-NEXT: br label [[EXIT]]
; CHECK: exit: ; CHECK: exit:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%cond = icmp eq i1 %b, true %cond = icmp eq i1 %b, true
br i1 %cond, label %exit, label %split br i1 %cond, label %exit, label %split
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Linesreturn: ; preds = %if.end, %if.then
%retval.0 = phi ptr [ %0, %if.then ], [ %call, %if.end ] %retval.0 = phi ptr [ %0, %if.then ], [ %call, %if.end ]
ret ptr %retval.0 ret ptr %retval.0
} }
define ptr @test_stack_allocate_always(i32 %size) { define ptr @test_stack_allocate_always(i32 %size) {
; CHECK-LABEL: define {{[^@]+}}@test_stack_allocate_always ; CHECK-LABEL: define {{[^@]+}}@test_stack_allocate_always
; CHECK-SAME: (i32 [[SIZE:%.*]]) { ; CHECK-SAME: (i32 [[SIZE:%.*]]) {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SAVEDSTACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[SAVEDSTACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[CMP_I:%.*]] = icmp ult i32 [[SIZE]], 100 ; CHECK-NEXT: [[CMP_I:%.*]] = icmp ult i32 [[SIZE]], 100
; CHECK-NEXT: [[CONV_I:%.*]] = zext i32 [[SIZE]] to i64 ; CHECK-NEXT: [[CONV_I:%.*]] = zext i32 [[SIZE]] to i64
; CHECK-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]] ; CHECK-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]]
; CHECK: if.then.i: ; CHECK: if.then.i:
; CHECK-NEXT: [[TMP0:%.*]] = alloca i8, i64 [[CONV_I]], align 8 ; CHECK-NEXT: [[TMP0:%.*]] = alloca i8, i64 [[CONV_I]], align 8
; CHECK-NEXT: br label [[STACK_ALLOCATE_EXIT:%.*]] ; CHECK-NEXT: br label [[STACK_ALLOCATE_EXIT:%.*]]
; CHECK: if.end.i: ; CHECK: if.end.i:
; CHECK-NEXT: [[CALL_I:%.*]] = tail call ptr @malloc(i64 [[CONV_I]]) #[[ATTR3]] ; CHECK-NEXT: [[CALL_I:%.*]] = tail call ptr @malloc(i64 [[CONV_I]]) #[[ATTR3]]
; CHECK-NEXT: br label [[STACK_ALLOCATE_EXIT]] ; CHECK-NEXT: br label [[STACK_ALLOCATE_EXIT]]
; CHECK: stack_allocate.exit: ; CHECK: stack_allocate.exit:
; CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi ptr [ [[TMP0]], [[IF_THEN_I]] ], [ [[CALL_I]], [[IF_END_I]] ] ; CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi ptr [ [[TMP0]], [[IF_THEN_I]] ], [ [[CALL_I]], [[IF_END_I]] ]
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[SAVEDSTACK]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[SAVEDSTACK]])
; CHECK-NEXT: ret ptr [[RETVAL_0_I]] ; CHECK-NEXT: ret ptr [[RETVAL_0_I]]
; ;
entry: entry:
%call = tail call ptr @stack_allocate(i32 %size) %call = tail call ptr @stack_allocate(i32 %size)
ret ptr %call ret ptr %call
} }
declare void @extern_call(ptr) declare void @extern_call(ptr)
attributes #1 = { argmemonly nounwind willreturn writeonly } attributes #1 = { argmemonly nounwind willreturn writeonly }
attributes #2 = { alwaysinline } attributes #2 = { alwaysinline }
attributes #3 = { nounwind } attributes #3 = { nounwind }

llvm/test/Transforms/Inline/inalloca-not-static.ll

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; Function Attrs: alwaysinline inlinehint nounwind ; Function Attrs: alwaysinline inlinehint nounwind
define internal void @h(ptr inalloca(<{ %struct.Foo }>)) alwaysinline { define internal void @h(ptr inalloca(<{ %struct.Foo }>)) alwaysinline {
entry: entry:
call x86_thiscallcc void @"\01??1Foo@@QAE@XZ"(ptr %0) call x86_thiscallcc void @"\01??1Foo@@QAE@XZ"(ptr %0)
ret void ret void
} }
; CHECK: define void @f() ; CHECK: define void @f()
; CHECK: %[[STACKSAVE:.*]] = call ptr @llvm.stacksave() ; CHECK: %[[STACKSAVE:.*]] = call ptr @llvm.stacksave.p0()
; CHECK: %[[ARGMEM:.*]] = alloca inalloca <{ %struct.Foo }>, align 4 ; CHECK: %[[ARGMEM:.*]] = alloca inalloca <{ %struct.Foo }>, align 4
; CHECK: %[[CALL:.*]] = call x86_thiscallcc ptr @"\01??0Foo@@QAE@XZ"(ptr %[[ARGMEM]]) ; CHECK: %[[CALL:.*]] = call x86_thiscallcc ptr @"\01??0Foo@@QAE@XZ"(ptr %[[ARGMEM]])
; CHECK: call x86_thiscallcc void @"\01??1Foo@@QAE@XZ"(ptr %[[ARGMEM]]) ; CHECK: call x86_thiscallcc void @"\01??1Foo@@QAE@XZ"(ptr %[[ARGMEM]])
; CHECK: call void @llvm.stackrestore(ptr %[[STACKSAVE]]) ; CHECK: call void @llvm.stackrestore.p0(ptr %[[STACKSAVE]])
; CHECK: ret void ; CHECK: ret void

llvm/test/Transforms/Inline/inline-tail.ll

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Linesdefine internal void @test_dynalloca_b(ptr byval(i32) %p, i32 %n) alwaysinline {
call void @escape(ptr %buf) ; escape it call void @escape(ptr %buf) ; escape it
musttail call void @test_dynalloca_c(ptr byval(i32) %p, i32 %n) musttail call void @test_dynalloca_c(ptr byval(i32) %p, i32 %n)
ret void ret void
} }
define void @test_dynalloca_a(ptr byval(i32) %p, i32 %n) { define void @test_dynalloca_a(ptr byval(i32) %p, i32 %n) {
; CHECK-LABEL: define void @test_dynalloca_a ; CHECK-LABEL: define void @test_dynalloca_a
; CHECK-SAME: (ptr byval(i32) [[P:%.*]], i32 [[N:%.*]]) { ; CHECK-SAME: (ptr byval(i32) [[P:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[P1:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[P1:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[SAVEDSTACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[SAVEDSTACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[P1]]) ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[P1]])
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[P1]], ptr align 1 [[P]], i64 4, i1 false) ; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[P1]], ptr align 1 [[P]], i64 4, i1 false)
; CHECK-NEXT: [[BUF_I:%.*]] = alloca i8, i32 [[N]], align 1 ; CHECK-NEXT: [[BUF_I:%.*]] = alloca i8, i32 [[N]], align 1
; CHECK-NEXT: call void @escape(ptr [[BUF_I]]) ; CHECK-NEXT: call void @escape(ptr [[BUF_I]])
; CHECK-NEXT: musttail call void @test_dynalloca_c(ptr byval(i32) [[P1]], i32 [[N]]) ; CHECK-NEXT: musttail call void @test_dynalloca_c(ptr byval(i32) [[P1]], i32 [[N]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
musttail call void @test_dynalloca_b(ptr byval(i32) %p, i32 %n) musttail call void @test_dynalloca_b(ptr byval(i32) %p, i32 %n)
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llvm/test/Transforms/InstCombine/sink-alloca.ll

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ret: ; preds = %sinktarget, %nonentry, %entry ret: ; preds = %sinktarget, %nonentry, %entry
ret void ret void
} }
; CHECK-LABEL: define void @foo(i32 %x) ; CHECK-LABEL: define void @foo(i32 %x)
; CHECK: nonentry: ; CHECK: nonentry:
; CHECK: %argmem = alloca i32, i32 %x ; CHECK: %argmem = alloca i32, i32 %x
; CHECK: %sp = call ptr @llvm.stacksave() ; CHECK: %sp = call ptr @llvm.stacksave.p0()
; CHECK: %c2 = call i1 @cond() ; CHECK: %c2 = call i1 @cond()
; CHECK: br i1 %c2, label %ret, label %sinktarget ; CHECK: br i1 %c2, label %ret, label %sinktarget
; CHECK: sinktarget: ; CHECK: sinktarget:
; CHECK: %p = call ptr @use_and_return(ptr nonnull %argmem) ; CHECK: %p = call ptr @use_and_return(ptr nonnull %argmem)
; CHECK: store i32 13, ptr %p ; CHECK: store i32 13, ptr %p
; CHECK: call void @llvm.stackrestore(ptr %sp) ; CHECK: call void @llvm.stackrestore.p0(ptr %sp)
; CHECK: %0 = call ptr @use_and_return(ptr nonnull %p) ; CHECK: %0 = call ptr @use_and_return(ptr nonnull %p)
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/Transforms/InstCombine/stacksaverestore.ll

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linesbb: ; preds = %bb, %bb.preheader
%exitcond = icmp eq i32 %indvar.next, %smax ; <i1> [#uses=1] %exitcond = icmp eq i32 %indvar.next, %smax ; <i1> [#uses=1]
br i1 %exitcond, label %return, label %bb br i1 %exitcond, label %return, label %bb
return: ; preds = %bb, %entry return: ; preds = %bb, %entry
ret void ret void
} }
; CHECK-LABEL: define void @foo( ; CHECK-LABEL: define void @foo(
; CHECK: %tmp = call ptr @llvm.stacksave() ; CHECK: %tmp = call ptr @llvm.stacksave.p0()
; CHECK: alloca i8 ; CHECK: alloca i8
; CHECK-NOT: stacksave ; CHECK-NOT: stacksave
; CHECK: call void @bar( ; CHECK: call void @bar(
; CHECK-NEXT: call void @llvm.stackrestore(ptr %tmp) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr %tmp)
; CHECK: ret void ; CHECK: ret void
declare void @bar(i32, ptr, ptr, ptr, ptr, i32) declare void @bar(i32, ptr, ptr, ptr, ptr, i32)
declare void @inalloca_callee(ptr inalloca(i32)) declare void @inalloca_callee(ptr inalloca(i32))
define void @test3(i32 %c) { define void @test3(i32 %c) {
entry: entry:
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return: return:
ret void ret void
} }
; CHECK-LABEL: define void @test3( ; CHECK-LABEL: define void @test3(
; CHECK: loop: ; CHECK: loop:
; CHECK: %i = phi i32 [ 0, %entry ], [ %i1, %loop ] ; CHECK: %i = phi i32 [ 0, %entry ], [ %i1, %loop ]
; CHECK: %save1 = call ptr @llvm.stacksave() ; CHECK: %save1 = call ptr @llvm.stacksave.p0()
; CHECK: %argmem = alloca inalloca i32 ; CHECK: %argmem = alloca inalloca i32
; CHECK: store i32 0, ptr %argmem ; CHECK: store i32 0, ptr %argmem
; CHECK: call void @inalloca_callee(ptr {{.*}} inalloca(i32) %argmem) ; CHECK: call void @inalloca_callee(ptr {{.*}} inalloca(i32) %argmem)
; CHECK: call void @llvm.stackrestore(ptr %save1) ; CHECK: call void @llvm.stackrestore.p0(ptr %save1)
; CHECK: br i1 %done, label %loop, label %return ; CHECK: br i1 %done, label %loop, label %return
; CHECK: ret void ; CHECK: ret void
define i32 @test4(i32 %m, ptr %a, ptr %b) { define i32 @test4(i32 %m, ptr %a, ptr %b) {
entry: entry:
br label %for.body br label %for.body
for.body: for.body:
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llvm/test/Transforms/MemCpyOpt/stackrestore.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines;
ret i32 0 ret i32 0
} }
; Do not propagate memcpy from %p across the stackrestore. ; Do not propagate memcpy from %p across the stackrestore.
define i32 @test_stackrestore() { define i32 @test_stackrestore() {
; CHECK-LABEL: @test_stackrestore( ; CHECK-LABEL: @test_stackrestore(
; CHECK-NEXT: [[TMPMEM:%.*]] = alloca [10 x i8], align 4 ; CHECK-NEXT: [[TMPMEM:%.*]] = alloca [10 x i8], align 4
; CHECK-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave() ; CHECK-NEXT: [[INALLOCA_SAVE:%.*]] = tail call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[ARGMEM:%.*]] = alloca inalloca [10 x i8], align 4 ; CHECK-NEXT: [[ARGMEM:%.*]] = alloca inalloca [10 x i8], align 4
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr [[ARGMEM]], ptr align 1 @str, i32 9, i1 false) ; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr [[ARGMEM]], ptr align 1 @str, i32 9, i1 false)
; CHECK-NEXT: [[P10:%.*]] = getelementptr inbounds [10 x i8], ptr [[ARGMEM]], i32 0, i32 9 ; CHECK-NEXT: [[P10:%.*]] = getelementptr inbounds [10 x i8], ptr [[ARGMEM]], i32 0, i32 9
; CHECK-NEXT: store i8 0, ptr [[P10]], align 1 ; CHECK-NEXT: store i8 0, ptr [[P10]], align 1
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr [[TMPMEM]], ptr [[ARGMEM]], i32 10, i1 false) ; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr [[TMPMEM]], ptr [[ARGMEM]], i32 10, i1 false)
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[INALLOCA_SAVE]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[INALLOCA_SAVE]])
; CHECK-NEXT: [[HEAP:%.*]] = call ptr @malloc(i32 9) ; CHECK-NEXT: [[HEAP:%.*]] = call ptr @malloc(i32 9)
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr [[HEAP]], ptr [[TMPMEM]], i32 9, i1 false) ; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr [[HEAP]], ptr [[TMPMEM]], i32 9, i1 false)
; CHECK-NEXT: call void @useit(ptr [[HEAP]]) ; CHECK-NEXT: call void @useit(ptr [[HEAP]])
; CHECK-NEXT: ret i32 0 ; CHECK-NEXT: ret i32 0
; ;
%tmpmem = alloca [10 x i8], align 4 %tmpmem = alloca [10 x i8], align 4
%inalloca.save = tail call ptr @llvm.stacksave() %inalloca.save = tail call ptr @llvm.stacksave()
%argmem = alloca inalloca [10 x i8], align 4 %argmem = alloca inalloca [10 x i8], align 4
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llvm/test/Transforms/ObjCARC/post-inlining.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; 3) Dynamic alloca markers. ; 3) Dynamic alloca markers.
declare ptr @llvm.stacksave() declare ptr @llvm.stacksave()
declare void @llvm.stackrestore(ptr) declare void @llvm.stackrestore(ptr)
; CHECK-LABEL: define ptr @testStack( ; CHECK-LABEL: define ptr @testStack(
; CHECK: entry: ; CHECK: entry:
; CHECK-NEXT: %save = tail call ptr @llvm.stacksave() ; CHECK-NEXT: %save = tail call ptr @llvm.stacksave.p0()
; CHECK-NEXT: %obj = alloca i8, i8 %arg ; CHECK-NEXT: %obj = alloca i8, i8 %arg
; CHECK-NEXT: call void @llvm.stackrestore(ptr %save) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr %save)
; CHECK-NEXT: ret ptr %call.i ; CHECK-NEXT: ret ptr %call.i
; CHECK-NEXT: } ; CHECK-NEXT: }
define ptr @testStack(ptr %call.i, i8 %arg) { define ptr @testStack(ptr %call.i, i8 %arg) {
entry: entry:
%save = tail call ptr @llvm.stacksave() %save = tail call ptr @llvm.stacksave()
%obj = alloca i8, i8 %arg %obj = alloca i8, i8 %arg
%0 = tail call ptr @llvm.objc.autoreleaseReturnValue(ptr %call.i) nounwind %0 = tail call ptr @llvm.objc.autoreleaseReturnValue(ptr %call.i) nounwind
call void @llvm.stackrestore(ptr %save) call void @llvm.stackrestore(ptr %save)
%1 = tail call ptr @llvm.objc.retainAutoreleasedReturnValue(ptr %call.i) nounwind %1 = tail call ptr @llvm.objc.retainAutoreleasedReturnValue(ptr %call.i) nounwind
ret ptr %call.i ret ptr %call.i
} }

llvm/test/Transforms/SLPVectorizer/X86/stackrestore-dependence.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=slp-vectorizer -slp-threshold=-999 -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake -S < %s | FileCheck %s ; RUN: opt -passes=slp-vectorizer -slp-threshold=-999 -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake -S < %s | FileCheck %s
; The test checks that loads should not be moved below a stackrestore boundary. ; The test checks that loads should not be moved below a stackrestore boundary.
define void @stackrestore1(ptr %out) { define void @stackrestore1(ptr %out) {
; CHECK-LABEL: @stackrestore1( ; CHECK-LABEL: @stackrestore1(
; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[LOCAL_ALLOCA:%.*]] = alloca [16 x i8], align 4 ; CHECK-NEXT: [[LOCAL_ALLOCA:%.*]] = alloca [16 x i8], align 4
; CHECK-NEXT: store <4 x float> <float 0x3FF3333340000000, float 0x3FF3333340000000, float 0x3FF3333340000000, float 0x3FF3333340000000>, ptr [[LOCAL_ALLOCA]], align 4 ; CHECK-NEXT: store <4 x float> <float 0x3FF3333340000000, float 0x3FF3333340000000, float 0x3FF3333340000000, float 0x3FF3333340000000>, ptr [[LOCAL_ALLOCA]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[LOCAL_ALLOCA]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[LOCAL_ALLOCA]], align 4
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[STACK]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: store <4 x float> [[SHUFFLE]], ptr [[OUT:%.*]], align 4 ; CHECK-NEXT: store <4 x float> [[TMP2]], ptr [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%stack = call ptr @llvm.stacksave() %stack = call ptr @llvm.stacksave()
%local_alloca = alloca [16 x i8], align 4 %local_alloca = alloca [16 x i8], align 4
store float 0x3FF3333340000000, ptr %local_alloca, align 4 store float 0x3FF3333340000000, ptr %local_alloca, align 4
%addr1 = getelementptr inbounds i8, ptr %local_alloca, i64 4 %addr1 = getelementptr inbounds i8, ptr %local_alloca, i64 4
store float 0x3FF3333340000000, ptr %addr1, align 4 store float 0x3FF3333340000000, ptr %addr1, align 4
%addr2 = getelementptr inbounds i8, ptr %local_alloca, i64 8 %addr2 = getelementptr inbounds i8, ptr %local_alloca, i64 8
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llvm/test/Transforms/SLPVectorizer/X86/stacksave-dependence.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; We must be careful not to lift the inalloca alloc above the stacksave here. ; We must be careful not to lift the inalloca alloc above the stacksave here.
; We used to miscompile this example before adding explicit dependency handling ; We used to miscompile this example before adding explicit dependency handling
; for stacksave. ; for stacksave.
define void @stacksave(ptr %a, ptr %b, ptr %c) { define void @stacksave(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: @stacksave( ; CHECK-LABEL: @stacksave(
; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[ADD1:%.*]] = getelementptr i8, ptr [[V1]], i32 1 ; CHECK-NEXT: [[ADD1:%.*]] = getelementptr i8, ptr [[V1]], i32 1
; CHECK-NEXT: store ptr [[ADD1]], ptr [[A:%.*]], align 8 ; CHECK-NEXT: store ptr [[ADD1]], ptr [[A:%.*]], align 8
; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[V2:%.*]] = alloca inalloca i8, align 1 ; CHECK-NEXT: [[V2:%.*]] = alloca inalloca i8, align 1
; CHECK-NEXT: call void @use(ptr inalloca(i8) [[V2]]) #[[ATTR4:[0-9]+]] ; CHECK-NEXT: call void @use(ptr inalloca(i8) [[V2]]) #[[ATTR4:[0-9]+]]
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[STACK]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
; CHECK-NEXT: [[ADD2:%.*]] = getelementptr i8, ptr [[V2]], i32 1 ; CHECK-NEXT: [[ADD2:%.*]] = getelementptr i8, ptr [[V2]], i32 1
; CHECK-NEXT: store ptr [[ADD1]], ptr [[B:%.*]], align 8 ; CHECK-NEXT: store ptr [[ADD1]], ptr [[B:%.*]], align 8
; CHECK-NEXT: [[B2:%.*]] = getelementptr ptr, ptr [[B]], i32 1 ; CHECK-NEXT: [[B2:%.*]] = getelementptr ptr, ptr [[B]], i32 1
; CHECK-NEXT: store ptr [[ADD2]], ptr [[B2]], align 8 ; CHECK-NEXT: store ptr [[ADD2]], ptr [[B2]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%v1 = alloca i8 %v1 = alloca i8
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%b2 = getelementptr ptr, ptr %b, i32 1 %b2 = getelementptr ptr, ptr %b, i32 1
store ptr %add2, ptr %b2 store ptr %add2, ptr %b2
ret void ret void
} }
define void @stacksave2(ptr %a, ptr %b, ptr %c) { define void @stacksave2(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: @stacksave2( ; CHECK-LABEL: @stacksave2(
; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[V2:%.*]] = alloca inalloca i8, align 1 ; CHECK-NEXT: [[V2:%.*]] = alloca inalloca i8, align 1
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[TMP3]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[TMP3]], i32 0
; CHECK-NEXT: store ptr [[TMP4]], ptr [[A:%.*]], align 8 ; CHECK-NEXT: store ptr [[TMP4]], ptr [[A:%.*]], align 8
; CHECK-NEXT: call void @use(ptr inalloca(i8) [[V2]]) #[[ATTR5:[0-9]+]] ; CHECK-NEXT: call void @use(ptr inalloca(i8) [[V2]]) #[[ATTR5:[0-9]+]]
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[STACK]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[B:%.*]], align 8 ; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%v1 = alloca i8 %v1 = alloca i8
%add1 = getelementptr i8, ptr %v1, i32 1 %add1 = getelementptr i8, ptr %v1, i32 1
%stack = call ptr @llvm.stacksave() %stack = call ptr @llvm.stacksave()
store ptr %add1, ptr %a store ptr %add1, ptr %a
%v2 = alloca inalloca i8 %v2 = alloca inalloca i8
call void @use(ptr inalloca(i8) %v2) readonly call void @use(ptr inalloca(i8) %v2) readonly
call void @llvm.stackrestore(ptr %stack) call void @llvm.stackrestore(ptr %stack)
%add2 = getelementptr i8, ptr %v2, i32 1 %add2 = getelementptr i8, ptr %v2, i32 1
store ptr %add1, ptr %b store ptr %add1, ptr %b
%b2 = getelementptr ptr, ptr %b, i32 1 %b2 = getelementptr ptr, ptr %b, i32 1
store ptr %add2, ptr %b2 store ptr %add2, ptr %b2
ret void ret void
} }
define void @stacksave3(ptr %a, ptr %b, ptr %c) { define void @stacksave3(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: @stacksave3( ; CHECK-LABEL: @stacksave3(
; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[V2:%.*]] = alloca inalloca i8, align 1 ; CHECK-NEXT: [[V2:%.*]] = alloca inalloca i8, align 1
; CHECK-NEXT: call void @use(ptr inalloca(i8) [[V2]]) #[[ATTR4]] ; CHECK-NEXT: call void @use(ptr inalloca(i8) [[V2]]) #[[ATTR4]]
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[STACK]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[B:%.*]], align 8 ; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%stack = call ptr @llvm.stacksave() %stack = call ptr @llvm.stacksave()
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; Here we have an alloca which needs to stay under the stacksave, but is not ; Here we have an alloca which needs to stay under the stacksave, but is not
; directly part of the vectorization tree. Instead, the stacksave is ; directly part of the vectorization tree. Instead, the stacksave is
; encountered during dependency scanning via the memory chain. ; encountered during dependency scanning via the memory chain.
define void @stacksave4(ptr %a, ptr %b, ptr %c) { define void @stacksave4(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: @stacksave4( ; CHECK-LABEL: @stacksave4(
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x ptr>, ptr [[A:%.*]], align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x ptr>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, <2 x ptr> [[TMP1]], <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, <2 x ptr> [[TMP1]], <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[X:%.*]] = alloca inalloca i8, align 1 ; CHECK-NEXT: [[X:%.*]] = alloca inalloca i8, align 1
; CHECK-NEXT: call void @use(ptr inalloca(i8) [[X]]) #[[ATTR4]] ; CHECK-NEXT: call void @use(ptr inalloca(i8) [[X]]) #[[ATTR4]]
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[STACK]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
; CHECK-NEXT: store <2 x ptr> [[TMP2]], ptr [[B:%.*]], align 8 ; CHECK-NEXT: store <2 x ptr> [[TMP2]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%v1 = load ptr, ptr %a %v1 = load ptr, ptr %a
%a2 = getelementptr ptr, ptr %a, i32 1 %a2 = getelementptr ptr, ptr %a, i32 1
%v2 = load ptr, ptr %a2 %v2 = load ptr, ptr %a2
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store ptr %add2, ptr %b2 store ptr %add2, ptr %b2
ret void ret void
} }
define void @stacksave5(ptr %a, ptr %b, ptr %c) { define void @stacksave5(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: @stacksave5( ; CHECK-LABEL: @stacksave5(
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x ptr>, ptr [[A:%.*]], align 8 ; CHECK-NEXT: [[TMP1:%.*]] = load <2 x ptr>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, <2 x ptr> [[TMP1]], <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, <2 x ptr> [[TMP1]], <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[X:%.*]] = alloca inalloca i8, align 1 ; CHECK-NEXT: [[X:%.*]] = alloca inalloca i8, align 1
; CHECK-NEXT: call void @use(ptr inalloca(i8) [[X]]) #[[ATTR4]] ; CHECK-NEXT: call void @use(ptr inalloca(i8) [[X]]) #[[ATTR4]]
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[STACK]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
; CHECK-NEXT: store <2 x ptr> [[TMP2]], ptr [[B:%.*]], align 8 ; CHECK-NEXT: store <2 x ptr> [[TMP2]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%v1 = load ptr, ptr %a %v1 = load ptr, ptr %a
%a2 = getelementptr ptr, ptr %a, i32 1 %a2 = getelementptr ptr, ptr %a, i32 1
%v2 = load ptr, ptr %a2 %v2 = load ptr, ptr %a2
Show All 11 Lines;
ret void ret void
} }
; Reordering the second alloca above the stackrestore while ; Reordering the second alloca above the stackrestore while
; leaving the write to it below would introduce a write-after-free ; leaving the write to it below would introduce a write-after-free
; bug. ; bug.
define void @stackrestore1(ptr %a, ptr %b, ptr %c) { define void @stackrestore1(ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: @stackrestore1( ; CHECK-LABEL: @stackrestore1(
; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[STACK:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[V1:%.*]] = alloca i8, align 1
; CHECK-NEXT: store i8 0, ptr [[V1]], align 1 ; CHECK-NEXT: store i8 0, ptr [[V1]], align 1
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[STACK]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[STACK]])
; CHECK-NEXT: [[V2:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[V2:%.*]] = alloca i8, align 1
; CHECK-NEXT: store i8 0, ptr [[V2]], align 1 ; CHECK-NEXT: store i8 0, ptr [[V2]], align 1
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x ptr> poison, ptr [[V1]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x ptr> [[TMP1]], ptr [[V2]], i32 1
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, <2 x ptr> [[TMP2]], <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[B:%.*]], align 8 ; CHECK-NEXT: store <2 x ptr> [[TMP3]], ptr [[B:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
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; CHECK-NEXT: [[VAR2:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[VAR2:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[VAR3:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[VAR3:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[VAR4:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[VAR4:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[VAR5:%.*]] = alloca i8, align 1 ; CHECK-NEXT: [[VAR5:%.*]] = alloca i8, align 1
; CHECK-NEXT: [[VAR12:%.*]] = alloca [12 x ptr], align 8 ; CHECK-NEXT: [[VAR12:%.*]] = alloca [12 x ptr], align 8
; CHECK-NEXT: [[VAR15:%.*]] = call ptr @wibble(ptr [[VAR2]]) ; CHECK-NEXT: [[VAR15:%.*]] = call ptr @wibble(ptr [[VAR2]])
; CHECK-NEXT: [[VAR16:%.*]] = call ptr @wibble(ptr [[VAR3]]) ; CHECK-NEXT: [[VAR16:%.*]] = call ptr @wibble(ptr [[VAR3]])
; CHECK-NEXT: [[VAR17:%.*]] = call ptr @wibble(ptr [[VAR4]]) ; CHECK-NEXT: [[VAR17:%.*]] = call ptr @wibble(ptr [[VAR4]])
; CHECK-NEXT: [[VAR23:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[VAR23:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[VAR24:%.*]] = alloca inalloca i32, align 4 ; CHECK-NEXT: [[VAR24:%.*]] = alloca inalloca i32, align 4
; CHECK-NEXT: call void @quux(ptr inalloca(i32) [[VAR24]]) ; CHECK-NEXT: call void @quux(ptr inalloca(i32) [[VAR24]])
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[VAR23]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[VAR23]])
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> poison, ptr [[VAR4]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x ptr> poison, ptr [[VAR4]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x ptr> [[TMP1]], <4 x ptr> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x ptr> [[TMP1]], <4 x ptr> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: store <4 x ptr> [[TMP2]], ptr [[VAR12]], align 8 ; CHECK-NEXT: store <4 x ptr> [[TMP2]], ptr [[VAR12]], align 8
; CHECK-NEXT: [[VAR36:%.*]] = getelementptr inbounds [12 x ptr], ptr [[VAR12]], i32 0, i32 4 ; CHECK-NEXT: [[VAR36:%.*]] = getelementptr inbounds [12 x ptr], ptr [[VAR12]], i32 0, i32 4
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[VAR5]], i32 1 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x ptr> [[TMP1]], ptr [[VAR5]], i32 1
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x ptr> [[TMP3]], <4 x ptr> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1> ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x ptr> [[TMP3]], <4 x ptr> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
; CHECK-NEXT: store <4 x ptr> [[TMP4]], ptr [[VAR36]], align 8 ; CHECK-NEXT: store <4 x ptr> [[TMP4]], ptr [[VAR36]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
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llvm/test/Transforms/SimplifyCFG/hoist-common-skip.ll

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
%w = add i16 %v, %u %w = add i16 %v, %u
ret i16 %w ret i16 %w
} }
;; Don't hoist stacksaves across inalloca allocas ;; Don't hoist stacksaves across inalloca allocas
define void @f10(i1 %cond) { define void @f10(i1 %cond) {
; CHECK-LABEL: @f10( ; CHECK-LABEL: @f10(
; CHECK-NEXT: [[SS:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[SS:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1: ; CHECK: bb1:
; CHECK-NEXT: [[I1:%.*]] = alloca inalloca i32, align 4 ; CHECK-NEXT: [[I1:%.*]] = alloca inalloca i32, align 4
; CHECK-NEXT: [[SS2:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[SS2:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[I2:%.*]] = alloca inalloca i64, align 8 ; CHECK-NEXT: [[I2:%.*]] = alloca inalloca i64, align 8
; CHECK-NEXT: call void @inalloca_i64(ptr inalloca(i64) [[I2]]) ; CHECK-NEXT: call void @inalloca_i64(ptr inalloca(i64) [[I2]])
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[SS2]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[SS2]])
; CHECK-NEXT: call void @inalloca_i32(ptr inalloca(i32) [[I1]]) ; CHECK-NEXT: call void @inalloca_i32(ptr inalloca(i32) [[I1]])
; CHECK-NEXT: br label [[END:%.*]] ; CHECK-NEXT: br label [[END:%.*]]
; CHECK: bb2: ; CHECK: bb2:
; CHECK-NEXT: [[I3:%.*]] = alloca inalloca i64, align 8 ; CHECK-NEXT: [[I3:%.*]] = alloca inalloca i64, align 8
; CHECK-NEXT: [[SS3:%.*]] = call ptr @llvm.stacksave() ; CHECK-NEXT: [[SS3:%.*]] = call ptr @llvm.stacksave.p0()
; CHECK-NEXT: [[I4:%.*]] = alloca inalloca i64, align 8 ; CHECK-NEXT: [[I4:%.*]] = alloca inalloca i64, align 8
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @inalloca_i64(ptr inalloca(i64) [[I4]]) ; CHECK-NEXT: [[TMP1:%.*]] = call ptr @inalloca_i64(ptr inalloca(i64) [[I4]])
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[SS3]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[SS3]])
; CHECK-NEXT: [[TMP2:%.*]] = call ptr @inalloca_i64(ptr inalloca(i64) [[I3]]) ; CHECK-NEXT: [[TMP2:%.*]] = call ptr @inalloca_i64(ptr inalloca(i64) [[I3]])
; CHECK-NEXT: br label [[END]] ; CHECK-NEXT: br label [[END]]
; CHECK: end: ; CHECK: end:
; CHECK-NEXT: call void @llvm.stackrestore(ptr [[SS]]) ; CHECK-NEXT: call void @llvm.stackrestore.p0(ptr [[SS]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%ss = call ptr @llvm.stacksave() %ss = call ptr @llvm.stacksave()
br i1 %cond, label %bb1, label %bb2 br i1 %cond, label %bb1, label %bb2
bb1: bb1:
%i1 = alloca inalloca i32 %i1 = alloca inalloca i32
%ss2 = call ptr @llvm.stacksave() %ss2 = call ptr @llvm.stacksave()
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