[RISCV] Fix the CFI offset for callee-saved registers stored by Zcmp push.

[Jim]

Summary

Issue mentioned: https://github.com/riscv/riscv-code-size-reduction/issues/182

The order of callee-saved registers stored by Zcmp push in memory is reversed.

Pseudo code for cm.push in https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.4-1/Zc.1.0.4-1.pdf

if (XLEN==32) bytes=4; else bytes=8;

addr=sp-bytes;
for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1)  {
  //if register i is in xreg_list
  if (xreg_list[i]) {
    switch(bytes) {
      4:  asm("sw x[i], 0(addr)");
      8:  asm("sd x[i], 0(addr)");
    }
    addr-=bytes;
  }
}

The placement order for push is s11, s10, ..., ra.

CFI offset should be calculed as reversed order for correct stack unwinding.

[Jim]

Fix comment

[KYG]

Maybe slightly shorter title? E.g., "Fix the CFI offset for callee-saved registers stored by Zcmp push/pop".

Otherwise LGTM, but wait for other reviewer's approve.

[fakepaper56]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

589

The original code looks like we expect negative frame indices are related to their saved location.
If we want to reserve the behavior of negative frame indices, I think we should have specific hasReservedSpillSlot behavior for Zcmp?

[Jim]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

589

I am not sure does any other take care about the order of callee-saved register stored in memory except CFI offset.

RISCVRegisterInfo::hasReservedSpillSlot now is unable to get the total number of callee-saved register stored for calculating frame index in reverse order. I would try to pass extra parameter number of callee-saved regsiter saved to RISCVRegisterInfo::hasReservedSpillSlot.

[kito-cheng]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

587–588

Drop this two line, it might cause confusion IMO.

[fakepaper56]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

585–590

Maybe add curly bracket here to make it more readable?

589

I am not sure does any other take care about the order of callee-saved register stored in memory except CFI offset.

I think you are right. Actually, my concern was that it increases the complexity of this piece of code. But I forgot it is hard for hasReservedSpillSlot to find out the sp offset when Zcmp enabled.
This part is good for me now and thank you for your feedback .

[Jim]

Address comments.

[fakepaper56]

LGTM.

[craig.topper]

Does this need to be backported to LLVM 17 branch?

[kito-cheng]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

584

Nit:

I think this need more curly brackets around there:

if (FrameIdx < 0) {
  if (RVFI->isPushable(MF)) {
    ...
  } else {
    ...
  }
} else {
  ...
}

[Jim]

Address @kito-cheng's comment.

[kito-cheng]

LGTM, and I think this should go to LLVM 17 branch, so don't forgot to create github issue for backport :)

[Jim]

In D156437#4552514, @kito-cheng wrote:

LGTM, and I think this should go to LLVM 17 branch, so don't forgot to create github issue for backport :)

Thanks. I created a issue https://github.com/llvm/llvm-project/issues/64330.

[Jim]

https://github.com/llvm/llvm-project-release-prs/pull/513

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
 
   // Iterate over list of callee-saved registers and emit .cfi_offset
   // directives.
   for (const auto &Entry : CSI) {
     int FrameIdx = Entry.getFrameIdx();
     int64_t Offset;
     // Offsets for objects with fixed locations (IE: those saved by libcall) are
     // simply calculated from the frame index.
     if (FrameIdx < 0)
-      Offset = FrameIdx * (int64_t) STI.getXLen() / 8;
+      if (RVFI->isPushable(MF)) {
+        // Callee-saved register stored by Zcmp push is in reverse order.
+        Offset = -(FrameIdx + RVFI->getRVPushRegs() + 1) *
+                 (int64_t)STI.getXLen() / 8;
+      } else
+        Offset = FrameIdx * (int64_t)STI.getXLen() / 8;
     else
       Offset = MFI.getObjectOffset(FrameIdx) -
                RVFI->getLibCallStackSize();
     Register Reg = Entry.getReg();
     unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
         nullptr, RI->getDwarfRegNum(Reg, true), Offset));
     BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex)

llvm/test/CodeGen/RISCV/push-pop-popret.ll

; RV64I-NEXT:    ret
   ret i32 0
 }
 
 define i32 @pushpopret0(i32 signext %size){
 ; RV32IZCMP-LABEL: pushpopret0:
 ; RV32IZCMP:       # %bb.0: # %entry
 ; RV32IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV32IZCMP-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-NEXT:    .cfi_offset s0, -8
+; RV32IZCMP-NEXT:    .cfi_offset ra, -8
+; RV32IZCMP-NEXT:    .cfi_offset s0, -4
 ; RV32IZCMP-NEXT:    addi s0, sp, 16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-NEXT:    addi a0, a0, 15
 ; RV32IZCMP-NEXT:    andi a0, a0, -16
 ; RV32IZCMP-NEXT:    sub a0, sp, a0
 ; RV32IZCMP-NEXT:    mv sp, a0
 ; RV32IZCMP-NEXT:    call callee_void@plt
 ; RV32IZCMP-NEXT:    addi sp, s0, -16
 ; RV32IZCMP-NEXT:    cm.popretz {ra, s0}, 16
 ;
 ; RV64IZCMP-LABEL: pushpopret0:
 ; RV64IZCMP:       # %bb.0: # %entry
 ; RV64IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV64IZCMP-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-NEXT:    .cfi_offset s0, -16
+; RV64IZCMP-NEXT:    .cfi_offset ra, -16
+; RV64IZCMP-NEXT:    .cfi_offset s0, -8
 ; RV64IZCMP-NEXT:    addi s0, sp, 16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-NEXT:    slli a0, a0, 32
 ; RV64IZCMP-NEXT:    srli a0, a0, 32
 ; RV64IZCMP-NEXT:    addi a0, a0, 15
 ; RV64IZCMP-NEXT:    andi a0, a0, -16
 ; RV64IZCMP-NEXT:    sub a0, sp, a0
 ; RV64IZCMP-NEXT:    mv sp, a0
entry:
   ret i32 0
 }
 
 define i32 @pushpopret1(i32 signext %size) {
 ; RV32IZCMP-LABEL: pushpopret1:
 ; RV32IZCMP:       # %bb.0: # %entry
 ; RV32IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV32IZCMP-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-NEXT:    .cfi_offset s0, -8
+; RV32IZCMP-NEXT:    .cfi_offset ra, -8
+; RV32IZCMP-NEXT:    .cfi_offset s0, -4
 ; RV32IZCMP-NEXT:    addi s0, sp, 16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-NEXT:    addi a0, a0, 15
 ; RV32IZCMP-NEXT:    andi a0, a0, -16
 ; RV32IZCMP-NEXT:    sub a0, sp, a0
 ; RV32IZCMP-NEXT:    mv sp, a0
 ; RV32IZCMP-NEXT:    call callee_void@plt
 ; RV32IZCMP-NEXT:    li a0, 1
 ; RV32IZCMP-NEXT:    addi sp, s0, -16
 ; RV32IZCMP-NEXT:    cm.popret {ra, s0}, 16
 ;
 ; RV64IZCMP-LABEL: pushpopret1:
 ; RV64IZCMP:       # %bb.0: # %entry
 ; RV64IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV64IZCMP-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-NEXT:    .cfi_offset s0, -16
+; RV64IZCMP-NEXT:    .cfi_offset ra, -16
+; RV64IZCMP-NEXT:    .cfi_offset s0, -8
 ; RV64IZCMP-NEXT:    addi s0, sp, 16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-NEXT:    slli a0, a0, 32
 ; RV64IZCMP-NEXT:    srli a0, a0, 32
 ; RV64IZCMP-NEXT:    addi a0, a0, 15
 ; RV64IZCMP-NEXT:    andi a0, a0, -16
 ; RV64IZCMP-NEXT:    sub a0, sp, a0
 ; RV64IZCMP-NEXT:    mv sp, a0
entry:
   ret i32 1
 }
 
 define i32 @pushpopretneg1(i32 signext %size) {
 ; RV32IZCMP-LABEL: pushpopretneg1:
 ; RV32IZCMP:       # %bb.0: # %entry
 ; RV32IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV32IZCMP-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-NEXT:    .cfi_offset s0, -8
+; RV32IZCMP-NEXT:    .cfi_offset ra, -8
+; RV32IZCMP-NEXT:    .cfi_offset s0, -4
 ; RV32IZCMP-NEXT:    addi s0, sp, 16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-NEXT:    addi a0, a0, 15
 ; RV32IZCMP-NEXT:    andi a0, a0, -16
 ; RV32IZCMP-NEXT:    sub a0, sp, a0
 ; RV32IZCMP-NEXT:    mv sp, a0
 ; RV32IZCMP-NEXT:    call callee_void@plt
 ; RV32IZCMP-NEXT:    li a0, -1
 ; RV32IZCMP-NEXT:    addi sp, s0, -16
 ; RV32IZCMP-NEXT:    cm.popret {ra, s0}, 16
 ;
 ; RV64IZCMP-LABEL: pushpopretneg1:
 ; RV64IZCMP:       # %bb.0: # %entry
 ; RV64IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV64IZCMP-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-NEXT:    .cfi_offset s0, -16
+; RV64IZCMP-NEXT:    .cfi_offset ra, -16
+; RV64IZCMP-NEXT:    .cfi_offset s0, -8
 ; RV64IZCMP-NEXT:    addi s0, sp, 16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-NEXT:    slli a0, a0, 32
 ; RV64IZCMP-NEXT:    srli a0, a0, 32
 ; RV64IZCMP-NEXT:    addi a0, a0, 15
 ; RV64IZCMP-NEXT:    andi a0, a0, -16
 ; RV64IZCMP-NEXT:    sub a0, sp, a0
 ; RV64IZCMP-NEXT:    mv sp, a0
entry:
   ret i32 -1
 }
 
 define i32 @pushpopret2(i32 signext %size) {
 ; RV32IZCMP-LABEL: pushpopret2:
 ; RV32IZCMP:       # %bb.0: # %entry
 ; RV32IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV32IZCMP-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-NEXT:    .cfi_offset s0, -8
+; RV32IZCMP-NEXT:    .cfi_offset ra, -8
+; RV32IZCMP-NEXT:    .cfi_offset s0, -4
 ; RV32IZCMP-NEXT:    addi s0, sp, 16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-NEXT:    addi a0, a0, 15
 ; RV32IZCMP-NEXT:    andi a0, a0, -16
 ; RV32IZCMP-NEXT:    sub a0, sp, a0
 ; RV32IZCMP-NEXT:    mv sp, a0
 ; RV32IZCMP-NEXT:    call callee_void@plt
 ; RV32IZCMP-NEXT:    li a0, 2
 ; RV32IZCMP-NEXT:    addi sp, s0, -16
 ; RV32IZCMP-NEXT:    cm.popret {ra, s0}, 16
 ;
 ; RV64IZCMP-LABEL: pushpopret2:
 ; RV64IZCMP:       # %bb.0: # %entry
 ; RV64IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV64IZCMP-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-NEXT:    .cfi_offset s0, -16
+; RV64IZCMP-NEXT:    .cfi_offset ra, -16
+; RV64IZCMP-NEXT:    .cfi_offset s0, -8
 ; RV64IZCMP-NEXT:    addi s0, sp, 16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-NEXT:    slli a0, a0, 32
 ; RV64IZCMP-NEXT:    srli a0, a0, 32
 ; RV64IZCMP-NEXT:    addi a0, a0, 15
 ; RV64IZCMP-NEXT:    andi a0, a0, -16
 ; RV64IZCMP-NEXT:    sub a0, sp, a0
 ; RV64IZCMP-NEXT:    mv sp, a0
entry:
   ret i32 2
 }
 
 define dso_local i32 @tailcall(i32 signext %size) local_unnamed_addr #0 {
 ; RV32IZCMP-LABEL: tailcall:
 ; RV32IZCMP:       # %bb.0: # %entry
 ; RV32IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV32IZCMP-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-NEXT:    .cfi_offset s0, -8
+; RV32IZCMP-NEXT:    .cfi_offset ra, -8
+; RV32IZCMP-NEXT:    .cfi_offset s0, -4
 ; RV32IZCMP-NEXT:    addi s0, sp, 16
 ; RV32IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-NEXT:    addi a0, a0, 15
 ; RV32IZCMP-NEXT:    andi a0, a0, -16
 ; RV32IZCMP-NEXT:    sub a0, sp, a0
 ; RV32IZCMP-NEXT:    mv sp, a0
 ; RV32IZCMP-NEXT:    addi sp, s0, -16
 ; RV32IZCMP-NEXT:    cm.pop {ra, s0}, 16
 ; RV32IZCMP-NEXT:    tail callee@plt
 ;
 ; RV64IZCMP-LABEL: tailcall:
 ; RV64IZCMP:       # %bb.0: # %entry
 ; RV64IZCMP-NEXT:    cm.push {ra, s0}, -16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 16
-; RV64IZCMP-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-NEXT:    .cfi_offset s0, -16
+; RV64IZCMP-NEXT:    .cfi_offset ra, -16
+; RV64IZCMP-NEXT:    .cfi_offset s0, -8
 ; RV64IZCMP-NEXT:    addi s0, sp, 16
 ; RV64IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-NEXT:    slli a0, a0, 32
 ; RV64IZCMP-NEXT:    srli a0, a0, 32
 ; RV64IZCMP-NEXT:    addi a0, a0, 15
 ; RV64IZCMP-NEXT:    andi a0, a0, -16
 ; RV64IZCMP-NEXT:    sub a0, sp, a0
 ; RV64IZCMP-NEXT:    mv sp, a0
 ; RV64IZCMP-NEXT:    addi sp, s0, -16
 ; RV64IZCMP-NEXT:    cm.pop {ra, s0}, 16
 ; RV64IZCMP-NEXT:    tail callee@plt
 ;
 ; RV32IZCMP-SR-LABEL: tailcall:
 ; RV32IZCMP-SR:       # %bb.0: # %entry
 ; RV32IZCMP-SR-NEXT:    cm.push {ra, s0}, -16
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 16
-; RV32IZCMP-SR-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-SR-NEXT:    .cfi_offset s0, -8
+; RV32IZCMP-SR-NEXT:    .cfi_offset ra, -8
+; RV32IZCMP-SR-NEXT:    .cfi_offset s0, -4
 ; RV32IZCMP-SR-NEXT:    addi s0, sp, 16
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-SR-NEXT:    addi a0, a0, 15
 ; RV32IZCMP-SR-NEXT:    andi a0, a0, -16
 ; RV32IZCMP-SR-NEXT:    sub a0, sp, a0
 ; RV32IZCMP-SR-NEXT:    mv sp, a0
 ; RV32IZCMP-SR-NEXT:    addi sp, s0, -16
 ; RV32IZCMP-SR-NEXT:    cm.pop {ra, s0}, 16
 ; RV32IZCMP-SR-NEXT:    tail callee@plt
 ;
 ; RV64IZCMP-SR-LABEL: tailcall:
 ; RV64IZCMP-SR:       # %bb.0: # %entry
 ; RV64IZCMP-SR-NEXT:    cm.push {ra, s0}, -16
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 16
-; RV64IZCMP-SR-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-SR-NEXT:    .cfi_offset s0, -16
+; RV64IZCMP-SR-NEXT:    .cfi_offset ra, -16
+; RV64IZCMP-SR-NEXT:    .cfi_offset s0, -8
 ; RV64IZCMP-SR-NEXT:    addi s0, sp, 16
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-SR-NEXT:    slli a0, a0, 32
 ; RV64IZCMP-SR-NEXT:    srli a0, a0, 32
 ; RV64IZCMP-SR-NEXT:    addi a0, a0, 15
 ; RV64IZCMP-SR-NEXT:    andi a0, a0, -16
 ; RV64IZCMP-SR-NEXT:    sub a0, sp, a0
 ; RV64IZCMP-SR-NEXT:    mv sp, a0

 }
 
 @var = global [5 x i32] zeroinitializer
 define i32 @nocompress(i32 signext %size) {
 ; RV32IZCMP-LABEL: nocompress:
 ; RV32IZCMP:       # %bb.0: # %entry
 ; RV32IZCMP-NEXT:    cm.push {ra, s0-s8}, -48
 ; RV32IZCMP-NEXT:    .cfi_def_cfa_offset 48
-; RV32IZCMP-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-NEXT:    .cfi_offset s0, -8
-; RV32IZCMP-NEXT:    .cfi_offset s1, -12
-; RV32IZCMP-NEXT:    .cfi_offset s2, -16
-; RV32IZCMP-NEXT:    .cfi_offset s3, -20
-; RV32IZCMP-NEXT:    .cfi_offset s4, -24
-; RV32IZCMP-NEXT:    .cfi_offset s5, -28
-; RV32IZCMP-NEXT:    .cfi_offset s6, -32
-; RV32IZCMP-NEXT:    .cfi_offset s7, -36
-; RV32IZCMP-NEXT:    .cfi_offset s8, -40
+; RV32IZCMP-NEXT:    .cfi_offset ra, -40
+; RV32IZCMP-NEXT:    .cfi_offset s0, -36
+; RV32IZCMP-NEXT:    .cfi_offset s1, -32
+; RV32IZCMP-NEXT:    .cfi_offset s2, -28
+; RV32IZCMP-NEXT:    .cfi_offset s3, -24
+; RV32IZCMP-NEXT:    .cfi_offset s4, -20
+; RV32IZCMP-NEXT:    .cfi_offset s5, -16
+; RV32IZCMP-NEXT:    .cfi_offset s6, -12
+; RV32IZCMP-NEXT:    .cfi_offset s7, -8
+; RV32IZCMP-NEXT:    .cfi_offset s8, -4
 ; RV32IZCMP-NEXT:    addi s0, sp, 48
 ; RV32IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-NEXT:    addi a0, a0, 15
 ; RV32IZCMP-NEXT:    andi a0, a0, -16
 ; RV32IZCMP-NEXT:    sub s2, sp, a0
 ; RV32IZCMP-NEXT:    mv sp, s2
 ; RV32IZCMP-NEXT:    lui s1, %hi(var)
 ; RV32IZCMP-NEXT:    lw s3, %lo(var)(s1)

 ; RV32IZCMP-NEXT:    addi sp, s0, -48
 ; RV32IZCMP-NEXT:    cm.pop {ra, s0-s8}, 48
 ; RV32IZCMP-NEXT:    tail callee@plt
 ;
 ; RV64IZCMP-LABEL: nocompress:
 ; RV64IZCMP:       # %bb.0: # %entry
 ; RV64IZCMP-NEXT:    cm.push {ra, s0-s8}, -80
 ; RV64IZCMP-NEXT:    .cfi_def_cfa_offset 80
-; RV64IZCMP-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-NEXT:    .cfi_offset s0, -16
-; RV64IZCMP-NEXT:    .cfi_offset s1, -24
-; RV64IZCMP-NEXT:    .cfi_offset s2, -32
-; RV64IZCMP-NEXT:    .cfi_offset s3, -40
-; RV64IZCMP-NEXT:    .cfi_offset s4, -48
-; RV64IZCMP-NEXT:    .cfi_offset s5, -56
-; RV64IZCMP-NEXT:    .cfi_offset s6, -64
-; RV64IZCMP-NEXT:    .cfi_offset s7, -72
-; RV64IZCMP-NEXT:    .cfi_offset s8, -80
+; RV64IZCMP-NEXT:    .cfi_offset ra, -80
+; RV64IZCMP-NEXT:    .cfi_offset s0, -72
+; RV64IZCMP-NEXT:    .cfi_offset s1, -64
+; RV64IZCMP-NEXT:    .cfi_offset s2, -56
+; RV64IZCMP-NEXT:    .cfi_offset s3, -48
+; RV64IZCMP-NEXT:    .cfi_offset s4, -40
+; RV64IZCMP-NEXT:    .cfi_offset s5, -32
+; RV64IZCMP-NEXT:    .cfi_offset s6, -24
+; RV64IZCMP-NEXT:    .cfi_offset s7, -16
+; RV64IZCMP-NEXT:    .cfi_offset s8, -8
 ; RV64IZCMP-NEXT:    addi s0, sp, 80
 ; RV64IZCMP-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-NEXT:    slli a0, a0, 32
 ; RV64IZCMP-NEXT:    srli a0, a0, 32
 ; RV64IZCMP-NEXT:    addi a0, a0, 15
 ; RV64IZCMP-NEXT:    andi a0, a0, -16
 ; RV64IZCMP-NEXT:    sub s2, sp, a0
 ; RV64IZCMP-NEXT:    mv sp, s2

 ; RV64IZCMP-NEXT:    addi sp, s0, -80
 ; RV64IZCMP-NEXT:    cm.pop {ra, s0-s8}, 80
 ; RV64IZCMP-NEXT:    tail callee@plt
 ;
 ; RV32IZCMP-SR-LABEL: nocompress:
 ; RV32IZCMP-SR:       # %bb.0: # %entry
 ; RV32IZCMP-SR-NEXT:    cm.push {ra, s0-s8}, -48
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa_offset 48
-; RV32IZCMP-SR-NEXT:    .cfi_offset ra, -4
-; RV32IZCMP-SR-NEXT:    .cfi_offset s0, -8
-; RV32IZCMP-SR-NEXT:    .cfi_offset s1, -12
-; RV32IZCMP-SR-NEXT:    .cfi_offset s2, -16
-; RV32IZCMP-SR-NEXT:    .cfi_offset s3, -20
-; RV32IZCMP-SR-NEXT:    .cfi_offset s4, -24
-; RV32IZCMP-SR-NEXT:    .cfi_offset s5, -28
-; RV32IZCMP-SR-NEXT:    .cfi_offset s6, -32
-; RV32IZCMP-SR-NEXT:    .cfi_offset s7, -36
-; RV32IZCMP-SR-NEXT:    .cfi_offset s8, -40
+; RV32IZCMP-SR-NEXT:    .cfi_offset ra, -40
+; RV32IZCMP-SR-NEXT:    .cfi_offset s0, -36
+; RV32IZCMP-SR-NEXT:    .cfi_offset s1, -32
+; RV32IZCMP-SR-NEXT:    .cfi_offset s2, -28
+; RV32IZCMP-SR-NEXT:    .cfi_offset s3, -24
+; RV32IZCMP-SR-NEXT:    .cfi_offset s4, -20
+; RV32IZCMP-SR-NEXT:    .cfi_offset s5, -16
+; RV32IZCMP-SR-NEXT:    .cfi_offset s6, -12
+; RV32IZCMP-SR-NEXT:    .cfi_offset s7, -8
+; RV32IZCMP-SR-NEXT:    .cfi_offset s8, -4
 ; RV32IZCMP-SR-NEXT:    addi s0, sp, 48
 ; RV32IZCMP-SR-NEXT:    .cfi_def_cfa s0, 0
 ; RV32IZCMP-SR-NEXT:    addi a0, a0, 15
 ; RV32IZCMP-SR-NEXT:    andi a0, a0, -16
 ; RV32IZCMP-SR-NEXT:    sub s2, sp, a0
 ; RV32IZCMP-SR-NEXT:    mv sp, s2
 ; RV32IZCMP-SR-NEXT:    lui s1, %hi(var)
 ; RV32IZCMP-SR-NEXT:    lw s3, %lo(var)(s1)

 ; RV32IZCMP-SR-NEXT:    addi sp, s0, -48
 ; RV32IZCMP-SR-NEXT:    cm.pop {ra, s0-s8}, 48
 ; RV32IZCMP-SR-NEXT:    tail callee@plt
 ;
 ; RV64IZCMP-SR-LABEL: nocompress:
 ; RV64IZCMP-SR:       # %bb.0: # %entry
 ; RV64IZCMP-SR-NEXT:    cm.push {ra, s0-s8}, -80
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa_offset 80
-; RV64IZCMP-SR-NEXT:    .cfi_offset ra, -8
-; RV64IZCMP-SR-NEXT:    .cfi_offset s0, -16
-; RV64IZCMP-SR-NEXT:    .cfi_offset s1, -24
-; RV64IZCMP-SR-NEXT:    .cfi_offset s2, -32
-; RV64IZCMP-SR-NEXT:    .cfi_offset s3, -40
-; RV64IZCMP-SR-NEXT:    .cfi_offset s4, -48
-; RV64IZCMP-SR-NEXT:    .cfi_offset s5, -56
-; RV64IZCMP-SR-NEXT:    .cfi_offset s6, -64
-; RV64IZCMP-SR-NEXT:    .cfi_offset s7, -72
-; RV64IZCMP-SR-NEXT:    .cfi_offset s8, -80
+; RV64IZCMP-SR-NEXT:    .cfi_offset ra, -80
+; RV64IZCMP-SR-NEXT:    .cfi_offset s0, -72
+; RV64IZCMP-SR-NEXT:    .cfi_offset s1, -64
+; RV64IZCMP-SR-NEXT:    .cfi_offset s2, -56
+; RV64IZCMP-SR-NEXT:    .cfi_offset s3, -48
+; RV64IZCMP-SR-NEXT:    .cfi_offset s4, -40
+; RV64IZCMP-SR-NEXT:    .cfi_offset s5, -32
+; RV64IZCMP-SR-NEXT:    .cfi_offset s6, -24
+; RV64IZCMP-SR-NEXT:    .cfi_offset s7, -16
+; RV64IZCMP-SR-NEXT:    .cfi_offset s8, -8
 ; RV64IZCMP-SR-NEXT:    addi s0, sp, 80
 ; RV64IZCMP-SR-NEXT:    .cfi_def_cfa s0, 0
 ; RV64IZCMP-SR-NEXT:    slli a0, a0, 32
 ; RV64IZCMP-SR-NEXT:    srli a0, a0, 32
 ; RV64IZCMP-SR-NEXT:    addi a0, a0, 15
 ; RV64IZCMP-SR-NEXT:    andi a0, a0, -16
 ; RV64IZCMP-SR-NEXT:    sub s2, sp, a0
 ; RV64IZCMP-SR-NEXT:    mv sp, s2