[RISCV] Refine getMaxPushPopReg like getLibCallID. NFC.

[Jim]

Summary

If save/restore libcall or Zcmp push/pop are enabled, callee-saved registers including ra would be
assigned a negative frame index (-1 for ra, -2 for s0, ..., -13 for s11) by RISCVRegisterInfo::hasReservedSpillSlot.

getLibCallID would find a callee-saved register that has max register id and with assigned negative frame index.
And use this max register to get which save/restore libcall should be selected.

In getMaxPushPopReg (for Zcmp push/pop, similar getLibCallID), it uses extra register class (PGPR) to
check the saved register is in ra, s0-s11 instead of checking the frame index is negative.

This patch just changes the checking for the saved register from is contained in PGPR to has a negative frame index.

[kito-cheng]

testcase?

[Jim]

In D156393#4537632, @kito-cheng wrote:

testcase?

It is hard to add testcase to show the differece. It only reuses the assumption that register in ra-s11 would be assigned a negative frame index
by RISCVRegisterInfo::hasReservedSpillSlot instead of adding a new register class PGPR to check register inside ra-s11.

[kito-cheng]

I guess I am confused, does it fix some bug or just kind of refine?

[jrtc27]

I have no clue either from skimming this, the patch summary is extremely unclear and really hard to parse as English.

[jrtc27]

Needs a clear summary at least

[fakepaper56]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

270–273

indexes -> indices.
by Push -> by Zcmp Push.

[Jim]

Address @fakepaper56's comment.

[kito-cheng]

So actually it's a NFC?

[Jim]

In D156393#4538011, @kito-cheng wrote:

So actually it's a NFC?

Yes, it is. Append NFC to title of this revision.

[Jim]

Rebase

[fakepaper56]

LGTM.

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

 
 // Get the max reg of Push/Pop for restoring callee saved registers.
 static Register getMaxPushPopReg(const MachineFunction &MF,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  unsigned &PushPopRegs) {
   Register MaxPushPopReg = RISCV::NoRegister;
   PushPopRegs = 0;
   for (auto &CS : CSI) {
-    Register Reg = CS.getReg();
-    if (RISCV::PGPRRegClass.contains(Reg)) {
-      MaxPushPopReg = std::max(MaxPushPopReg.id(), Reg.id());
+    // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indices to
+    // registers which can be saved by Zcmp Push.
+    if (CS.getFrameIdx() < 0) {
+      MaxPushPopReg = std::max(MaxPushPopReg.id(), CS.getReg().id());
       PushPopRegs += 1;
     }
   }
   // if rlist is {rs, s0-s10}, then s11 will also be included
   if (MaxPushPopReg == RISCV::X26) {
     MaxPushPopReg = RISCV::X27;
     PushPopRegs = 13;
   }

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
 }
 
 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
   return CSR_NoRegs_RegMask;
 }
 
 // Frame indexes representing locations of CSRs which are given a fixed location
-// by save/restore libcalls.
+// by save/restore libcalls or Zcmp Push/Pop.
 static const std::pair<unsigned, int> FixedCSRFIMap[] = {
   {/*ra*/  RISCV::X1,   -1},
   {/*s0*/  RISCV::X8,   -2},
   {/*s1*/  RISCV::X9,   -3},
   {/*s2*/  RISCV::X18,  -4},
   {/*s3*/  RISCV::X19,  -5},
   {/*s4*/  RISCV::X20,  -6},
   {/*s5*/  RISCV::X21,  -7},

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

def GPRTC : GPRRegisterClass<(add (sequence "X%u", 6, 7),
                                   (sequence "X%u", 28, 31))>;
 
 def SP : GPRRegisterClass<(add X2)>;
 
 // Saved Registers from s0 to s7, for C.MVA01S07 instruction in Zcmp extension
 def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
                                  (sequence "X%u", 18, 23))>;
 
-// Registers saveable by PUSH/POP instruction in Zcmp extension
-def PGPR : RegisterClass<"RISCV", [XLenVT], 32, (add
-    (sequence "X%u", 8, 9),
-    (sequence "X%u", 18, 27),
-    X1
-  )> {
-  let RegInfos = XLenRI;
-}
-
 // Floating point registers
 let RegAltNameIndices = [ABIRegAltName] in {
   def F0_H  : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
   def F1_H  : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>;
   def F2_H  : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>;
   def F3_H  : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>;
   def F4_H  : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>;
   def F5_H  : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>;